1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/arm_pmuv3.h> 81 #include <asm/cpu.h> 82 #include <asm/cpufeature.h> 83 #include <asm/cpu_ops.h> 84 #include <asm/fpsimd.h> 85 #include <asm/hwcap.h> 86 #include <asm/insn.h> 87 #include <asm/kvm_host.h> 88 #include <asm/mmu.h> 89 #include <asm/mmu_context.h> 90 #include <asm/mpam.h> 91 #include <asm/mte.h> 92 #include <asm/hypervisor.h> 93 #include <asm/processor.h> 94 #include <asm/smp.h> 95 #include <asm/sysreg.h> 96 #include <asm/traps.h> 97 #include <asm/vectors.h> 98 #include <asm/virt.h> 99 100 #include <asm/spectre.h> 101 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 102 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 103 104 #ifdef CONFIG_COMPAT 105 #define COMPAT_ELF_HWCAP_DEFAULT \ 106 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 107 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 108 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 109 COMPAT_HWCAP_LPAE) 110 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 111 unsigned int compat_elf_hwcap2 __read_mostly; 112 unsigned int compat_elf_hwcap3 __read_mostly; 113 #endif 114 115 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 116 EXPORT_SYMBOL(system_cpucaps); 117 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 118 119 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 120 121 /* 122 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 123 * ends up in the .bss section where it is initialized in early_map_kernel() 124 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 125 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 126 * may end up generating an incorrect idmap page table attributes. 127 */ 128 bool arm64_use_ng_mappings __read_mostly = false; 129 EXPORT_SYMBOL(arm64_use_ng_mappings); 130 131 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 132 133 /* 134 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 135 * support it? 136 */ 137 static bool __read_mostly allow_mismatched_32bit_el0; 138 139 /* 140 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 141 * seen at least one CPU capable of 32-bit EL0. 142 */ 143 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 144 145 /* 146 * Mask of CPUs supporting 32-bit EL0. 147 * Only valid if arm64_mismatched_32bit_el0 is enabled. 148 */ 149 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 150 151 void dump_cpu_features(void) 152 { 153 /* file-wide pr_fmt adds "CPU features: " prefix */ 154 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 155 } 156 157 #define __ARM64_MAX_POSITIVE(reg, field) \ 158 ((reg##_##field##_SIGNED ? \ 159 BIT(reg##_##field##_WIDTH - 1) : \ 160 BIT(reg##_##field##_WIDTH)) - 1) 161 162 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 163 164 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 165 .sys_reg = SYS_##reg, \ 166 .field_pos = reg##_##field##_SHIFT, \ 167 .field_width = reg##_##field##_WIDTH, \ 168 .sign = reg##_##field##_SIGNED, \ 169 .min_field_value = min_value, \ 170 .max_field_value = max_value, 171 172 /* 173 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 174 * an implicit maximum that depends on the sign-ess of the field. 175 * 176 * An unsigned field will be capped at all ones, while a signed field 177 * will be limited to the positive half only. 178 */ 179 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 180 __ARM64_CPUID_FIELDS(reg, field, \ 181 SYS_FIELD_VALUE(reg, field, min_value), \ 182 __ARM64_MAX_POSITIVE(reg, field)) 183 184 /* 185 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 186 * implicit minimal value to max_value. This should be used when 187 * matching a non-implemented property. 188 */ 189 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 190 __ARM64_CPUID_FIELDS(reg, field, \ 191 __ARM64_MIN_NEGATIVE(reg, field), \ 192 SYS_FIELD_VALUE(reg, field, max_value)) 193 194 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 195 { \ 196 .sign = SIGNED, \ 197 .visible = VISIBLE, \ 198 .strict = STRICT, \ 199 .type = TYPE, \ 200 .shift = SHIFT, \ 201 .width = WIDTH, \ 202 .safe_val = SAFE_VAL, \ 203 } 204 205 /* Define a feature with unsigned values */ 206 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 /* Define a feature with a signed value */ 210 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 211 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 212 213 #define ARM64_FTR_END \ 214 { \ 215 .width = 0, \ 216 } 217 218 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 219 220 static bool __system_matches_cap(unsigned int n); 221 222 /* 223 * NOTE: Any changes to the visibility of features should be kept in 224 * sync with the documentation of the CPU feature register ABI. 225 */ 226 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 241 ARM64_FTR_END, 242 }; 243 244 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LS64_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 261 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 263 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 265 ARM64_FTR_END, 266 }; 267 268 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_ATS1A_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 277 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 279 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 282 ARM64_FTR_END, 283 }; 284 285 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 286 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 290 ARM64_FTR_END, 291 }; 292 293 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 301 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 304 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 305 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 310 ARM64_FTR_END, 311 }; 312 313 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 316 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 317 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 324 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 325 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 326 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 327 ARM64_FTR_END, 328 }; 329 330 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 331 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI), 333 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 334 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 335 ARM64_FTR_END, 336 }; 337 338 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 344 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 346 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 348 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 350 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 352 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 354 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 356 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 358 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 360 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 362 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 363 ARM64_FTR_END, 364 }; 365 366 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUT6_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 393 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 394 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 395 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 396 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 398 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 400 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 402 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 404 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 405 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 406 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 407 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 408 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 409 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 410 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 412 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 414 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 415 ARM64_FTR_END, 416 }; 417 418 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 421 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 424 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 425 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F16MM2_SHIFT, 1, 0), 426 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 427 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 428 ARM64_FTR_END, 429 }; 430 431 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 432 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 435 /* 436 * Page size not being supported at Stage-2 is not fatal. You 437 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 438 * your favourite nesting hypervisor. 439 * 440 * There is a small corner case where the hypervisor explicitly 441 * advertises a given granule size at Stage-2 (value 2) on some 442 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 443 * vCPUs. Although this is not forbidden by the architecture, it 444 * indicates that the hypervisor is being silly (or buggy). 445 * 446 * We make no effort to cope with this and pretend that if these 447 * fields are inconsistent across vCPUs, then it isn't worth 448 * trying to bring KVM up. 449 */ 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 453 /* 454 * We already refuse to boot CPUs that don't support our configured 455 * page size, so we can only detect mismatches for a page size other 456 * than the one we're currently using. Unfortunately, SoCs like this 457 * exist in the wild so, even though we don't like it, we'll have to go 458 * along with it and treat them as non-strict. 459 */ 460 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 461 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 463 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 465 /* Linux shouldn't care about secure memory */ 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 469 /* 470 * Differing PARange is fine as long as all peripherals and memory are mapped 471 * within the minimum PARange of all CPUs 472 */ 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 474 ARM64_FTR_END, 475 }; 476 477 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 492 ARM64_FTR_END, 493 }; 494 495 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 515 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 516 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 520 ARM64_FTR_END, 521 }; 522 523 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 524 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 526 ARM64_FTR_END, 527 }; 528 529 static const struct arm64_ftr_bits ftr_ctr[] = { 530 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 531 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 532 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 533 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 536 /* 537 * Linux can handle differing I-cache policies. Userspace JITs will 538 * make use of *minLine. 539 * If we have differing I-cache policies, report it as the weakest - VIPT. 540 */ 541 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 542 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 543 ARM64_FTR_END, 544 }; 545 546 static struct arm64_ftr_override __ro_after_init no_override = { }; 547 548 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 549 .name = "SYS_CTR_EL0", 550 .ftr_bits = ftr_ctr, 551 .override = &no_override, 552 }; 553 554 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 555 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 560 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 563 ARM64_FTR_END, 564 }; 565 566 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 567 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 572 /* 573 * We can instantiate multiple PMU instances with different levels 574 * of support. 575 */ 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_mvfr0[] = { 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_mvfr1[] = { 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 596 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 602 ARM64_FTR_END, 603 }; 604 605 static const struct arm64_ftr_bits ftr_mvfr2[] = { 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 608 ARM64_FTR_END, 609 }; 610 611 static const struct arm64_ftr_bits ftr_dczid[] = { 612 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 613 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 614 ARM64_FTR_END, 615 }; 616 617 static const struct arm64_ftr_bits ftr_gmid[] = { 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 619 ARM64_FTR_END, 620 }; 621 622 static const struct arm64_ftr_bits ftr_id_isar0[] = { 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 630 ARM64_FTR_END, 631 }; 632 633 static const struct arm64_ftr_bits ftr_id_isar5[] = { 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 640 ARM64_FTR_END, 641 }; 642 643 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 651 652 /* 653 * SpecSEI = 1 indicates that the PE might generate an SError on an 654 * external abort on speculative read. It is safe to assume that an 655 * SError might be generated than it will not be. Hence it has been 656 * classified as FTR_HIGHER_SAFE. 657 */ 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 659 ARM64_FTR_END, 660 }; 661 662 static const struct arm64_ftr_bits ftr_id_isar4[] = { 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 671 ARM64_FTR_END, 672 }; 673 674 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 676 ARM64_FTR_END, 677 }; 678 679 static const struct arm64_ftr_bits ftr_id_isar6[] = { 680 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 687 ARM64_FTR_END, 688 }; 689 690 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 697 ARM64_FTR_END, 698 }; 699 700 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 701 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 702 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 703 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 709 ARM64_FTR_END, 710 }; 711 712 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 713 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 715 ARM64_FTR_END, 716 }; 717 718 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 719 /* [31:28] TraceFilt */ 720 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 721 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 727 ARM64_FTR_END, 728 }; 729 730 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 731 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 732 ARM64_FTR_END, 733 }; 734 735 static const struct arm64_ftr_bits ftr_mpamidr[] = { 736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 740 ARM64_FTR_END, 741 }; 742 743 /* 744 * Common ftr bits for a 32bit register with all hidden, strict 745 * attributes, with 4bit feature fields and a default safe value of 746 * 0. Covers the following 32bit registers: 747 * id_isar[1-3], id_mmfr[1-3] 748 */ 749 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 750 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 751 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 752 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 753 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 754 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 755 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 756 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 757 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 758 ARM64_FTR_END, 759 }; 760 761 /* Table for a single 32bit feature value */ 762 static const struct arm64_ftr_bits ftr_single32[] = { 763 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 764 ARM64_FTR_END, 765 }; 766 767 static const struct arm64_ftr_bits ftr_raz[] = { 768 ARM64_FTR_END, 769 }; 770 771 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 772 .sys_id = id, \ 773 .reg = &(struct arm64_ftr_reg){ \ 774 .name = id_str, \ 775 .override = (ovr), \ 776 .ftr_bits = &((table)[0]), \ 777 }} 778 779 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 780 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 781 782 #define ARM64_FTR_REG(id, table) \ 783 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 784 785 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 786 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 787 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 788 struct arm64_ftr_override __read_mostly id_aa64mmfr4_override; 789 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 790 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 791 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 792 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 793 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 794 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 795 796 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 797 798 static const struct __ftr_reg_entry { 799 u32 sys_id; 800 struct arm64_ftr_reg *reg; 801 } arm64_ftr_regs[] = { 802 803 /* Op1 = 0, CRn = 0, CRm = 1 */ 804 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 805 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 806 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 807 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 808 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 809 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 810 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 811 812 /* Op1 = 0, CRn = 0, CRm = 2 */ 813 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 814 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 815 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 816 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 817 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 818 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 819 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 820 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 821 822 /* Op1 = 0, CRn = 0, CRm = 3 */ 823 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 824 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 825 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 826 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 827 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 828 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 829 830 /* Op1 = 0, CRn = 0, CRm = 4 */ 831 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 832 &id_aa64pfr0_override), 833 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 834 &id_aa64pfr1_override), 835 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 836 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 837 &id_aa64zfr0_override), 838 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 839 &id_aa64smfr0_override), 840 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 841 842 /* Op1 = 0, CRn = 0, CRm = 5 */ 843 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 844 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 845 846 /* Op1 = 0, CRn = 0, CRm = 6 */ 847 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 848 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 849 &id_aa64isar1_override), 850 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 851 &id_aa64isar2_override), 852 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 853 854 /* Op1 = 0, CRn = 0, CRm = 7 */ 855 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 856 &id_aa64mmfr0_override), 857 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 858 &id_aa64mmfr1_override), 859 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 860 &id_aa64mmfr2_override), 861 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 862 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4, 863 &id_aa64mmfr4_override), 864 865 /* Op1 = 0, CRn = 10, CRm = 4 */ 866 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 867 868 /* Op1 = 1, CRn = 0, CRm = 0 */ 869 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 870 871 /* Op1 = 3, CRn = 0, CRm = 0 */ 872 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 873 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 874 875 /* Op1 = 3, CRn = 14, CRm = 0 */ 876 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 877 }; 878 879 static int search_cmp_ftr_reg(const void *id, const void *regp) 880 { 881 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 882 } 883 884 /* 885 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 886 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 887 * ascending order of sys_id, we use binary search to find a matching 888 * entry. 889 * 890 * returns - Upon success, matching ftr_reg entry for id. 891 * - NULL on failure. It is upto the caller to decide 892 * the impact of a failure. 893 */ 894 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 895 { 896 const struct __ftr_reg_entry *ret; 897 898 ret = bsearch((const void *)(unsigned long)sys_id, 899 arm64_ftr_regs, 900 ARRAY_SIZE(arm64_ftr_regs), 901 sizeof(arm64_ftr_regs[0]), 902 search_cmp_ftr_reg); 903 if (ret) 904 return ret->reg; 905 return NULL; 906 } 907 908 /* 909 * get_arm64_ftr_reg - Looks up a feature register entry using 910 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 911 * 912 * returns - Upon success, matching ftr_reg entry for id. 913 * - NULL on failure but with an WARN_ON(). 914 */ 915 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 916 { 917 struct arm64_ftr_reg *reg; 918 919 reg = get_arm64_ftr_reg_nowarn(sys_id); 920 921 /* 922 * Requesting a non-existent register search is an error. Warn 923 * and let the caller handle it. 924 */ 925 WARN_ON(!reg); 926 return reg; 927 } 928 929 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 930 s64 ftr_val) 931 { 932 u64 mask = arm64_ftr_mask(ftrp); 933 934 reg &= ~mask; 935 reg |= (ftr_val << ftrp->shift) & mask; 936 return reg; 937 } 938 939 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 940 s64 cur) 941 { 942 s64 ret = 0; 943 944 switch (ftrp->type) { 945 case FTR_EXACT: 946 ret = ftrp->safe_val; 947 break; 948 case FTR_LOWER_SAFE: 949 ret = min(new, cur); 950 break; 951 case FTR_HIGHER_OR_ZERO_SAFE: 952 if (!cur || !new) 953 break; 954 fallthrough; 955 case FTR_HIGHER_SAFE: 956 ret = max(new, cur); 957 break; 958 default: 959 BUG(); 960 } 961 962 return ret; 963 } 964 965 static void __init sort_ftr_regs(void) 966 { 967 unsigned int i; 968 969 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 970 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 971 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 972 unsigned int j = 0; 973 974 /* 975 * Features here must be sorted in descending order with respect 976 * to their shift values and should not overlap with each other. 977 */ 978 for (; ftr_bits->width != 0; ftr_bits++, j++) { 979 unsigned int width = ftr_reg->ftr_bits[j].width; 980 unsigned int shift = ftr_reg->ftr_bits[j].shift; 981 unsigned int prev_shift; 982 983 WARN((shift + width) > 64, 984 "%s has invalid feature at shift %d\n", 985 ftr_reg->name, shift); 986 987 /* 988 * Skip the first feature. There is nothing to 989 * compare against for now. 990 */ 991 if (j == 0) 992 continue; 993 994 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 995 WARN((shift + width) > prev_shift, 996 "%s has feature overlap at shift %d\n", 997 ftr_reg->name, shift); 998 } 999 1000 /* 1001 * Skip the first register. There is nothing to 1002 * compare against for now. 1003 */ 1004 if (i == 0) 1005 continue; 1006 /* 1007 * Registers here must be sorted in ascending order with respect 1008 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 1009 * to work correctly. 1010 */ 1011 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1012 } 1013 } 1014 1015 /* 1016 * Initialise the CPU feature register from Boot CPU values. 1017 * Also initialises the strict_mask for the register. 1018 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1019 * RES0 for the system-wide value, and must strictly match. 1020 */ 1021 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1022 { 1023 u64 val = 0; 1024 u64 strict_mask = ~0x0ULL; 1025 u64 user_mask = 0; 1026 u64 valid_mask = 0; 1027 1028 const struct arm64_ftr_bits *ftrp; 1029 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1030 1031 if (!reg) 1032 return; 1033 1034 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1035 u64 ftr_mask = arm64_ftr_mask(ftrp); 1036 s64 ftr_new = arm64_ftr_value(ftrp, new); 1037 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1038 1039 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1040 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1041 char *str = NULL; 1042 1043 if (ftr_ovr != tmp) { 1044 /* Unsafe, remove the override */ 1045 reg->override->mask &= ~ftr_mask; 1046 reg->override->val &= ~ftr_mask; 1047 tmp = ftr_ovr; 1048 str = "ignoring override"; 1049 } else if (ftr_new != tmp) { 1050 /* Override was valid */ 1051 ftr_new = tmp; 1052 str = "forced"; 1053 } else { 1054 /* Override was the safe value */ 1055 str = "already set"; 1056 } 1057 1058 pr_warn("%s[%d:%d]: %s to %llx\n", 1059 reg->name, 1060 ftrp->shift + ftrp->width - 1, 1061 ftrp->shift, str, 1062 tmp & (BIT(ftrp->width) - 1)); 1063 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1064 reg->override->val &= ~ftr_mask; 1065 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1066 reg->name, 1067 ftrp->shift + ftrp->width - 1, 1068 ftrp->shift); 1069 } 1070 1071 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1072 1073 valid_mask |= ftr_mask; 1074 if (!ftrp->strict) 1075 strict_mask &= ~ftr_mask; 1076 if (ftrp->visible) 1077 user_mask |= ftr_mask; 1078 else 1079 reg->user_val = arm64_ftr_set_value(ftrp, 1080 reg->user_val, 1081 ftrp->safe_val); 1082 } 1083 1084 val &= valid_mask; 1085 1086 reg->sys_val = val; 1087 reg->strict_mask = strict_mask; 1088 reg->user_mask = user_mask; 1089 } 1090 1091 extern const struct arm64_cpu_capabilities arm64_errata[]; 1092 static const struct arm64_cpu_capabilities arm64_features[]; 1093 1094 static void __init 1095 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1096 { 1097 for (; caps->matches; caps++) { 1098 if (WARN(caps->capability >= ARM64_NCAPS, 1099 "Invalid capability %d\n", caps->capability)) 1100 continue; 1101 if (WARN(cpucap_ptrs[caps->capability], 1102 "Duplicate entry for capability %d\n", 1103 caps->capability)) 1104 continue; 1105 cpucap_ptrs[caps->capability] = caps; 1106 } 1107 } 1108 1109 static void __init init_cpucap_indirect_list(void) 1110 { 1111 init_cpucap_indirect_list_from_array(arm64_features); 1112 init_cpucap_indirect_list_from_array(arm64_errata); 1113 } 1114 1115 static void __init setup_boot_cpu_capabilities(void); 1116 1117 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1118 { 1119 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1120 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1121 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1122 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1123 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1124 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1125 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1126 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1127 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1128 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1129 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1130 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1131 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1132 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1133 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1134 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1135 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1136 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1137 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1138 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1139 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1140 } 1141 1142 #ifdef CONFIG_ARM64_PSEUDO_NMI 1143 static bool enable_pseudo_nmi; 1144 1145 static int __init early_enable_pseudo_nmi(char *p) 1146 { 1147 return kstrtobool(p, &enable_pseudo_nmi); 1148 } 1149 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1150 1151 static __init void detect_system_supports_pseudo_nmi(void) 1152 { 1153 struct device_node *np; 1154 1155 if (!enable_pseudo_nmi) 1156 return; 1157 1158 /* 1159 * Detect broken MediaTek firmware that doesn't properly save and 1160 * restore GIC priorities. 1161 */ 1162 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1163 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1164 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1165 enable_pseudo_nmi = false; 1166 } 1167 of_node_put(np); 1168 } 1169 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1170 static inline void detect_system_supports_pseudo_nmi(void) { } 1171 #endif 1172 1173 static bool detect_ftr_has_mpam(void) 1174 { 1175 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1176 u64 pfr1 = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1177 1178 return id_aa64pfr0_mpam(pfr0) || id_aa64pfr1_mpamfrac(pfr1); 1179 } 1180 1181 bool gmid_el1_accessible(const struct cpuinfo_arm64 *info) 1182 { 1183 const struct arm64_ftr_bits *ftrp; 1184 s64 mte, ovr; 1185 u64 ftr_mask; 1186 1187 /* No ID register reflects CONFIG_ARM64_MTE. */ 1188 if (!IS_ENABLED(CONFIG_ARM64_MTE)) 1189 return false; 1190 1191 for (ftrp = ftr_id_aa64pfr1; ftrp->width; ftrp++) { 1192 if (ftrp->shift == ID_AA64PFR1_EL1_MTE_SHIFT) 1193 break; 1194 } 1195 1196 ftr_mask = arm64_ftr_mask(ftrp); 1197 mte = arm64_ftr_value(ftrp, info->reg_id_aa64pfr1); 1198 1199 /* The boot CPU runs before init_cpu_ftr_reg() strips unsafe overrides. */ 1200 if ((id_aa64pfr1_override.mask & ftr_mask) == ftr_mask) { 1201 ovr = arm64_ftr_value(ftrp, id_aa64pfr1_override.val); 1202 mte = arm64_ftr_safe_value(ftrp, ovr, mte); 1203 } 1204 1205 return mte >= ID_AA64PFR1_EL1_MTE_MTE2; 1206 } 1207 1208 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1209 { 1210 /* Before we start using the tables, make sure it is sorted */ 1211 sort_ftr_regs(); 1212 1213 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1214 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1215 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1216 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1217 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1218 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1219 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1220 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1221 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1222 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1223 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1224 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1225 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1226 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1227 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1228 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1229 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1230 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1231 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1232 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1233 1234 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1235 init_32bit_cpu_features(&info->aarch32); 1236 1237 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1238 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1239 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1240 1241 vec_init_vq_map(ARM64_VEC_SVE); 1242 1243 cpacr_restore(cpacr); 1244 } 1245 1246 if (IS_ENABLED(CONFIG_ARM64_SME) && 1247 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1248 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1249 1250 vec_init_vq_map(ARM64_VEC_SME); 1251 1252 cpacr_restore(cpacr); 1253 } 1254 1255 if (detect_ftr_has_mpam()) { 1256 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1257 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1258 } 1259 1260 if (gmid_el1_accessible(info)) 1261 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1262 } 1263 1264 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1265 { 1266 const struct arm64_ftr_bits *ftrp; 1267 1268 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1269 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1270 s64 ftr_new = arm64_ftr_value(ftrp, new); 1271 1272 if (ftr_cur == ftr_new) 1273 continue; 1274 /* Find a safe value */ 1275 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1276 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1277 } 1278 1279 } 1280 1281 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1282 { 1283 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1284 1285 if (!regp) 1286 return 0; 1287 1288 update_cpu_ftr_reg(regp, val); 1289 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1290 return 0; 1291 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1292 regp->name, boot, cpu, val); 1293 return 1; 1294 } 1295 1296 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1297 { 1298 const struct arm64_ftr_bits *ftrp; 1299 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1300 1301 if (!regp) 1302 return; 1303 1304 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1305 if (ftrp->shift == field) { 1306 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1307 break; 1308 } 1309 } 1310 1311 /* Bogus field? */ 1312 WARN_ON(!ftrp->width); 1313 } 1314 1315 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1316 struct cpuinfo_arm64 *boot) 1317 { 1318 static bool boot_cpu_32bit_regs_overridden = false; 1319 1320 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1321 return; 1322 1323 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1324 return; 1325 1326 boot->aarch32 = info->aarch32; 1327 init_32bit_cpu_features(&boot->aarch32); 1328 boot_cpu_32bit_regs_overridden = true; 1329 } 1330 1331 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1332 struct cpuinfo_32bit *boot) 1333 { 1334 int taint = 0; 1335 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1336 1337 /* 1338 * If we don't have AArch32 at EL1, then relax the strictness of 1339 * EL1-dependent register fields to avoid spurious sanity check fails. 1340 */ 1341 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1342 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1343 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1344 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1345 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1346 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1347 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1348 } 1349 1350 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1351 info->reg_id_dfr0, boot->reg_id_dfr0); 1352 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1353 info->reg_id_dfr1, boot->reg_id_dfr1); 1354 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1355 info->reg_id_isar0, boot->reg_id_isar0); 1356 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1357 info->reg_id_isar1, boot->reg_id_isar1); 1358 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1359 info->reg_id_isar2, boot->reg_id_isar2); 1360 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1361 info->reg_id_isar3, boot->reg_id_isar3); 1362 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1363 info->reg_id_isar4, boot->reg_id_isar4); 1364 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1365 info->reg_id_isar5, boot->reg_id_isar5); 1366 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1367 info->reg_id_isar6, boot->reg_id_isar6); 1368 1369 /* 1370 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1371 * ACTLR formats could differ across CPUs and therefore would have to 1372 * be trapped for virtualization anyway. 1373 */ 1374 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1375 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1376 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1377 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1378 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1379 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1380 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1381 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1382 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1383 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1384 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1385 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1386 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1387 info->reg_id_pfr0, boot->reg_id_pfr0); 1388 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1389 info->reg_id_pfr1, boot->reg_id_pfr1); 1390 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1391 info->reg_id_pfr2, boot->reg_id_pfr2); 1392 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1393 info->reg_mvfr0, boot->reg_mvfr0); 1394 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1395 info->reg_mvfr1, boot->reg_mvfr1); 1396 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1397 info->reg_mvfr2, boot->reg_mvfr2); 1398 1399 return taint; 1400 } 1401 1402 /* 1403 * Update system wide CPU feature registers with the values from a 1404 * non-boot CPU. Also performs SANITY checks to make sure that there 1405 * aren't any insane variations from that of the boot CPU. 1406 */ 1407 void update_cpu_features(int cpu, 1408 struct cpuinfo_arm64 *info, 1409 struct cpuinfo_arm64 *boot) 1410 { 1411 int taint = 0; 1412 1413 /* 1414 * The kernel can handle differing I-cache policies, but otherwise 1415 * caches should look identical. Userspace JITs will make use of 1416 * *minLine. 1417 */ 1418 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1419 info->reg_ctr, boot->reg_ctr); 1420 1421 /* 1422 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1423 * could result in too much or too little memory being zeroed if a 1424 * process is preempted and migrated between CPUs. 1425 */ 1426 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1427 info->reg_dczid, boot->reg_dczid); 1428 1429 /* If different, timekeeping will be broken (especially with KVM) */ 1430 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1431 info->reg_cntfrq, boot->reg_cntfrq); 1432 1433 /* 1434 * The kernel uses self-hosted debug features and expects CPUs to 1435 * support identical debug features. We presently need CTX_CMPs, WRPs, 1436 * and BRPs to be identical. 1437 * ID_AA64DFR1 is currently RES0. 1438 */ 1439 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1440 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1441 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1442 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1443 /* 1444 * Even in big.LITTLE, processors should be identical instruction-set 1445 * wise. 1446 */ 1447 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1448 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1449 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1450 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1451 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1452 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1453 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1454 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1455 1456 /* 1457 * Differing PARange support is fine as long as all peripherals and 1458 * memory are mapped within the minimum PARange of all CPUs. 1459 * Linux should not care about secure memory. 1460 */ 1461 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1462 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1463 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1464 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1465 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1466 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1467 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1468 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1469 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1470 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1471 1472 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1473 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1474 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1475 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1476 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1477 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1478 1479 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1480 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1481 1482 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1483 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1484 1485 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1486 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1487 1488 /* Probe vector lengths */ 1489 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1490 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1491 if (!system_capabilities_finalized()) { 1492 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1493 1494 vec_update_vq_map(ARM64_VEC_SVE); 1495 1496 cpacr_restore(cpacr); 1497 } 1498 } 1499 1500 if (IS_ENABLED(CONFIG_ARM64_SME) && 1501 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1502 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1503 1504 /* Probe vector lengths */ 1505 if (!system_capabilities_finalized()) 1506 vec_update_vq_map(ARM64_VEC_SME); 1507 1508 cpacr_restore(cpacr); 1509 } 1510 1511 if (detect_ftr_has_mpam()) { 1512 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1513 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1514 info->reg_mpamidr, boot->reg_mpamidr); 1515 } 1516 1517 /* 1518 * The kernel uses the LDGM/STGM instructions and the number of tags 1519 * they read/write depends on the GMID_EL1.BS field. Check that the 1520 * value is the same on all CPUs. 1521 */ 1522 if (gmid_el1_accessible(info)) 1523 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1524 info->reg_gmid, boot->reg_gmid); 1525 1526 /* 1527 * If we don't have AArch32 at all then skip the checks entirely 1528 * as the register values may be UNKNOWN and we're not going to be 1529 * using them for anything. 1530 * 1531 * This relies on a sanitised view of the AArch64 ID registers 1532 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1533 */ 1534 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1535 lazy_init_32bit_cpu_features(info, boot); 1536 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1537 &boot->aarch32); 1538 } 1539 1540 /* 1541 * Mismatched CPU features are a recipe for disaster. Don't even 1542 * pretend to support them. 1543 */ 1544 if (taint) { 1545 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1546 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1547 } 1548 } 1549 1550 u64 read_sanitised_ftr_reg(u32 id) 1551 { 1552 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1553 1554 if (!regp) 1555 return 0; 1556 return regp->sys_val; 1557 } 1558 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1559 1560 #define read_sysreg_case(r) \ 1561 case r: val = read_sysreg_s(r); break; 1562 1563 /* 1564 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1565 * Read the system register on the current CPU 1566 */ 1567 u64 __read_sysreg_by_encoding(u32 sys_id) 1568 { 1569 struct arm64_ftr_reg *regp; 1570 u64 val; 1571 1572 switch (sys_id) { 1573 read_sysreg_case(SYS_ID_PFR0_EL1); 1574 read_sysreg_case(SYS_ID_PFR1_EL1); 1575 read_sysreg_case(SYS_ID_PFR2_EL1); 1576 read_sysreg_case(SYS_ID_DFR0_EL1); 1577 read_sysreg_case(SYS_ID_DFR1_EL1); 1578 read_sysreg_case(SYS_ID_MMFR0_EL1); 1579 read_sysreg_case(SYS_ID_MMFR1_EL1); 1580 read_sysreg_case(SYS_ID_MMFR2_EL1); 1581 read_sysreg_case(SYS_ID_MMFR3_EL1); 1582 read_sysreg_case(SYS_ID_MMFR4_EL1); 1583 read_sysreg_case(SYS_ID_MMFR5_EL1); 1584 read_sysreg_case(SYS_ID_ISAR0_EL1); 1585 read_sysreg_case(SYS_ID_ISAR1_EL1); 1586 read_sysreg_case(SYS_ID_ISAR2_EL1); 1587 read_sysreg_case(SYS_ID_ISAR3_EL1); 1588 read_sysreg_case(SYS_ID_ISAR4_EL1); 1589 read_sysreg_case(SYS_ID_ISAR5_EL1); 1590 read_sysreg_case(SYS_ID_ISAR6_EL1); 1591 read_sysreg_case(SYS_MVFR0_EL1); 1592 read_sysreg_case(SYS_MVFR1_EL1); 1593 read_sysreg_case(SYS_MVFR2_EL1); 1594 1595 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1596 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1597 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1598 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1599 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1600 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1601 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1602 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1603 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1604 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1605 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1606 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1607 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1608 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1609 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1610 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1611 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1612 1613 read_sysreg_case(SYS_CNTFRQ_EL0); 1614 read_sysreg_case(SYS_CTR_EL0); 1615 read_sysreg_case(SYS_DCZID_EL0); 1616 1617 default: 1618 BUG(); 1619 return 0; 1620 } 1621 1622 regp = get_arm64_ftr_reg(sys_id); 1623 if (regp) { 1624 val &= ~regp->override->mask; 1625 val |= (regp->override->val & regp->override->mask); 1626 } 1627 1628 return val; 1629 } 1630 1631 #include <linux/irqchip/arm-gic-v3.h> 1632 1633 static bool 1634 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1635 { 1636 return true; 1637 } 1638 1639 static bool 1640 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1641 { 1642 int val, min, max; 1643 u64 tmp; 1644 1645 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1646 entry->field_width, 1647 entry->sign); 1648 1649 tmp = entry->min_field_value; 1650 tmp <<= entry->field_pos; 1651 1652 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1653 entry->field_width, 1654 entry->sign); 1655 1656 tmp = entry->max_field_value; 1657 tmp <<= entry->field_pos; 1658 1659 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1660 entry->field_width, 1661 entry->sign); 1662 1663 return val >= min && val <= max; 1664 } 1665 1666 static u64 1667 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1668 { 1669 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1670 if (scope == SCOPE_SYSTEM) 1671 return read_sanitised_ftr_reg(entry->sys_reg); 1672 else 1673 return __read_sysreg_by_encoding(entry->sys_reg); 1674 } 1675 1676 static bool 1677 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1678 { 1679 int mask; 1680 struct arm64_ftr_reg *regp; 1681 u64 val = read_scoped_sysreg(entry, scope); 1682 1683 regp = get_arm64_ftr_reg(entry->sys_reg); 1684 if (!regp) 1685 return false; 1686 1687 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1688 entry->field_pos, 1689 entry->field_width); 1690 if (!mask) 1691 return false; 1692 1693 return feature_matches(val, entry); 1694 } 1695 1696 static bool 1697 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1698 { 1699 u64 val = read_scoped_sysreg(entry, scope); 1700 return feature_matches(val, entry); 1701 } 1702 1703 const struct cpumask *system_32bit_el0_cpumask(void) 1704 { 1705 if (!system_supports_32bit_el0()) 1706 return cpu_none_mask; 1707 1708 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1709 return cpu_32bit_el0_mask; 1710 1711 return cpu_possible_mask; 1712 } 1713 1714 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1715 { 1716 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_DOMAIN)); 1717 } 1718 1719 static int __init parse_32bit_el0_param(char *str) 1720 { 1721 allow_mismatched_32bit_el0 = true; 1722 return 0; 1723 } 1724 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1725 1726 static ssize_t aarch32_el0_show(struct device *dev, 1727 struct device_attribute *attr, char *buf) 1728 { 1729 const struct cpumask *mask = system_32bit_el0_cpumask(); 1730 1731 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1732 } 1733 static const DEVICE_ATTR_RO(aarch32_el0); 1734 1735 static int __init aarch32_el0_sysfs_init(void) 1736 { 1737 struct device *dev_root; 1738 int ret = 0; 1739 1740 if (!allow_mismatched_32bit_el0) 1741 return 0; 1742 1743 dev_root = bus_get_dev_root(&cpu_subsys); 1744 if (dev_root) { 1745 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1746 put_device(dev_root); 1747 } 1748 return ret; 1749 } 1750 device_initcall(aarch32_el0_sysfs_init); 1751 1752 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1753 { 1754 if (!has_cpuid_feature(entry, scope)) 1755 return allow_mismatched_32bit_el0; 1756 1757 if (scope == SCOPE_SYSTEM) 1758 pr_info("detected: 32-bit EL0 Support\n"); 1759 1760 return true; 1761 } 1762 1763 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1764 { 1765 bool has_sre; 1766 1767 if (!has_cpuid_feature(entry, scope)) 1768 return false; 1769 1770 has_sre = gic_enable_sre(); 1771 if (!has_sre) 1772 pr_warn_once("%s present but disabled by higher exception level\n", 1773 entry->desc); 1774 1775 return has_sre; 1776 } 1777 1778 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1779 int scope) 1780 { 1781 u64 ctr; 1782 1783 if (scope == SCOPE_SYSTEM) 1784 ctr = arm64_ftr_reg_ctrel0.sys_val; 1785 else 1786 ctr = read_cpuid_effective_cachetype(); 1787 1788 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1789 } 1790 1791 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1792 { 1793 /* 1794 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1795 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1796 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1797 * value. 1798 */ 1799 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1800 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1801 } 1802 1803 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1804 int scope) 1805 { 1806 u64 ctr; 1807 1808 if (scope == SCOPE_SYSTEM) 1809 ctr = arm64_ftr_reg_ctrel0.sys_val; 1810 else 1811 ctr = read_cpuid_cachetype(); 1812 1813 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1814 } 1815 1816 static bool __maybe_unused 1817 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1818 { 1819 /* 1820 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1821 * may share TLB entries with a CPU stuck in the crashed 1822 * kernel. 1823 */ 1824 if (is_kdump_kernel()) 1825 return false; 1826 1827 if (cpus_have_cap(ARM64_WORKAROUND_DISABLE_CNP)) 1828 return false; 1829 1830 return has_cpuid_feature(entry, scope); 1831 } 1832 1833 static bool __meltdown_safe = true; 1834 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1835 1836 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1837 int scope) 1838 { 1839 /* List of CPUs that are not vulnerable and don't need KPTI */ 1840 static const struct midr_range kpti_safe_list[] = { 1841 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1842 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1843 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1844 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1845 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1846 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1847 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1848 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1849 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1850 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1851 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1852 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1853 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1854 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1855 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1856 { /* sentinel */ } 1857 }; 1858 char const *str = "kpti command line option"; 1859 bool meltdown_safe; 1860 1861 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1862 1863 /* Defer to CPU feature registers */ 1864 if (has_cpuid_feature(entry, scope)) 1865 meltdown_safe = true; 1866 1867 if (!meltdown_safe) 1868 __meltdown_safe = false; 1869 1870 /* 1871 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1872 * ThunderX leads to apparent I-cache corruption of kernel text, which 1873 * ends as well as you might imagine. Don't even try. We cannot rely 1874 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1875 * because cpucap detection order may change. However, since we know 1876 * affected CPUs are always in a homogeneous configuration, it is 1877 * safe to rely on this_cpu_has_cap() here. 1878 */ 1879 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1880 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1881 __kpti_forced = -1; 1882 } 1883 1884 /* Useful for KASLR robustness */ 1885 if (kaslr_enabled() && kaslr_requires_kpti()) { 1886 if (!__kpti_forced) { 1887 str = "KASLR"; 1888 __kpti_forced = 1; 1889 } 1890 } 1891 1892 if (cpu_mitigations_off() && !__kpti_forced) { 1893 str = "mitigations=off"; 1894 __kpti_forced = -1; 1895 } 1896 1897 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1898 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1899 return false; 1900 } 1901 1902 /* Forced? */ 1903 if (__kpti_forced) { 1904 pr_info_once("kernel page table isolation forced %s by %s\n", 1905 __kpti_forced > 0 ? "ON" : "OFF", str); 1906 return __kpti_forced > 0; 1907 } 1908 1909 return !meltdown_safe; 1910 } 1911 1912 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1913 { 1914 /* 1915 * Although the Apple M2 family appears to support NV1, the 1916 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1917 * that it doesn't support NV1 at all. 1918 */ 1919 static const struct midr_range nv1_ni_list[] = { 1920 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1921 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1922 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1923 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1924 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1925 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1926 {} 1927 }; 1928 1929 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1930 !(has_cpuid_feature(entry, scope) || 1931 is_midr_in_range_list(nv1_ni_list))); 1932 } 1933 1934 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1935 static bool has_lpa2_at_stage1(u64 mmfr0) 1936 { 1937 unsigned int tgran; 1938 1939 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1940 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1941 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1942 } 1943 1944 static bool has_lpa2_at_stage2(u64 mmfr0) 1945 { 1946 unsigned int tgran; 1947 1948 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1949 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1950 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1951 } 1952 1953 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1954 { 1955 u64 mmfr0; 1956 1957 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1958 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1959 } 1960 #else 1961 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1962 { 1963 return false; 1964 } 1965 #endif 1966 1967 #ifdef CONFIG_HW_PERF_EVENTS 1968 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1969 { 1970 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1971 unsigned int pmuver; 1972 1973 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1974 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1975 1976 return pmuv3_implemented(pmuver); 1977 } 1978 #endif 1979 1980 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1981 { 1982 if (__this_cpu_read(this_cpu_vector) == vectors) { 1983 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1984 1985 __this_cpu_write(this_cpu_vector, v); 1986 } 1987 1988 } 1989 1990 static int __init parse_kpti(char *str) 1991 { 1992 bool enabled; 1993 int ret = kstrtobool(str, &enabled); 1994 1995 if (ret) 1996 return ret; 1997 1998 __kpti_forced = enabled ? 1 : -1; 1999 return 0; 2000 } 2001 early_param("kpti", parse_kpti); 2002 2003 #ifdef CONFIG_ARM64_HW_AFDBM 2004 static struct cpumask dbm_cpus __read_mostly; 2005 2006 static inline void __cpu_enable_hw_dbm(void) 2007 { 2008 u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD; 2009 2010 write_sysreg(tcr, tcr_el1); 2011 isb(); 2012 local_flush_tlb_all(); 2013 } 2014 2015 static bool cpu_has_broken_dbm(void) 2016 { 2017 /* List of CPUs which have broken DBM support. */ 2018 static const struct midr_range cpus[] = { 2019 #ifdef CONFIG_ARM64_ERRATUM_1024718 2020 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2021 /* Kryo4xx Silver (rdpe => r1p0) */ 2022 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2023 #endif 2024 #ifdef CONFIG_ARM64_ERRATUM_2051678 2025 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2026 #endif 2027 {}, 2028 }; 2029 2030 return is_midr_in_range_list(cpus); 2031 } 2032 2033 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2034 { 2035 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2036 !cpu_has_broken_dbm(); 2037 } 2038 2039 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2040 { 2041 if (cpu_can_use_dbm(cap)) { 2042 __cpu_enable_hw_dbm(); 2043 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2044 } 2045 } 2046 2047 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2048 int __unused) 2049 { 2050 /* 2051 * DBM is a non-conflicting feature. i.e, the kernel can safely 2052 * run a mix of CPUs with and without the feature. So, we 2053 * unconditionally enable the capability to allow any late CPU 2054 * to use the feature. We only enable the control bits on the 2055 * CPU, if it is supported. 2056 */ 2057 2058 return true; 2059 } 2060 2061 #endif 2062 2063 #ifdef CONFIG_ARM64_AMU_EXTN 2064 2065 /* 2066 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2067 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2068 * information regarding all the events that it supports. When a CPU bit is 2069 * set in the cpumask, the user of this feature can only rely on the presence 2070 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2071 * counters are enabled or access to these counters is enabled by code 2072 * executed at higher exception levels (firmware). 2073 */ 2074 static struct cpumask amu_cpus __read_mostly; 2075 2076 bool cpu_has_amu_feat(int cpu) 2077 { 2078 return cpumask_test_cpu(cpu, &amu_cpus); 2079 } 2080 2081 int get_cpu_with_amu_feat(void) 2082 { 2083 return cpumask_any(&amu_cpus); 2084 } 2085 2086 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2087 { 2088 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2089 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2090 2091 /* 0 reference values signal broken/disabled counters */ 2092 if (!this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT)) 2093 update_freq_counters_refs(); 2094 } 2095 } 2096 2097 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2098 int __unused) 2099 { 2100 /* 2101 * The AMU extension is a non-conflicting feature: the kernel can 2102 * safely run a mix of CPUs with and without support for the 2103 * activity monitors extension. Therefore, unconditionally enable 2104 * the capability to allow any late CPU to use the feature. 2105 * 2106 * With this feature unconditionally enabled, the cpu_enable 2107 * function will be called for all CPUs that match the criteria, 2108 * including secondary and hotplugged, marking this feature as 2109 * present on that respective CPU. The enable function will also 2110 * print a detection message. 2111 */ 2112 2113 return true; 2114 } 2115 #else 2116 int get_cpu_with_amu_feat(void) 2117 { 2118 return nr_cpu_ids; 2119 } 2120 #endif 2121 2122 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2123 { 2124 return is_kernel_in_hyp_mode(); 2125 } 2126 2127 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2128 { 2129 /* 2130 * Copy register values that aren't redirected by hardware. 2131 * 2132 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2133 * this value to tpidr_el2 before we patch the code. Once we've done 2134 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2135 * do anything here. 2136 */ 2137 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2138 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2139 } 2140 2141 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2142 int scope) 2143 { 2144 if (kvm_get_mode() != KVM_MODE_NV) 2145 return false; 2146 2147 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2148 pr_warn("unavailable: %s\n", cap->desc); 2149 return false; 2150 } 2151 2152 return true; 2153 } 2154 2155 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2156 int __unused) 2157 { 2158 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2159 } 2160 2161 bool cpu_supports_bbml3(void) 2162 { 2163 /* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */ 2164 static const struct midr_range supports_bbml3_list[] = { 2165 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2166 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2167 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2168 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2169 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2170 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2171 MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), 2172 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 2173 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), 2174 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 2175 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 2176 MIDR_ALL_VERSIONS(MIDR_C1_NANO), 2177 MIDR_ALL_VERSIONS(MIDR_C1_PRO), 2178 /* Erratum 3683289 fixed in r1p1 */ 2179 MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf), 2180 MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf), 2181 {} 2182 }; 2183 u64 mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); 2184 2185 if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) 2186 return true; 2187 2188 return is_midr_in_range_list(supports_bbml3_list); 2189 } 2190 2191 static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) 2192 { 2193 return cpu_supports_bbml3(); 2194 } 2195 2196 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2197 { 2198 /* 2199 * We modify PSTATE. This won't work from irq context as the PSTATE 2200 * is discarded once we return from the exception. 2201 */ 2202 WARN_ON_ONCE(in_interrupt()); 2203 2204 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2205 set_pstate_pan(1); 2206 } 2207 2208 #ifdef CONFIG_ARM64_RAS_EXTN 2209 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2210 { 2211 /* Firmware may have left a deferred SError in this register. */ 2212 write_sysreg_s(0, SYS_DISR_EL1); 2213 } 2214 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2215 { 2216 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2217 { 2218 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2219 }, 2220 { 2221 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2222 }, 2223 { 2224 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2225 }, 2226 }; 2227 2228 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2229 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2230 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2231 } 2232 #endif /* CONFIG_ARM64_RAS_EXTN */ 2233 2234 #ifdef CONFIG_ARM64_PTR_AUTH 2235 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2236 { 2237 int boot_val, sec_val; 2238 2239 /* We don't expect to be called with SCOPE_SYSTEM */ 2240 WARN_ON(scope == SCOPE_SYSTEM); 2241 /* 2242 * The ptr-auth feature levels are not intercompatible with lower 2243 * levels. Hence we must match ptr-auth feature level of the secondary 2244 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2245 * from the sanitised register whereas direct register read is done for 2246 * the secondary CPUs. 2247 * The sanitised feature state is guaranteed to match that of the 2248 * boot CPU as a mismatched secondary CPU is parked before it gets 2249 * a chance to update the state, with the capability. 2250 */ 2251 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2252 entry->field_pos, entry->sign); 2253 if (scope & SCOPE_BOOT_CPU) 2254 return boot_val >= entry->min_field_value; 2255 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2256 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2257 entry->field_pos, entry->sign); 2258 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2259 } 2260 2261 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2262 int scope) 2263 { 2264 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2265 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2266 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2267 2268 return apa || apa3 || api; 2269 } 2270 2271 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2272 int __unused) 2273 { 2274 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2275 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2276 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2277 2278 return gpa || gpa3 || gpi; 2279 } 2280 #endif /* CONFIG_ARM64_PTR_AUTH */ 2281 2282 #ifdef CONFIG_ARM64_E0PD 2283 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2284 { 2285 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2286 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2287 } 2288 #endif /* CONFIG_ARM64_E0PD */ 2289 2290 static void cpu_enable_ls64(struct arm64_cpu_capabilities const *cap) 2291 { 2292 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnALS, SCTLR_EL1_EnALS); 2293 } 2294 2295 static void cpu_enable_ls64_v(struct arm64_cpu_capabilities const *cap) 2296 { 2297 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnASR, 0); 2298 } 2299 2300 #ifdef CONFIG_ARM64_PSEUDO_NMI 2301 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2302 int scope) 2303 { 2304 /* 2305 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2306 * feature, so will be detected earlier. 2307 */ 2308 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2309 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2310 return false; 2311 2312 return enable_pseudo_nmi; 2313 } 2314 2315 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2316 int scope) 2317 { 2318 /* 2319 * If we're not using priority masking then we won't be poking PMR_EL1, 2320 * and there's no need to relax synchronization of writes to it, and 2321 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2322 * that. 2323 * 2324 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2325 * feature, so will be detected earlier. 2326 */ 2327 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2328 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2329 return false; 2330 2331 /* 2332 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2333 * hint for interrupt distribution, a DSB is not necessary when 2334 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2335 * 2336 * Linux itself doesn't use 1:N distribution, so has no need to 2337 * set PMHE. The only reason to have it set is if EL3 requires it 2338 * (and we can't change it). 2339 */ 2340 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2341 } 2342 #endif 2343 2344 static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, 2345 int scope) 2346 { 2347 static const struct midr_range has_vgic_v3[] = { 2348 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 2349 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 2350 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 2351 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 2352 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 2353 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 2354 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 2355 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 2356 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 2357 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 2358 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 2359 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 2360 {}, 2361 }; 2362 struct arm_smccc_res res = {}; 2363 2364 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); 2365 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); 2366 if (!is_hyp_mode_available()) 2367 return false; 2368 2369 if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) 2370 return true; 2371 2372 if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && 2373 !is_midr_in_range_list(has_vgic_v3)) 2374 return false; 2375 2376 /* 2377 * pKVM prevents late onlining of CPUs. This means that whatever 2378 * state the capability is in after deprivilege cannot be affected 2379 * by a new CPU booting -- this is garanteed to be a CPU we have 2380 * already seen, and the cap is therefore unchanged. 2381 */ 2382 if (system_capabilities_finalized() && is_protected_kvm_enabled()) 2383 return cpus_have_final_cap(ARM64_HAS_ICH_HCR_EL2_TDIR); 2384 2385 if (is_kernel_in_hyp_mode()) 2386 res.a1 = read_sysreg_s(SYS_ICH_VTR_EL2); 2387 else 2388 arm_smccc_1_1_hvc(HVC_GET_ICH_VTR_EL2, &res); 2389 2390 if (res.a0 == HVC_STUB_ERR) 2391 return false; 2392 2393 return res.a1 & ICH_VTR_EL2_TDS; 2394 } 2395 2396 #ifdef CONFIG_ARM64_BTI 2397 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2398 { 2399 /* 2400 * Use of X16/X17 for tail-calls and trampolines that jump to 2401 * function entry points using BR is a requirement for 2402 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2403 * So, be strict and forbid other BRs using other registers to 2404 * jump onto a PACIxSP instruction: 2405 */ 2406 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2407 isb(); 2408 } 2409 #endif /* CONFIG_ARM64_BTI */ 2410 2411 #ifdef CONFIG_ARM64_MTE 2412 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2413 { 2414 static bool cleared_zero_page = false; 2415 2416 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2417 2418 mte_cpu_setup(); 2419 2420 /* 2421 * Clear the tags in the zero page. This needs to be done via the 2422 * linear map which has the Tagged attribute. Since this page is 2423 * always mapped as pte_special(), set_pte_at() will not attempt to 2424 * clear the tags or set PG_mte_tagged. 2425 */ 2426 if (!cleared_zero_page) { 2427 cleared_zero_page = true; 2428 mte_clear_page_tags(lm_alias(empty_zero_page)); 2429 } 2430 2431 kasan_init_hw_tags_cpu(); 2432 } 2433 #endif /* CONFIG_ARM64_MTE */ 2434 2435 static void user_feature_fixup(void) 2436 { 2437 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2438 struct arm64_ftr_reg *regp; 2439 2440 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2441 if (regp) 2442 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2443 } 2444 2445 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2446 struct arm64_ftr_reg *regp; 2447 2448 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2449 if (regp) 2450 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2451 } 2452 } 2453 2454 static void elf_hwcap_fixup(void) 2455 { 2456 #ifdef CONFIG_COMPAT 2457 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2458 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2459 #endif /* CONFIG_COMPAT */ 2460 } 2461 2462 #ifdef CONFIG_KVM 2463 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2464 { 2465 return kvm_get_mode() == KVM_MODE_PROTECTED; 2466 } 2467 #endif /* CONFIG_KVM */ 2468 2469 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2470 { 2471 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2472 } 2473 2474 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2475 { 2476 set_pstate_dit(1); 2477 } 2478 2479 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2480 { 2481 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2482 } 2483 2484 #ifdef CONFIG_ARM64_POE 2485 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2486 { 2487 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2488 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2489 } 2490 #endif 2491 2492 #ifdef CONFIG_ARM64_GCS 2493 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2494 { 2495 /* GCSPR_EL0 is always readable */ 2496 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2497 } 2498 #endif 2499 2500 /* Internal helper functions to match cpu capability type */ 2501 static bool 2502 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2503 { 2504 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2505 } 2506 2507 static bool 2508 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2509 { 2510 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2511 } 2512 2513 static bool 2514 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2515 { 2516 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2517 } 2518 2519 static bool 2520 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2521 { 2522 if (!detect_ftr_has_mpam()) 2523 return false; 2524 2525 /* Check firmware actually enabled MPAM on this cpu. */ 2526 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2527 } 2528 2529 static void 2530 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2531 { 2532 int cpu = smp_processor_id(); 2533 u64 regval = 0; 2534 2535 if (IS_ENABLED(CONFIG_ARM64_MPAM) && static_branch_likely(&mpam_enabled)) 2536 regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); 2537 2538 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 2539 if (cpus_have_cap(ARM64_SME)) 2540 write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); 2541 isb(); 2542 2543 /* Synchronising the EL0 write is left until the ERET to EL0 */ 2544 write_sysreg_s(regval, SYS_MPAM0_EL1); 2545 } 2546 2547 static bool 2548 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2549 { 2550 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2551 2552 return idr & MPAMIDR_EL1_HAS_HCR; 2553 } 2554 2555 static bool 2556 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2557 { 2558 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2559 return false; 2560 2561 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2562 } 2563 2564 static const struct arm64_cpu_capabilities arm64_features[] = { 2565 { 2566 .capability = ARM64_ALWAYS_BOOT, 2567 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2568 .matches = has_always, 2569 }, 2570 { 2571 .capability = ARM64_ALWAYS_SYSTEM, 2572 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2573 .matches = has_always, 2574 }, 2575 { 2576 .desc = "GICv3 CPU interface", 2577 .capability = ARM64_HAS_GICV3_CPUIF, 2578 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2579 .matches = has_useable_gicv3_cpuif, 2580 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2581 }, 2582 { 2583 .desc = "Enhanced Counter Virtualization", 2584 .capability = ARM64_HAS_ECV, 2585 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2586 .matches = has_cpuid_feature, 2587 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2588 }, 2589 { 2590 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2591 .capability = ARM64_HAS_ECV_CNTPOFF, 2592 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2593 .matches = has_cpuid_feature, 2594 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2595 }, 2596 { 2597 .desc = "Privileged Access Never", 2598 .capability = ARM64_HAS_PAN, 2599 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2600 .matches = has_cpuid_feature, 2601 .cpu_enable = cpu_enable_pan, 2602 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2603 }, 2604 #ifdef CONFIG_ARM64_EPAN 2605 { 2606 .desc = "Enhanced Privileged Access Never", 2607 .capability = ARM64_HAS_EPAN, 2608 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2609 .matches = has_cpuid_feature, 2610 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2611 }, 2612 #endif /* CONFIG_ARM64_EPAN */ 2613 { 2614 .desc = "LSE atomic instructions", 2615 .capability = ARM64_HAS_LSE_ATOMICS, 2616 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2617 .matches = has_cpuid_feature, 2618 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2619 }, 2620 { 2621 .desc = "Virtualization Host Extensions", 2622 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2623 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2624 .matches = runs_at_el2, 2625 .cpu_enable = cpu_copy_el2regs, 2626 }, 2627 { 2628 .desc = "Nested Virtualization Support", 2629 .capability = ARM64_HAS_NESTED_VIRT, 2630 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2631 .matches = has_nested_virt_support, 2632 .match_list = (const struct arm64_cpu_capabilities []){ 2633 { 2634 .matches = has_cpuid_feature, 2635 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2636 }, 2637 { 2638 .matches = has_cpuid_feature, 2639 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2640 }, 2641 { /* Sentinel */ } 2642 }, 2643 }, 2644 { 2645 .desc = "FEAT_NV2p1", 2646 .capability = ARM64_HAS_NV2P1, 2647 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2648 .matches = has_cpuid_feature, 2649 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2P1) 2650 }, 2651 { 2652 .desc = "FEAT_NV3", 2653 .capability = ARM64_HAS_NV3, 2654 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2655 .matches = has_cpuid_feature, 2656 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV3) 2657 }, 2658 { 2659 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2660 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2661 .matches = has_32bit_el0, 2662 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2663 }, 2664 #ifdef CONFIG_KVM 2665 { 2666 .desc = "32-bit EL1 Support", 2667 .capability = ARM64_HAS_32BIT_EL1, 2668 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2669 .matches = has_cpuid_feature, 2670 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2671 }, 2672 { 2673 .desc = "Protected KVM", 2674 .capability = ARM64_KVM_PROTECTED_MODE, 2675 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2676 .matches = is_kvm_protected_mode, 2677 }, 2678 { 2679 .desc = "HCRX_EL2 register", 2680 .capability = ARM64_HAS_HCX, 2681 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2682 .matches = has_cpuid_feature, 2683 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2684 }, 2685 #endif 2686 { 2687 .desc = "Kernel page table isolation (KPTI)", 2688 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2689 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2690 .cpu_enable = cpu_enable_kpti, 2691 .matches = unmap_kernel_at_el0, 2692 /* 2693 * The ID feature fields below are used to indicate that 2694 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2695 * more details. 2696 */ 2697 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2698 }, 2699 { 2700 .capability = ARM64_HAS_FPSIMD, 2701 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2702 .matches = has_cpuid_feature, 2703 .cpu_enable = cpu_enable_fpsimd, 2704 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2705 }, 2706 #ifdef CONFIG_ARM64_PMEM 2707 { 2708 .desc = "Data cache clean to Point of Persistence", 2709 .capability = ARM64_HAS_DCPOP, 2710 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2711 .matches = has_cpuid_feature, 2712 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2713 }, 2714 { 2715 .desc = "Data cache clean to Point of Deep Persistence", 2716 .capability = ARM64_HAS_DCPODP, 2717 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2718 .matches = has_cpuid_feature, 2719 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2720 }, 2721 #endif 2722 #ifdef CONFIG_ARM64_SVE 2723 { 2724 .desc = "Scalable Vector Extension", 2725 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2726 .capability = ARM64_SVE, 2727 .cpu_enable = cpu_enable_sve, 2728 .matches = has_cpuid_feature, 2729 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2730 }, 2731 #endif /* CONFIG_ARM64_SVE */ 2732 #ifdef CONFIG_ARM64_RAS_EXTN 2733 { 2734 .desc = "RAS Extension Support", 2735 .capability = ARM64_HAS_RAS_EXTN, 2736 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2737 .matches = has_cpuid_feature, 2738 .cpu_enable = cpu_clear_disr, 2739 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2740 }, 2741 { 2742 .desc = "RASv1p1 Extension Support", 2743 .capability = ARM64_HAS_RASV1P1_EXTN, 2744 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2745 .matches = has_rasv1p1, 2746 }, 2747 #endif /* CONFIG_ARM64_RAS_EXTN */ 2748 #ifdef CONFIG_ARM64_AMU_EXTN 2749 { 2750 .desc = "Activity Monitors Unit (AMU)", 2751 .capability = ARM64_HAS_AMU_EXTN, 2752 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2753 .matches = has_amu, 2754 .cpu_enable = cpu_amu_enable, 2755 .cpus = &amu_cpus, 2756 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2757 }, 2758 #endif /* CONFIG_ARM64_AMU_EXTN */ 2759 { 2760 .desc = "Data cache clean to the PoU not required for I/D coherence", 2761 .capability = ARM64_HAS_CACHE_IDC, 2762 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2763 .matches = has_cache_idc, 2764 .cpu_enable = cpu_emulate_effective_ctr, 2765 }, 2766 { 2767 .desc = "Instruction cache invalidation not required for I/D coherence", 2768 .capability = ARM64_HAS_CACHE_DIC, 2769 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2770 .matches = has_cache_dic, 2771 }, 2772 { 2773 .desc = "Stage-2 Force Write-Back", 2774 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2775 .capability = ARM64_HAS_STAGE2_FWB, 2776 .matches = has_cpuid_feature, 2777 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2778 }, 2779 { 2780 .desc = "ARMv8.4 Translation Table Level", 2781 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2782 .capability = ARM64_HAS_ARMv8_4_TTL, 2783 .matches = has_cpuid_feature, 2784 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2785 }, 2786 { 2787 .desc = "TLB range maintenance instructions", 2788 .capability = ARM64_HAS_TLB_RANGE, 2789 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2790 .matches = has_cpuid_feature, 2791 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2792 }, 2793 #ifdef CONFIG_ARM64_HW_AFDBM 2794 { 2795 .desc = "Hardware dirty bit management", 2796 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2797 .capability = ARM64_HW_DBM, 2798 .matches = has_hw_dbm, 2799 .cpu_enable = cpu_enable_hw_dbm, 2800 .cpus = &dbm_cpus, 2801 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2802 }, 2803 #endif 2804 #ifdef CONFIG_ARM64_HAFT 2805 { 2806 .desc = "Hardware managed Access Flag for Table Descriptors", 2807 /* 2808 * Contrary to the page/block access flag, the table access flag 2809 * cannot be emulated in software (no access fault will occur). 2810 * Therefore this should be used only if it's supported system 2811 * wide. 2812 */ 2813 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2814 .capability = ARM64_HAFT, 2815 .matches = has_cpuid_feature, 2816 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2817 }, 2818 #endif 2819 { 2820 .desc = "CRC32 instructions", 2821 .capability = ARM64_HAS_CRC32, 2822 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2823 .matches = has_cpuid_feature, 2824 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2825 }, 2826 { 2827 .desc = "Speculative Store Bypassing Safe (SSBS)", 2828 .capability = ARM64_SSBS, 2829 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2830 .matches = has_cpuid_feature, 2831 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2832 }, 2833 #ifdef CONFIG_ARM64_CNP 2834 { 2835 .desc = "Common not Private translations", 2836 .capability = ARM64_HAS_CNP, 2837 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2838 .matches = has_useable_cnp, 2839 .cpu_enable = cpu_enable_cnp, 2840 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2841 }, 2842 #endif 2843 { 2844 .desc = "Speculation barrier (SB)", 2845 .capability = ARM64_HAS_SB, 2846 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2847 .matches = has_cpuid_feature, 2848 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2849 }, 2850 #ifdef CONFIG_ARM64_PTR_AUTH 2851 { 2852 .desc = "Address authentication (architected QARMA5 algorithm)", 2853 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2854 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2855 .matches = has_address_auth_cpucap, 2856 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2857 }, 2858 { 2859 .desc = "Address authentication (architected QARMA3 algorithm)", 2860 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2861 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2862 .matches = has_address_auth_cpucap, 2863 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2864 }, 2865 { 2866 .desc = "Address authentication (IMP DEF algorithm)", 2867 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2868 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2869 .matches = has_address_auth_cpucap, 2870 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2871 }, 2872 { 2873 .capability = ARM64_HAS_ADDRESS_AUTH, 2874 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2875 .matches = has_address_auth_metacap, 2876 }, 2877 { 2878 .desc = "Generic authentication (architected QARMA5 algorithm)", 2879 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2880 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2881 .matches = has_cpuid_feature, 2882 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2883 }, 2884 { 2885 .desc = "Generic authentication (architected QARMA3 algorithm)", 2886 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2887 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2888 .matches = has_cpuid_feature, 2889 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2890 }, 2891 { 2892 .desc = "Generic authentication (IMP DEF algorithm)", 2893 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2894 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2895 .matches = has_cpuid_feature, 2896 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2897 }, 2898 { 2899 .capability = ARM64_HAS_GENERIC_AUTH, 2900 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2901 .matches = has_generic_auth, 2902 }, 2903 #endif /* CONFIG_ARM64_PTR_AUTH */ 2904 #ifdef CONFIG_ARM64_PSEUDO_NMI 2905 { 2906 /* 2907 * Depends on having GICv3 2908 */ 2909 .desc = "IRQ priority masking", 2910 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2911 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2912 .matches = can_use_gic_priorities, 2913 }, 2914 { 2915 /* 2916 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2917 */ 2918 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2919 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2920 .matches = has_gic_prio_relaxed_sync, 2921 }, 2922 #endif 2923 { 2924 /* 2925 * Depends on having GICv3 2926 */ 2927 .desc = "ICV_DIR_EL1 trapping", 2928 .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, 2929 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2930 .matches = can_trap_icv_dir_el1, 2931 }, 2932 #ifdef CONFIG_ARM64_E0PD 2933 { 2934 .desc = "E0PD", 2935 .capability = ARM64_HAS_E0PD, 2936 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2937 .cpu_enable = cpu_enable_e0pd, 2938 .matches = has_cpuid_feature, 2939 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2940 }, 2941 #endif 2942 { 2943 .desc = "Random Number Generator", 2944 .capability = ARM64_HAS_RNG, 2945 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2946 .matches = has_cpuid_feature, 2947 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2948 }, 2949 #ifdef CONFIG_ARM64_BTI 2950 { 2951 .desc = "Branch Target Identification", 2952 .capability = ARM64_BTI, 2953 #ifdef CONFIG_ARM64_BTI_KERNEL 2954 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2955 #else 2956 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2957 #endif 2958 .matches = has_cpuid_feature, 2959 .cpu_enable = bti_enable, 2960 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2961 }, 2962 #endif 2963 #ifdef CONFIG_ARM64_MTE 2964 { 2965 .desc = "Memory Tagging Extension", 2966 .capability = ARM64_MTE, 2967 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2968 .matches = has_cpuid_feature, 2969 .cpu_enable = cpu_enable_mte, 2970 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2971 }, 2972 { 2973 .desc = "Asymmetric MTE Tag Check Fault", 2974 .capability = ARM64_MTE_ASYMM, 2975 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2976 .matches = has_cpuid_feature, 2977 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2978 }, 2979 { 2980 .desc = "FAR on MTE Tag Check Fault", 2981 .capability = ARM64_MTE_FAR, 2982 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2983 .matches = has_cpuid_feature, 2984 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2985 }, 2986 { 2987 .desc = "Store Only MTE Tag Check", 2988 .capability = ARM64_MTE_STORE_ONLY, 2989 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2990 .matches = has_cpuid_feature, 2991 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2992 }, 2993 #endif /* CONFIG_ARM64_MTE */ 2994 { 2995 .desc = "RCpc load-acquire (LDAPR)", 2996 .capability = ARM64_HAS_LDAPR, 2997 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2998 .matches = has_cpuid_feature, 2999 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 3000 }, 3001 { 3002 .desc = "Fine Grained Traps", 3003 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3004 .capability = ARM64_HAS_FGT, 3005 .matches = has_cpuid_feature, 3006 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 3007 }, 3008 { 3009 .desc = "Fine Grained Traps 2", 3010 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3011 .capability = ARM64_HAS_FGT2, 3012 .matches = has_cpuid_feature, 3013 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 3014 }, 3015 #ifdef CONFIG_ARM64_SME 3016 { 3017 .desc = "Scalable Matrix Extension", 3018 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3019 .capability = ARM64_SME, 3020 .matches = has_cpuid_feature, 3021 .cpu_enable = cpu_enable_sme, 3022 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 3023 }, 3024 /* FA64 should be sorted after the base SME capability */ 3025 { 3026 .desc = "FA64", 3027 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3028 .capability = ARM64_SME_FA64, 3029 .matches = has_cpuid_feature, 3030 .cpu_enable = cpu_enable_fa64, 3031 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 3032 }, 3033 { 3034 .desc = "SME2", 3035 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3036 .capability = ARM64_SME2, 3037 .matches = has_cpuid_feature, 3038 .cpu_enable = cpu_enable_sme2, 3039 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 3040 }, 3041 #endif /* CONFIG_ARM64_SME */ 3042 { 3043 .desc = "WFx with timeout", 3044 .capability = ARM64_HAS_WFXT, 3045 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3046 .matches = has_cpuid_feature, 3047 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 3048 }, 3049 { 3050 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 3051 .capability = ARM64_HAS_TIDCP1, 3052 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3053 .matches = has_cpuid_feature, 3054 .cpu_enable = cpu_trap_el0_impdef, 3055 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 3056 }, 3057 { 3058 .desc = "Data independent timing control (DIT)", 3059 .capability = ARM64_HAS_DIT, 3060 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3061 .matches = has_cpuid_feature, 3062 .cpu_enable = cpu_enable_dit, 3063 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 3064 }, 3065 { 3066 .desc = "Memory Copy and Memory Set instructions", 3067 .capability = ARM64_HAS_MOPS, 3068 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3069 .matches = has_cpuid_feature, 3070 .cpu_enable = cpu_enable_mops, 3071 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 3072 }, 3073 { 3074 .capability = ARM64_HAS_TCR2, 3075 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3076 .matches = has_cpuid_feature, 3077 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3078 }, 3079 { 3080 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3081 .capability = ARM64_HAS_S1PIE, 3082 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3083 .matches = has_cpuid_feature, 3084 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3085 }, 3086 { 3087 .desc = "VHE for hypervisor only", 3088 .capability = ARM64_KVM_HVHE, 3089 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3090 .matches = hvhe_possible, 3091 }, 3092 { 3093 .desc = "Enhanced Virtualization Traps", 3094 .capability = ARM64_HAS_EVT, 3095 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3096 .matches = has_cpuid_feature, 3097 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3098 }, 3099 { 3100 .desc = "BBM Level 3", 3101 .capability = ARM64_HAS_BBML3, 3102 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3103 .matches = has_bbml3, 3104 }, 3105 { 3106 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3107 .capability = ARM64_HAS_LPA2, 3108 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3109 .matches = has_lpa2, 3110 }, 3111 { 3112 .desc = "FPMR", 3113 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3114 .capability = ARM64_HAS_FPMR, 3115 .matches = has_cpuid_feature, 3116 .cpu_enable = cpu_enable_fpmr, 3117 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3118 }, 3119 #ifdef CONFIG_ARM64_VA_BITS_52 3120 { 3121 .capability = ARM64_HAS_VA52, 3122 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3123 .matches = has_cpuid_feature, 3124 #ifdef CONFIG_ARM64_64K_PAGES 3125 .desc = "52-bit Virtual Addressing (LVA)", 3126 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3127 #else 3128 .desc = "52-bit Virtual Addressing (LPA2)", 3129 #ifdef CONFIG_ARM64_4K_PAGES 3130 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3131 #else 3132 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3133 #endif 3134 #endif 3135 }, 3136 #endif 3137 { 3138 .desc = "Memory Partitioning And Monitoring", 3139 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3140 .capability = ARM64_MPAM, 3141 .matches = test_has_mpam, 3142 .cpu_enable = cpu_enable_mpam, 3143 }, 3144 { 3145 .desc = "Memory Partitioning And Monitoring Virtualisation", 3146 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3147 .capability = ARM64_MPAM_HCR, 3148 .matches = test_has_mpam_hcr, 3149 }, 3150 { 3151 .desc = "NV1", 3152 .capability = ARM64_HAS_HCR_NV1, 3153 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3154 .matches = has_nv1, 3155 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3156 }, 3157 #ifdef CONFIG_ARM64_POE 3158 { 3159 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3160 .capability = ARM64_HAS_S1POE, 3161 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3162 .matches = has_cpuid_feature, 3163 .cpu_enable = cpu_enable_poe, 3164 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3165 }, 3166 #endif 3167 #ifdef CONFIG_ARM64_GCS 3168 { 3169 .desc = "Guarded Control Stack (GCS)", 3170 .capability = ARM64_HAS_GCS, 3171 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3172 .cpu_enable = cpu_enable_gcs, 3173 .matches = has_cpuid_feature, 3174 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3175 }, 3176 #endif 3177 #ifdef CONFIG_HW_PERF_EVENTS 3178 { 3179 .desc = "PMUv3", 3180 .capability = ARM64_HAS_PMUV3, 3181 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3182 .matches = has_pmuv3, 3183 }, 3184 #endif 3185 { 3186 .desc = "SCTLR2", 3187 .capability = ARM64_HAS_SCTLR2, 3188 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3189 .matches = has_cpuid_feature, 3190 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3191 }, 3192 { 3193 .desc = "GICv5 CPU interface", 3194 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3195 .capability = ARM64_HAS_GICV5_CPUIF, 3196 .matches = has_cpuid_feature, 3197 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3198 }, 3199 { 3200 .desc = "GICv5 Legacy vCPU interface", 3201 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3202 .capability = ARM64_HAS_GICV5_LEGACY, 3203 .matches = test_has_gicv5_legacy, 3204 }, 3205 { 3206 .desc = "XNX", 3207 .capability = ARM64_HAS_XNX, 3208 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3209 .matches = has_cpuid_feature, 3210 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3211 }, 3212 { 3213 .desc = "LS64", 3214 .capability = ARM64_HAS_LS64, 3215 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3216 .matches = has_cpuid_feature, 3217 .cpu_enable = cpu_enable_ls64, 3218 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64) 3219 }, 3220 { 3221 .desc = "LS64_V", 3222 .capability = ARM64_HAS_LS64_V, 3223 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3224 .matches = has_cpuid_feature, 3225 .cpu_enable = cpu_enable_ls64_v, 3226 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3227 }, 3228 #ifdef CONFIG_ARM64_LSUI 3229 { 3230 .desc = "Unprivileged Load Store Instructions (LSUI)", 3231 .capability = ARM64_HAS_LSUI, 3232 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3233 .matches = has_cpuid_feature, 3234 ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) 3235 }, 3236 #endif 3237 {}, 3238 }; 3239 3240 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3241 .matches = has_user_cpuid_feature, \ 3242 ARM64_CPUID_FIELDS(reg, field, min_value) 3243 3244 #define __HWCAP_CAP(name, cap_type, cap) \ 3245 .desc = name, \ 3246 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3247 .hwcap_type = cap_type, \ 3248 .hwcap = cap, \ 3249 3250 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3251 { \ 3252 __HWCAP_CAP(#cap, cap_type, cap) \ 3253 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3254 } 3255 3256 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3257 { \ 3258 __HWCAP_CAP(#cap, cap_type, cap) \ 3259 .matches = cpucap_multi_entry_cap_matches, \ 3260 .match_list = list, \ 3261 } 3262 3263 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3264 { \ 3265 __HWCAP_CAP(#cap, cap_type, cap) \ 3266 .matches = match, \ 3267 } 3268 3269 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3270 { \ 3271 __HWCAP_CAP(#cap, cap_type, cap) \ 3272 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3273 .matches = match, \ 3274 } 3275 3276 #ifdef CONFIG_ARM64_PTR_AUTH 3277 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3278 { 3279 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3280 }, 3281 { 3282 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3283 }, 3284 { 3285 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3286 }, 3287 {}, 3288 }; 3289 3290 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3291 { 3292 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3293 }, 3294 { 3295 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3296 }, 3297 { 3298 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3299 }, 3300 {}, 3301 }; 3302 #endif 3303 3304 #ifdef CONFIG_ARM64_SVE 3305 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3306 { 3307 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3308 } 3309 #endif 3310 3311 #ifdef CONFIG_ARM64_SME 3312 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3313 { 3314 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3315 } 3316 #endif 3317 3318 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3319 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3320 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3321 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3322 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3323 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3324 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3325 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3326 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3327 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3328 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3329 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3330 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3331 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3332 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3333 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32DOT, CAP_HWCAP, KERNEL_HWCAP_F16F32DOT), 3334 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32MM, CAP_HWCAP, KERNEL_HWCAP_F16F32MM), 3335 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3336 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3337 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3338 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3339 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3340 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3341 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3342 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3343 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3344 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3345 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3346 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3347 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3348 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3349 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3350 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3351 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3352 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3353 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3354 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3355 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3356 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3357 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3358 HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), 3359 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3360 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3361 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3362 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3363 #ifdef CONFIG_ARM64_SVE 3364 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ISAR2_EL1, LUT, LUT6, CAP_HWCAP, KERNEL_HWCAP_SVE_LUT6), 3365 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3366 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p3, CAP_HWCAP, KERNEL_HWCAP_SVE2P3), 3367 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3368 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3369 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3370 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3371 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3372 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3373 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3374 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3375 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3376 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, B16MM, CAP_HWCAP, KERNEL_HWCAP_SVE_B16MM), 3377 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3378 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3379 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3380 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3381 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3382 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3383 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3384 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3385 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3386 #endif 3387 #ifdef CONFIG_ARM64_GCS 3388 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3389 #endif 3390 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3391 #ifdef CONFIG_ARM64_BTI 3392 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3393 #endif 3394 #ifdef CONFIG_ARM64_PTR_AUTH 3395 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3396 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3397 #endif 3398 #ifdef CONFIG_ARM64_MTE 3399 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3400 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3401 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3402 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3403 #endif /* CONFIG_ARM64_MTE */ 3404 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3405 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3406 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3407 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3408 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3409 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3410 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3411 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3412 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3413 #ifdef CONFIG_ARM64_SME 3414 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3415 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3416 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUT6, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUT6), 3417 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3418 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p3, CAP_HWCAP, KERNEL_HWCAP_SME2P3), 3419 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3420 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3421 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3422 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3423 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3424 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3425 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3426 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3427 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3428 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3429 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3430 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3431 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3432 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3433 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3434 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3435 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3436 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3437 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3438 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3439 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3440 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3441 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3442 #endif /* CONFIG_ARM64_SME */ 3443 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3444 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3445 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3446 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3447 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3448 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3449 HWCAP_CAP(ID_AA64FPFR0_EL1, F16MM2, IMP, CAP_HWCAP, KERNEL_HWCAP_F16MM), 3450 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3451 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3452 #ifdef CONFIG_ARM64_POE 3453 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3454 #endif 3455 {}, 3456 }; 3457 3458 #ifdef CONFIG_COMPAT 3459 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3460 { 3461 /* 3462 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3463 * in line with that of arm32 as in vfp_init(). We make sure that the 3464 * check is future proof, by making sure value is non-zero. 3465 */ 3466 u32 mvfr1; 3467 3468 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3469 if (scope == SCOPE_SYSTEM) 3470 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3471 else 3472 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3473 3474 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3475 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3476 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3477 } 3478 #endif 3479 3480 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3481 #ifdef CONFIG_COMPAT 3482 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3483 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3484 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3485 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3486 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3487 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3488 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3489 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3490 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3491 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3492 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3493 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3494 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3495 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3496 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3497 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3498 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3499 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3500 #endif 3501 {}, 3502 }; 3503 3504 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3505 { 3506 switch (cap->hwcap_type) { 3507 case CAP_HWCAP: 3508 cpu_set_feature(cap->hwcap); 3509 break; 3510 #ifdef CONFIG_COMPAT 3511 case CAP_COMPAT_HWCAP: 3512 compat_elf_hwcap |= (u32)cap->hwcap; 3513 break; 3514 case CAP_COMPAT_HWCAP2: 3515 compat_elf_hwcap2 |= (u32)cap->hwcap; 3516 break; 3517 #endif 3518 default: 3519 WARN_ON(1); 3520 break; 3521 } 3522 } 3523 3524 /* Check if we have a particular HWCAP enabled */ 3525 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3526 { 3527 bool rc; 3528 3529 switch (cap->hwcap_type) { 3530 case CAP_HWCAP: 3531 rc = cpu_have_feature(cap->hwcap); 3532 break; 3533 #ifdef CONFIG_COMPAT 3534 case CAP_COMPAT_HWCAP: 3535 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3536 break; 3537 case CAP_COMPAT_HWCAP2: 3538 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3539 break; 3540 #endif 3541 default: 3542 WARN_ON(1); 3543 rc = false; 3544 } 3545 3546 return rc; 3547 } 3548 3549 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3550 { 3551 /* We support emulation of accesses to CPU ID feature registers */ 3552 cpu_set_named_feature(CPUID); 3553 for (; hwcaps->matches; hwcaps++) 3554 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3555 cap_set_elf_hwcap(hwcaps); 3556 } 3557 3558 static void update_cpu_capabilities(u16 scope_mask) 3559 { 3560 int i; 3561 const struct arm64_cpu_capabilities *caps; 3562 3563 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3564 for (i = 0; i < ARM64_NCAPS; i++) { 3565 bool match_all = false; 3566 bool caps_set = false; 3567 bool boot_cpu = false; 3568 3569 caps = cpucap_ptrs[i]; 3570 if (!caps || !(caps->type & scope_mask)) 3571 continue; 3572 3573 match_all = cpucap_match_all_early_cpus(caps); 3574 caps_set = cpus_have_cap(caps->capability); 3575 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3576 3577 /* 3578 * Unless it's a match-all CPUs feature, avoid probing if 3579 * already detected. 3580 */ 3581 if (!match_all && caps_set) 3582 continue; 3583 3584 /* 3585 * A match-all CPUs capability is only set when probing the 3586 * boot CPU. It may be cleared subsequently if not detected on 3587 * secondary ones. 3588 */ 3589 if (match_all && !caps_set && !boot_cpu) 3590 continue; 3591 3592 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3593 if (match_all) 3594 __clear_bit(caps->capability, system_cpucaps); 3595 continue; 3596 } 3597 3598 /* 3599 * Match-all CPUs capabilities are logged later when the 3600 * system capabilities are finalised. 3601 */ 3602 if (!match_all && caps->desc && !caps->cpus) 3603 pr_info("detected: %s\n", caps->desc); 3604 3605 __set_bit(caps->capability, system_cpucaps); 3606 3607 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3608 set_bit(caps->capability, boot_cpucaps); 3609 } 3610 } 3611 3612 /* 3613 * Enable all the available capabilities on this CPU. The capabilities 3614 * with BOOT_CPU scope are handled separately and hence skipped here. 3615 */ 3616 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3617 { 3618 int i; 3619 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3620 3621 for_each_available_cap(i) { 3622 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3623 3624 if (WARN_ON(!cap)) 3625 continue; 3626 3627 if (!(cap->type & non_boot_scope)) 3628 continue; 3629 3630 if (cap->cpu_enable) 3631 cap->cpu_enable(cap); 3632 } 3633 return 0; 3634 } 3635 3636 /* 3637 * Run through the enabled capabilities and enable() it on all active 3638 * CPUs 3639 */ 3640 static void __init enable_cpu_capabilities(u16 scope_mask) 3641 { 3642 int i; 3643 const struct arm64_cpu_capabilities *caps; 3644 bool boot_scope; 3645 3646 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3647 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3648 3649 for (i = 0; i < ARM64_NCAPS; i++) { 3650 caps = cpucap_ptrs[i]; 3651 if (!caps || !(caps->type & scope_mask) || 3652 !cpus_have_cap(caps->capability)) 3653 continue; 3654 3655 if (boot_scope && caps->cpu_enable) 3656 /* 3657 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3658 * before any secondary CPU boots. Thus, each secondary 3659 * will enable the capability as appropriate via 3660 * check_local_cpu_capabilities(). The only exception is 3661 * the boot CPU, for which the capability must be 3662 * enabled here. This approach avoids costly 3663 * stop_machine() calls for this case. 3664 */ 3665 caps->cpu_enable(caps); 3666 } 3667 3668 /* 3669 * For all non-boot scope capabilities, use stop_machine() 3670 * as it schedules the work allowing us to modify PSTATE, 3671 * instead of on_each_cpu() which uses an IPI, giving us a 3672 * PSTATE that disappears when we return. 3673 */ 3674 if (!boot_scope) 3675 stop_machine(cpu_enable_non_boot_scope_capabilities, 3676 NULL, cpu_online_mask); 3677 } 3678 3679 /* 3680 * Run through the list of capabilities to check for conflicts. 3681 * If the system has already detected a capability, take necessary 3682 * action on this CPU. 3683 */ 3684 static void verify_local_cpu_caps(u16 scope_mask) 3685 { 3686 int i; 3687 bool cpu_has_cap, system_has_cap; 3688 const struct arm64_cpu_capabilities *caps; 3689 3690 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3691 3692 for (i = 0; i < ARM64_NCAPS; i++) { 3693 caps = cpucap_ptrs[i]; 3694 if (!caps || !(caps->type & scope_mask)) 3695 continue; 3696 3697 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3698 system_has_cap = cpus_have_cap(caps->capability); 3699 3700 if (system_has_cap) { 3701 /* 3702 * Check if the new CPU misses an advertised feature, 3703 * which is not safe to miss. 3704 */ 3705 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3706 break; 3707 /* 3708 * We have to issue cpu_enable() irrespective of 3709 * whether the CPU has it or not, as it is enabeld 3710 * system wide. It is upto the call back to take 3711 * appropriate action on this CPU. 3712 */ 3713 if (caps->cpu_enable) 3714 caps->cpu_enable(caps); 3715 } else { 3716 /* 3717 * Check if the CPU has this capability if it isn't 3718 * safe to have when the system doesn't. 3719 */ 3720 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3721 break; 3722 } 3723 } 3724 3725 if (i < ARM64_NCAPS) { 3726 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3727 smp_processor_id(), caps->capability, 3728 caps->desc, system_has_cap, cpu_has_cap); 3729 3730 if (cpucap_panic_on_conflict(caps)) 3731 cpu_panic_kernel(); 3732 else 3733 cpu_die_early(); 3734 } 3735 } 3736 3737 /* 3738 * Check for CPU features that are used in early boot 3739 * based on the Boot CPU value. 3740 */ 3741 static void check_early_cpu_features(void) 3742 { 3743 verify_cpu_asid_bits(); 3744 3745 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3746 } 3747 3748 static void 3749 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3750 { 3751 3752 for (; caps->matches; caps++) 3753 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3754 pr_crit("CPU%d: missing HWCAP: %s\n", 3755 smp_processor_id(), caps->desc); 3756 cpu_die_early(); 3757 } 3758 } 3759 3760 static void verify_local_elf_hwcaps(void) 3761 { 3762 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3763 3764 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3765 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3766 } 3767 3768 static void verify_sve_features(void) 3769 { 3770 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3771 3772 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3773 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3774 smp_processor_id()); 3775 cpu_die_early(); 3776 } 3777 3778 cpacr_restore(cpacr); 3779 } 3780 3781 static void verify_sme_features(void) 3782 { 3783 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3784 3785 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3786 pr_crit("CPU%d: SME: vector length support mismatch\n", 3787 smp_processor_id()); 3788 cpu_die_early(); 3789 } 3790 3791 cpacr_restore(cpacr); 3792 } 3793 3794 static void verify_hyp_capabilities(void) 3795 { 3796 u64 safe_mmfr1, mmfr0, mmfr1; 3797 int parange, ipa_max; 3798 unsigned int safe_vmid_bits, vmid_bits; 3799 3800 if (!IS_ENABLED(CONFIG_KVM)) 3801 return; 3802 3803 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3804 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3805 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3806 3807 /* Verify VMID bits */ 3808 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3809 vmid_bits = get_vmid_bits(mmfr1); 3810 if (vmid_bits < safe_vmid_bits) { 3811 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3812 cpu_die_early(); 3813 } 3814 3815 /* Verify IPA range */ 3816 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3817 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3818 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3819 if (ipa_max < get_kvm_ipa_limit()) { 3820 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3821 cpu_die_early(); 3822 } 3823 } 3824 3825 static void verify_mpam_capabilities(void) 3826 { 3827 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3828 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3829 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3830 3831 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3832 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3833 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3834 cpu_die_early(); 3835 } 3836 3837 cpu_idr = read_cpuid(MPAMIDR_EL1); 3838 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3839 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3840 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3841 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3842 cpu_die_early(); 3843 } 3844 3845 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3846 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3847 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3848 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3849 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3850 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3851 cpu_die_early(); 3852 } 3853 } 3854 3855 /* 3856 * Run through the enabled system capabilities and enable() it on this CPU. 3857 * The capabilities were decided based on the available CPUs at the boot time. 3858 * Any new CPU should match the system wide status of the capability. If the 3859 * new CPU doesn't have a capability which the system now has enabled, we 3860 * cannot do anything to fix it up and could cause unexpected failures. So 3861 * we park the CPU. 3862 */ 3863 static void verify_local_cpu_capabilities(void) 3864 { 3865 /* 3866 * The capabilities with SCOPE_BOOT_CPU are checked from 3867 * check_early_cpu_features(), as they need to be verified 3868 * on all secondary CPUs. 3869 */ 3870 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3871 verify_local_elf_hwcaps(); 3872 3873 if (system_supports_sve()) 3874 verify_sve_features(); 3875 3876 if (system_supports_sme()) 3877 verify_sme_features(); 3878 3879 if (is_hyp_mode_available()) 3880 verify_hyp_capabilities(); 3881 3882 if (system_supports_mpam()) 3883 verify_mpam_capabilities(); 3884 } 3885 3886 void check_local_cpu_capabilities(void) 3887 { 3888 /* 3889 * All secondary CPUs should conform to the early CPU features 3890 * in use by the kernel based on boot CPU. 3891 */ 3892 check_early_cpu_features(); 3893 3894 /* 3895 * If we haven't finalised the system capabilities, this CPU gets 3896 * a chance to update the errata work arounds and local features. 3897 * Otherwise, this CPU should verify that it has all the system 3898 * advertised capabilities. 3899 */ 3900 if (!system_capabilities_finalized()) 3901 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3902 else 3903 verify_local_cpu_capabilities(); 3904 } 3905 3906 bool this_cpu_has_cap(unsigned int n) 3907 { 3908 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3909 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3910 3911 if (cap) 3912 return cap->matches(cap, SCOPE_LOCAL_CPU); 3913 } 3914 3915 return false; 3916 } 3917 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3918 3919 /* 3920 * This helper function is used in a narrow window when, 3921 * - The system wide safe registers are set with all the SMP CPUs and, 3922 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3923 */ 3924 static bool __maybe_unused __system_matches_cap(unsigned int n) 3925 { 3926 if (n < ARM64_NCAPS) { 3927 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3928 3929 if (cap) 3930 return cap->matches(cap, SCOPE_SYSTEM); 3931 } 3932 return false; 3933 } 3934 3935 void cpu_set_feature(unsigned int num) 3936 { 3937 set_bit(num, elf_hwcap); 3938 } 3939 3940 bool cpu_have_feature(unsigned int num) 3941 { 3942 return test_bit(num, elf_hwcap); 3943 } 3944 EXPORT_SYMBOL_GPL(cpu_have_feature); 3945 3946 unsigned long cpu_get_elf_hwcap(void) 3947 { 3948 /* 3949 * We currently only populate the first 32 bits of AT_HWCAP. Please 3950 * note that for userspace compatibility we guarantee that bits 62 3951 * and 63 will always be returned as 0. 3952 */ 3953 return elf_hwcap[0]; 3954 } 3955 3956 unsigned long cpu_get_elf_hwcap2(void) 3957 { 3958 return elf_hwcap[1]; 3959 } 3960 3961 unsigned long cpu_get_elf_hwcap3(void) 3962 { 3963 return elf_hwcap[2]; 3964 } 3965 3966 static void __init setup_boot_cpu_capabilities(void) 3967 { 3968 kvm_arm_target_impl_cpu_init(); 3969 /* 3970 * The boot CPU's feature register values have been recorded. Detect 3971 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3972 * patch alternatives for the available boot cpucaps. 3973 */ 3974 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3975 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3976 apply_boot_alternatives(); 3977 } 3978 3979 void __init setup_boot_cpu_features(void) 3980 { 3981 /* 3982 * Initialize the indirect array of CPU capabilities pointers before we 3983 * handle the boot CPU. 3984 */ 3985 init_cpucap_indirect_list(); 3986 3987 /* 3988 * Detect broken pseudo-NMI. Must be called _before_ the call to 3989 * setup_boot_cpu_capabilities() since it interacts with 3990 * can_use_gic_priorities(). 3991 */ 3992 detect_system_supports_pseudo_nmi(); 3993 3994 setup_boot_cpu_capabilities(); 3995 } 3996 3997 static void __init setup_system_capabilities(void) 3998 { 3999 /* 4000 * The system-wide safe feature register values have been finalized. 4001 * Detect, enable, and patch alternatives for the available system 4002 * cpucaps. 4003 */ 4004 update_cpu_capabilities(SCOPE_SYSTEM); 4005 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 4006 apply_alternatives_all(); 4007 4008 for (int i = 0; i < ARM64_NCAPS; i++) { 4009 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 4010 4011 if (!caps || !caps->desc) 4012 continue; 4013 4014 /* 4015 * Log any cpucaps with a cpumask as these aren't logged by 4016 * update_cpu_capabilities(). 4017 */ 4018 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 4019 pr_info("detected: %s on CPU%*pbl\n", 4020 caps->desc, cpumask_pr_args(caps->cpus)); 4021 4022 /* Log match-all CPUs capabilities */ 4023 if (cpucap_match_all_early_cpus(caps) && 4024 cpus_have_cap(caps->capability)) 4025 pr_info("detected: %s\n", caps->desc); 4026 } 4027 4028 /* 4029 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 4030 */ 4031 if (system_uses_ttbr0_pan()) 4032 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 4033 4034 /* 4035 * Report Spectre mitigations status. 4036 */ 4037 spectre_print_disabled_mitigations(); 4038 } 4039 4040 void __init setup_system_features(void) 4041 { 4042 setup_system_capabilities(); 4043 4044 linear_map_maybe_split_to_ptes(); 4045 kpti_install_ng_mappings(); 4046 4047 sve_setup(); 4048 sme_setup(); 4049 4050 /* 4051 * Check for sane CTR_EL0.CWG value. 4052 */ 4053 if (!cache_type_cwg()) 4054 pr_warn("No Cache Writeback Granule information, assuming %d\n", 4055 ARCH_DMA_MINALIGN); 4056 } 4057 4058 void __init setup_user_features(void) 4059 { 4060 user_feature_fixup(); 4061 4062 setup_elf_hwcaps(arm64_elf_hwcaps); 4063 4064 if (system_supports_32bit_el0()) { 4065 setup_elf_hwcaps(compat_elf_hwcaps); 4066 elf_hwcap_fixup(); 4067 } 4068 4069 minsigstksz_setup(); 4070 } 4071 4072 static int enable_mismatched_32bit_el0(unsigned int cpu) 4073 { 4074 /* 4075 * The first 32-bit-capable CPU we detected and so can no longer 4076 * be offlined by userspace. -1 indicates we haven't yet onlined 4077 * a 32-bit-capable CPU. 4078 */ 4079 static int lucky_winner = -1; 4080 4081 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 4082 bool cpu_32bit = false; 4083 4084 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 4085 if (!housekeeping_cpu(cpu, HK_TYPE_DOMAIN)) 4086 pr_info("Treating domain isolated CPU %u as 64-bit only\n", cpu); 4087 else 4088 cpu_32bit = true; 4089 } 4090 4091 if (cpu_32bit) { 4092 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 4093 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 4094 } 4095 4096 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 4097 return 0; 4098 4099 if (lucky_winner >= 0) 4100 return 0; 4101 4102 /* 4103 * We've detected a mismatch. We need to keep one of our CPUs with 4104 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 4105 * every CPU in the system for a 32-bit task. 4106 */ 4107 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 4108 cpu_active_mask); 4109 dev_set_offline_disabled(get_cpu_device(lucky_winner)); 4110 setup_elf_hwcaps(compat_elf_hwcaps); 4111 elf_hwcap_fixup(); 4112 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 4113 cpu, lucky_winner); 4114 return 0; 4115 } 4116 4117 static int __init init_32bit_el0_mask(void) 4118 { 4119 if (!allow_mismatched_32bit_el0) 4120 return 0; 4121 4122 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4123 return -ENOMEM; 4124 4125 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4126 "arm64/mismatched_32bit_el0:online", 4127 enable_mismatched_32bit_el0, NULL); 4128 } 4129 subsys_initcall_sync(init_32bit_el0_mask); 4130 4131 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4132 { 4133 cpu_enable_swapper_cnp(); 4134 } 4135 4136 /* 4137 * We emulate only the following system register space. 4138 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4139 * See Table C5-6 System instruction encodings for System register accesses, 4140 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4141 */ 4142 static inline bool __attribute_const__ is_emulated(u32 id) 4143 { 4144 return (sys_reg_Op0(id) == 0x3 && 4145 sys_reg_CRn(id) == 0x0 && 4146 sys_reg_Op1(id) == 0x0 && 4147 (sys_reg_CRm(id) == 0 || 4148 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4149 } 4150 4151 /* 4152 * With CRm == 0, reg should be one of : 4153 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4154 */ 4155 static inline int emulate_id_reg(u32 id, u64 *valp) 4156 { 4157 switch (id) { 4158 case SYS_MIDR_EL1: 4159 *valp = read_cpuid_id(); 4160 break; 4161 case SYS_MPIDR_EL1: 4162 *valp = SYS_MPIDR_SAFE_VAL; 4163 break; 4164 case SYS_REVIDR_EL1: 4165 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4166 *valp = 0; 4167 break; 4168 default: 4169 return -EINVAL; 4170 } 4171 4172 return 0; 4173 } 4174 4175 static int emulate_sys_reg(u32 id, u64 *valp) 4176 { 4177 struct arm64_ftr_reg *regp; 4178 4179 if (!is_emulated(id)) 4180 return -EINVAL; 4181 4182 if (sys_reg_CRm(id) == 0) 4183 return emulate_id_reg(id, valp); 4184 4185 regp = get_arm64_ftr_reg_nowarn(id); 4186 if (regp) 4187 *valp = arm64_ftr_reg_user_value(regp); 4188 else 4189 /* 4190 * The untracked registers are either IMPLEMENTATION DEFINED 4191 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4192 */ 4193 *valp = 0; 4194 return 0; 4195 } 4196 4197 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4198 { 4199 int rc; 4200 u64 val; 4201 4202 rc = emulate_sys_reg(sys_reg, &val); 4203 if (!rc) { 4204 pt_regs_write_reg(regs, rt, val); 4205 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4206 } 4207 return rc; 4208 } 4209 4210 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4211 { 4212 u32 sys_reg, rt; 4213 4214 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4215 return false; 4216 4217 /* 4218 * sys_reg values are defined as used in mrs/msr instruction. 4219 * shift the imm value to get the encoding. 4220 */ 4221 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4222 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4223 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4224 } 4225 4226 enum mitigation_state arm64_get_meltdown_state(void) 4227 { 4228 if (__meltdown_safe) 4229 return SPECTRE_UNAFFECTED; 4230 4231 if (arm64_kernel_unmapped_at_el0()) 4232 return SPECTRE_MITIGATED; 4233 4234 return SPECTRE_VULNERABLE; 4235 } 4236 4237 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4238 char *buf) 4239 { 4240 switch (arm64_get_meltdown_state()) { 4241 case SPECTRE_UNAFFECTED: 4242 return sprintf(buf, "Not affected\n"); 4243 4244 case SPECTRE_MITIGATED: 4245 return sprintf(buf, "Mitigation: PTI\n"); 4246 4247 default: 4248 return sprintf(buf, "Vulnerable\n"); 4249 } 4250 } 4251