1 /* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #include <linux/backlight.h> 24 #include <linux/delay.h> 25 #include <linux/dynamic_debug.h> 26 #include <linux/errno.h> 27 #include <linux/i2c.h> 28 #include <linux/init.h> 29 #include <linux/iopoll.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/sched.h> 33 #include <linux/seq_file.h> 34 #include <linux/string_helpers.h> 35 36 #include <drm/display/drm_dp_helper.h> 37 #include <drm/display/drm_dp_mst_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_fixed.h> 40 #include <drm/drm_print.h> 41 #include <drm/drm_vblank.h> 42 #include <drm/drm_panel.h> 43 44 #include "drm_dp_helper_internal.h" 45 46 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 47 "DRM_UT_CORE", 48 "DRM_UT_DRIVER", 49 "DRM_UT_KMS", 50 "DRM_UT_PRIME", 51 "DRM_UT_ATOMIC", 52 "DRM_UT_VBL", 53 "DRM_UT_STATE", 54 "DRM_UT_LEASE", 55 "DRM_UT_DP", 56 "DRM_UT_DRMRES"); 57 58 struct dp_aux_backlight { 59 struct backlight_device *base; 60 struct drm_dp_aux *aux; 61 struct drm_edp_backlight_info info; 62 bool enabled; 63 }; 64 65 /** 66 * DOC: dp helpers 67 * 68 * These functions contain some common logic and helpers at various abstraction 69 * levels to deal with Display Port sink devices and related things like DP aux 70 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 71 * blocks, ... 72 */ 73 74 /* Helpers for DP link training */ 75 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 76 { 77 return link_status[r - DP_LANE0_1_STATUS]; 78 } 79 80 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 81 int lane) 82 { 83 int i = DP_LANE0_1_STATUS + (lane >> 1); 84 int s = (lane & 1) * 4; 85 u8 l = dp_link_status(link_status, i); 86 87 return (l >> s) & 0xf; 88 } 89 90 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 91 int lane_count) 92 { 93 u8 lane_align; 94 u8 lane_status; 95 int lane; 96 97 lane_align = dp_link_status(link_status, 98 DP_LANE_ALIGN_STATUS_UPDATED); 99 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 100 return false; 101 for (lane = 0; lane < lane_count; lane++) { 102 lane_status = dp_get_lane_status(link_status, lane); 103 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 104 return false; 105 } 106 return true; 107 } 108 EXPORT_SYMBOL(drm_dp_channel_eq_ok); 109 110 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 111 int lane_count) 112 { 113 int lane; 114 u8 lane_status; 115 116 for (lane = 0; lane < lane_count; lane++) { 117 lane_status = dp_get_lane_status(link_status, lane); 118 if ((lane_status & DP_LANE_CR_DONE) == 0) 119 return false; 120 } 121 return true; 122 } 123 EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 124 125 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 126 int lane) 127 { 128 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 129 int s = ((lane & 1) ? 130 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 131 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 132 u8 l = dp_link_status(link_status, i); 133 134 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 135 } 136 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 137 138 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 139 int lane) 140 { 141 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 142 int s = ((lane & 1) ? 143 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 144 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 145 u8 l = dp_link_status(link_status, i); 146 147 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 148 } 149 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 150 151 /* DP 2.0 128b/132b */ 152 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 153 int lane) 154 { 155 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 156 int s = ((lane & 1) ? 157 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : 158 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); 159 u8 l = dp_link_status(link_status, i); 160 161 return (l >> s) & 0xf; 162 } 163 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); 164 165 /* DP 2.0 errata for 128b/132b */ 166 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 167 int lane_count) 168 { 169 u8 lane_align, lane_status; 170 int lane; 171 172 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 173 if (!(lane_align & DP_INTERLANE_ALIGN_DONE)) 174 return false; 175 176 for (lane = 0; lane < lane_count; lane++) { 177 lane_status = dp_get_lane_status(link_status, lane); 178 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE)) 179 return false; 180 } 181 return true; 182 } 183 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done); 184 185 /* DP 2.0 errata for 128b/132b */ 186 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 187 int lane_count) 188 { 189 u8 lane_status; 190 int lane; 191 192 for (lane = 0; lane < lane_count; lane++) { 193 lane_status = dp_get_lane_status(link_status, lane); 194 if (!(lane_status & DP_LANE_SYMBOL_LOCKED)) 195 return false; 196 } 197 return true; 198 } 199 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked); 200 201 /* DP 2.0 errata for 128b/132b */ 202 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 203 { 204 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 205 206 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE; 207 } 208 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done); 209 210 /* DP 2.0 errata for 128b/132b */ 211 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 212 { 213 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 214 215 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE; 216 } 217 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done); 218 219 /* DP 2.0 errata for 128b/132b */ 220 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]) 221 { 222 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 223 224 return status & DP_128B132B_LT_FAILED; 225 } 226 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed); 227 228 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 229 { 230 if (rd_interval > 4) 231 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 232 aux->name, rd_interval); 233 234 if (rd_interval == 0) 235 return 100; 236 237 return rd_interval * 4 * USEC_PER_MSEC; 238 } 239 240 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 241 { 242 if (rd_interval > 4) 243 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 244 aux->name, rd_interval); 245 246 if (rd_interval == 0) 247 return 400; 248 249 return rd_interval * 4 * USEC_PER_MSEC; 250 } 251 252 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 253 { 254 switch (rd_interval) { 255 default: 256 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", 257 aux->name, rd_interval); 258 fallthrough; 259 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US: 260 return 400; 261 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS: 262 return 4000; 263 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS: 264 return 8000; 265 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS: 266 return 12000; 267 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS: 268 return 16000; 269 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS: 270 return 32000; 271 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS: 272 return 64000; 273 } 274 } 275 276 /* 277 * The link training delays are different for: 278 * 279 * - Clock recovery vs. channel equalization 280 * - DPRX vs. LTTPR 281 * - 128b/132b vs. 8b/10b 282 * - DPCD rev 1.3 vs. later 283 * 284 * Get the correct delay in us, reading DPCD if necessary. 285 */ 286 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 287 enum drm_dp_phy dp_phy, bool uhbr, bool cr) 288 { 289 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval); 290 unsigned int offset; 291 u8 rd_interval, mask; 292 293 if (dp_phy == DP_PHY_DPRX) { 294 if (uhbr) { 295 if (cr) 296 return 100; 297 298 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL; 299 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 300 parse = __128b132b_channel_eq_delay_us; 301 } else { 302 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 303 return 100; 304 305 offset = DP_TRAINING_AUX_RD_INTERVAL; 306 mask = DP_TRAINING_AUX_RD_MASK; 307 if (cr) 308 parse = __8b10b_clock_recovery_delay_us; 309 else 310 parse = __8b10b_channel_eq_delay_us; 311 } 312 } else { 313 if (uhbr) { 314 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 315 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 316 parse = __128b132b_channel_eq_delay_us; 317 } else { 318 if (cr) 319 return 100; 320 321 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 322 mask = DP_TRAINING_AUX_RD_MASK; 323 parse = __8b10b_channel_eq_delay_us; 324 } 325 } 326 327 if (offset < DP_RECEIVER_CAP_SIZE) { 328 rd_interval = dpcd[offset]; 329 } else { 330 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) { 331 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", 332 aux->name); 333 /* arbitrary default delay */ 334 return 400; 335 } 336 } 337 338 return parse(aux, rd_interval & mask); 339 } 340 341 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 342 enum drm_dp_phy dp_phy, bool uhbr) 343 { 344 return __read_delay(aux, dpcd, dp_phy, uhbr, true); 345 } 346 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay); 347 348 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 349 enum drm_dp_phy dp_phy, bool uhbr) 350 { 351 return __read_delay(aux, dpcd, dp_phy, uhbr, false); 352 } 353 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); 354 355 /* Per DP 2.0 Errata */ 356 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) 357 { 358 int unit; 359 u8 val; 360 361 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { 362 drm_err(aux->drm_dev, "%s: failed rd interval read\n", 363 aux->name); 364 /* default to max */ 365 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 366 } 367 368 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2; 369 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 370 371 return (val + 1) * unit * 1000; 372 } 373 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval); 374 375 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 376 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 377 { 378 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 379 DP_TRAINING_AUX_RD_MASK; 380 int delay_us; 381 382 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 383 delay_us = 100; 384 else 385 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); 386 387 usleep_range(delay_us, delay_us * 2); 388 } 389 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 390 391 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 392 u8 rd_interval) 393 { 394 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); 395 396 usleep_range(delay_us, delay_us * 2); 397 } 398 399 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 400 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 401 { 402 __drm_dp_link_train_channel_eq_delay(aux, 403 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 404 DP_TRAINING_AUX_RD_MASK); 405 } 406 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 407 408 /** 409 * drm_dp_phy_name() - Get the name of the given DP PHY 410 * @dp_phy: The DP PHY identifier 411 * 412 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or 413 * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always 414 * non-NULL and valid. 415 * 416 * Returns: Name of the DP PHY. 417 */ 418 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy) 419 { 420 static const char * const phy_names[] = { 421 [DP_PHY_DPRX] = "DPRX", 422 [DP_PHY_LTTPR1] = "LTTPR 1", 423 [DP_PHY_LTTPR2] = "LTTPR 2", 424 [DP_PHY_LTTPR3] = "LTTPR 3", 425 [DP_PHY_LTTPR4] = "LTTPR 4", 426 [DP_PHY_LTTPR5] = "LTTPR 5", 427 [DP_PHY_LTTPR6] = "LTTPR 6", 428 [DP_PHY_LTTPR7] = "LTTPR 7", 429 [DP_PHY_LTTPR8] = "LTTPR 8", 430 }; 431 432 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || 433 WARN_ON(!phy_names[dp_phy])) 434 return "<INVALID DP PHY>"; 435 436 return phy_names[dp_phy]; 437 } 438 EXPORT_SYMBOL(drm_dp_phy_name); 439 440 void drm_dp_lttpr_link_train_clock_recovery_delay(void) 441 { 442 usleep_range(100, 200); 443 } 444 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay); 445 446 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) 447 { 448 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; 449 } 450 451 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 452 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) 453 { 454 u8 interval = dp_lttpr_phy_cap(phy_cap, 455 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & 456 DP_TRAINING_AUX_RD_MASK; 457 458 __drm_dp_link_train_channel_eq_delay(aux, interval); 459 } 460 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); 461 462 /** 463 * drm_dp_lttpr_wake_timeout_setup() - Grant extended time for sink to wake up 464 * @aux: The DP AUX channel to use 465 * @transparent_mode: This is true if lttpr is in transparent mode 466 * 467 * This function checks if the sink needs any extended wake time, if it does 468 * it grants this request. Post this setup the source device can keep trying 469 * the Aux transaction till the granted wake timeout. 470 * If this function is not called all Aux transactions are expected to take 471 * a default of 1ms before they throw an error. 472 */ 473 void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode) 474 { 475 u8 val = 1; 476 int ret; 477 478 if (transparent_mode) { 479 static const u8 timeout_mapping[] = { 480 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_1_MS] = 1, 481 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_20_MS] = 20, 482 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_40_MS] = 40, 483 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_60_MS] = 60, 484 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS] = 80, 485 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS] = 100, 486 }; 487 488 ret = drm_dp_dpcd_readb(aux, DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST, &val); 489 if (ret != 1) { 490 drm_dbg_kms(aux->drm_dev, 491 "Failed to read Extended sleep wake timeout request\n"); 492 return; 493 } 494 495 val = (val < sizeof(timeout_mapping) && timeout_mapping[val]) ? 496 timeout_mapping[val] : 1; 497 498 if (val > 1) 499 drm_dp_dpcd_writeb(aux, 500 DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT, 501 DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_GRANTED); 502 } else { 503 ret = drm_dp_dpcd_readb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &val); 504 if (ret != 1) { 505 drm_dbg_kms(aux->drm_dev, 506 "Failed to read Extended sleep wake timeout request\n"); 507 return; 508 } 509 510 val = (val & DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK) ? 511 (val & DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK) * 10 : 1; 512 513 if (val > 1) 514 drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, 515 DP_EXTENDED_WAKE_TIMEOUT_GRANT); 516 } 517 } 518 EXPORT_SYMBOL(drm_dp_lttpr_wake_timeout_setup); 519 520 u8 drm_dp_link_rate_to_bw_code(int link_rate) 521 { 522 switch (link_rate) { 523 case 1000000: 524 return DP_LINK_BW_10; 525 case 1350000: 526 return DP_LINK_BW_13_5; 527 case 2000000: 528 return DP_LINK_BW_20; 529 default: 530 /* Spec says link_bw = link_rate / 0.27Gbps */ 531 return link_rate / 27000; 532 } 533 } 534 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 535 536 int drm_dp_bw_code_to_link_rate(u8 link_bw) 537 { 538 switch (link_bw) { 539 case DP_LINK_BW_10: 540 return 1000000; 541 case DP_LINK_BW_13_5: 542 return 1350000; 543 case DP_LINK_BW_20: 544 return 2000000; 545 default: 546 /* Spec says link_rate = link_bw * 0.27Gbps */ 547 return link_bw * 27000; 548 } 549 } 550 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 551 552 #define AUX_RETRY_INTERVAL 500 /* us */ 553 554 static inline void 555 drm_dp_dump_access(const struct drm_dp_aux *aux, 556 u8 request, uint offset, void *buffer, int ret) 557 { 558 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; 559 560 if (ret > 0) 561 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", 562 aux->name, offset, arrow, ret, min(ret, 20), buffer); 563 else 564 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", 565 aux->name, offset, arrow, ret); 566 } 567 568 /** 569 * DOC: dp helpers 570 * 571 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 572 * independent access to AUX functionality. Drivers can take advantage of 573 * this by filling in the fields of the drm_dp_aux structure. 574 * 575 * Transactions are described using a hardware-independent drm_dp_aux_msg 576 * structure, which is passed into a driver's .transfer() implementation. 577 * Both native and I2C-over-AUX transactions are supported. 578 */ 579 580 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 581 unsigned int offset, void *buffer, size_t size) 582 { 583 struct drm_dp_aux_msg msg; 584 unsigned int retry, native_reply; 585 int err = 0, ret = 0; 586 587 memset(&msg, 0, sizeof(msg)); 588 msg.address = offset; 589 msg.request = request; 590 msg.buffer = buffer; 591 msg.size = size; 592 593 mutex_lock(&aux->hw_mutex); 594 595 /* 596 * If the device attached to the aux bus is powered down then there's 597 * no reason to attempt a transfer. Error out immediately. 598 */ 599 if (aux->powered_down) { 600 ret = -EBUSY; 601 goto unlock; 602 } 603 604 /* 605 * The specification doesn't give any recommendation on how often to 606 * retry native transactions. We used to retry 7 times like for 607 * aux i2c transactions but real world devices this wasn't 608 * sufficient, bump to 32 which makes Dell 4k monitors happier. 609 */ 610 for (retry = 0; retry < 32; retry++) { 611 if (ret != 0 && ret != -ETIMEDOUT) { 612 usleep_range(AUX_RETRY_INTERVAL, 613 AUX_RETRY_INTERVAL + 100); 614 } 615 616 ret = aux->transfer(aux, &msg); 617 if (ret >= 0) { 618 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 619 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 620 if (ret == size) 621 goto unlock; 622 623 ret = -EPROTO; 624 } else 625 ret = -EIO; 626 } 627 628 /* 629 * We want the error we return to be the error we received on 630 * the first transaction, since we may get a different error the 631 * next time we retry 632 */ 633 if (!err) 634 err = ret; 635 } 636 637 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", 638 aux->name, err); 639 ret = err; 640 641 unlock: 642 mutex_unlock(&aux->hw_mutex); 643 return ret; 644 } 645 646 /** 647 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access 648 * @aux: DisplayPort AUX channel (SST) 649 * @offset: address of the register to probe 650 * 651 * Probe the provided DPCD address by reading 1 byte from it. The function can 652 * be used to trigger some side-effect the read access has, like waking up the 653 * sink, without the need for the read-out value. 654 * 655 * Returns 0 if the read access suceeded, or a negative error code on failure. 656 */ 657 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset) 658 { 659 u8 buffer; 660 int ret; 661 662 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1); 663 WARN_ON(ret == 0); 664 665 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret); 666 667 return ret < 0 ? ret : 0; 668 } 669 EXPORT_SYMBOL(drm_dp_dpcd_probe); 670 671 /** 672 * drm_dp_dpcd_set_powered() - Set whether the DP device is powered 673 * @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here 674 * and the function will be a no-op. 675 * @powered: true if powered; false if not 676 * 677 * If the endpoint device on the DP AUX bus is known to be powered down 678 * then this function can be called to make future transfers fail immediately 679 * instead of needing to time out. 680 * 681 * If this function is never called then a device defaults to being powered. 682 */ 683 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered) 684 { 685 if (!aux) 686 return; 687 688 mutex_lock(&aux->hw_mutex); 689 aux->powered_down = !powered; 690 mutex_unlock(&aux->hw_mutex); 691 } 692 EXPORT_SYMBOL(drm_dp_dpcd_set_powered); 693 694 /** 695 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 696 * @aux: DisplayPort AUX channel (SST or MST) 697 * @offset: address of the (first) register to read 698 * @buffer: buffer to store the register values 699 * @size: number of bytes in @buffer 700 * 701 * Returns the number of bytes transferred on success, or a negative error 702 * code on failure. -EIO is returned if the request was NAKed by the sink or 703 * if the retry count was exceeded. If not all bytes were transferred, this 704 * function returns -EPROTO. Errors from the underlying AUX channel transfer 705 * function, with the exception of -EBUSY (which causes the transaction to 706 * be retried), are propagated to the caller. 707 */ 708 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 709 void *buffer, size_t size) 710 { 711 int ret; 712 713 /* 714 * HP ZR24w corrupts the first DPCD access after entering power save 715 * mode. Eg. on a read, the entire buffer will be filled with the same 716 * byte. Do a throw away read to avoid corrupting anything we care 717 * about. Afterwards things will work correctly until the monitor 718 * gets woken up and subsequently re-enters power save mode. 719 * 720 * The user pressing any button on the monitor is enough to wake it 721 * up, so there is no particularly good place to do the workaround. 722 * We just have to do it before any DPCD access and hope that the 723 * monitor doesn't power down exactly after the throw away read. 724 */ 725 if (!aux->is_remote) { 726 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); 727 if (ret < 0) 728 return ret; 729 } 730 731 if (aux->is_remote) 732 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); 733 else 734 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 735 buffer, size); 736 737 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); 738 return ret; 739 } 740 EXPORT_SYMBOL(drm_dp_dpcd_read); 741 742 /** 743 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 744 * @aux: DisplayPort AUX channel (SST or MST) 745 * @offset: address of the (first) register to write 746 * @buffer: buffer containing the values to write 747 * @size: number of bytes in @buffer 748 * 749 * Returns the number of bytes transferred on success, or a negative error 750 * code on failure. -EIO is returned if the request was NAKed by the sink or 751 * if the retry count was exceeded. If not all bytes were transferred, this 752 * function returns -EPROTO. Errors from the underlying AUX channel transfer 753 * function, with the exception of -EBUSY (which causes the transaction to 754 * be retried), are propagated to the caller. 755 */ 756 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 757 void *buffer, size_t size) 758 { 759 int ret; 760 761 if (aux->is_remote) 762 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); 763 else 764 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 765 buffer, size); 766 767 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); 768 return ret; 769 } 770 EXPORT_SYMBOL(drm_dp_dpcd_write); 771 772 /** 773 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 774 * @aux: DisplayPort AUX channel 775 * @status: buffer to store the link status in (must be at least 6 bytes) 776 * 777 * Returns the number of bytes transferred on success or a negative error 778 * code on failure. 779 */ 780 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 781 u8 status[DP_LINK_STATUS_SIZE]) 782 { 783 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 784 DP_LINK_STATUS_SIZE); 785 } 786 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 787 788 /** 789 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY 790 * @aux: DisplayPort AUX channel 791 * @dp_phy: the DP PHY to get the link status for 792 * @link_status: buffer to return the status in 793 * 794 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The 795 * layout of the returned @link_status matches the DPCD register layout of the 796 * DPRX PHY link status. 797 * 798 * Returns 0 if the information was read successfully or a negative error code 799 * on failure. 800 */ 801 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 802 enum drm_dp_phy dp_phy, 803 u8 link_status[DP_LINK_STATUS_SIZE]) 804 { 805 int ret; 806 807 if (dp_phy == DP_PHY_DPRX) { 808 ret = drm_dp_dpcd_read(aux, 809 DP_LANE0_1_STATUS, 810 link_status, 811 DP_LINK_STATUS_SIZE); 812 813 if (ret < 0) 814 return ret; 815 816 WARN_ON(ret != DP_LINK_STATUS_SIZE); 817 818 return 0; 819 } 820 821 ret = drm_dp_dpcd_read(aux, 822 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), 823 link_status, 824 DP_LINK_STATUS_SIZE - 1); 825 826 if (ret < 0) 827 return ret; 828 829 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); 830 831 /* Convert the LTTPR to the sink PHY link status layout */ 832 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], 833 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], 834 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); 835 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; 836 837 return 0; 838 } 839 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status); 840 841 static int read_payload_update_status(struct drm_dp_aux *aux) 842 { 843 int ret; 844 u8 status; 845 846 ret = drm_dp_dpcd_readb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status); 847 if (ret < 0) 848 return ret; 849 850 return status; 851 } 852 853 /** 854 * drm_dp_dpcd_write_payload() - Write Virtual Channel information to payload table 855 * @aux: DisplayPort AUX channel 856 * @vcpid: Virtual Channel Payload ID 857 * @start_time_slot: Starting time slot 858 * @time_slot_count: Time slot count 859 * 860 * Write the Virtual Channel payload allocation table, checking the payload 861 * update status and retrying as necessary. 862 * 863 * Returns: 864 * 0 on success, negative error otherwise 865 */ 866 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux, 867 int vcpid, u8 start_time_slot, u8 time_slot_count) 868 { 869 u8 payload_alloc[3], status; 870 int ret; 871 int retries = 0; 872 873 drm_dp_dpcd_writeb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, 874 DP_PAYLOAD_TABLE_UPDATED); 875 876 payload_alloc[0] = vcpid; 877 payload_alloc[1] = start_time_slot; 878 payload_alloc[2] = time_slot_count; 879 880 ret = drm_dp_dpcd_write(aux, DP_PAYLOAD_ALLOCATE_SET, payload_alloc, 3); 881 if (ret != 3) { 882 drm_dbg_kms(aux->drm_dev, "failed to write payload allocation %d\n", ret); 883 goto fail; 884 } 885 886 retry: 887 ret = drm_dp_dpcd_readb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status); 888 if (ret < 0) { 889 drm_dbg_kms(aux->drm_dev, "failed to read payload table status %d\n", ret); 890 goto fail; 891 } 892 893 if (!(status & DP_PAYLOAD_TABLE_UPDATED)) { 894 retries++; 895 if (retries < 20) { 896 usleep_range(10000, 20000); 897 goto retry; 898 } 899 drm_dbg_kms(aux->drm_dev, "status not set after read payload table status %d\n", 900 status); 901 ret = -EINVAL; 902 goto fail; 903 } 904 ret = 0; 905 fail: 906 return ret; 907 } 908 EXPORT_SYMBOL(drm_dp_dpcd_write_payload); 909 910 /** 911 * drm_dp_dpcd_clear_payload() - Clear the entire VC Payload ID table 912 * @aux: DisplayPort AUX channel 913 * 914 * Clear the entire VC Payload ID table. 915 * 916 * Returns: 0 on success, negative error code on errors. 917 */ 918 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux) 919 { 920 return drm_dp_dpcd_write_payload(aux, 0, 0, 0x3f); 921 } 922 EXPORT_SYMBOL(drm_dp_dpcd_clear_payload); 923 924 /** 925 * drm_dp_dpcd_poll_act_handled() - Poll for ACT handled status 926 * @aux: DisplayPort AUX channel 927 * @timeout_ms: Timeout in ms 928 * 929 * Try waiting for the sink to finish updating its payload table by polling for 930 * the ACT handled bit of DP_PAYLOAD_TABLE_UPDATE_STATUS for up to @timeout_ms 931 * milliseconds, defaulting to 3000 ms if 0. 932 * 933 * Returns: 934 * 0 if the ACT was handled in time, negative error code on failure. 935 */ 936 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms) 937 { 938 int ret, status; 939 940 /* default to 3 seconds, this is arbitrary */ 941 timeout_ms = timeout_ms ?: 3000; 942 943 ret = readx_poll_timeout(read_payload_update_status, aux, status, 944 status & DP_PAYLOAD_ACT_HANDLED || status < 0, 945 200, timeout_ms * USEC_PER_MSEC); 946 if (ret < 0 && status >= 0) { 947 drm_err(aux->drm_dev, "Failed to get ACT after %d ms, last status: %02x\n", 948 timeout_ms, status); 949 return -EINVAL; 950 } else if (status < 0) { 951 /* 952 * Failure here isn't unexpected - the hub may have 953 * just been unplugged 954 */ 955 drm_dbg_kms(aux->drm_dev, "Failed to read payload table status: %d\n", status); 956 return status; 957 } 958 959 return 0; 960 } 961 EXPORT_SYMBOL(drm_dp_dpcd_poll_act_handled); 962 963 static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid) 964 { 965 /* FIXME: get rid of drm_edid_raw() */ 966 const struct edid *edid = drm_edid_raw(drm_edid); 967 968 return edid && edid->revision >= 4 && 969 edid->input & DRM_EDID_INPUT_DIGITAL && 970 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; 971 } 972 973 /** 974 * drm_dp_downstream_is_type() - is the downstream facing port of certain type? 975 * @dpcd: DisplayPort configuration data 976 * @port_cap: port capabilities 977 * @type: port type to be checked. Can be: 978 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI, 979 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID, 980 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS. 981 * 982 * Caveat: Only works with DPCD 1.1+ port caps. 983 * 984 * Returns: whether the downstream facing port matches the type. 985 */ 986 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 987 const u8 port_cap[4], u8 type) 988 { 989 return drm_dp_is_branch(dpcd) && 990 dpcd[DP_DPCD_REV] >= 0x11 && 991 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; 992 } 993 EXPORT_SYMBOL(drm_dp_downstream_is_type); 994 995 /** 996 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? 997 * @dpcd: DisplayPort configuration data 998 * @port_cap: port capabilities 999 * @drm_edid: EDID 1000 * 1001 * Returns: whether the downstream facing port is TMDS (HDMI/DVI). 1002 */ 1003 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1004 const u8 port_cap[4], 1005 const struct drm_edid *drm_edid) 1006 { 1007 if (dpcd[DP_DPCD_REV] < 0x11) { 1008 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1009 case DP_DWN_STRM_PORT_TYPE_TMDS: 1010 return true; 1011 default: 1012 return false; 1013 } 1014 } 1015 1016 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1017 case DP_DS_PORT_TYPE_DP_DUALMODE: 1018 if (is_edid_digital_input_dp(drm_edid)) 1019 return false; 1020 fallthrough; 1021 case DP_DS_PORT_TYPE_DVI: 1022 case DP_DS_PORT_TYPE_HDMI: 1023 return true; 1024 default: 1025 return false; 1026 } 1027 } 1028 EXPORT_SYMBOL(drm_dp_downstream_is_tmds); 1029 1030 /** 1031 * drm_dp_send_real_edid_checksum() - send back real edid checksum value 1032 * @aux: DisplayPort AUX channel 1033 * @real_edid_checksum: real edid checksum for the last block 1034 * 1035 * Returns: 1036 * True on success 1037 */ 1038 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 1039 u8 real_edid_checksum) 1040 { 1041 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0; 1042 1043 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 1044 &auto_test_req, 1) < 1) { 1045 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 1046 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 1047 return false; 1048 } 1049 auto_test_req &= DP_AUTOMATED_TEST_REQUEST; 1050 1051 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) { 1052 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 1053 aux->name, DP_TEST_REQUEST); 1054 return false; 1055 } 1056 link_edid_read &= DP_TEST_LINK_EDID_READ; 1057 1058 if (!auto_test_req || !link_edid_read) { 1059 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", 1060 aux->name); 1061 return false; 1062 } 1063 1064 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 1065 &auto_test_req, 1) < 1) { 1066 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 1067 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 1068 return false; 1069 } 1070 1071 /* send back checksum for the last edid extension block data */ 1072 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, 1073 &real_edid_checksum, 1) < 1) { 1074 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 1075 aux->name, DP_TEST_EDID_CHECKSUM); 1076 return false; 1077 } 1078 1079 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE; 1080 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { 1081 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 1082 aux->name, DP_TEST_RESPONSE); 1083 return false; 1084 } 1085 1086 return true; 1087 } 1088 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); 1089 1090 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1091 { 1092 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; 1093 1094 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) 1095 port_count = 4; 1096 1097 return port_count; 1098 } 1099 1100 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, 1101 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1102 { 1103 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; 1104 int ret; 1105 1106 /* 1107 * Prior to DP1.3 the bit represented by 1108 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 1109 * If it is set DP_DPCD_REV at 0000h could be at a value less than 1110 * the true capability of the panel. The only way to check is to 1111 * then compare 0000h and 2200h. 1112 */ 1113 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 1114 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 1115 return 0; 1116 1117 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, 1118 sizeof(dpcd_ext)); 1119 if (ret < 0) 1120 return ret; 1121 if (ret != sizeof(dpcd_ext)) 1122 return -EIO; 1123 1124 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 1125 drm_dbg_kms(aux->drm_dev, 1126 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", 1127 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); 1128 return 0; 1129 } 1130 1131 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) 1132 return 0; 1133 1134 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 1135 1136 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); 1137 1138 return 0; 1139 } 1140 1141 /** 1142 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if 1143 * available 1144 * @aux: DisplayPort AUX channel 1145 * @dpcd: Buffer to store the resulting DPCD in 1146 * 1147 * Attempts to read the base DPCD caps for @aux. Additionally, this function 1148 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if 1149 * present. 1150 * 1151 * Returns: %0 if the DPCD was read successfully, negative error code 1152 * otherwise. 1153 */ 1154 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 1155 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1156 { 1157 int ret; 1158 1159 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); 1160 if (ret < 0) 1161 return ret; 1162 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) 1163 return -EIO; 1164 1165 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); 1166 if (ret < 0) 1167 return ret; 1168 1169 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 1170 1171 return ret; 1172 } 1173 EXPORT_SYMBOL(drm_dp_read_dpcd_caps); 1174 1175 /** 1176 * drm_dp_read_downstream_info() - read DPCD downstream port info if available 1177 * @aux: DisplayPort AUX channel 1178 * @dpcd: A cached copy of the port's DPCD 1179 * @downstream_ports: buffer to store the downstream port info in 1180 * 1181 * See also: 1182 * drm_dp_downstream_max_clock() 1183 * drm_dp_downstream_max_bpc() 1184 * 1185 * Returns: 0 if either the downstream port info was read successfully or 1186 * there was no downstream info to read, or a negative error code otherwise. 1187 */ 1188 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 1189 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1190 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) 1191 { 1192 int ret; 1193 u8 len; 1194 1195 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); 1196 1197 /* No downstream info to read */ 1198 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) 1199 return 0; 1200 1201 /* Some branches advertise having 0 downstream ports, despite also advertising they have a 1202 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since 1203 * some branches do it we need to handle it regardless. 1204 */ 1205 len = drm_dp_downstream_port_count(dpcd); 1206 if (!len) 1207 return 0; 1208 1209 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) 1210 len *= 4; 1211 1212 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len); 1213 if (ret < 0) 1214 return ret; 1215 if (ret != len) 1216 return -EIO; 1217 1218 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); 1219 1220 return 0; 1221 } 1222 EXPORT_SYMBOL(drm_dp_read_downstream_info); 1223 1224 /** 1225 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock 1226 * @dpcd: DisplayPort configuration data 1227 * @port_cap: port capabilities 1228 * 1229 * Returns: Downstream facing port max dot clock in kHz on success, 1230 * or 0 if max clock not defined 1231 */ 1232 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1233 const u8 port_cap[4]) 1234 { 1235 if (!drm_dp_is_branch(dpcd)) 1236 return 0; 1237 1238 if (dpcd[DP_DPCD_REV] < 0x11) 1239 return 0; 1240 1241 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1242 case DP_DS_PORT_TYPE_VGA: 1243 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1244 return 0; 1245 return port_cap[1] * 8000; 1246 default: 1247 return 0; 1248 } 1249 } 1250 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock); 1251 1252 /** 1253 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock 1254 * @dpcd: DisplayPort configuration data 1255 * @port_cap: port capabilities 1256 * @drm_edid: EDID 1257 * 1258 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, 1259 * or 0 if max TMDS clock not defined 1260 */ 1261 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1262 const u8 port_cap[4], 1263 const struct drm_edid *drm_edid) 1264 { 1265 if (!drm_dp_is_branch(dpcd)) 1266 return 0; 1267 1268 if (dpcd[DP_DPCD_REV] < 0x11) { 1269 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1270 case DP_DWN_STRM_PORT_TYPE_TMDS: 1271 return 165000; 1272 default: 1273 return 0; 1274 } 1275 } 1276 1277 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1278 case DP_DS_PORT_TYPE_DP_DUALMODE: 1279 if (is_edid_digital_input_dp(drm_edid)) 1280 return 0; 1281 /* 1282 * It's left up to the driver to check the 1283 * DP dual mode adapter's max TMDS clock. 1284 * 1285 * Unfortunately it looks like branch devices 1286 * may not fordward that the DP dual mode i2c 1287 * access so we just usually get i2c nak :( 1288 */ 1289 fallthrough; 1290 case DP_DS_PORT_TYPE_HDMI: 1291 /* 1292 * We should perhaps assume 165 MHz when detailed cap 1293 * info is not available. But looks like many typical 1294 * branch devices fall into that category and so we'd 1295 * probably end up with users complaining that they can't 1296 * get high resolution modes with their favorite dongle. 1297 * 1298 * So let's limit to 300 MHz instead since DPCD 1.4 1299 * HDMI 2.0 DFPs are required to have the detailed cap 1300 * info. So it's more likely we're dealing with a HDMI 1.4 1301 * compatible* device here. 1302 */ 1303 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1304 return 300000; 1305 return port_cap[1] * 2500; 1306 case DP_DS_PORT_TYPE_DVI: 1307 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1308 return 165000; 1309 /* FIXME what to do about DVI dual link? */ 1310 return port_cap[1] * 2500; 1311 default: 1312 return 0; 1313 } 1314 } 1315 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock); 1316 1317 /** 1318 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock 1319 * @dpcd: DisplayPort configuration data 1320 * @port_cap: port capabilities 1321 * @drm_edid: EDID 1322 * 1323 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, 1324 * or 0 if max TMDS clock not defined 1325 */ 1326 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1327 const u8 port_cap[4], 1328 const struct drm_edid *drm_edid) 1329 { 1330 if (!drm_dp_is_branch(dpcd)) 1331 return 0; 1332 1333 if (dpcd[DP_DPCD_REV] < 0x11) { 1334 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1335 case DP_DWN_STRM_PORT_TYPE_TMDS: 1336 return 25000; 1337 default: 1338 return 0; 1339 } 1340 } 1341 1342 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1343 case DP_DS_PORT_TYPE_DP_DUALMODE: 1344 if (is_edid_digital_input_dp(drm_edid)) 1345 return 0; 1346 fallthrough; 1347 case DP_DS_PORT_TYPE_DVI: 1348 case DP_DS_PORT_TYPE_HDMI: 1349 /* 1350 * Unclear whether the protocol converter could 1351 * utilize pixel replication. Assume it won't. 1352 */ 1353 return 25000; 1354 default: 1355 return 0; 1356 } 1357 } 1358 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock); 1359 1360 /** 1361 * drm_dp_downstream_max_bpc() - extract downstream facing port max 1362 * bits per component 1363 * @dpcd: DisplayPort configuration data 1364 * @port_cap: downstream facing port capabilities 1365 * @drm_edid: EDID 1366 * 1367 * Returns: Max bpc on success or 0 if max bpc not defined 1368 */ 1369 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1370 const u8 port_cap[4], 1371 const struct drm_edid *drm_edid) 1372 { 1373 if (!drm_dp_is_branch(dpcd)) 1374 return 0; 1375 1376 if (dpcd[DP_DPCD_REV] < 0x11) { 1377 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1378 case DP_DWN_STRM_PORT_TYPE_DP: 1379 return 0; 1380 default: 1381 return 8; 1382 } 1383 } 1384 1385 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1386 case DP_DS_PORT_TYPE_DP: 1387 return 0; 1388 case DP_DS_PORT_TYPE_DP_DUALMODE: 1389 if (is_edid_digital_input_dp(drm_edid)) 1390 return 0; 1391 fallthrough; 1392 case DP_DS_PORT_TYPE_HDMI: 1393 case DP_DS_PORT_TYPE_DVI: 1394 case DP_DS_PORT_TYPE_VGA: 1395 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1396 return 8; 1397 1398 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) { 1399 case DP_DS_8BPC: 1400 return 8; 1401 case DP_DS_10BPC: 1402 return 10; 1403 case DP_DS_12BPC: 1404 return 12; 1405 case DP_DS_16BPC: 1406 return 16; 1407 default: 1408 return 8; 1409 } 1410 break; 1411 default: 1412 return 8; 1413 } 1414 } 1415 EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 1416 1417 /** 1418 * drm_dp_downstream_420_passthrough() - determine downstream facing port 1419 * YCbCr 4:2:0 pass-through capability 1420 * @dpcd: DisplayPort configuration data 1421 * @port_cap: downstream facing port capabilities 1422 * 1423 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0 1424 */ 1425 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1426 const u8 port_cap[4]) 1427 { 1428 if (!drm_dp_is_branch(dpcd)) 1429 return false; 1430 1431 if (dpcd[DP_DPCD_REV] < 0x13) 1432 return false; 1433 1434 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1435 case DP_DS_PORT_TYPE_DP: 1436 return true; 1437 case DP_DS_PORT_TYPE_HDMI: 1438 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1439 return false; 1440 1441 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH; 1442 default: 1443 return false; 1444 } 1445 } 1446 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough); 1447 1448 /** 1449 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port 1450 * YCbCr 4:4:4->4:2:0 conversion capability 1451 * @dpcd: DisplayPort configuration data 1452 * @port_cap: downstream facing port capabilities 1453 * 1454 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0 1455 */ 1456 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1457 const u8 port_cap[4]) 1458 { 1459 if (!drm_dp_is_branch(dpcd)) 1460 return false; 1461 1462 if (dpcd[DP_DPCD_REV] < 0x13) 1463 return false; 1464 1465 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1466 case DP_DS_PORT_TYPE_HDMI: 1467 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1468 return false; 1469 1470 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV; 1471 default: 1472 return false; 1473 } 1474 } 1475 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion); 1476 1477 /** 1478 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port 1479 * RGB->YCbCr conversion capability 1480 * @dpcd: DisplayPort configuration data 1481 * @port_cap: downstream facing port capabilities 1482 * @color_spc: Colorspace for which conversion cap is sought 1483 * 1484 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given 1485 * colorspace. 1486 */ 1487 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1488 const u8 port_cap[4], 1489 u8 color_spc) 1490 { 1491 if (!drm_dp_is_branch(dpcd)) 1492 return false; 1493 1494 if (dpcd[DP_DPCD_REV] < 0x13) 1495 return false; 1496 1497 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1498 case DP_DS_PORT_TYPE_HDMI: 1499 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1500 return false; 1501 1502 return port_cap[3] & color_spc; 1503 default: 1504 return false; 1505 } 1506 } 1507 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion); 1508 1509 /** 1510 * drm_dp_downstream_mode() - return a mode for downstream facing port 1511 * @dev: DRM device 1512 * @dpcd: DisplayPort configuration data 1513 * @port_cap: port capabilities 1514 * 1515 * Provides a suitable mode for downstream facing ports without EDID. 1516 * 1517 * Returns: A new drm_display_mode on success or NULL on failure 1518 */ 1519 struct drm_display_mode * 1520 drm_dp_downstream_mode(struct drm_device *dev, 1521 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1522 const u8 port_cap[4]) 1523 1524 { 1525 u8 vic; 1526 1527 if (!drm_dp_is_branch(dpcd)) 1528 return NULL; 1529 1530 if (dpcd[DP_DPCD_REV] < 0x11) 1531 return NULL; 1532 1533 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1534 case DP_DS_PORT_TYPE_NON_EDID: 1535 switch (port_cap[0] & DP_DS_NON_EDID_MASK) { 1536 case DP_DS_NON_EDID_720x480i_60: 1537 vic = 6; 1538 break; 1539 case DP_DS_NON_EDID_720x480i_50: 1540 vic = 21; 1541 break; 1542 case DP_DS_NON_EDID_1920x1080i_60: 1543 vic = 5; 1544 break; 1545 case DP_DS_NON_EDID_1920x1080i_50: 1546 vic = 20; 1547 break; 1548 case DP_DS_NON_EDID_1280x720_60: 1549 vic = 4; 1550 break; 1551 case DP_DS_NON_EDID_1280x720_50: 1552 vic = 19; 1553 break; 1554 default: 1555 return NULL; 1556 } 1557 return drm_display_mode_from_cea_vic(dev, vic); 1558 default: 1559 return NULL; 1560 } 1561 } 1562 EXPORT_SYMBOL(drm_dp_downstream_mode); 1563 1564 /** 1565 * drm_dp_downstream_id() - identify branch device 1566 * @aux: DisplayPort AUX channel 1567 * @id: DisplayPort branch device id 1568 * 1569 * Returns branch device id on success or NULL on failure 1570 */ 1571 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 1572 { 1573 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 1574 } 1575 EXPORT_SYMBOL(drm_dp_downstream_id); 1576 1577 /** 1578 * drm_dp_downstream_debug() - debug DP branch devices 1579 * @m: pointer for debugfs file 1580 * @dpcd: DisplayPort configuration data 1581 * @port_cap: port capabilities 1582 * @drm_edid: EDID 1583 * @aux: DisplayPort AUX channel 1584 * 1585 */ 1586 void drm_dp_downstream_debug(struct seq_file *m, 1587 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1588 const u8 port_cap[4], 1589 const struct drm_edid *drm_edid, 1590 struct drm_dp_aux *aux) 1591 { 1592 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1593 DP_DETAILED_CAP_INFO_AVAILABLE; 1594 int clk; 1595 int bpc; 1596 char id[7]; 1597 int len; 1598 uint8_t rev[2]; 1599 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1600 bool branch_device = drm_dp_is_branch(dpcd); 1601 1602 seq_printf(m, "\tDP branch device present: %s\n", 1603 str_yes_no(branch_device)); 1604 1605 if (!branch_device) 1606 return; 1607 1608 switch (type) { 1609 case DP_DS_PORT_TYPE_DP: 1610 seq_puts(m, "\t\tType: DisplayPort\n"); 1611 break; 1612 case DP_DS_PORT_TYPE_VGA: 1613 seq_puts(m, "\t\tType: VGA\n"); 1614 break; 1615 case DP_DS_PORT_TYPE_DVI: 1616 seq_puts(m, "\t\tType: DVI\n"); 1617 break; 1618 case DP_DS_PORT_TYPE_HDMI: 1619 seq_puts(m, "\t\tType: HDMI\n"); 1620 break; 1621 case DP_DS_PORT_TYPE_NON_EDID: 1622 seq_puts(m, "\t\tType: others without EDID support\n"); 1623 break; 1624 case DP_DS_PORT_TYPE_DP_DUALMODE: 1625 seq_puts(m, "\t\tType: DP++\n"); 1626 break; 1627 case DP_DS_PORT_TYPE_WIRELESS: 1628 seq_puts(m, "\t\tType: Wireless\n"); 1629 break; 1630 default: 1631 seq_puts(m, "\t\tType: N/A\n"); 1632 } 1633 1634 memset(id, 0, sizeof(id)); 1635 drm_dp_downstream_id(aux, id); 1636 seq_printf(m, "\t\tID: %s\n", id); 1637 1638 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 1639 if (len > 0) 1640 seq_printf(m, "\t\tHW: %d.%d\n", 1641 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 1642 1643 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); 1644 if (len > 0) 1645 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 1646 1647 if (detailed_cap_info) { 1648 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); 1649 if (clk > 0) 1650 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 1651 1652 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid); 1653 if (clk > 0) 1654 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 1655 1656 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid); 1657 if (clk > 0) 1658 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk); 1659 1660 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid); 1661 1662 if (bpc > 0) 1663 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 1664 } 1665 } 1666 EXPORT_SYMBOL(drm_dp_downstream_debug); 1667 1668 /** 1669 * drm_dp_subconnector_type() - get DP branch device type 1670 * @dpcd: DisplayPort configuration data 1671 * @port_cap: port capabilities 1672 */ 1673 enum drm_mode_subconnector 1674 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1675 const u8 port_cap[4]) 1676 { 1677 int type; 1678 if (!drm_dp_is_branch(dpcd)) 1679 return DRM_MODE_SUBCONNECTOR_Native; 1680 /* DP 1.0 approach */ 1681 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { 1682 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1683 DP_DWN_STRM_PORT_TYPE_MASK; 1684 1685 switch (type) { 1686 case DP_DWN_STRM_PORT_TYPE_TMDS: 1687 /* Can be HDMI or DVI-D, DVI-D is a safer option */ 1688 return DRM_MODE_SUBCONNECTOR_DVID; 1689 case DP_DWN_STRM_PORT_TYPE_ANALOG: 1690 /* Can be VGA or DVI-A, VGA is more popular */ 1691 return DRM_MODE_SUBCONNECTOR_VGA; 1692 case DP_DWN_STRM_PORT_TYPE_DP: 1693 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1694 case DP_DWN_STRM_PORT_TYPE_OTHER: 1695 default: 1696 return DRM_MODE_SUBCONNECTOR_Unknown; 1697 } 1698 } 1699 type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1700 1701 switch (type) { 1702 case DP_DS_PORT_TYPE_DP: 1703 case DP_DS_PORT_TYPE_DP_DUALMODE: 1704 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1705 case DP_DS_PORT_TYPE_VGA: 1706 return DRM_MODE_SUBCONNECTOR_VGA; 1707 case DP_DS_PORT_TYPE_DVI: 1708 return DRM_MODE_SUBCONNECTOR_DVID; 1709 case DP_DS_PORT_TYPE_HDMI: 1710 return DRM_MODE_SUBCONNECTOR_HDMIA; 1711 case DP_DS_PORT_TYPE_WIRELESS: 1712 return DRM_MODE_SUBCONNECTOR_Wireless; 1713 case DP_DS_PORT_TYPE_NON_EDID: 1714 default: 1715 return DRM_MODE_SUBCONNECTOR_Unknown; 1716 } 1717 } 1718 EXPORT_SYMBOL(drm_dp_subconnector_type); 1719 1720 /** 1721 * drm_dp_set_subconnector_property - set subconnector for DP connector 1722 * @connector: connector to set property on 1723 * @status: connector status 1724 * @dpcd: DisplayPort configuration data 1725 * @port_cap: port capabilities 1726 * 1727 * Called by a driver on every detect event. 1728 */ 1729 void drm_dp_set_subconnector_property(struct drm_connector *connector, 1730 enum drm_connector_status status, 1731 const u8 *dpcd, 1732 const u8 port_cap[4]) 1733 { 1734 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 1735 1736 if (status == connector_status_connected) 1737 subconnector = drm_dp_subconnector_type(dpcd, port_cap); 1738 drm_object_property_set_value(&connector->base, 1739 connector->dev->mode_config.dp_subconnector_property, 1740 subconnector); 1741 } 1742 EXPORT_SYMBOL(drm_dp_set_subconnector_property); 1743 1744 /** 1745 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink 1746 * count 1747 * @connector: The DRM connector to check 1748 * @dpcd: A cached copy of the connector's DPCD RX capabilities 1749 * @desc: A cached copy of the connector's DP descriptor 1750 * 1751 * See also: drm_dp_read_sink_count() 1752 * 1753 * Returns: %True if the (e)DP connector has a valid sink count that should 1754 * be probed, %false otherwise. 1755 */ 1756 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 1757 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1758 const struct drm_dp_desc *desc) 1759 { 1760 /* Some eDP panels don't set a valid value for the sink count */ 1761 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && 1762 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && 1763 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && 1764 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT); 1765 } 1766 EXPORT_SYMBOL(drm_dp_read_sink_count_cap); 1767 1768 /** 1769 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink 1770 * @aux: The DP AUX channel to use 1771 * 1772 * See also: drm_dp_read_sink_count_cap() 1773 * 1774 * Returns: The current sink count reported by @aux, or a negative error code 1775 * otherwise. 1776 */ 1777 int drm_dp_read_sink_count(struct drm_dp_aux *aux) 1778 { 1779 u8 count; 1780 int ret; 1781 1782 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count); 1783 if (ret < 0) 1784 return ret; 1785 if (ret != 1) 1786 return -EIO; 1787 1788 return DP_GET_SINK_COUNT(count); 1789 } 1790 EXPORT_SYMBOL(drm_dp_read_sink_count); 1791 1792 /* 1793 * I2C-over-AUX implementation 1794 */ 1795 1796 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 1797 { 1798 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1799 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 1800 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1801 I2C_FUNC_10BIT_ADDR; 1802 } 1803 1804 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 1805 { 1806 /* 1807 * In case of i2c defer or short i2c ack reply to a write, 1808 * we need to switch to WRITE_STATUS_UPDATE to drain the 1809 * rest of the message 1810 */ 1811 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 1812 msg->request &= DP_AUX_I2C_MOT; 1813 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 1814 } 1815 } 1816 1817 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 1818 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 1819 #define AUX_STOP_LEN 4 1820 #define AUX_CMD_LEN 4 1821 #define AUX_ADDRESS_LEN 20 1822 #define AUX_REPLY_PAD_LEN 4 1823 #define AUX_LENGTH_LEN 8 1824 1825 /* 1826 * Calculate the duration of the AUX request/reply in usec. Gives the 1827 * "best" case estimate, ie. successful while as short as possible. 1828 */ 1829 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 1830 { 1831 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1832 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 1833 1834 if ((msg->request & DP_AUX_I2C_READ) == 0) 1835 len += msg->size * 8; 1836 1837 return len; 1838 } 1839 1840 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 1841 { 1842 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1843 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 1844 1845 /* 1846 * For read we expect what was asked. For writes there will 1847 * be 0 or 1 data bytes. Assume 0 for the "best" case. 1848 */ 1849 if (msg->request & DP_AUX_I2C_READ) 1850 len += msg->size * 8; 1851 1852 return len; 1853 } 1854 1855 #define I2C_START_LEN 1 1856 #define I2C_STOP_LEN 1 1857 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 1858 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 1859 1860 /* 1861 * Calculate the length of the i2c transfer in usec, assuming 1862 * the i2c bus speed is as specified. Gives the "worst" 1863 * case estimate, ie. successful while as long as possible. 1864 * Doesn't account the "MOT" bit, and instead assumes each 1865 * message includes a START, ADDRESS and STOP. Neither does it 1866 * account for additional random variables such as clock stretching. 1867 */ 1868 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 1869 int i2c_speed_khz) 1870 { 1871 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 1872 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 1873 msg->size * I2C_DATA_LEN + 1874 I2C_STOP_LEN) * 1000, i2c_speed_khz); 1875 } 1876 1877 /* 1878 * Determine how many retries should be attempted to successfully transfer 1879 * the specified message, based on the estimated durations of the 1880 * i2c and AUX transfers. 1881 */ 1882 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 1883 int i2c_speed_khz) 1884 { 1885 int aux_time_us = drm_dp_aux_req_duration(msg) + 1886 drm_dp_aux_reply_duration(msg); 1887 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 1888 1889 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 1890 } 1891 1892 /* 1893 * FIXME currently assumes 10 kHz as some real world devices seem 1894 * to require it. We should query/set the speed via DPCD if supported. 1895 */ 1896 static int dp_aux_i2c_speed_khz __read_mostly = 10; 1897 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); 1898 MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 1899 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 1900 1901 /* 1902 * Transfer a single I2C-over-AUX message and handle various error conditions, 1903 * retrying the transaction as appropriate. It is assumed that the 1904 * &drm_dp_aux.transfer function does not modify anything in the msg other than the 1905 * reply field. 1906 * 1907 * Returns bytes transferred on success, or a negative error code on failure. 1908 */ 1909 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1910 { 1911 unsigned int retry, defer_i2c; 1912 int ret; 1913 /* 1914 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 1915 * is required to retry at least seven times upon receiving AUX_DEFER 1916 * before giving up the AUX transaction. 1917 * 1918 * We also try to account for the i2c bus speed. 1919 */ 1920 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 1921 1922 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 1923 ret = aux->transfer(aux, msg); 1924 if (ret < 0) { 1925 if (ret == -EBUSY) 1926 continue; 1927 1928 /* 1929 * While timeouts can be errors, they're usually normal 1930 * behavior (for instance, when a driver tries to 1931 * communicate with a non-existent DisplayPort device). 1932 * Avoid spamming the kernel log with timeout errors. 1933 */ 1934 if (ret == -ETIMEDOUT) 1935 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", 1936 aux->name); 1937 else 1938 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", 1939 aux->name, ret); 1940 return ret; 1941 } 1942 1943 1944 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 1945 case DP_AUX_NATIVE_REPLY_ACK: 1946 /* 1947 * For I2C-over-AUX transactions this isn't enough, we 1948 * need to check for the I2C ACK reply. 1949 */ 1950 break; 1951 1952 case DP_AUX_NATIVE_REPLY_NACK: 1953 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", 1954 aux->name, ret, msg->size); 1955 return -EREMOTEIO; 1956 1957 case DP_AUX_NATIVE_REPLY_DEFER: 1958 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); 1959 /* 1960 * We could check for I2C bit rate capabilities and if 1961 * available adjust this interval. We could also be 1962 * more careful with DP-to-legacy adapters where a 1963 * long legacy cable may force very low I2C bit rates. 1964 * 1965 * For now just defer for long enough to hopefully be 1966 * safe for all use-cases. 1967 */ 1968 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1969 continue; 1970 1971 default: 1972 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", 1973 aux->name, msg->reply); 1974 return -EREMOTEIO; 1975 } 1976 1977 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 1978 case DP_AUX_I2C_REPLY_ACK: 1979 /* 1980 * Both native ACK and I2C ACK replies received. We 1981 * can assume the transfer was successful. 1982 */ 1983 if (ret != msg->size) 1984 drm_dp_i2c_msg_write_status_update(msg); 1985 return ret; 1986 1987 case DP_AUX_I2C_REPLY_NACK: 1988 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", 1989 aux->name, ret, msg->size); 1990 aux->i2c_nack_count++; 1991 return -EREMOTEIO; 1992 1993 case DP_AUX_I2C_REPLY_DEFER: 1994 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); 1995 /* DP Compliance Test 4.2.2.5 Requirement: 1996 * Must have at least 7 retries for I2C defers on the 1997 * transaction to pass this test 1998 */ 1999 aux->i2c_defer_count++; 2000 if (defer_i2c < 7) 2001 defer_i2c++; 2002 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 2003 drm_dp_i2c_msg_write_status_update(msg); 2004 2005 continue; 2006 2007 default: 2008 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", 2009 aux->name, msg->reply); 2010 return -EREMOTEIO; 2011 } 2012 } 2013 2014 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); 2015 return -EREMOTEIO; 2016 } 2017 2018 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 2019 const struct i2c_msg *i2c_msg) 2020 { 2021 msg->request = (i2c_msg->flags & I2C_M_RD) ? 2022 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 2023 if (!(i2c_msg->flags & I2C_M_STOP)) 2024 msg->request |= DP_AUX_I2C_MOT; 2025 } 2026 2027 /* 2028 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 2029 * 2030 * Returns an error code on failure, or a recommended transfer size on success. 2031 */ 2032 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 2033 { 2034 int err, ret = orig_msg->size; 2035 struct drm_dp_aux_msg msg = *orig_msg; 2036 2037 while (msg.size > 0) { 2038 err = drm_dp_i2c_do_msg(aux, &msg); 2039 if (err <= 0) 2040 return err == 0 ? -EPROTO : err; 2041 2042 if (err < msg.size && err < ret) { 2043 drm_dbg_kms(aux->drm_dev, 2044 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n", 2045 aux->name, msg.size, err); 2046 ret = err; 2047 } 2048 2049 msg.size -= err; 2050 msg.buffer += err; 2051 } 2052 2053 return ret; 2054 } 2055 2056 /* 2057 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 2058 * packets to be as large as possible. If not, the I2C transactions never 2059 * succeed. Hence the default is maximum. 2060 */ 2061 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 2062 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); 2063 MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 2064 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 2065 2066 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 2067 int num) 2068 { 2069 struct drm_dp_aux *aux = adapter->algo_data; 2070 unsigned int i, j; 2071 unsigned transfer_size; 2072 struct drm_dp_aux_msg msg; 2073 int err = 0; 2074 2075 if (aux->powered_down) 2076 return -EBUSY; 2077 2078 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 2079 2080 memset(&msg, 0, sizeof(msg)); 2081 2082 for (i = 0; i < num; i++) { 2083 msg.address = msgs[i].addr; 2084 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 2085 /* Send a bare address packet to start the transaction. 2086 * Zero sized messages specify an address only (bare 2087 * address) transaction. 2088 */ 2089 msg.buffer = NULL; 2090 msg.size = 0; 2091 err = drm_dp_i2c_do_msg(aux, &msg); 2092 2093 /* 2094 * Reset msg.request in case in case it got 2095 * changed into a WRITE_STATUS_UPDATE. 2096 */ 2097 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 2098 2099 if (err < 0) 2100 break; 2101 /* We want each transaction to be as large as possible, but 2102 * we'll go to smaller sizes if the hardware gives us a 2103 * short reply. 2104 */ 2105 transfer_size = dp_aux_i2c_transfer_size; 2106 for (j = 0; j < msgs[i].len; j += msg.size) { 2107 msg.buffer = msgs[i].buf + j; 2108 msg.size = min(transfer_size, msgs[i].len - j); 2109 2110 err = drm_dp_i2c_drain_msg(aux, &msg); 2111 2112 /* 2113 * Reset msg.request in case in case it got 2114 * changed into a WRITE_STATUS_UPDATE. 2115 */ 2116 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 2117 2118 if (err < 0) 2119 break; 2120 transfer_size = err; 2121 } 2122 if (err < 0) 2123 break; 2124 } 2125 if (err >= 0) 2126 err = num; 2127 /* Send a bare address packet to close out the transaction. 2128 * Zero sized messages specify an address only (bare 2129 * address) transaction. 2130 */ 2131 msg.request &= ~DP_AUX_I2C_MOT; 2132 msg.buffer = NULL; 2133 msg.size = 0; 2134 (void)drm_dp_i2c_do_msg(aux, &msg); 2135 2136 return err; 2137 } 2138 2139 static const struct i2c_algorithm drm_dp_i2c_algo = { 2140 .functionality = drm_dp_i2c_functionality, 2141 .master_xfer = drm_dp_i2c_xfer, 2142 }; 2143 2144 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 2145 { 2146 return container_of(i2c, struct drm_dp_aux, ddc); 2147 } 2148 2149 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 2150 { 2151 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 2152 } 2153 2154 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 2155 { 2156 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 2157 } 2158 2159 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 2160 { 2161 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 2162 } 2163 2164 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 2165 .lock_bus = lock_bus, 2166 .trylock_bus = trylock_bus, 2167 .unlock_bus = unlock_bus, 2168 }; 2169 2170 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) 2171 { 2172 u8 buf, count; 2173 int ret; 2174 2175 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2176 if (ret < 0) 2177 return ret; 2178 2179 WARN_ON(!(buf & DP_TEST_SINK_START)); 2180 2181 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); 2182 if (ret < 0) 2183 return ret; 2184 2185 count = buf & DP_TEST_COUNT_MASK; 2186 if (count == aux->crc_count) 2187 return -EAGAIN; /* No CRC yet */ 2188 2189 aux->crc_count = count; 2190 2191 /* 2192 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes 2193 * per component (RGB or CrYCb). 2194 */ 2195 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); 2196 if (ret < 0) 2197 return ret; 2198 2199 return 0; 2200 } 2201 2202 static void drm_dp_aux_crc_work(struct work_struct *work) 2203 { 2204 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, 2205 crc_work); 2206 struct drm_crtc *crtc; 2207 u8 crc_bytes[6]; 2208 uint32_t crcs[3]; 2209 int ret; 2210 2211 if (WARN_ON(!aux->crtc)) 2212 return; 2213 2214 crtc = aux->crtc; 2215 while (crtc->crc.opened) { 2216 drm_crtc_wait_one_vblank(crtc); 2217 if (!crtc->crc.opened) 2218 break; 2219 2220 ret = drm_dp_aux_get_crc(aux, crc_bytes); 2221 if (ret == -EAGAIN) { 2222 usleep_range(1000, 2000); 2223 ret = drm_dp_aux_get_crc(aux, crc_bytes); 2224 } 2225 2226 if (ret == -EAGAIN) { 2227 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", 2228 aux->name, ret); 2229 continue; 2230 } else if (ret) { 2231 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); 2232 continue; 2233 } 2234 2235 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; 2236 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; 2237 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; 2238 drm_crtc_add_crc_entry(crtc, false, 0, crcs); 2239 } 2240 } 2241 2242 /** 2243 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel 2244 * @aux: DisplayPort AUX channel 2245 * 2246 * Used for remote aux channel in general. Merely initialize the crc work 2247 * struct. 2248 */ 2249 void drm_dp_remote_aux_init(struct drm_dp_aux *aux) 2250 { 2251 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2252 } 2253 EXPORT_SYMBOL(drm_dp_remote_aux_init); 2254 2255 /** 2256 * drm_dp_aux_init() - minimally initialise an aux channel 2257 * @aux: DisplayPort AUX channel 2258 * 2259 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with 2260 * the outside world, call drm_dp_aux_init() first. For drivers which are 2261 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a 2262 * &drm_connector), you must still call drm_dp_aux_register() once the connector 2263 * has been registered to allow userspace access to the auxiliary DP channel. 2264 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as 2265 * early as possible so that the &drm_device that corresponds to the AUX adapter 2266 * may be mentioned in debugging output from the DRM DP helpers. 2267 * 2268 * For devices which use a separate platform device for their AUX adapters, this 2269 * may be called as early as required by the driver. 2270 * 2271 */ 2272 void drm_dp_aux_init(struct drm_dp_aux *aux) 2273 { 2274 mutex_init(&aux->hw_mutex); 2275 mutex_init(&aux->cec.lock); 2276 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2277 2278 aux->ddc.algo = &drm_dp_i2c_algo; 2279 aux->ddc.algo_data = aux; 2280 aux->ddc.retries = 3; 2281 2282 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 2283 } 2284 EXPORT_SYMBOL(drm_dp_aux_init); 2285 2286 /** 2287 * drm_dp_aux_register() - initialise and register aux channel 2288 * @aux: DisplayPort AUX channel 2289 * 2290 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This 2291 * should only be called once the parent of @aux, &drm_dp_aux.dev, is 2292 * initialized. For devices which are grandparents of their AUX channels, 2293 * &drm_dp_aux.dev will typically be the &drm_connector &device which 2294 * corresponds to @aux. For these devices, it's advised to call 2295 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to 2296 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister. 2297 * Functions which don't follow this will likely Oops when 2298 * %CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is enabled. 2299 * 2300 * For devices where the AUX channel is a device that exists independently of 2301 * the &drm_device that uses it, such as SoCs and bridge devices, it is 2302 * recommended to call drm_dp_aux_register() after a &drm_device has been 2303 * assigned to &drm_dp_aux.drm_dev, and likewise to call 2304 * drm_dp_aux_unregister() once the &drm_device should no longer be associated 2305 * with the AUX channel (e.g. on bridge detach). 2306 * 2307 * Drivers which need to use the aux channel before either of the two points 2308 * mentioned above need to call drm_dp_aux_init() in order to use the AUX 2309 * channel before registration. 2310 * 2311 * Returns 0 on success or a negative error code on failure. 2312 */ 2313 int drm_dp_aux_register(struct drm_dp_aux *aux) 2314 { 2315 int ret; 2316 2317 WARN_ON_ONCE(!aux->drm_dev); 2318 2319 if (!aux->ddc.algo) 2320 drm_dp_aux_init(aux); 2321 2322 aux->ddc.owner = THIS_MODULE; 2323 aux->ddc.dev.parent = aux->dev; 2324 2325 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 2326 sizeof(aux->ddc.name)); 2327 2328 ret = drm_dp_aux_register_devnode(aux); 2329 if (ret) 2330 return ret; 2331 2332 ret = i2c_add_adapter(&aux->ddc); 2333 if (ret) { 2334 drm_dp_aux_unregister_devnode(aux); 2335 return ret; 2336 } 2337 2338 return 0; 2339 } 2340 EXPORT_SYMBOL(drm_dp_aux_register); 2341 2342 /** 2343 * drm_dp_aux_unregister() - unregister an AUX adapter 2344 * @aux: DisplayPort AUX channel 2345 */ 2346 void drm_dp_aux_unregister(struct drm_dp_aux *aux) 2347 { 2348 drm_dp_aux_unregister_devnode(aux); 2349 i2c_del_adapter(&aux->ddc); 2350 } 2351 EXPORT_SYMBOL(drm_dp_aux_unregister); 2352 2353 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 2354 2355 /** 2356 * drm_dp_psr_setup_time() - PSR setup in time usec 2357 * @psr_cap: PSR capabilities from DPCD 2358 * 2359 * Returns: 2360 * PSR setup time for the panel in microseconds, negative 2361 * error code on failure. 2362 */ 2363 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 2364 { 2365 static const u16 psr_setup_time_us[] = { 2366 PSR_SETUP_TIME(330), 2367 PSR_SETUP_TIME(275), 2368 PSR_SETUP_TIME(220), 2369 PSR_SETUP_TIME(165), 2370 PSR_SETUP_TIME(110), 2371 PSR_SETUP_TIME(55), 2372 PSR_SETUP_TIME(0), 2373 }; 2374 int i; 2375 2376 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 2377 if (i >= ARRAY_SIZE(psr_setup_time_us)) 2378 return -EINVAL; 2379 2380 return psr_setup_time_us[i]; 2381 } 2382 EXPORT_SYMBOL(drm_dp_psr_setup_time); 2383 2384 #undef PSR_SETUP_TIME 2385 2386 /** 2387 * drm_dp_start_crc() - start capture of frame CRCs 2388 * @aux: DisplayPort AUX channel 2389 * @crtc: CRTC displaying the frames whose CRCs are to be captured 2390 * 2391 * Returns 0 on success or a negative error code on failure. 2392 */ 2393 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) 2394 { 2395 u8 buf; 2396 int ret; 2397 2398 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2399 if (ret < 0) 2400 return ret; 2401 2402 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); 2403 if (ret < 0) 2404 return ret; 2405 2406 aux->crc_count = 0; 2407 aux->crtc = crtc; 2408 schedule_work(&aux->crc_work); 2409 2410 return 0; 2411 } 2412 EXPORT_SYMBOL(drm_dp_start_crc); 2413 2414 /** 2415 * drm_dp_stop_crc() - stop capture of frame CRCs 2416 * @aux: DisplayPort AUX channel 2417 * 2418 * Returns 0 on success or a negative error code on failure. 2419 */ 2420 int drm_dp_stop_crc(struct drm_dp_aux *aux) 2421 { 2422 u8 buf; 2423 int ret; 2424 2425 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2426 if (ret < 0) 2427 return ret; 2428 2429 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); 2430 if (ret < 0) 2431 return ret; 2432 2433 flush_work(&aux->crc_work); 2434 aux->crtc = NULL; 2435 2436 return 0; 2437 } 2438 EXPORT_SYMBOL(drm_dp_stop_crc); 2439 2440 struct dpcd_quirk { 2441 u8 oui[3]; 2442 u8 device_id[6]; 2443 bool is_branch; 2444 u32 quirks; 2445 }; 2446 2447 #define OUI(first, second, third) { (first), (second), (third) } 2448 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ 2449 { (first), (second), (third), (fourth), (fifth), (sixth) } 2450 2451 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) 2452 2453 static const struct dpcd_quirk dpcd_quirk_list[] = { 2454 /* Analogix 7737 needs reduced M and N at HBR2 link rates */ 2455 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2456 /* LG LP140WF6-SPM1 eDP panel */ 2457 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2458 /* Apple panels need some additional handling to support PSR */ 2459 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, 2460 /* CH7511 seems to leave SINK_COUNT zeroed */ 2461 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, 2462 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ 2463 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, 2464 /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */ 2465 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, 2466 /* MediaTek panels (at least in U3224KBA) require DSC for modes with a short HBLANK on UHBR links. */ 2467 { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, 2468 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ 2469 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, 2470 }; 2471 2472 #undef OUI 2473 2474 /* 2475 * Get a bit mask of DPCD quirks for the sink/branch device identified by 2476 * ident. The quirk data is shared but it's up to the drivers to act on the 2477 * data. 2478 * 2479 * For now, only the OUI (first three bytes) is used, but this may be extended 2480 * to device identification string and hardware/firmware revisions later. 2481 */ 2482 static u32 2483 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 2484 { 2485 const struct dpcd_quirk *quirk; 2486 u32 quirks = 0; 2487 int i; 2488 u8 any_device[] = DEVICE_ID_ANY; 2489 2490 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { 2491 quirk = &dpcd_quirk_list[i]; 2492 2493 if (quirk->is_branch != is_branch) 2494 continue; 2495 2496 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) 2497 continue; 2498 2499 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && 2500 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) 2501 continue; 2502 2503 quirks |= quirk->quirks; 2504 } 2505 2506 return quirks; 2507 } 2508 2509 #undef DEVICE_ID_ANY 2510 #undef DEVICE_ID 2511 2512 static int drm_dp_read_ident(struct drm_dp_aux *aux, unsigned int offset, 2513 struct drm_dp_dpcd_ident *ident) 2514 { 2515 int ret; 2516 2517 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); 2518 2519 return ret < 0 ? ret : 0; 2520 } 2521 2522 static void drm_dp_dump_desc(struct drm_dp_aux *aux, 2523 const char *device_name, const struct drm_dp_desc *desc) 2524 { 2525 const struct drm_dp_dpcd_ident *ident = &desc->ident; 2526 2527 drm_dbg_kms(aux->drm_dev, 2528 "%s: %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", 2529 aux->name, device_name, 2530 (int)sizeof(ident->oui), ident->oui, 2531 (int)strnlen(ident->device_id, sizeof(ident->device_id)), ident->device_id, 2532 ident->hw_rev >> 4, ident->hw_rev & 0xf, 2533 ident->sw_major_rev, ident->sw_minor_rev, 2534 desc->quirks); 2535 } 2536 2537 /** 2538 * drm_dp_read_desc - read sink/branch descriptor from DPCD 2539 * @aux: DisplayPort AUX channel 2540 * @desc: Device descriptor to fill from DPCD 2541 * @is_branch: true for branch devices, false for sink devices 2542 * 2543 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the 2544 * identification. 2545 * 2546 * Returns 0 on success or a negative error code on failure. 2547 */ 2548 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 2549 bool is_branch) 2550 { 2551 struct drm_dp_dpcd_ident *ident = &desc->ident; 2552 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; 2553 int ret; 2554 2555 ret = drm_dp_read_ident(aux, offset, ident); 2556 if (ret < 0) 2557 return ret; 2558 2559 desc->quirks = drm_dp_get_quirks(ident, is_branch); 2560 2561 drm_dp_dump_desc(aux, is_branch ? "DP branch" : "DP sink", desc); 2562 2563 return 0; 2564 } 2565 EXPORT_SYMBOL(drm_dp_read_desc); 2566 2567 /** 2568 * drm_dp_dump_lttpr_desc - read and dump the DPCD descriptor for an LTTPR PHY 2569 * @aux: DisplayPort AUX channel 2570 * @dp_phy: LTTPR PHY instance 2571 * 2572 * Read the DPCD LTTPR PHY descriptor for @dp_phy and print a debug message 2573 * with its details to dmesg. 2574 * 2575 * Returns 0 on success or a negative error code on failure. 2576 */ 2577 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy) 2578 { 2579 struct drm_dp_desc desc = {}; 2580 int ret; 2581 2582 if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT)) 2583 return -EINVAL; 2584 2585 ret = drm_dp_read_ident(aux, DP_OUI_PHY_REPEATER(dp_phy), &desc.ident); 2586 if (ret < 0) 2587 return ret; 2588 2589 drm_dp_dump_desc(aux, drm_dp_phy_name(dp_phy), &desc); 2590 2591 return 0; 2592 } 2593 EXPORT_SYMBOL(drm_dp_dump_lttpr_desc); 2594 2595 /** 2596 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment 2597 * @dsc_dpcd: DSC capabilities from DPCD 2598 * 2599 * Returns the bpp precision supported by the DP sink. 2600 */ 2601 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2602 { 2603 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; 2604 2605 switch (bpp_increment_dpcd & DP_DSC_BITS_PER_PIXEL_MASK) { 2606 case DP_DSC_BITS_PER_PIXEL_1_16: 2607 return 16; 2608 case DP_DSC_BITS_PER_PIXEL_1_8: 2609 return 8; 2610 case DP_DSC_BITS_PER_PIXEL_1_4: 2611 return 4; 2612 case DP_DSC_BITS_PER_PIXEL_1_2: 2613 return 2; 2614 case DP_DSC_BITS_PER_PIXEL_1_1: 2615 return 1; 2616 } 2617 2618 return 0; 2619 } 2620 EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr); 2621 2622 /** 2623 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 2624 * supported by the DSC sink. 2625 * @dsc_dpcd: DSC capabilities from DPCD 2626 * @is_edp: true if its eDP, false for DP 2627 * 2628 * Read the slice capabilities DPCD register from DSC sink to get 2629 * the maximum slice count supported. This is used to populate 2630 * the DSC parameters in the &struct drm_dsc_config by the driver. 2631 * Driver creates an infoframe using these parameters to populate 2632 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2633 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2634 * 2635 * Returns: 2636 * Maximum slice count supported by DSC sink or 0 its invalid 2637 */ 2638 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2639 bool is_edp) 2640 { 2641 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 2642 2643 if (is_edp) { 2644 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 2645 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2646 return 4; 2647 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2648 return 2; 2649 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2650 return 1; 2651 } else { 2652 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2653 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2654 2655 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2656 return 24; 2657 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2658 return 20; 2659 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2660 return 16; 2661 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2662 return 12; 2663 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2664 return 10; 2665 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2666 return 8; 2667 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2668 return 6; 2669 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2670 return 4; 2671 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2672 return 2; 2673 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2674 return 1; 2675 } 2676 2677 return 0; 2678 } 2679 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 2680 2681 /** 2682 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits 2683 * @dsc_dpcd: DSC capabilities from DPCD 2684 * 2685 * Read the DSC DPCD register to parse the line buffer depth in bits which is 2686 * number of bits of precision within the decoder line buffer supported by 2687 * the DSC sink. This is used to populate the DSC parameters in the 2688 * &struct drm_dsc_config by the driver. 2689 * Driver creates an infoframe using these parameters to populate 2690 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2691 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2692 * 2693 * Returns: 2694 * Line buffer depth supported by DSC panel or 0 its invalid 2695 */ 2696 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2697 { 2698 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; 2699 2700 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { 2701 case DP_DSC_LINE_BUF_BIT_DEPTH_9: 2702 return 9; 2703 case DP_DSC_LINE_BUF_BIT_DEPTH_10: 2704 return 10; 2705 case DP_DSC_LINE_BUF_BIT_DEPTH_11: 2706 return 11; 2707 case DP_DSC_LINE_BUF_BIT_DEPTH_12: 2708 return 12; 2709 case DP_DSC_LINE_BUF_BIT_DEPTH_13: 2710 return 13; 2711 case DP_DSC_LINE_BUF_BIT_DEPTH_14: 2712 return 14; 2713 case DP_DSC_LINE_BUF_BIT_DEPTH_15: 2714 return 15; 2715 case DP_DSC_LINE_BUF_BIT_DEPTH_16: 2716 return 16; 2717 case DP_DSC_LINE_BUF_BIT_DEPTH_8: 2718 return 8; 2719 } 2720 2721 return 0; 2722 } 2723 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); 2724 2725 /** 2726 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component 2727 * values supported by the DSC sink. 2728 * @dsc_dpcd: DSC capabilities from DPCD 2729 * @dsc_bpc: An array to be filled by this helper with supported 2730 * input bpcs. 2731 * 2732 * Read the DSC DPCD from the sink device to parse the supported bits per 2733 * component values. This is used to populate the DSC parameters 2734 * in the &struct drm_dsc_config by the driver. 2735 * Driver creates an infoframe using these parameters to populate 2736 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2737 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2738 * 2739 * Returns: 2740 * Number of input BPC values parsed from the DPCD 2741 */ 2742 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2743 u8 dsc_bpc[3]) 2744 { 2745 int num_bpc = 0; 2746 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; 2747 2748 if (!drm_dp_sink_supports_dsc(dsc_dpcd)) 2749 return 0; 2750 2751 if (color_depth & DP_DSC_12_BPC) 2752 dsc_bpc[num_bpc++] = 12; 2753 if (color_depth & DP_DSC_10_BPC) 2754 dsc_bpc[num_bpc++] = 10; 2755 2756 /* A DP DSC Sink device shall support 8 bpc. */ 2757 dsc_bpc[num_bpc++] = 8; 2758 2759 return num_bpc; 2760 } 2761 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 2762 2763 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, 2764 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, 2765 u8 *buf, int buf_size) 2766 { 2767 /* 2768 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns 2769 * corrupted values when reading from the 0xF0000- range with a block 2770 * size bigger than 1. 2771 */ 2772 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size; 2773 int offset; 2774 int ret; 2775 2776 for (offset = 0; offset < buf_size; offset += block_size) { 2777 ret = drm_dp_dpcd_read(aux, 2778 address + offset, 2779 &buf[offset], block_size); 2780 if (ret < 0) 2781 return ret; 2782 2783 WARN_ON(ret != block_size); 2784 } 2785 2786 return 0; 2787 } 2788 2789 /** 2790 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities 2791 * @aux: DisplayPort AUX channel 2792 * @dpcd: DisplayPort configuration data 2793 * @caps: buffer to return the capability info in 2794 * 2795 * Read capabilities common to all LTTPRs. 2796 * 2797 * Returns 0 on success or a negative error code on failure. 2798 */ 2799 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 2800 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2801 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2802 { 2803 return drm_dp_read_lttpr_regs(aux, dpcd, 2804 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 2805 caps, DP_LTTPR_COMMON_CAP_SIZE); 2806 } 2807 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps); 2808 2809 /** 2810 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY 2811 * @aux: DisplayPort AUX channel 2812 * @dpcd: DisplayPort configuration data 2813 * @dp_phy: LTTPR PHY to read the capabilities for 2814 * @caps: buffer to return the capability info in 2815 * 2816 * Read the capabilities for the given LTTPR PHY. 2817 * 2818 * Returns 0 on success or a negative error code on failure. 2819 */ 2820 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 2821 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2822 enum drm_dp_phy dp_phy, 2823 u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2824 { 2825 return drm_dp_read_lttpr_regs(aux, dpcd, 2826 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), 2827 caps, DP_LTTPR_PHY_CAP_SIZE); 2828 } 2829 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps); 2830 2831 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r) 2832 { 2833 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 2834 } 2835 2836 /** 2837 * drm_dp_lttpr_count - get the number of detected LTTPRs 2838 * @caps: LTTPR common capabilities 2839 * 2840 * Get the number of detected LTTPRs from the LTTPR common capabilities info. 2841 * 2842 * Returns: 2843 * -ERANGE if more than supported number (8) of LTTPRs are detected 2844 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value 2845 * otherwise the number of detected LTTPRs 2846 */ 2847 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2848 { 2849 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT); 2850 2851 switch (hweight8(count)) { 2852 case 0: 2853 return 0; 2854 case 1: 2855 return 8 - ilog2(count); 2856 case 8: 2857 return -ERANGE; 2858 default: 2859 return -EINVAL; 2860 } 2861 } 2862 EXPORT_SYMBOL(drm_dp_lttpr_count); 2863 2864 /** 2865 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs 2866 * @caps: LTTPR common capabilities 2867 * 2868 * Returns the maximum link rate supported by all detected LTTPRs. 2869 */ 2870 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2871 { 2872 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER); 2873 2874 return drm_dp_bw_code_to_link_rate(rate); 2875 } 2876 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); 2877 2878 /** 2879 * drm_dp_lttpr_set_transparent_mode() - set the LTTPR in transparent mode 2880 * @aux: DisplayPort AUX channel 2881 * @enable: Enable or disable transparent mode 2882 * 2883 * Returns: 0 on success or a negative error code on failure. 2884 */ 2885 int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable) 2886 { 2887 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 2888 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 2889 int ret = drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, val); 2890 2891 if (ret < 0) 2892 return ret; 2893 2894 return (ret == 1) ? 0 : -EIO; 2895 } 2896 EXPORT_SYMBOL(drm_dp_lttpr_set_transparent_mode); 2897 2898 /** 2899 * drm_dp_lttpr_init() - init LTTPR transparency mode according to DP standard 2900 * @aux: DisplayPort AUX channel 2901 * @lttpr_count: Number of LTTPRs. Between 0 and 8, according to DP standard. 2902 * Negative error code for any non-valid number. 2903 * See drm_dp_lttpr_count(). 2904 * 2905 * Returns: 0 on success or a negative error code on failure. 2906 */ 2907 int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count) 2908 { 2909 int ret; 2910 2911 if (!lttpr_count) 2912 return 0; 2913 2914 /* 2915 * See DP Standard v2.0 3.6.6.1 about the explicit disabling of 2916 * non-transparent mode and the disable->enable non-transparent mode 2917 * sequence. 2918 */ 2919 ret = drm_dp_lttpr_set_transparent_mode(aux, true); 2920 if (ret) 2921 return ret; 2922 2923 if (lttpr_count < 0) 2924 return -ENODEV; 2925 2926 if (drm_dp_lttpr_set_transparent_mode(aux, false)) { 2927 /* 2928 * Roll-back to transparent mode if setting non-transparent 2929 * mode has failed 2930 */ 2931 drm_dp_lttpr_set_transparent_mode(aux, true); 2932 return -EINVAL; 2933 } 2934 2935 return 0; 2936 } 2937 EXPORT_SYMBOL(drm_dp_lttpr_init); 2938 2939 /** 2940 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs 2941 * @caps: LTTPR common capabilities 2942 * 2943 * Returns the maximum lane count supported by all detected LTTPRs. 2944 */ 2945 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2946 { 2947 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); 2948 2949 return max_lanes & DP_MAX_LANE_COUNT_MASK; 2950 } 2951 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count); 2952 2953 /** 2954 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support 2955 * @caps: LTTPR PHY capabilities 2956 * 2957 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2958 * voltage swing level 3. 2959 */ 2960 bool 2961 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2962 { 2963 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2964 2965 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED; 2966 } 2967 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported); 2968 2969 /** 2970 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support 2971 * @caps: LTTPR PHY capabilities 2972 * 2973 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2974 * pre-emphasis level 3. 2975 */ 2976 bool 2977 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2978 { 2979 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2980 2981 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED; 2982 } 2983 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported); 2984 2985 /** 2986 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. 2987 * @aux: DisplayPort AUX channel 2988 * @data: DP phy compliance test parameters. 2989 * 2990 * Returns 0 on success or a negative error code on failure. 2991 */ 2992 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 2993 struct drm_dp_phy_test_params *data) 2994 { 2995 int err; 2996 u8 rate, lanes; 2997 2998 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate); 2999 if (err < 0) 3000 return err; 3001 data->link_rate = drm_dp_bw_code_to_link_rate(rate); 3002 3003 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); 3004 if (err < 0) 3005 return err; 3006 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; 3007 3008 if (lanes & DP_ENHANCED_FRAME_CAP) 3009 data->enhanced_frame_cap = true; 3010 3011 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); 3012 if (err < 0) 3013 return err; 3014 3015 switch (data->phy_pattern) { 3016 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 3017 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, 3018 &data->custom80, sizeof(data->custom80)); 3019 if (err < 0) 3020 return err; 3021 3022 break; 3023 case DP_PHY_TEST_PATTERN_CP2520: 3024 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, 3025 &data->hbr2_reset, 3026 sizeof(data->hbr2_reset)); 3027 if (err < 0) 3028 return err; 3029 } 3030 3031 return 0; 3032 } 3033 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern); 3034 3035 /** 3036 * drm_dp_set_phy_test_pattern() - set the pattern to the sink. 3037 * @aux: DisplayPort AUX channel 3038 * @data: DP phy compliance test parameters. 3039 * @dp_rev: DP revision to use for compliance testing 3040 * 3041 * Returns 0 on success or a negative error code on failure. 3042 */ 3043 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 3044 struct drm_dp_phy_test_params *data, u8 dp_rev) 3045 { 3046 int err, i; 3047 u8 test_pattern; 3048 3049 test_pattern = data->phy_pattern; 3050 if (dp_rev < 0x12) { 3051 test_pattern = (test_pattern << 2) & 3052 DP_LINK_QUAL_PATTERN_11_MASK; 3053 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, 3054 test_pattern); 3055 if (err < 0) 3056 return err; 3057 } else { 3058 for (i = 0; i < data->num_lanes; i++) { 3059 err = drm_dp_dpcd_writeb(aux, 3060 DP_LINK_QUAL_LANE0_SET + i, 3061 test_pattern); 3062 if (err < 0) 3063 return err; 3064 } 3065 } 3066 3067 return 0; 3068 } 3069 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern); 3070 3071 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat) 3072 { 3073 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 3074 return "Invalid"; 3075 3076 switch (pixelformat) { 3077 case DP_PIXELFORMAT_RGB: 3078 return "RGB"; 3079 case DP_PIXELFORMAT_YUV444: 3080 return "YUV444"; 3081 case DP_PIXELFORMAT_YUV422: 3082 return "YUV422"; 3083 case DP_PIXELFORMAT_YUV420: 3084 return "YUV420"; 3085 case DP_PIXELFORMAT_Y_ONLY: 3086 return "Y_ONLY"; 3087 case DP_PIXELFORMAT_RAW: 3088 return "RAW"; 3089 default: 3090 return "Reserved"; 3091 } 3092 } 3093 3094 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat, 3095 enum dp_colorimetry colorimetry) 3096 { 3097 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 3098 return "Invalid"; 3099 3100 switch (colorimetry) { 3101 case DP_COLORIMETRY_DEFAULT: 3102 switch (pixelformat) { 3103 case DP_PIXELFORMAT_RGB: 3104 return "sRGB"; 3105 case DP_PIXELFORMAT_YUV444: 3106 case DP_PIXELFORMAT_YUV422: 3107 case DP_PIXELFORMAT_YUV420: 3108 return "BT.601"; 3109 case DP_PIXELFORMAT_Y_ONLY: 3110 return "DICOM PS3.14"; 3111 case DP_PIXELFORMAT_RAW: 3112 return "Custom Color Profile"; 3113 default: 3114 return "Reserved"; 3115 } 3116 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */ 3117 switch (pixelformat) { 3118 case DP_PIXELFORMAT_RGB: 3119 return "Wide Fixed"; 3120 case DP_PIXELFORMAT_YUV444: 3121 case DP_PIXELFORMAT_YUV422: 3122 case DP_PIXELFORMAT_YUV420: 3123 return "BT.709"; 3124 default: 3125 return "Reserved"; 3126 } 3127 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */ 3128 switch (pixelformat) { 3129 case DP_PIXELFORMAT_RGB: 3130 return "Wide Float"; 3131 case DP_PIXELFORMAT_YUV444: 3132 case DP_PIXELFORMAT_YUV422: 3133 case DP_PIXELFORMAT_YUV420: 3134 return "xvYCC 601"; 3135 default: 3136 return "Reserved"; 3137 } 3138 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */ 3139 switch (pixelformat) { 3140 case DP_PIXELFORMAT_RGB: 3141 return "OpRGB"; 3142 case DP_PIXELFORMAT_YUV444: 3143 case DP_PIXELFORMAT_YUV422: 3144 case DP_PIXELFORMAT_YUV420: 3145 return "xvYCC 709"; 3146 default: 3147 return "Reserved"; 3148 } 3149 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */ 3150 switch (pixelformat) { 3151 case DP_PIXELFORMAT_RGB: 3152 return "DCI-P3"; 3153 case DP_PIXELFORMAT_YUV444: 3154 case DP_PIXELFORMAT_YUV422: 3155 case DP_PIXELFORMAT_YUV420: 3156 return "sYCC 601"; 3157 default: 3158 return "Reserved"; 3159 } 3160 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */ 3161 switch (pixelformat) { 3162 case DP_PIXELFORMAT_RGB: 3163 return "Custom Profile"; 3164 case DP_PIXELFORMAT_YUV444: 3165 case DP_PIXELFORMAT_YUV422: 3166 case DP_PIXELFORMAT_YUV420: 3167 return "OpYCC 601"; 3168 default: 3169 return "Reserved"; 3170 } 3171 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */ 3172 switch (pixelformat) { 3173 case DP_PIXELFORMAT_RGB: 3174 return "BT.2020 RGB"; 3175 case DP_PIXELFORMAT_YUV444: 3176 case DP_PIXELFORMAT_YUV422: 3177 case DP_PIXELFORMAT_YUV420: 3178 return "BT.2020 CYCC"; 3179 default: 3180 return "Reserved"; 3181 } 3182 case DP_COLORIMETRY_BT2020_YCC: 3183 switch (pixelformat) { 3184 case DP_PIXELFORMAT_YUV444: 3185 case DP_PIXELFORMAT_YUV422: 3186 case DP_PIXELFORMAT_YUV420: 3187 return "BT.2020 YCC"; 3188 default: 3189 return "Reserved"; 3190 } 3191 default: 3192 return "Invalid"; 3193 } 3194 } 3195 3196 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range) 3197 { 3198 switch (dynamic_range) { 3199 case DP_DYNAMIC_RANGE_VESA: 3200 return "VESA range"; 3201 case DP_DYNAMIC_RANGE_CTA: 3202 return "CTA range"; 3203 default: 3204 return "Invalid"; 3205 } 3206 } 3207 3208 static const char *dp_content_type_get_name(enum dp_content_type content_type) 3209 { 3210 switch (content_type) { 3211 case DP_CONTENT_TYPE_NOT_DEFINED: 3212 return "Not defined"; 3213 case DP_CONTENT_TYPE_GRAPHICS: 3214 return "Graphics"; 3215 case DP_CONTENT_TYPE_PHOTO: 3216 return "Photo"; 3217 case DP_CONTENT_TYPE_VIDEO: 3218 return "Video"; 3219 case DP_CONTENT_TYPE_GAME: 3220 return "Game"; 3221 default: 3222 return "Reserved"; 3223 } 3224 } 3225 3226 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc) 3227 { 3228 drm_printf(p, "DP SDP: VSC, revision %u, length %u\n", 3229 vsc->revision, vsc->length); 3230 drm_printf(p, " pixelformat: %s\n", 3231 dp_pixelformat_get_name(vsc->pixelformat)); 3232 drm_printf(p, " colorimetry: %s\n", 3233 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); 3234 drm_printf(p, " bpc: %u\n", vsc->bpc); 3235 drm_printf(p, " dynamic range: %s\n", 3236 dp_dynamic_range_get_name(vsc->dynamic_range)); 3237 drm_printf(p, " content type: %s\n", 3238 dp_content_type_get_name(vsc->content_type)); 3239 } 3240 EXPORT_SYMBOL(drm_dp_vsc_sdp_log); 3241 3242 void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp) 3243 { 3244 drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n", 3245 as_sdp->revision, as_sdp->length); 3246 drm_printf(p, " vtotal: %d\n", as_sdp->vtotal); 3247 drm_printf(p, " target_rr: %d\n", as_sdp->target_rr); 3248 drm_printf(p, " duration_incr_ms: %d\n", as_sdp->duration_incr_ms); 3249 drm_printf(p, " duration_decr_ms: %d\n", as_sdp->duration_decr_ms); 3250 drm_printf(p, " operation_mode: %d\n", as_sdp->mode); 3251 } 3252 EXPORT_SYMBOL(drm_dp_as_sdp_log); 3253 3254 /** 3255 * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported 3256 * @aux: DisplayPort AUX channel 3257 * @dpcd: DisplayPort configuration data 3258 * 3259 * Returns true if adaptive sync sdp is supported, else returns false 3260 */ 3261 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 3262 { 3263 u8 rx_feature; 3264 3265 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13) 3266 return false; 3267 3268 if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1, 3269 &rx_feature) != 1) { 3270 drm_dbg_dp(aux->drm_dev, 3271 "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n"); 3272 return false; 3273 } 3274 3275 return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED); 3276 } 3277 EXPORT_SYMBOL(drm_dp_as_sdp_supported); 3278 3279 /** 3280 * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported 3281 * @aux: DisplayPort AUX channel 3282 * @dpcd: DisplayPort configuration data 3283 * 3284 * Returns true if vsc sdp is supported, else returns false 3285 */ 3286 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 3287 { 3288 u8 rx_feature; 3289 3290 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13) 3291 return false; 3292 3293 if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST, &rx_feature) != 1) { 3294 drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n"); 3295 return false; 3296 } 3297 3298 return (rx_feature & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 3299 } 3300 EXPORT_SYMBOL(drm_dp_vsc_sdp_supported); 3301 3302 /** 3303 * drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp 3304 * @vsc: vsc sdp initialized according to its purpose as defined in 3305 * table 2-118 - table 2-120 in DP 1.4a specification 3306 * @sdp: valid handle to the generic dp_sdp which will be packed 3307 * 3308 * Returns length of sdp on success and error code on failure 3309 */ 3310 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 3311 struct dp_sdp *sdp) 3312 { 3313 size_t length = sizeof(struct dp_sdp); 3314 3315 memset(sdp, 0, sizeof(struct dp_sdp)); 3316 3317 /* 3318 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 3319 * VSC SDP Header Bytes 3320 */ 3321 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ 3322 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ 3323 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ 3324 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ 3325 3326 if (vsc->revision == 0x6) { 3327 sdp->db[0] = 1; 3328 sdp->db[3] = 1; 3329 } 3330 3331 /* 3332 * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry 3333 * Format as per DP 1.4a spec and DP 2.0 respectively. 3334 */ 3335 if (!(vsc->revision == 0x5 || vsc->revision == 0x7)) 3336 goto out; 3337 3338 /* VSC SDP Payload for DB16 through DB18 */ 3339 /* Pixel Encoding and Colorimetry Formats */ 3340 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ 3341 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ 3342 3343 switch (vsc->bpc) { 3344 case 6: 3345 /* 6bpc: 0x0 */ 3346 break; 3347 case 8: 3348 sdp->db[17] = 0x1; /* DB17[3:0] */ 3349 break; 3350 case 10: 3351 sdp->db[17] = 0x2; 3352 break; 3353 case 12: 3354 sdp->db[17] = 0x3; 3355 break; 3356 case 16: 3357 sdp->db[17] = 0x4; 3358 break; 3359 default: 3360 WARN(1, "Missing case %d\n", vsc->bpc); 3361 return -EINVAL; 3362 } 3363 3364 /* Dynamic Range and Component Bit Depth */ 3365 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 3366 sdp->db[17] |= 0x80; /* DB17[7] */ 3367 3368 /* Content Type */ 3369 sdp->db[18] = vsc->content_type & 0x7; 3370 3371 out: 3372 return length; 3373 } 3374 EXPORT_SYMBOL(drm_dp_vsc_sdp_pack); 3375 3376 /** 3377 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON 3378 * @dpcd: DisplayPort configuration data 3379 * @port_cap: port capabilities 3380 * 3381 * Returns maximum frl bandwidth supported by PCON in GBPS, 3382 * returns 0 if not supported. 3383 */ 3384 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 3385 const u8 port_cap[4]) 3386 { 3387 int bw; 3388 u8 buf; 3389 3390 buf = port_cap[2]; 3391 bw = buf & DP_PCON_MAX_FRL_BW; 3392 3393 switch (bw) { 3394 case DP_PCON_MAX_9GBPS: 3395 return 9; 3396 case DP_PCON_MAX_18GBPS: 3397 return 18; 3398 case DP_PCON_MAX_24GBPS: 3399 return 24; 3400 case DP_PCON_MAX_32GBPS: 3401 return 32; 3402 case DP_PCON_MAX_40GBPS: 3403 return 40; 3404 case DP_PCON_MAX_48GBPS: 3405 return 48; 3406 case DP_PCON_MAX_0GBPS: 3407 default: 3408 return 0; 3409 } 3410 3411 return 0; 3412 } 3413 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw); 3414 3415 /** 3416 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL. 3417 * @aux: DisplayPort AUX channel 3418 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY. 3419 * 3420 * Returns 0 if success, else returns negative error code. 3421 */ 3422 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd) 3423 { 3424 int ret; 3425 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE | 3426 DP_PCON_ENABLE_LINK_FRL_MODE; 3427 3428 if (enable_frl_ready_hpd) 3429 buf |= DP_PCON_ENABLE_HPD_READY; 3430 3431 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3432 3433 return ret; 3434 } 3435 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare); 3436 3437 /** 3438 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL 3439 * @aux: DisplayPort AUX channel 3440 * 3441 * Returns true if success, else returns false. 3442 */ 3443 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) 3444 { 3445 int ret; 3446 u8 buf; 3447 3448 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 3449 if (ret < 0) 3450 return false; 3451 3452 if (buf & DP_PCON_FRL_READY) 3453 return true; 3454 3455 return false; 3456 } 3457 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); 3458 3459 /** 3460 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 3461 * @aux: DisplayPort AUX channel 3462 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink 3463 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. 3464 * In Concurrent Mode, the FRL link bring up can be done along with 3465 * DP Link training. In Sequential mode, the FRL link bring up is done prior to 3466 * the DP Link training. 3467 * 3468 * Returns 0 if success, else returns negative error code. 3469 */ 3470 3471 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 3472 u8 frl_mode) 3473 { 3474 int ret; 3475 u8 buf; 3476 3477 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3478 if (ret < 0) 3479 return ret; 3480 3481 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) 3482 buf |= DP_PCON_ENABLE_CONCURRENT_LINK; 3483 else 3484 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; 3485 3486 switch (max_frl_gbps) { 3487 case 9: 3488 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS; 3489 break; 3490 case 18: 3491 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS; 3492 break; 3493 case 24: 3494 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS; 3495 break; 3496 case 32: 3497 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS; 3498 break; 3499 case 40: 3500 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS; 3501 break; 3502 case 48: 3503 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS; 3504 break; 3505 case 0: 3506 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS; 3507 break; 3508 default: 3509 return -EINVAL; 3510 } 3511 3512 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3513 if (ret < 0) 3514 return ret; 3515 3516 return 0; 3517 } 3518 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); 3519 3520 /** 3521 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 3522 * @aux: DisplayPort AUX channel 3523 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink 3524 * @frl_type : FRL training type, can be Extended, or Normal. 3525 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask 3526 * starting from min, and stops when link training is successful. In Extended 3527 * FRL training, all frl bw selected in the mask are trained by the PCON. 3528 * 3529 * Returns 0 if success, else returns negative error code. 3530 */ 3531 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 3532 u8 frl_type) 3533 { 3534 int ret; 3535 u8 buf = max_frl_mask; 3536 3537 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) 3538 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3539 else 3540 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3541 3542 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); 3543 if (ret < 0) 3544 return ret; 3545 3546 return 0; 3547 } 3548 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2); 3549 3550 /** 3551 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration. 3552 * @aux: DisplayPort AUX channel 3553 * 3554 * Returns 0 if success, else returns negative error code. 3555 */ 3556 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) 3557 { 3558 int ret; 3559 3560 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0); 3561 if (ret < 0) 3562 return ret; 3563 3564 return 0; 3565 } 3566 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config); 3567 3568 /** 3569 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL 3570 * @aux: DisplayPort AUX channel 3571 * 3572 * Returns 0 if success, else returns negative error code. 3573 */ 3574 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) 3575 { 3576 int ret; 3577 u8 buf = 0; 3578 3579 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3580 if (ret < 0) 3581 return ret; 3582 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) { 3583 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", 3584 aux->name); 3585 return -EINVAL; 3586 } 3587 buf |= DP_PCON_ENABLE_HDMI_LINK; 3588 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3589 if (ret < 0) 3590 return ret; 3591 3592 return 0; 3593 } 3594 EXPORT_SYMBOL(drm_dp_pcon_frl_enable); 3595 3596 /** 3597 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active. 3598 * @aux: DisplayPort AUX channel 3599 * 3600 * Returns true if link is active else returns false. 3601 */ 3602 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) 3603 { 3604 u8 buf; 3605 int ret; 3606 3607 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 3608 if (ret < 0) 3609 return false; 3610 3611 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE; 3612 } 3613 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active); 3614 3615 /** 3616 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE 3617 * @aux: DisplayPort AUX channel 3618 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration. 3619 * Valid only if the MODE returned is FRL. For Normal Link training mode 3620 * only 1 of the bits will be set, but in case of Extended mode, more than 3621 * one bits can be set. 3622 * 3623 * Returns the link mode : TMDS or FRL on success, else returns negative error 3624 * code. 3625 */ 3626 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask) 3627 { 3628 u8 buf; 3629 int mode; 3630 int ret; 3631 3632 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf); 3633 if (ret < 0) 3634 return ret; 3635 3636 mode = buf & DP_PCON_HDMI_LINK_MODE; 3637 3638 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode) 3639 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1; 3640 3641 return mode; 3642 } 3643 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode); 3644 3645 /** 3646 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane 3647 * during link failure between PCON and HDMI sink 3648 * @aux: DisplayPort AUX channel 3649 * @connector: DRM connector 3650 * code. 3651 **/ 3652 3653 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 3654 struct drm_connector *connector) 3655 { 3656 u8 buf, error_count; 3657 int i, num_error; 3658 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3659 3660 for (i = 0; i < hdmi->max_lanes; i++) { 3661 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0) 3662 return; 3663 3664 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK; 3665 switch (error_count) { 3666 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS: 3667 num_error = 100; 3668 break; 3669 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS: 3670 num_error = 10; 3671 break; 3672 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS: 3673 num_error = 3; 3674 break; 3675 default: 3676 num_error = 0; 3677 } 3678 3679 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", 3680 aux->name, num_error, i); 3681 } 3682 } 3683 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count); 3684 3685 /* 3686 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2 3687 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3688 * 3689 * Returns true is PCON encoder is DSC 1.2 else returns false. 3690 */ 3691 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3692 { 3693 u8 buf; 3694 u8 major_v, minor_v; 3695 3696 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; 3697 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT; 3698 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT; 3699 3700 if (major_v == 1 && minor_v == 2) 3701 return true; 3702 3703 return false; 3704 } 3705 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2); 3706 3707 /* 3708 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder 3709 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3710 * 3711 * Returns maximum no. of slices supported by the PCON DSC Encoder. 3712 */ 3713 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3714 { 3715 u8 slice_cap1, slice_cap2; 3716 3717 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; 3718 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; 3719 3720 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC) 3721 return 24; 3722 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC) 3723 return 20; 3724 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC) 3725 return 16; 3726 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC) 3727 return 12; 3728 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC) 3729 return 10; 3730 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC) 3731 return 8; 3732 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC) 3733 return 6; 3734 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC) 3735 return 4; 3736 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC) 3737 return 2; 3738 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC) 3739 return 1; 3740 3741 return 0; 3742 } 3743 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices); 3744 3745 /* 3746 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder 3747 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3748 * 3749 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320. 3750 */ 3751 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3752 { 3753 u8 buf; 3754 3755 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; 3756 3757 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER; 3758 } 3759 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width); 3760 3761 /* 3762 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder 3763 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3764 * 3765 * Returns the bpp precision supported by the PCON encoder. 3766 */ 3767 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3768 { 3769 u8 buf; 3770 3771 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; 3772 3773 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) { 3774 case DP_PCON_DSC_ONE_16TH_BPP: 3775 return 16; 3776 case DP_PCON_DSC_ONE_8TH_BPP: 3777 return 8; 3778 case DP_PCON_DSC_ONE_4TH_BPP: 3779 return 4; 3780 case DP_PCON_DSC_ONE_HALF_BPP: 3781 return 2; 3782 case DP_PCON_DSC_ONE_BPP: 3783 return 1; 3784 } 3785 3786 return 0; 3787 } 3788 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr); 3789 3790 static 3791 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config) 3792 { 3793 u8 buf; 3794 int ret; 3795 3796 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3797 if (ret < 0) 3798 return ret; 3799 3800 buf |= DP_PCON_ENABLE_DSC_ENCODER; 3801 3802 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) { 3803 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK; 3804 buf |= pps_buf_config << 2; 3805 } 3806 3807 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3808 if (ret < 0) 3809 return ret; 3810 3811 return 0; 3812 } 3813 3814 /** 3815 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters 3816 * for DSC1.2 between PCON & HDMI2.1 sink 3817 * @aux: DisplayPort AUX channel 3818 * 3819 * Returns 0 on success, else returns negative error code. 3820 */ 3821 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) 3822 { 3823 int ret; 3824 3825 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED); 3826 if (ret < 0) 3827 return ret; 3828 3829 return 0; 3830 } 3831 EXPORT_SYMBOL(drm_dp_pcon_pps_default); 3832 3833 /** 3834 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for 3835 * HDMI sink 3836 * @aux: DisplayPort AUX channel 3837 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON. 3838 * 3839 * Returns 0 on success, else returns negative error code. 3840 */ 3841 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]) 3842 { 3843 int ret; 3844 3845 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128); 3846 if (ret < 0) 3847 return ret; 3848 3849 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3850 if (ret < 0) 3851 return ret; 3852 3853 return 0; 3854 } 3855 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf); 3856 3857 /* 3858 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder 3859 * override registers 3860 * @aux: DisplayPort AUX channel 3861 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height, 3862 * bits_per_pixel. 3863 * 3864 * Returns 0 on success, else returns negative error code. 3865 */ 3866 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]) 3867 { 3868 int ret; 3869 3870 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2); 3871 if (ret < 0) 3872 return ret; 3873 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2); 3874 if (ret < 0) 3875 return ret; 3876 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2); 3877 if (ret < 0) 3878 return ret; 3879 3880 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3881 if (ret < 0) 3882 return ret; 3883 3884 return 0; 3885 } 3886 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param); 3887 3888 /* 3889 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr 3890 * @aux: displayPort AUX channel 3891 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable. 3892 * 3893 * Returns 0 on success, else returns negative error code. 3894 */ 3895 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc) 3896 { 3897 int ret; 3898 u8 buf; 3899 3900 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3901 if (ret < 0) 3902 return ret; 3903 3904 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK) 3905 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK); 3906 else 3907 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK; 3908 3909 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3910 if (ret < 0) 3911 return ret; 3912 3913 return 0; 3914 } 3915 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr); 3916 3917 /** 3918 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX 3919 * @aux: The DP AUX channel to use 3920 * @bl: Backlight capability info from drm_edp_backlight_init() 3921 * @level: The brightness level to set 3922 * 3923 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must 3924 * already have been enabled by the driver by calling drm_edp_backlight_enable(). 3925 * 3926 * Returns: %0 on success, negative error code on failure 3927 */ 3928 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3929 u16 level) 3930 { 3931 int ret; 3932 u8 buf[2] = { 0 }; 3933 3934 /* The panel uses the PWM for controlling brightness levels */ 3935 if (!bl->aux_set) 3936 return 0; 3937 3938 if (bl->lsb_reg_used) { 3939 buf[0] = (level & 0xff00) >> 8; 3940 buf[1] = (level & 0x00ff); 3941 } else { 3942 buf[0] = level; 3943 } 3944 3945 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf)); 3946 if (ret != sizeof(buf)) { 3947 drm_err(aux->drm_dev, 3948 "%s: Failed to write aux backlight level: %d\n", 3949 aux->name, ret); 3950 return ret < 0 ? ret : -EIO; 3951 } 3952 3953 return 0; 3954 } 3955 EXPORT_SYMBOL(drm_edp_backlight_set_level); 3956 3957 static int 3958 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3959 bool enable) 3960 { 3961 int ret; 3962 u8 buf; 3963 3964 /* This panel uses the EDP_BL_PWR GPIO for enablement */ 3965 if (!bl->aux_enable) 3966 return 0; 3967 3968 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf); 3969 if (ret != 1) { 3970 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", 3971 aux->name, ret); 3972 return ret < 0 ? ret : -EIO; 3973 } 3974 if (enable) 3975 buf |= DP_EDP_BACKLIGHT_ENABLE; 3976 else 3977 buf &= ~DP_EDP_BACKLIGHT_ENABLE; 3978 3979 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf); 3980 if (ret != 1) { 3981 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", 3982 aux->name, ret); 3983 return ret < 0 ? ret : -EIO; 3984 } 3985 3986 return 0; 3987 } 3988 3989 /** 3990 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD 3991 * @aux: The DP AUX channel to use 3992 * @bl: Backlight capability info from drm_edp_backlight_init() 3993 * @level: The initial backlight level to set via AUX, if there is one 3994 * 3995 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally 3996 * restoring any important backlight state such as the given backlight level, the brightness byte 3997 * count, backlight frequency, etc. 3998 * 3999 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 4000 * that the driver handle enabling/disabling the panel through implementation-specific means using 4001 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 4002 * this function becomes a no-op, and the driver is expected to handle powering the panel on using 4003 * the EDP_BL_PWR GPIO. 4004 * 4005 * Returns: %0 on success, negative error code on failure. 4006 */ 4007 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 4008 const u16 level) 4009 { 4010 int ret; 4011 u8 dpcd_buf; 4012 4013 if (bl->aux_set) 4014 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; 4015 else 4016 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM; 4017 4018 if (bl->pwmgen_bit_count) { 4019 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); 4020 if (ret != 1) 4021 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 4022 aux->name, ret); 4023 } 4024 4025 if (bl->pwm_freq_pre_divider) { 4026 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); 4027 if (ret != 1) 4028 drm_dbg_kms(aux->drm_dev, 4029 "%s: Failed to write aux backlight frequency: %d\n", 4030 aux->name, ret); 4031 else 4032 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; 4033 } 4034 4035 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf); 4036 if (ret != 1) { 4037 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", 4038 aux->name, ret); 4039 return ret < 0 ? ret : -EIO; 4040 } 4041 4042 ret = drm_edp_backlight_set_level(aux, bl, level); 4043 if (ret < 0) 4044 return ret; 4045 ret = drm_edp_backlight_set_enable(aux, bl, true); 4046 if (ret < 0) 4047 return ret; 4048 4049 return 0; 4050 } 4051 EXPORT_SYMBOL(drm_edp_backlight_enable); 4052 4053 /** 4054 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported 4055 * @aux: The DP AUX channel to use 4056 * @bl: Backlight capability info from drm_edp_backlight_init() 4057 * 4058 * This function handles disabling DPCD backlight controls on a panel over AUX. 4059 * 4060 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 4061 * that the driver handle enabling/disabling the panel through implementation-specific means using 4062 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 4063 * this function becomes a no-op, and the driver is expected to handle powering the panel off using 4064 * the EDP_BL_PWR GPIO. 4065 * 4066 * Returns: %0 on success or no-op, negative error code on failure. 4067 */ 4068 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl) 4069 { 4070 int ret; 4071 4072 ret = drm_edp_backlight_set_enable(aux, bl, false); 4073 if (ret < 0) 4074 return ret; 4075 4076 return 0; 4077 } 4078 EXPORT_SYMBOL(drm_edp_backlight_disable); 4079 4080 static inline int 4081 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 4082 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 4083 { 4084 int fxp, fxp_min, fxp_max, fxp_actual, f = 1; 4085 int ret; 4086 u8 pn, pn_min, pn_max; 4087 4088 if (!bl->aux_set) 4089 return 0; 4090 4091 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn); 4092 if (ret != 1) { 4093 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", 4094 aux->name, ret); 4095 return -ENODEV; 4096 } 4097 4098 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 4099 bl->max = (1 << pn) - 1; 4100 if (!driver_pwm_freq_hz) 4101 return 0; 4102 4103 /* 4104 * Set PWM Frequency divider to match desired frequency provided by the driver. 4105 * The PWM Frequency is calculated as 27Mhz / (F x P). 4106 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the 4107 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h) 4108 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the 4109 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h) 4110 */ 4111 4112 /* Find desired value of (F x P) 4113 * Note that, if F x P is out of supported range, the maximum value or minimum value will 4114 * applied automatically. So no need to check that. 4115 */ 4116 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz); 4117 4118 /* Use highest possible value of Pn for more granularity of brightness adjustment while 4119 * satisfying the conditions below. 4120 * - Pn is in the range of Pn_min and Pn_max 4121 * - F is in the range of 1 and 255 4122 * - FxP is within 25% of desired value. 4123 * Note: 25% is arbitrary value and may need some tweak. 4124 */ 4125 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); 4126 if (ret != 1) { 4127 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", 4128 aux->name, ret); 4129 return 0; 4130 } 4131 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); 4132 if (ret != 1) { 4133 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", 4134 aux->name, ret); 4135 return 0; 4136 } 4137 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 4138 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 4139 4140 /* Ensure frequency is within 25% of desired value */ 4141 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); 4142 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); 4143 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { 4144 drm_dbg_kms(aux->drm_dev, 4145 "%s: Driver defined backlight frequency (%d) out of range\n", 4146 aux->name, driver_pwm_freq_hz); 4147 return 0; 4148 } 4149 4150 for (pn = pn_max; pn >= pn_min; pn--) { 4151 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); 4152 fxp_actual = f << pn; 4153 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) 4154 break; 4155 } 4156 4157 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn); 4158 if (ret != 1) { 4159 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 4160 aux->name, ret); 4161 return 0; 4162 } 4163 bl->pwmgen_bit_count = pn; 4164 bl->max = (1 << pn) - 1; 4165 4166 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) { 4167 bl->pwm_freq_pre_divider = f; 4168 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", 4169 aux->name, driver_pwm_freq_hz); 4170 } 4171 4172 return 0; 4173 } 4174 4175 static inline int 4176 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 4177 u8 *current_mode) 4178 { 4179 int ret; 4180 u8 buf[2]; 4181 u8 mode_reg; 4182 4183 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg); 4184 if (ret != 1) { 4185 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", 4186 aux->name, ret); 4187 return ret < 0 ? ret : -EIO; 4188 } 4189 4190 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK); 4191 if (!bl->aux_set) 4192 return 0; 4193 4194 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { 4195 int size = 1 + bl->lsb_reg_used; 4196 4197 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size); 4198 if (ret != size) { 4199 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", 4200 aux->name, ret); 4201 return ret < 0 ? ret : -EIO; 4202 } 4203 4204 if (bl->lsb_reg_used) 4205 return (buf[0] << 8) | buf[1]; 4206 else 4207 return buf[0]; 4208 } 4209 4210 /* 4211 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and 4212 * the driver should assume max brightness 4213 */ 4214 return bl->max; 4215 } 4216 4217 /** 4218 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight 4219 * interface. 4220 * @aux: The DP aux device to use for probing 4221 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight 4222 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz 4223 * @edp_dpcd: A cached copy of the eDP DPCD 4224 * @current_level: Where to store the probed brightness level, if any 4225 * @current_mode: Where to store the currently set backlight control mode 4226 * 4227 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities, 4228 * along with also probing the current and maximum supported brightness levels. 4229 * 4230 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the 4231 * default frequency from the panel is used. 4232 * 4233 * Returns: %0 on success, negative error code on failure. 4234 */ 4235 int 4236 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 4237 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 4238 u16 *current_level, u8 *current_mode) 4239 { 4240 int ret; 4241 4242 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) 4243 bl->aux_enable = true; 4244 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) 4245 bl->aux_set = true; 4246 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) 4247 bl->lsb_reg_used = true; 4248 4249 /* Sanity check caps */ 4250 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { 4251 drm_dbg_kms(aux->drm_dev, 4252 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n", 4253 aux->name); 4254 return -EINVAL; 4255 } 4256 4257 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd); 4258 if (ret < 0) 4259 return ret; 4260 4261 ret = drm_edp_backlight_probe_state(aux, bl, current_mode); 4262 if (ret < 0) 4263 return ret; 4264 *current_level = ret; 4265 4266 drm_dbg_kms(aux->drm_dev, 4267 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n", 4268 aux->name, bl->aux_set, bl->aux_enable, *current_mode); 4269 if (bl->aux_set) { 4270 drm_dbg_kms(aux->drm_dev, 4271 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n", 4272 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, 4273 bl->lsb_reg_used); 4274 } 4275 4276 return 0; 4277 } 4278 EXPORT_SYMBOL(drm_edp_backlight_init); 4279 4280 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 4281 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)) 4282 4283 static int dp_aux_backlight_update_status(struct backlight_device *bd) 4284 { 4285 struct dp_aux_backlight *bl = bl_get_data(bd); 4286 u16 brightness = backlight_get_brightness(bd); 4287 int ret = 0; 4288 4289 if (!backlight_is_blank(bd)) { 4290 if (!bl->enabled) { 4291 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); 4292 bl->enabled = true; 4293 return 0; 4294 } 4295 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); 4296 } else { 4297 if (bl->enabled) { 4298 drm_edp_backlight_disable(bl->aux, &bl->info); 4299 bl->enabled = false; 4300 } 4301 } 4302 4303 return ret; 4304 } 4305 4306 static const struct backlight_ops dp_aux_bl_ops = { 4307 .update_status = dp_aux_backlight_update_status, 4308 }; 4309 4310 /** 4311 * drm_panel_dp_aux_backlight - create and use DP AUX backlight 4312 * @panel: DRM panel 4313 * @aux: The DP AUX channel to use 4314 * 4315 * Use this function to create and handle backlight if your panel 4316 * supports backlight control over DP AUX channel using DPCD 4317 * registers as per VESA's standard backlight control interface. 4318 * 4319 * When the panel is enabled backlight will be enabled after a 4320 * successful call to &drm_panel_funcs.enable() 4321 * 4322 * When the panel is disabled backlight will be disabled before the 4323 * call to &drm_panel_funcs.disable(). 4324 * 4325 * A typical implementation for a panel driver supporting backlight 4326 * control over DP AUX will call this function at probe time. 4327 * Backlight will then be handled transparently without requiring 4328 * any intervention from the driver. 4329 * 4330 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init(). 4331 * 4332 * Return: 0 on success or a negative error code on failure. 4333 */ 4334 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) 4335 { 4336 struct dp_aux_backlight *bl; 4337 struct backlight_properties props = { 0 }; 4338 u16 current_level; 4339 u8 current_mode; 4340 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 4341 int ret; 4342 4343 if (!panel || !panel->dev || !aux) 4344 return -EINVAL; 4345 4346 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd, 4347 EDP_DISPLAY_CTL_CAP_SIZE); 4348 if (ret < 0) 4349 return ret; 4350 4351 if (!drm_edp_backlight_supported(edp_dpcd)) { 4352 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); 4353 return 0; 4354 } 4355 4356 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); 4357 if (!bl) 4358 return -ENOMEM; 4359 4360 bl->aux = aux; 4361 4362 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, 4363 ¤t_level, ¤t_mode); 4364 if (ret < 0) 4365 return ret; 4366 4367 props.type = BACKLIGHT_RAW; 4368 props.brightness = current_level; 4369 props.max_brightness = bl->info.max; 4370 4371 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", 4372 panel->dev, bl, 4373 &dp_aux_bl_ops, &props); 4374 if (IS_ERR(bl->base)) 4375 return PTR_ERR(bl->base); 4376 4377 backlight_disable(bl->base); 4378 4379 panel->backlight = bl->base; 4380 4381 return 0; 4382 } 4383 EXPORT_SYMBOL(drm_panel_dp_aux_backlight); 4384 4385 #endif 4386 4387 /* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */ 4388 static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16, 4389 int symbol_size, bool is_mst) 4390 { 4391 int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count); 4392 int align = is_mst ? 4 / lane_count : 1; 4393 4394 return ALIGN(cycles, align); 4395 } 4396 4397 static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count, 4398 int bpp_x16, int symbol_size, bool is_mst) 4399 { 4400 int slice_pixels = DIV_ROUND_UP(pixels, slice_count); 4401 int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels, 4402 bpp_x16, symbol_size, is_mst); 4403 int slice_eoc_cycles = is_mst ? 4 / lane_count : 1; 4404 4405 return slice_count * (slice_data_cycles + slice_eoc_cycles); 4406 } 4407 4408 /** 4409 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream 4410 * @lane_count: DP link lane count 4411 * @hactive: pixel count of the active period in one scanline of the stream 4412 * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set 4413 * @bpp_x16: bits per pixel in .4 binary fixed point 4414 * @flags: DRM_DP_OVERHEAD_x flags 4415 * 4416 * Calculate the BW allocation overhead of a DP link stream, depending 4417 * on the link's 4418 * - @lane_count 4419 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST) 4420 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR) 4421 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC) 4422 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK) 4423 * as well as the stream's 4424 * - @hactive timing 4425 * - @bpp_x16 color depth 4426 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC). 4427 * Note that this overhead doesn't account for the 8b/10b, 128b/132b 4428 * channel coding efficiency, for that see 4429 * @drm_dp_link_bw_channel_coding_efficiency(). 4430 * 4431 * Returns the overhead as 100% + overhead% in 1ppm units. 4432 */ 4433 int drm_dp_bw_overhead(int lane_count, int hactive, 4434 int dsc_slice_count, 4435 int bpp_x16, unsigned long flags) 4436 { 4437 int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8; 4438 bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST; 4439 u32 overhead = 1000000; 4440 int symbol_cycles; 4441 4442 if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) { 4443 DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d, hactive %d, bpp_x16 " FXP_Q4_FMT "\n", 4444 lane_count, hactive, 4445 FXP_Q4_ARGS(bpp_x16)); 4446 return 0; 4447 } 4448 4449 /* 4450 * DP Standard v2.1 2.6.4.1 4451 * SSC downspread and ref clock variation margin: 4452 * 5300ppm + 300ppm ~ 0.6% 4453 */ 4454 if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK) 4455 overhead += 6000; 4456 4457 /* 4458 * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4: 4459 * FEC symbol insertions for 8b/10b channel coding: 4460 * After each 250 data symbols on 2-4 lanes: 4461 * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block) 4462 * After each 2 x 250 data symbols on 1 lane: 4463 * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block) 4464 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks: 4465 * 256 * 256 bytes + 1 FEC_PM 4466 * or 4467 * 128 * 512 bytes + 1 FEC_PM 4468 * (256 * 6 + 1) / (256 * 250) = 2.4015625 % 4469 */ 4470 if (flags & DRM_DP_BW_OVERHEAD_FEC) 4471 overhead += 24016; 4472 4473 /* 4474 * DP Standard v2.1 2.7.9, 5.9.7 4475 * The FEC overhead for UHBR is accounted for in its 96.71% channel 4476 * coding efficiency. 4477 */ 4478 WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) && 4479 (flags & DRM_DP_BW_OVERHEAD_FEC)); 4480 4481 if (flags & DRM_DP_BW_OVERHEAD_DSC) 4482 symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive, 4483 dsc_slice_count, 4484 bpp_x16, symbol_size, 4485 is_mst); 4486 else 4487 symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive, 4488 bpp_x16, symbol_size, 4489 is_mst); 4490 4491 return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count, 4492 overhead * 16), 4493 hactive * bpp_x16); 4494 } 4495 EXPORT_SYMBOL(drm_dp_bw_overhead); 4496 4497 /** 4498 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency 4499 * @is_uhbr: Whether the link has a 128b/132b channel coding 4500 * 4501 * Return the channel coding efficiency of the given DP link type, which is 4502 * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes 4503 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead 4504 * and for 128b/132b any link or PHY level control symbol insertion overhead 4505 * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the 4506 * corresponding FEC overhead is BW allocation specific, included in the value 4507 * returned by drm_dp_bw_overhead(). 4508 * 4509 * Returns the efficiency in the 100%/coding-overhead% ratio in 4510 * 1ppm units. 4511 */ 4512 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr) 4513 { 4514 if (is_uhbr) 4515 return 967100; 4516 else 4517 /* 4518 * Note that on 8b/10b MST the efficiency is only 4519 * 78.75% due to the 1 out of 64 MTPH packet overhead, 4520 * not accounted for here. 4521 */ 4522 return 800000; 4523 } 4524 EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency); 4525 4526 /** 4527 * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink 4528 * @max_link_rate: max DPRX link rate in 10kbps units 4529 * @max_lanes: max DPRX lane count 4530 * 4531 * Given a link rate and lanes, get the data bandwidth. 4532 * 4533 * Data bandwidth is the actual payload rate, which depends on the data 4534 * bandwidth efficiency and the link rate. 4535 * 4536 * Note that protocol layers above the DPRX link level considered here can 4537 * further limit the maximum data rate. Such layers are the MST topology (with 4538 * limits on the link between the source and first branch device as well as on 4539 * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels - 4540 * which in turn can encapsulate an MST link with its own limit - with each 4541 * SST or MST encapsulated tunnel sharing the BW of a tunnel group. 4542 * 4543 * Returns the maximum data rate in kBps units. 4544 */ 4545 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes) 4546 { 4547 int ch_coding_efficiency = 4548 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate)); 4549 4550 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes, 4551 ch_coding_efficiency), 4552 1000000 * 8); 4553 } 4554 EXPORT_SYMBOL(drm_dp_max_dprx_data_rate); 4555