1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 /* Copyright (c) 2008-2019, IBM Corporation */ 5 6 #ifndef _SIW_H 7 #define _SIW_H 8 9 #include <rdma/ib_verbs.h> 10 #include <rdma/restrack.h> 11 #include <linux/socket.h> 12 #include <linux/skbuff.h> 13 #include <linux/crc32.h> 14 #include <linux/crc32c.h> 15 #include <linux/unaligned.h> 16 17 #include <rdma/siw-abi.h> 18 #include "iwarp.h" 19 20 #define SIW_VENDOR_ID 0x626d74 /* ascii 'bmt' for now */ 21 #define SIW_VENDORT_PART_ID 0 22 #define SIW_MAX_QP (1024 * 100) 23 #define SIW_MAX_QP_WR (1024 * 32) 24 #define SIW_MAX_ORD_QP 128 25 #define SIW_MAX_IRD_QP 128 26 #define SIW_MAX_SGE_PBL 256 /* max num sge's for PBL */ 27 #define SIW_MAX_SGE_RD 1 /* iwarp limitation. we could relax */ 28 #define SIW_MAX_CQ (1024 * 100) 29 #define SIW_MAX_CQE (SIW_MAX_QP_WR * 100) 30 #define SIW_MAX_MR (SIW_MAX_QP * 10) 31 #define SIW_MAX_PD SIW_MAX_QP 32 #define SIW_MAX_MW 0 /* to be set if MW's are supported */ 33 #define SIW_MAX_SRQ SIW_MAX_QP 34 #define SIW_MAX_SRQ_WR (SIW_MAX_QP_WR * 10) 35 #define SIW_MAX_CONTEXT SIW_MAX_PD 36 37 /* Min number of bytes for using zero copy transmit */ 38 #define SENDPAGE_THRESH PAGE_SIZE 39 40 /* Maximum number of frames which can be send in one SQ processing */ 41 #define SQ_USER_MAXBURST 100 42 43 /* Maximum number of consecutive IRQ elements which get served 44 * if SQ has pending work. Prevents starving local SQ processing 45 * by serving peer Read Requests. 46 */ 47 #define SIW_IRQ_MAXBURST_SQ_ACTIVE 4 48 49 /* There is always only a port 1 per siw device */ 50 #define SIW_PORT 1 51 52 struct siw_dev_cap { 53 int max_qp; 54 int max_qp_wr; 55 int max_ord; /* max. outbound read queue depth */ 56 int max_ird; /* max. inbound read queue depth */ 57 int max_sge; 58 int max_sge_rd; 59 int max_cq; 60 int max_cqe; 61 int max_mr; 62 int max_pd; 63 int max_mw; 64 int max_srq; 65 int max_srq_wr; 66 int max_srq_sge; 67 }; 68 69 struct siw_pd { 70 struct ib_pd base_pd; 71 }; 72 73 struct siw_device { 74 struct ib_device base_dev; 75 struct siw_dev_cap attrs; 76 77 u32 vendor_part_id; 78 int numa_node; 79 char raw_gid[ETH_ALEN]; 80 81 spinlock_t lock; 82 83 struct xarray qp_xa; 84 struct xarray mem_xa; 85 86 struct list_head cep_list; 87 struct list_head qp_list; 88 89 /* active objects statistics to enforce limits */ 90 atomic_t num_qp; 91 atomic_t num_cq; 92 atomic_t num_pd; 93 atomic_t num_mr; 94 atomic_t num_srq; 95 atomic_t num_ctx; 96 }; 97 98 struct siw_ucontext { 99 struct ib_ucontext base_ucontext; 100 struct siw_device *sdev; 101 }; 102 103 /* 104 * The RDMA core does not define LOCAL_READ access, which is always 105 * enabled implictely. 106 */ 107 #define IWARP_ACCESS_MASK \ 108 (IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE | \ 109 IB_ACCESS_REMOTE_READ) 110 111 /* 112 * siw presentation of user memory registered as source 113 * or target of RDMA operations. 114 */ 115 116 struct siw_page_chunk { 117 struct page **plist; 118 }; 119 120 struct siw_umem { 121 struct ib_umem *base_mem; 122 unsigned int num_pages; 123 unsigned int num_chunks; 124 u64 fp_addr; /* First page base address */ 125 struct siw_page_chunk page_chunk[] __counted_by(num_chunks); 126 }; 127 128 struct siw_pble { 129 dma_addr_t addr; /* Address of assigned buffer */ 130 unsigned int size; /* Size of this entry */ 131 unsigned long pbl_off; /* Total offset from start of PBL */ 132 }; 133 134 struct siw_pbl { 135 unsigned int num_buf; 136 unsigned int max_buf; 137 struct siw_pble pbe[] __counted_by(max_buf); 138 }; 139 140 /* 141 * Generic memory representation for registered siw memory. 142 * Memory lookup always via higher 24 bit of STag (STag index). 143 */ 144 struct siw_mem { 145 struct siw_device *sdev; 146 struct kref ref; 147 u64 va; /* VA of memory */ 148 u64 len; /* length of the memory buffer in bytes */ 149 u32 stag; /* iWarp memory access steering tag */ 150 u8 stag_valid; /* VALID or INVALID */ 151 u8 is_pbl; /* PBL or user space mem */ 152 u8 is_mw; /* Memory Region or Memory Window */ 153 enum ib_access_flags perms; /* local/remote READ & WRITE */ 154 union { 155 struct siw_umem *umem; 156 struct siw_pbl *pbl; 157 void *mem_obj; 158 }; 159 struct ib_pd *pd; 160 }; 161 162 struct siw_mr { 163 struct ib_mr base_mr; 164 struct siw_mem *mem; 165 struct rcu_head rcu; 166 }; 167 168 /* 169 * Error codes for local or remote 170 * access to registered memory 171 */ 172 enum siw_access_state { 173 E_ACCESS_OK, 174 E_STAG_INVALID, 175 E_BASE_BOUNDS, 176 E_ACCESS_PERM, 177 E_PD_MISMATCH 178 }; 179 180 enum siw_wr_state { 181 SIW_WR_IDLE, 182 SIW_WR_QUEUED, /* processing has not started yet */ 183 SIW_WR_INPROGRESS /* initiated processing of the WR */ 184 }; 185 186 /* The WQE currently being processed (RX or TX) */ 187 struct siw_wqe { 188 /* Copy of applications SQE or RQE */ 189 union { 190 struct siw_sqe sqe; 191 struct siw_rqe rqe; 192 }; 193 struct siw_mem *mem[SIW_MAX_SGE]; /* per sge's resolved mem */ 194 enum siw_wr_state wr_status; 195 enum siw_wc_status wc_status; 196 u32 bytes; /* total bytes to process */ 197 u32 processed; /* bytes processed */ 198 }; 199 200 struct siw_cq { 201 struct ib_cq base_cq; 202 spinlock_t lock; 203 struct siw_cq_ctrl *notify; 204 struct siw_cqe *queue; 205 u32 cq_put; 206 u32 cq_get; 207 u32 num_cqe; 208 struct rdma_user_mmap_entry *cq_entry; /* mmap info for CQE array */ 209 u32 id; /* For debugging only */ 210 }; 211 212 enum siw_qp_state { 213 SIW_QP_STATE_IDLE, 214 SIW_QP_STATE_RTR, 215 SIW_QP_STATE_RTS, 216 SIW_QP_STATE_CLOSING, 217 SIW_QP_STATE_TERMINATE, 218 SIW_QP_STATE_ERROR, 219 SIW_QP_STATE_COUNT 220 }; 221 222 enum siw_qp_flags { 223 SIW_RDMA_BIND_ENABLED = (1 << 0), 224 SIW_RDMA_WRITE_ENABLED = (1 << 1), 225 SIW_RDMA_READ_ENABLED = (1 << 2), 226 SIW_SIGNAL_ALL_WR = (1 << 3), 227 SIW_MPA_CRC = (1 << 4), 228 SIW_QP_IN_DESTROY = (1 << 5) 229 }; 230 231 enum siw_qp_attr_mask { 232 SIW_QP_ATTR_STATE = (1 << 0), 233 SIW_QP_ATTR_ACCESS_FLAGS = (1 << 1), 234 SIW_QP_ATTR_LLP_HANDLE = (1 << 2), 235 SIW_QP_ATTR_ORD = (1 << 3), 236 SIW_QP_ATTR_IRD = (1 << 4), 237 SIW_QP_ATTR_SQ_SIZE = (1 << 5), 238 SIW_QP_ATTR_RQ_SIZE = (1 << 6), 239 SIW_QP_ATTR_MPA = (1 << 7) 240 }; 241 242 struct siw_srq { 243 struct ib_srq base_srq; 244 spinlock_t lock; 245 u32 max_sge; 246 u32 limit; /* low watermark for async event */ 247 struct siw_rqe *recvq; 248 u32 rq_put; 249 u32 rq_get; 250 u32 num_rqe; /* max # of wqe's allowed */ 251 struct rdma_user_mmap_entry *srq_entry; /* mmap info for SRQ array */ 252 bool armed:1; /* inform user if limit hit */ 253 bool is_kernel_res:1; /* true if kernel client */ 254 }; 255 256 struct siw_qp_attrs { 257 enum siw_qp_state state; 258 u32 sq_size; 259 u32 rq_size; 260 u32 orq_size; 261 u32 irq_size; 262 u32 sq_max_sges; 263 u32 rq_max_sges; 264 enum siw_qp_flags flags; 265 266 struct socket *sk; 267 }; 268 269 enum siw_tx_ctx { 270 SIW_SEND_HDR, /* start or continue sending HDR */ 271 SIW_SEND_DATA, /* start or continue sending DDP payload */ 272 SIW_SEND_TRAILER, /* start or continue sending TRAILER */ 273 SIW_SEND_SHORT_FPDU/* send whole FPDU hdr|data|trailer at once */ 274 }; 275 276 enum siw_rx_state { 277 SIW_GET_HDR, /* await new hdr or within hdr */ 278 SIW_GET_DATA_START, /* start of inbound DDP payload */ 279 SIW_GET_DATA_MORE, /* continuation of (misaligned) DDP payload */ 280 SIW_GET_TRAILER/* await new trailer or within trailer */ 281 }; 282 283 struct siw_rx_stream { 284 struct sk_buff *skb; 285 int skb_new; /* pending unread bytes in skb */ 286 int skb_offset; /* offset in skb */ 287 int skb_copied; /* processed bytes in skb */ 288 289 enum siw_rx_state state; 290 291 union iwarp_hdr hdr; 292 struct mpa_trailer trailer; 293 u32 mpa_crc; 294 bool mpa_crc_enabled; 295 296 /* 297 * For each FPDU, main RX loop runs through 3 stages: 298 * Receiving protocol headers, placing DDP payload and receiving 299 * trailer information (CRC + possibly padding). 300 * Next two variables keep state on receive status of the 301 * current FPDU part (hdr, data, trailer). 302 */ 303 int fpdu_part_rcvd; /* bytes in pkt part copied */ 304 int fpdu_part_rem; /* bytes in pkt part not seen */ 305 306 /* 307 * Next expected DDP MSN for each QN + 308 * expected steering tag + 309 * expected DDP tagget offset (all HBO) 310 */ 311 u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT]; 312 u32 ddp_stag; 313 u64 ddp_to; 314 u32 inval_stag; /* Stag to be invalidated */ 315 316 u8 rx_suspend : 1; 317 u8 pad : 2; /* # of pad bytes expected */ 318 u8 rdmap_op : 4; /* opcode of current frame */ 319 }; 320 321 struct siw_rx_fpdu { 322 /* 323 * Local destination memory of inbound RDMA operation. 324 * Valid, according to wqe->wr_status 325 */ 326 struct siw_wqe wqe_active; 327 328 unsigned int pbl_idx; /* Index into current PBL */ 329 unsigned int sge_idx; /* current sge in rx */ 330 unsigned int sge_off; /* already rcvd in curr. sge */ 331 332 char first_ddp_seg; /* this is the first DDP seg */ 333 char more_ddp_segs; /* more DDP segs expected */ 334 u8 prev_rdmap_op : 4; /* opcode of prev frame */ 335 }; 336 337 /* 338 * Shorthands for short packets w/o payload 339 * to be transmitted more efficient. 340 */ 341 struct siw_send_pkt { 342 struct iwarp_send send; 343 __be32 crc; 344 }; 345 346 struct siw_write_pkt { 347 struct iwarp_rdma_write write; 348 __be32 crc; 349 }; 350 351 struct siw_rreq_pkt { 352 struct iwarp_rdma_rreq rreq; 353 __be32 crc; 354 }; 355 356 struct siw_rresp_pkt { 357 struct iwarp_rdma_rresp rresp; 358 __be32 crc; 359 }; 360 361 struct siw_iwarp_tx { 362 union { 363 union iwarp_hdr hdr; 364 365 /* Generic part of FPDU header */ 366 struct iwarp_ctrl ctrl; 367 struct iwarp_ctrl_untagged c_untagged; 368 struct iwarp_ctrl_tagged c_tagged; 369 370 /* FPDU headers */ 371 struct iwarp_rdma_write rwrite; 372 struct iwarp_rdma_rreq rreq; 373 struct iwarp_rdma_rresp rresp; 374 struct iwarp_terminate terminate; 375 struct iwarp_send send; 376 struct iwarp_send_inv send_inv; 377 378 /* complete short FPDUs */ 379 struct siw_send_pkt send_pkt; 380 struct siw_write_pkt write_pkt; 381 struct siw_rreq_pkt rreq_pkt; 382 struct siw_rresp_pkt rresp_pkt; 383 } pkt; 384 385 struct mpa_trailer trailer; 386 /* DDP MSN for untagged messages */ 387 u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT]; 388 389 enum siw_tx_ctx state; 390 u16 ctrl_len; /* ddp+rdmap hdr */ 391 u16 ctrl_sent; 392 int burst; 393 int bytes_unsent; /* ddp payload bytes */ 394 395 u32 mpa_crc; 396 bool mpa_crc_enabled; 397 398 u8 do_crc : 1; /* do crc for segment */ 399 u8 use_sendpage : 1; /* send w/o copy */ 400 u8 tx_suspend : 1; /* stop sending DDP segs. */ 401 u8 pad : 2; /* # pad in current fpdu */ 402 u8 orq_fence : 1; /* ORQ full or Send fenced */ 403 u8 in_syscall : 1; /* TX out of user context */ 404 u8 zcopy_tx : 1; /* Use TCP_SENDPAGE if possible */ 405 u8 gso_seg_limit; /* Maximum segments for GSO, 0 = unbound */ 406 407 u16 fpdu_len; /* len of FPDU to tx */ 408 unsigned int tcp_seglen; /* remaining tcp seg space */ 409 410 struct siw_wqe wqe_active; 411 412 int pbl_idx; /* Index into current PBL */ 413 int sge_idx; /* current sge in tx */ 414 u32 sge_off; /* already sent in curr. sge */ 415 }; 416 417 struct siw_qp { 418 struct ib_qp base_qp; 419 struct siw_device *sdev; 420 int tx_cpu; 421 struct kref ref; 422 struct completion qp_free; 423 struct list_head devq; 424 struct siw_qp_attrs attrs; 425 426 struct siw_cep *cep; 427 struct rw_semaphore state_lock; 428 429 struct ib_pd *pd; 430 struct siw_cq *scq; 431 struct siw_cq *rcq; 432 struct siw_srq *srq; 433 434 struct siw_iwarp_tx tx_ctx; /* Transmit context */ 435 spinlock_t sq_lock; 436 struct siw_sqe *sendq; /* send queue element array */ 437 uint32_t sq_get; /* consumer index into sq array */ 438 uint32_t sq_put; /* kernel prod. index into sq array */ 439 struct llist_node tx_list; 440 441 struct siw_sqe *orq; /* outbound read queue element array */ 442 spinlock_t orq_lock; 443 uint32_t orq_get; /* consumer index into orq array */ 444 uint32_t orq_put; /* shared producer index for ORQ */ 445 446 struct siw_rx_stream rx_stream; 447 struct siw_rx_fpdu *rx_fpdu; 448 struct siw_rx_fpdu rx_tagged; 449 struct siw_rx_fpdu rx_untagged; 450 spinlock_t rq_lock; 451 struct siw_rqe *recvq; /* recv queue element array */ 452 uint32_t rq_get; /* consumer index into rq array */ 453 uint32_t rq_put; /* kernel prod. index into rq array */ 454 455 struct siw_sqe *irq; /* inbound read queue element array */ 456 uint32_t irq_get; /* consumer index into irq array */ 457 uint32_t irq_put; /* producer index into irq array */ 458 int irq_burst; 459 460 struct { /* information to be carried in TERMINATE pkt, if valid */ 461 u8 valid; 462 u8 in_tx; 463 u8 layer : 4, etype : 4; 464 u8 ecode; 465 } term_info; 466 struct rdma_user_mmap_entry *sq_entry; /* mmap info for SQE array */ 467 struct rdma_user_mmap_entry *rq_entry; /* mmap info for RQE array */ 468 }; 469 470 /* helper macros */ 471 #define rx_qp(rx) container_of(rx, struct siw_qp, rx_stream) 472 #define tx_qp(tx) container_of(tx, struct siw_qp, tx_ctx) 473 #define tx_wqe(qp) (&(qp)->tx_ctx.wqe_active) 474 #define rx_wqe(rctx) (&(rctx)->wqe_active) 475 #define rx_mem(rctx) ((rctx)->wqe_active.mem[0]) 476 #define tx_type(wqe) ((wqe)->sqe.opcode) 477 #define rx_type(wqe) ((wqe)->rqe.opcode) 478 #define tx_flags(wqe) ((wqe)->sqe.flags) 479 480 struct iwarp_msg_info { 481 int hdr_len; 482 struct iwarp_ctrl ctrl; 483 int (*rx_data)(struct siw_qp *qp); 484 }; 485 486 struct siw_user_mmap_entry { 487 struct rdma_user_mmap_entry rdma_entry; 488 void *address; 489 }; 490 491 /* Global siw parameters. Currently set in siw_main.c */ 492 extern const bool zcopy_tx; 493 extern const bool try_gso; 494 extern const bool loopback_enabled; 495 extern const bool mpa_crc_required; 496 extern const bool mpa_crc_strict; 497 extern const bool siw_tcp_nagle; 498 extern u_char mpa_version; 499 extern const bool peer_to_peer; 500 extern struct task_struct *siw_tx_thread[]; 501 502 extern struct iwarp_msg_info iwarp_pktinfo[RDMAP_TERMINATE + 1]; 503 504 /* QP general functions */ 505 int siw_qp_modify(struct siw_qp *qp, struct siw_qp_attrs *attr, 506 enum siw_qp_attr_mask mask); 507 int siw_qp_mpa_rts(struct siw_qp *qp, enum mpa_v2_ctrl ctrl); 508 void siw_qp_llp_close(struct siw_qp *qp); 509 void siw_qp_cm_drop(struct siw_qp *qp, int schedule); 510 void siw_send_terminate(struct siw_qp *qp); 511 512 void siw_qp_get_ref(struct ib_qp *qp); 513 void siw_qp_put_ref(struct ib_qp *qp); 514 int siw_qp_add(struct siw_device *sdev, struct siw_qp *qp); 515 void siw_free_qp(struct kref *ref); 516 517 void siw_init_terminate(struct siw_qp *qp, enum term_elayer layer, 518 u8 etype, u8 ecode, int in_tx); 519 enum ddp_ecode siw_tagged_error(enum siw_access_state state); 520 enum rdmap_ecode siw_rdmap_error(enum siw_access_state state); 521 522 void siw_read_to_orq(struct siw_sqe *rreq, struct siw_sqe *sqe); 523 int siw_sqe_complete(struct siw_qp *qp, struct siw_sqe *sqe, u32 bytes, 524 enum siw_wc_status status); 525 int siw_rqe_complete(struct siw_qp *qp, struct siw_rqe *rqe, u32 bytes, 526 u32 inval_stag, enum siw_wc_status status); 527 void siw_qp_llp_data_ready(struct sock *sk); 528 void siw_qp_llp_write_space(struct sock *sk); 529 530 /* QP TX path functions */ 531 int siw_create_tx_threads(void); 532 void siw_stop_tx_threads(void); 533 int siw_run_sq(void *arg); 534 int siw_qp_sq_process(struct siw_qp *qp); 535 int siw_sq_start(struct siw_qp *qp); 536 int siw_activate_tx(struct siw_qp *qp); 537 int siw_get_tx_cpu(struct siw_device *sdev); 538 void siw_put_tx_cpu(int cpu); 539 540 /* QP RX path functions */ 541 int siw_proc_send(struct siw_qp *qp); 542 int siw_proc_rreq(struct siw_qp *qp); 543 int siw_proc_rresp(struct siw_qp *qp); 544 int siw_proc_write(struct siw_qp *qp); 545 int siw_proc_terminate(struct siw_qp *qp); 546 547 int siw_tcp_rx_data(read_descriptor_t *rd_desc, struct sk_buff *skb, 548 unsigned int off, size_t len); 549 550 static inline void set_rx_fpdu_context(struct siw_qp *qp, u8 opcode) 551 { 552 if (opcode == RDMAP_RDMA_WRITE || opcode == RDMAP_RDMA_READ_RESP) 553 qp->rx_fpdu = &qp->rx_tagged; 554 else 555 qp->rx_fpdu = &qp->rx_untagged; 556 557 qp->rx_stream.rdmap_op = opcode; 558 } 559 560 static inline struct siw_ucontext *to_siw_ctx(struct ib_ucontext *base_ctx) 561 { 562 return container_of(base_ctx, struct siw_ucontext, base_ucontext); 563 } 564 565 static inline struct siw_qp *to_siw_qp(struct ib_qp *base_qp) 566 { 567 return container_of(base_qp, struct siw_qp, base_qp); 568 } 569 570 static inline struct siw_cq *to_siw_cq(struct ib_cq *base_cq) 571 { 572 return container_of(base_cq, struct siw_cq, base_cq); 573 } 574 575 static inline struct siw_srq *to_siw_srq(struct ib_srq *base_srq) 576 { 577 return container_of(base_srq, struct siw_srq, base_srq); 578 } 579 580 static inline struct siw_device *to_siw_dev(struct ib_device *base_dev) 581 { 582 return container_of(base_dev, struct siw_device, base_dev); 583 } 584 585 static inline struct siw_mr *to_siw_mr(struct ib_mr *base_mr) 586 { 587 return container_of(base_mr, struct siw_mr, base_mr); 588 } 589 590 static inline struct siw_user_mmap_entry * 591 to_siw_mmap_entry(struct rdma_user_mmap_entry *rdma_mmap) 592 { 593 return container_of(rdma_mmap, struct siw_user_mmap_entry, rdma_entry); 594 } 595 596 static inline struct siw_qp *siw_qp_id2obj(struct siw_device *sdev, int id) 597 { 598 struct siw_qp *qp; 599 600 rcu_read_lock(); 601 qp = xa_load(&sdev->qp_xa, id); 602 if (likely(qp && kref_get_unless_zero(&qp->ref))) { 603 rcu_read_unlock(); 604 return qp; 605 } 606 rcu_read_unlock(); 607 return NULL; 608 } 609 610 static inline u32 qp_id(struct siw_qp *qp) 611 { 612 return qp->base_qp.qp_num; 613 } 614 615 static inline void siw_qp_get(struct siw_qp *qp) 616 { 617 kref_get(&qp->ref); 618 } 619 620 static inline void siw_qp_put(struct siw_qp *qp) 621 { 622 kref_put(&qp->ref, siw_free_qp); 623 } 624 625 static inline int siw_sq_empty(struct siw_qp *qp) 626 { 627 struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size]; 628 629 return READ_ONCE(sqe->flags) == 0; 630 } 631 632 static inline struct siw_sqe *sq_get_next(struct siw_qp *qp) 633 { 634 struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size]; 635 636 if (READ_ONCE(sqe->flags) & SIW_WQE_VALID) 637 return sqe; 638 639 return NULL; 640 } 641 642 static inline struct siw_sqe *orq_get_current(struct siw_qp *qp) 643 { 644 return &qp->orq[qp->orq_get % qp->attrs.orq_size]; 645 } 646 647 static inline struct siw_sqe *orq_get_free(struct siw_qp *qp) 648 { 649 struct siw_sqe *orq_e = &qp->orq[qp->orq_put % qp->attrs.orq_size]; 650 651 if (READ_ONCE(orq_e->flags) == 0) 652 return orq_e; 653 654 return NULL; 655 } 656 657 static inline int siw_orq_empty(struct siw_qp *qp) 658 { 659 return orq_get_current(qp)->flags == 0 ? 1 : 0; 660 } 661 662 static inline struct siw_sqe *irq_alloc_free(struct siw_qp *qp) 663 { 664 struct siw_sqe *irq_e = &qp->irq[qp->irq_put % qp->attrs.irq_size]; 665 666 if (READ_ONCE(irq_e->flags) == 0) { 667 qp->irq_put++; 668 return irq_e; 669 } 670 return NULL; 671 } 672 673 static inline void siw_crc_init(u32 *crc) 674 { 675 *crc = ~0; 676 } 677 678 static inline void siw_crc_update(u32 *crc, const void *data, size_t len) 679 { 680 *crc = crc32c(*crc, data, len); 681 } 682 683 static inline void siw_crc_final(u32 *crc, u8 out[4]) 684 { 685 put_unaligned_le32(~*crc, out); 686 } 687 688 static inline void siw_crc_oneshot(const void *data, size_t len, u8 out[4]) 689 { 690 u32 crc; 691 692 siw_crc_init(&crc); 693 siw_crc_update(&crc, data, len); 694 return siw_crc_final(&crc, out); 695 } 696 697 static inline void siw_crc_skb(struct siw_rx_stream *srx, unsigned int len) 698 { 699 srx->mpa_crc = skb_crc32c(srx->skb, srx->skb_offset, len, srx->mpa_crc); 700 } 701 702 #define siw_dbg(ibdev, fmt, ...) \ 703 ibdev_dbg(ibdev, "%s: " fmt, __func__, ##__VA_ARGS__) 704 705 #define siw_dbg_qp(qp, fmt, ...) \ 706 ibdev_dbg(&qp->sdev->base_dev, "QP[%u] %s: " fmt, qp_id(qp), __func__, \ 707 ##__VA_ARGS__) 708 709 #define siw_dbg_cq(cq, fmt, ...) \ 710 ibdev_dbg(cq->base_cq.device, "CQ[%u] %s: " fmt, cq->id, __func__, \ 711 ##__VA_ARGS__) 712 713 #define siw_dbg_pd(pd, fmt, ...) \ 714 ibdev_dbg(pd->device, "PD[%u] %s: " fmt, pd->res.id, __func__, \ 715 ##__VA_ARGS__) 716 717 #define siw_dbg_mem(mem, fmt, ...) \ 718 ibdev_dbg(&mem->sdev->base_dev, \ 719 "MEM[0x%08x] %s: " fmt, mem->stag, __func__, ##__VA_ARGS__) 720 721 #define siw_dbg_cep(cep, fmt, ...) \ 722 ibdev_dbg(&cep->sdev->base_dev, "CEP[0x%p] %s: " fmt, \ 723 cep, __func__, ##__VA_ARGS__) 724 725 void siw_cq_flush(struct siw_cq *cq); 726 void siw_sq_flush(struct siw_qp *qp); 727 void siw_rq_flush(struct siw_qp *qp); 728 int siw_reap_cqe(struct siw_cq *cq, struct ib_wc *wc); 729 730 #endif 731