xref: /linux/drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h (revision db5d28c0bfe566908719bec8e25443aabecbb802)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef __BXT_DPIO_PHY_REGS_H__
7 #define __BXT_DPIO_PHY_REGS_H__
8 
9 #include "intel_display_reg_defs.h"
10 
11 /* BXT PHY registers */
12 #define _BXT_PHY0_BASE			0x6C000
13 #define _BXT_PHY1_BASE			0x162000
14 #define _BXT_PHY2_BASE			0x163000
15 #define BXT_PHY_BASE(phy) \
16 	 _PICK_EVEN_2RANGES(phy, 1, \
17 			    _BXT_PHY0_BASE, _BXT_PHY0_BASE, \
18 			    _BXT_PHY1_BASE, _BXT_PHY2_BASE)
19 
20 #define _BXT_PHY(phy, reg) \
21 	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
22 
23 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
24 	(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
25 					 (reg_ch1) - _BXT_PHY0_BASE))
26 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
27 	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
28 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 + \
29 					  ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \
31 	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
32 
33 /* BXT PHY PLL registers */
34 #define _PORT_PLL_A			0x46074
35 #define _PORT_PLL_B			0x46078
36 #define _PORT_PLL_C			0x4607c
37 #define   PORT_PLL_ENABLE		REG_BIT(31)
38 #define   PORT_PLL_LOCK			REG_BIT(30)
39 #define   PORT_PLL_REF_SEL		REG_BIT(27)
40 #define   PORT_PLL_POWER_ENABLE		REG_BIT(26)
41 #define   PORT_PLL_POWER_STATE		REG_BIT(25)
42 #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
43 
44 #define _PORT_PLL_EBB_0_A		0x162034
45 #define _PORT_PLL_EBB_0_B		0x6C034
46 #define _PORT_PLL_EBB_0_C		0x6C340
47 #define   PORT_PLL_P1_MASK		REG_GENMASK(15, 13)
48 #define   PORT_PLL_P1(p1)		REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
49 #define   PORT_PLL_P2_MASK		REG_GENMASK(12, 8)
50 #define   PORT_PLL_P2(p2)		REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
51 #define BXT_PORT_PLL_EBB_0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
52 							 _PORT_PLL_EBB_0_B, \
53 							 _PORT_PLL_EBB_0_C)
54 
55 #define _PORT_PLL_EBB_4_A		0x162038
56 #define _PORT_PLL_EBB_4_B		0x6C038
57 #define _PORT_PLL_EBB_4_C		0x6C344
58 #define   PORT_PLL_RECALIBRATE		REG_BIT(14)
59 #define   PORT_PLL_10BIT_CLK_ENABLE	REG_BIT(13)
60 #define BXT_PORT_PLL_EBB_4(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
61 							 _PORT_PLL_EBB_4_B, \
62 							 _PORT_PLL_EBB_4_C)
63 
64 #define _PORT_PLL_0_A			0x162100
65 #define _PORT_PLL_0_B			0x6C100
66 #define _PORT_PLL_0_C			0x6C380
67 /* PORT_PLL_0_A */
68 #define   PORT_PLL_M2_INT_MASK		REG_GENMASK(7, 0)
69 #define   PORT_PLL_M2_INT(m2_int)	REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
70 /* PORT_PLL_1_A */
71 #define   PORT_PLL_N_MASK		REG_GENMASK(11, 8)
72 #define   PORT_PLL_N(n)			REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
73 /* PORT_PLL_2_A */
74 #define   PORT_PLL_M2_FRAC_MASK		REG_GENMASK(21, 0)
75 #define   PORT_PLL_M2_FRAC(m2_frac)	REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
76 /* PORT_PLL_3_A */
77 #define   PORT_PLL_M2_FRAC_ENABLE	REG_BIT(16)
78 /* PORT_PLL_6_A */
79 #define   PORT_PLL_GAIN_CTL_MASK	REG_GENMASK(18, 16)
80 #define   PORT_PLL_GAIN_CTL(x)		REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
81 #define   PORT_PLL_INT_COEFF_MASK	REG_GENMASK(12, 8)
82 #define   PORT_PLL_INT_COEFF(x)		REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
83 #define   PORT_PLL_PROP_COEFF_MASK	REG_GENMASK(3, 0)
84 #define   PORT_PLL_PROP_COEFF(x)	REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
85 /* PORT_PLL_8_A */
86 #define   PORT_PLL_TARGET_CNT_MASK	REG_GENMASK(9, 0)
87 #define   PORT_PLL_TARGET_CNT(x)	REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
88 /* PORT_PLL_9_A */
89 #define  PORT_PLL_LOCK_THRESHOLD_MASK	REG_GENMASK(3, 1)
90 #define  PORT_PLL_LOCK_THRESHOLD(x)	REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
91 /* PORT_PLL_10_A */
92 #define  PORT_PLL_DCO_AMP_OVR_EN_H	REG_BIT(27)
93 #define  PORT_PLL_DCO_AMP_MASK		REG_GENMASK(13, 10)
94 #define  PORT_PLL_DCO_AMP(x)		REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
95 #define _PORT_PLL_BASE(phy, ch)		_BXT_PHY_CH(phy, ch, \
96 						    _PORT_PLL_0_B, \
97 						    _PORT_PLL_0_C)
98 #define BXT_PORT_PLL(phy, ch, idx)	_MMIO(_PORT_PLL_BASE(phy, ch) + \
99 					      (idx) * 4)
100 
101 /* BXT PHY common lane registers */
102 #define _PORT_CL1CM_DW0_A		0x162000
103 #define _PORT_CL1CM_DW0_BC		0x6C000
104 #define   PHY_POWER_GOOD		REG_BIT(16)
105 #define   PHY_RESERVED			REG_BIT(7)
106 #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
107 
108 #define _PORT_CL1CM_DW9_A		0x162024
109 #define _PORT_CL1CM_DW9_BC		0x6C024
110 #define   IREF0RC_OFFSET_MASK		REG_GENMASK(15, 8)
111 #define   IREF0RC_OFFSET(x)		REG_FIELD_PREP(IREF0RC_OFFSET_MASK, (x))
112 #define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
113 
114 #define _PORT_CL1CM_DW10_A		0x162028
115 #define _PORT_CL1CM_DW10_BC		0x6C028
116 #define   IREF1RC_OFFSET_MASK		REG_GENMASK(15, 8)
117 #define   IREF1RC_OFFSET(x)		REG_FIELD_PREP(IREF1RC_OFFSET_MASK, (x))
118 #define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
119 
120 #define _PORT_CL1CM_DW28_A		0x162070
121 #define _PORT_CL1CM_DW28_BC		0x6C070
122 #define   OCL1_POWER_DOWN_EN		REG_BIT(23)
123 #define   DW28_OLDO_DYN_PWR_DOWN_EN	REG_BIT(22)
124 #define   SUS_CLK_CONFIG		REG_GENMASK(1, 0)
125 #define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
126 
127 #define _PORT_CL1CM_DW30_A		0x162078
128 #define _PORT_CL1CM_DW30_BC		0x6C078
129 #define   OCL2_LDOFUSE_PWR_DIS		REG_BIT(6)
130 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
131 
132 /* The spec defines this only for BXT PHY0, but lets assume that this
133  * would exist for PHY1 too if it had a second channel.
134  */
135 #define _PORT_CL2CM_DW6_A		0x162358
136 #define _PORT_CL2CM_DW6_BC		0x6C358
137 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
138 #define   DW6_OLDO_DYN_PWR_DOWN_EN	REG_BIT(28)
139 
140 /* BXT PHY Ref registers */
141 #define _PORT_REF_DW3_A			0x16218C
142 #define _PORT_REF_DW3_BC		0x6C18C
143 #define   GRC_DONE			REG_BIT(22)
144 #define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC)
145 
146 #define _PORT_REF_DW6_A			0x162198
147 #define _PORT_REF_DW6_BC		0x6C198
148 #define   GRC_CODE_MASK			REG_GENMASK(31, 24)
149 #define   GRC_CODE(x)			REG_FIELD_PREP(GRC_CODE_MASK, (x))
150 #define   GRC_CODE_FAST_MASK		REG_GENMASK(23, 16)
151 #define   GRC_CODE_FAST(x)		REG_FIELD_PREP(GRC_CODE_FAST_MASK, (x))
152 #define   GRC_CODE_SLOW_MASK		REG_GENMASK(15, 8)
153 #define   GRC_CODE_SLOW(x)		REG_FIELD_PREP(GRC_CODE_SLOW_MASK, (x))
154 #define   GRC_CODE_NOM_MASK		REG_GENMASK(7, 0)
155 #define   GRC_CODE_NOM(x)		REG_FIELD_PREP(GRC_CODE_NOM_MASK, (x))
156 #define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC)
157 
158 #define _PORT_REF_DW8_A			0x1621A0
159 #define _PORT_REF_DW8_BC		0x6C1A0
160 #define   GRC_DIS			REG_BIT(15)
161 #define   GRC_RDY_OVRD			REG_BIT(1)
162 #define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC)
163 
164 /* BXT PHY PCS registers */
165 #define _PORT_PCS_DW10_LN01_A		0x162428
166 #define _PORT_PCS_DW10_LN01_B		0x6C428
167 #define _PORT_PCS_DW10_LN01_C		0x6C828
168 #define _PORT_PCS_DW10_GRP_A		0x162C28
169 #define _PORT_PCS_DW10_GRP_B		0x6CC28
170 #define _PORT_PCS_DW10_GRP_C		0x6CE28
171 #define BXT_PORT_PCS_DW10_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
172 							 _PORT_PCS_DW10_LN01_B, \
173 							 _PORT_PCS_DW10_LN01_C)
174 #define BXT_PORT_PCS_DW10_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
175 							 _PORT_PCS_DW10_GRP_B, \
176 							 _PORT_PCS_DW10_GRP_C)
177 
178 #define   TX2_SWING_CALC_INIT		REG_BIT(31)
179 #define   TX1_SWING_CALC_INIT		REG_BIT(30)
180 
181 #define _PORT_PCS_DW12_LN01_A		0x162430
182 #define _PORT_PCS_DW12_LN01_B		0x6C430
183 #define _PORT_PCS_DW12_LN01_C		0x6C830
184 #define _PORT_PCS_DW12_LN23_A		0x162630
185 #define _PORT_PCS_DW12_LN23_B		0x6C630
186 #define _PORT_PCS_DW12_LN23_C		0x6CA30
187 #define _PORT_PCS_DW12_GRP_A		0x162c30
188 #define _PORT_PCS_DW12_GRP_B		0x6CC30
189 #define _PORT_PCS_DW12_GRP_C		0x6CE30
190 #define   LANESTAGGER_STRAP_OVRD	REG_BIT(6)
191 #define   LANE_STAGGER_MASK		REG_GENMASK(4, 0)
192 #define BXT_PORT_PCS_DW12_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
193 							 _PORT_PCS_DW12_LN01_B, \
194 							 _PORT_PCS_DW12_LN01_C)
195 #define BXT_PORT_PCS_DW12_LN23(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
196 							 _PORT_PCS_DW12_LN23_B, \
197 							 _PORT_PCS_DW12_LN23_C)
198 #define BXT_PORT_PCS_DW12_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
199 							 _PORT_PCS_DW12_GRP_B, \
200 							 _PORT_PCS_DW12_GRP_C)
201 
202 /* BXT PHY TX registers */
203 #define _PORT_TX_DW2_LN0_A		0x162508
204 #define _PORT_TX_DW2_LN0_B		0x6C508
205 #define _PORT_TX_DW2_LN0_C		0x6C908
206 #define _PORT_TX_DW2_GRP_A		0x162D08
207 #define _PORT_TX_DW2_GRP_B		0x6CD08
208 #define _PORT_TX_DW2_GRP_C		0x6CF08
209 #define BXT_PORT_TX_DW2_LN(phy, ch, lane)	_MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
210 								    _PORT_TX_DW2_LN0_B,	\
211 								    _PORT_TX_DW2_LN0_C)
212 #define BXT_PORT_TX_DW2_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
213 							 _PORT_TX_DW2_GRP_B, \
214 							 _PORT_TX_DW2_GRP_C)
215 #define   MARGIN_000_MASK		REG_GENMASK(23, 16)
216 #define   MARGIN_000(x)			REG_FIELD_PREP(MARGIN_000_MASK, (x))
217 #define   UNIQ_TRANS_SCALE_MASK		REG_GENMASK(15, 8)
218 #define   UNIQ_TRANS_SCALE(x)		REG_FIELD_PREP(UNIQ_TRANS_SCALE_MASK, (x))
219 
220 #define _PORT_TX_DW3_LN0_A		0x16250C
221 #define _PORT_TX_DW3_LN0_B		0x6C50C
222 #define _PORT_TX_DW3_LN0_C		0x6C90C
223 #define _PORT_TX_DW3_GRP_A		0x162D0C
224 #define _PORT_TX_DW3_GRP_B		0x6CD0C
225 #define _PORT_TX_DW3_GRP_C		0x6CF0C
226 #define BXT_PORT_TX_DW3_LN(phy, ch, lane)	_MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
227 								    _PORT_TX_DW3_LN0_B, \
228 								    _PORT_TX_DW3_LN0_C)
229 #define BXT_PORT_TX_DW3_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
230 							 _PORT_TX_DW3_GRP_B, \
231 							 _PORT_TX_DW3_GRP_C)
232 #define   SCALE_DCOMP_METHOD		REG_BIT(26)
233 #define   UNIQUE_TRANGE_EN_METHOD	REG_BIT(27)
234 
235 #define _PORT_TX_DW4_LN0_A		0x162510
236 #define _PORT_TX_DW4_LN0_B		0x6C510
237 #define _PORT_TX_DW4_LN0_C		0x6C910
238 #define _PORT_TX_DW4_GRP_A		0x162D10
239 #define _PORT_TX_DW4_GRP_B		0x6CD10
240 #define _PORT_TX_DW4_GRP_C		0x6CF10
241 #define BXT_PORT_TX_DW4_LN(phy, ch, lane)	_MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
242 								    _PORT_TX_DW4_LN0_B, \
243 								    _PORT_TX_DW4_LN0_C)
244 #define BXT_PORT_TX_DW4_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
245 							 _PORT_TX_DW4_GRP_B, \
246 							 _PORT_TX_DW4_GRP_C)
247 #define   DE_EMPHASIS_MASK		REG_GENMASK(31, 24)
248 #define   DE_EMPHASIS(x)		REG_FIELD_PREP(DE_EMPHASIS_MASK, (x))
249 
250 #define _PORT_TX_DW5_LN0_A		0x162514
251 #define _PORT_TX_DW5_LN0_B		0x6C514
252 #define _PORT_TX_DW5_LN0_C		0x6C914
253 #define _PORT_TX_DW5_GRP_A		0x162D14
254 #define _PORT_TX_DW5_GRP_B		0x6CD14
255 #define _PORT_TX_DW5_GRP_C		0x6CF14
256 #define BXT_PORT_TX_DW5_LN(phy, ch, lane)	_MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
257 								    _PORT_TX_DW5_LN0_B, \
258 								    _PORT_TX_DW5_LN0_C)
259 #define BXT_PORT_TX_DW5_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
260 							 _PORT_TX_DW5_GRP_B, \
261 							 _PORT_TX_DW5_GRP_C)
262 #define   DCC_DELAY_RANGE_1		REG_BIT(9)
263 #define   DCC_DELAY_RANGE_2		REG_BIT(8)
264 
265 #define _PORT_TX_DW14_LN0_A		0x162538
266 #define _PORT_TX_DW14_LN0_B		0x6C538
267 #define _PORT_TX_DW14_LN0_C		0x6C938
268 #define   LATENCY_OPTIM			REG_BIT(30)
269 #define BXT_PORT_TX_DW14_LN(phy, ch, lane)	_MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
270 								    _PORT_TX_DW14_LN0_B, \
271 								    _PORT_TX_DW14_LN0_C)
272 
273 #endif /* __BXT_DPIO_PHY_REGS_H__ */
274