1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2024 Intel Corporation 4 */ 5 6 #ifndef __SKL_UNIVERSAL_PLANE_REGS_H__ 7 #define __SKL_UNIVERSAL_PLANE_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ 12 _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b))) 13 #define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ 14 (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4) 15 #define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ 16 _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) 17 #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ 18 _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) 19 20 #define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ 21 _PICK_EVEN_2RANGES((plane), PLANE_5, \ 22 _PIPE((pipe), (reg_1_a), (reg_1_b)), \ 23 _PIPE((pipe), (reg_2_a), (reg_2_b)), \ 24 _PIPE((pipe), (reg_5_a), (reg_5_b)), \ 25 _PIPE((pipe), (reg_6_a), (reg_6_b))) 26 #define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ 27 _MMIO(_SEL_FETCH((pipe), (plane), \ 28 (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b), \ 29 (reg_5_a), (reg_5_b), (reg_6_a), (reg_6_b))) 30 31 #define _PLANE_CTL_1_A 0x70180 32 #define _PLANE_CTL_2_A 0x70280 33 #define _PLANE_CTL_1_B 0x71180 34 #define _PLANE_CTL_2_B 0x71280 35 #define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 36 _PLANE_CTL_1_A, _PLANE_CTL_1_B, \ 37 _PLANE_CTL_2_A, _PLANE_CTL_2_B) 38 #define PLANE_CTL_ENABLE REG_BIT(31) 39 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 40 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 41 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 42 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 43 /* 44 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 45 * expanded to include bit 23 as well. However, the shift-24 based values 46 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 47 */ 48 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 49 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 50 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 51 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 52 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 53 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 54 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 55 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 56 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 57 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 58 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 59 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 60 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 61 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 62 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 63 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 64 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 65 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 66 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 67 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 68 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 69 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 70 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 71 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 72 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 73 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 74 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 75 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 76 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 77 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 78 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 79 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 80 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 81 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 82 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 83 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 84 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 85 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 86 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 87 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 88 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 89 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 90 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 91 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 92 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 93 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 94 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 95 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 96 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 97 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 98 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 99 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 100 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 101 102 #define _PLANE_STRIDE_1_A 0x70188 103 #define _PLANE_STRIDE_2_A 0x70288 104 #define _PLANE_STRIDE_1_B 0x71188 105 #define _PLANE_STRIDE_2_B 0x71288 106 #define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 107 _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \ 108 _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 109 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 110 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 111 112 #define _PLANE_POS_1_A 0x7018c 113 #define _PLANE_POS_2_A 0x7028c 114 #define _PLANE_POS_1_B 0x7118c 115 #define _PLANE_POS_2_B 0x7128c 116 #define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 117 _PLANE_POS_1_A, _PLANE_POS_1_B, \ 118 _PLANE_POS_2_A, _PLANE_POS_2_B) 119 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 120 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 121 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 122 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 123 124 #define _PLANE_SIZE_1_A 0x70190 125 #define _PLANE_SIZE_2_A 0x70290 126 #define _PLANE_SIZE_1_B 0x71190 127 #define _PLANE_SIZE_2_B 0x71290 128 #define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 129 _PLANE_SIZE_1_A, _PLANE_SIZE_1_B, \ 130 _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 131 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 132 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 133 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 134 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 135 136 #define _PLANE_KEYVAL_1_A 0x70194 137 #define _PLANE_KEYVAL_2_A 0x70294 138 #define _PLANE_KEYVAL_1_B 0x71194 139 #define _PLANE_KEYVAL_2_B 0x71294 140 #define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\ 141 _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B, \ 142 _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 143 144 #define _PLANE_KEYMSK_1_A 0x70198 145 #define _PLANE_KEYMSK_2_A 0x70298 146 #define _PLANE_KEYMSK_1_B 0x71198 147 #define _PLANE_KEYMSK_2_B 0x71298 148 #define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 149 _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B, \ 150 _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 151 #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) 152 153 #define _PLANE_SURF_1_A 0x7019c 154 #define _PLANE_SURF_2_A 0x7029c 155 #define _PLANE_SURF_1_B 0x7119c 156 #define _PLANE_SURF_2_B 0x7129c 157 #define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 158 _PLANE_SURF_1_A, _PLANE_SURF_1_B, \ 159 _PLANE_SURF_2_A, _PLANE_SURF_2_B) 160 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 161 #define PLANE_SURF_DECRYPT REG_BIT(2) 162 163 #define _PLANE_KEYMAX_1_A 0x701a0 164 #define _PLANE_KEYMAX_2_A 0x702a0 165 #define _PLANE_KEYMAX_1_B 0x711a0 166 #define _PLANE_KEYMAX_2_B 0x712a0 167 #define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 168 _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B, \ 169 _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 170 #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) 171 #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) 172 173 #define _PLANE_OFFSET_1_A 0x701a4 174 #define _PLANE_OFFSET_2_A 0x702a4 175 #define _PLANE_OFFSET_1_B 0x711a4 176 #define _PLANE_OFFSET_2_B 0x712a4 177 #define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 178 _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B, \ 179 _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 180 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 181 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 182 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 183 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 184 185 #define _PLANE_SURFLIVE_1_A 0x701ac 186 #define _PLANE_SURFLIVE_2_A 0x702ac 187 #define _PLANE_SURFLIVE_1_B 0x711ac 188 #define _PLANE_SURFLIVE_2_B 0x712ac 189 #define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 190 _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B, \ 191 _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) 192 193 #define _PLANE_CC_VAL_1_A 0x701b4 194 #define _PLANE_CC_VAL_2_A 0x702b4 195 #define _PLANE_CC_VAL_1_B 0x711b4 196 #define _PLANE_CC_VAL_2_B 0x712b4 197 #define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \ 198 _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B, \ 199 _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) 200 201 #define _PLANE_AUX_DIST_1_A 0x701c0 202 #define _PLANE_AUX_DIST_2_A 0x702c0 203 #define _PLANE_AUX_DIST_1_B 0x711c0 204 #define _PLANE_AUX_DIST_2_B 0x712c0 205 #define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 206 _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B, \ 207 _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 208 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 209 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 210 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 211 212 #define _PLANE_AUX_OFFSET_1_A 0x701c4 213 #define _PLANE_AUX_OFFSET_2_A 0x702c4 214 #define _PLANE_AUX_OFFSET_1_B 0x711c4 215 #define _PLANE_AUX_OFFSET_2_B 0x712c4 216 #define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 217 _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B, \ 218 _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 219 220 #define _PLANE_CUS_CTL_1_A 0x701c8 221 #define _PLANE_CUS_CTL_2_A 0x702c8 222 #define _PLANE_CUS_CTL_1_B 0x711c8 223 #define _PLANE_CUS_CTL_2_B 0x712c8 224 #define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 225 _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B, \ 226 _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 227 #define PLANE_CUS_ENABLE REG_BIT(31) 228 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 229 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 230 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 231 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 232 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 233 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 234 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 235 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 236 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 237 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 238 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 239 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 240 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 241 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 242 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 243 244 #define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */ 245 #define _PLANE_COLOR_CTL_2_A 0x702cc 246 #define _PLANE_COLOR_CTL_1_B 0x711cc 247 #define _PLANE_COLOR_CTL_2_B 0x712cc 248 #define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 249 _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B, \ 250 _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 251 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 252 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 253 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 254 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 255 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 256 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 257 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 258 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 259 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 260 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 261 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 262 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 263 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 264 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 265 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 266 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 267 268 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0 269 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0 270 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0 271 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0 272 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ 273 _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B, \ 274 _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B) 275 276 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8 277 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8 278 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8 279 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8 280 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ 281 _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B, \ 282 _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B) 283 284 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 285 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 286 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 287 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 288 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ 289 _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \ 290 _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 291 292 #define _PLANE_CSC_RY_GY_1_A 0x70210 293 #define _PLANE_CSC_RY_GY_2_A 0x70310 294 #define _PLANE_CSC_RY_GY_1_B 0x71210 295 #define _PLANE_CSC_RY_GY_2_B 0x71310 296 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ 297 _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B, \ 298 _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B) 299 300 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 301 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 302 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 303 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 304 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ 305 _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B, \ 306 _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B) 307 308 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 309 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 310 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 311 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 312 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ 313 _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B, \ 314 _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B) 315 #define _PLANE_WM_1_A_0 0x70240 316 #define _PLANE_WM_1_B_0 0x71240 317 #define _PLANE_WM_2_A_0 0x70340 318 #define _PLANE_WM_2_B_0 0x71340 319 #define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \ 320 _PLANE_WM_1_A_0, _PLANE_WM_1_B_0, \ 321 _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 322 #define PLANE_WM_EN REG_BIT(31) 323 #define PLANE_WM_IGNORE_LINES REG_BIT(30) 324 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) 325 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) 326 327 #define _PLANE_WM_SAGV_1_A 0x70258 328 #define _PLANE_WM_SAGV_1_B 0x71258 329 #define _PLANE_WM_SAGV_2_A 0x70358 330 #define _PLANE_WM_SAGV_2_B 0x71358 331 #define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 332 _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B, \ 333 _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) 334 335 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025c 336 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125c 337 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035c 338 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135c 339 #define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 340 _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B, \ 341 _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) 342 343 #define _PLANE_WM_TRANS_1_A 0x70268 344 #define _PLANE_WM_TRANS_1_B 0x71268 345 #define _PLANE_WM_TRANS_2_A 0x70368 346 #define _PLANE_WM_TRANS_2_B 0x71368 347 #define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 348 _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B, \ 349 _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) 350 351 #define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */ 352 #define _PLANE_CHICKEN_2_A 0x7036c 353 #define _PLANE_CHICKEN_1_B 0x7126c 354 #define _PLANE_CHICKEN_2_B 0x7136c 355 #define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 356 _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B, \ 357 _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) 358 #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ 359 360 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 361 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 362 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 363 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 364 #define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 365 _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B, \ 366 _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 367 368 #define _PLANE_BUF_CFG_1_A 0x7027c 369 #define _PLANE_BUF_CFG_2_A 0x7037c 370 #define _PLANE_BUF_CFG_1_B 0x7127c 371 #define _PLANE_BUF_CFG_2_B 0x7137c 372 #define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ 373 _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \ 374 _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 375 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 376 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 377 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 378 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 379 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 380 381 /* tgl+ */ 382 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 383 #define _SEL_FETCH_PLANE_CTL_2_A 0x708b0 384 #define _SEL_FETCH_PLANE_CTL_5_A 0x70920 385 #define _SEL_FETCH_PLANE_CTL_6_A 0x70940 386 #define _SEL_FETCH_PLANE_CTL_1_B 0x71890 387 #define _SEL_FETCH_PLANE_CTL_2_B 0x718b0 388 #define _SEL_FETCH_PLANE_CTL_5_B 0x71920 389 #define _SEL_FETCH_PLANE_CTL_6_B 0x71940 390 #define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ 391 _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \ 392 _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \ 393 _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \ 394 _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B) 395 #define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) 396 397 /* tgl+ */ 398 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 399 #define _SEL_FETCH_PLANE_POS_2_A 0x708b4 400 #define _SEL_FETCH_PLANE_POS_5_A 0x70924 401 #define _SEL_FETCH_PLANE_POS_6_A 0x70944 402 #define _SEL_FETCH_PLANE_POS_1_B 0x71894 403 #define _SEL_FETCH_PLANE_POS_2_B 0x718b4 404 #define _SEL_FETCH_PLANE_POS_5_B 0x71924 405 #define _SEL_FETCH_PLANE_POS_6_B 0x71944 406 #define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ 407 _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ 408 _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ 409 _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ 410 _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) 411 412 /* tgl+ */ 413 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 414 #define _SEL_FETCH_PLANE_SIZE_2_A 0x708b8 415 #define _SEL_FETCH_PLANE_SIZE_5_A 0x70928 416 #define _SEL_FETCH_PLANE_SIZE_6_A 0x70948 417 #define _SEL_FETCH_PLANE_SIZE_1_B 0x71898 418 #define _SEL_FETCH_PLANE_SIZE_2_B 0x718b8 419 #define _SEL_FETCH_PLANE_SIZE_5_B 0x71928 420 #define _SEL_FETCH_PLANE_SIZE_6_B 0x71948 421 #define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ 422 _SEL_FETCH_PLANE_SIZE_1_A, _SEL_FETCH_PLANE_SIZE_1_B, \ 423 _SEL_FETCH_PLANE_SIZE_2_A, _SEL_FETCH_PLANE_SIZE_2_B, \ 424 _SEL_FETCH_PLANE_SIZE_5_A, _SEL_FETCH_PLANE_SIZE_5_B, \ 425 _SEL_FETCH_PLANE_SIZE_6_A, _SEL_FETCH_PLANE_SIZE_6_B) 426 427 /* tgl+ */ 428 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089c 429 #define _SEL_FETCH_PLANE_OFFSET_2_A 0x708bc 430 #define _SEL_FETCH_PLANE_OFFSET_5_A 0x7092c 431 #define _SEL_FETCH_PLANE_OFFSET_6_A 0x7094c 432 #define _SEL_FETCH_PLANE_OFFSET_1_B 0x7189c 433 #define _SEL_FETCH_PLANE_OFFSET_2_B 0x718bc 434 #define _SEL_FETCH_PLANE_OFFSET_5_B 0x7192c 435 #define _SEL_FETCH_PLANE_OFFSET_6_B 0x7194c 436 #define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ 437 _SEL_FETCH_PLANE_OFFSET_1_A, _SEL_FETCH_PLANE_OFFSET_1_B, \ 438 _SEL_FETCH_PLANE_OFFSET_2_A, _SEL_FETCH_PLANE_OFFSET_2_B, \ 439 _SEL_FETCH_PLANE_OFFSET_5_A, _SEL_FETCH_PLANE_OFFSET_5_B, \ 440 _SEL_FETCH_PLANE_OFFSET_6_A, _SEL_FETCH_PLANE_OFFSET_6_B) 441 442 #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */ 443