1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_COLOR_REGS_H__ 7 #define __INTEL_COLOR_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 /* GMCH palette */ 12 #define _PALETTE_A 0xa000 13 #define _PALETTE_B 0xa800 14 #define _CHV_PALETTE_C 0xc000 15 /* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ 16 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 17 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 18 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 19 /* pre-i965 10bit interpolated mode ldw */ 20 #define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) 21 #define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) 22 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) 23 /* pre-i965 10bit interpolated mode udw */ 24 #define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) 25 #define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) 26 #define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) 27 #define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) 28 #define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) 29 #define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) 30 #define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) 31 #define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) 32 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) 33 #define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 34 _PICK_EVEN_2RANGES(pipe, 2, \ 35 _PALETTE_A, _PALETTE_B, \ 36 _CHV_PALETTE_C, _CHV_PALETTE_C) + \ 37 (i) * 4) 38 39 /* i965/g4x/vlv/chv */ 40 #define _PIPEAGCMAX 0x70010 41 #define _PIPEBGCMAX 0x71010 42 #define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ 43 44 /* ilk+ palette */ 45 #define _LGC_PALETTE_A 0x4a000 46 #define _LGC_PALETTE_B 0x4a800 47 /* see PALETTE_* for the bits */ 48 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 49 50 /* ilk/snb precision palette */ 51 #define _PREC_PALETTE_A 0x4b000 52 #define _PREC_PALETTE_B 0x4c000 53 /* 10bit mode */ 54 #define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20) 55 #define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10) 56 #define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0) 57 /* 12.4 interpolated mode ldw */ 58 #define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24) 59 #define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14) 60 #define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4) 61 /* 12.4 interpolated mode udw */ 62 #define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20) 63 #define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10) 64 #define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0) 65 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 66 67 #define _PREC_PIPEAGCMAX 0x4d000 68 #define _PREC_PIPEBGCMAX 0x4d010 69 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */ 70 71 #define _GAMMA_MODE_A 0x4a480 72 #define _GAMMA_MODE_B 0x4ac80 73 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 74 #define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */ 75 #define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */ 76 #define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */ 77 #define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0) 78 #define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0) 79 #define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1) 80 #define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2) 81 #define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */ 82 #define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */ 83 84 /* pipe CSC */ 85 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 86 #define _PIPE_A_CSC_COEFF_BY 0x49014 87 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 88 #define _PIPE_A_CSC_COEFF_BU 0x4901c 89 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 90 #define _PIPE_A_CSC_COEFF_BV 0x49024 91 92 #define _PIPE_A_CSC_MODE 0x49028 93 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 94 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 95 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 96 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 97 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 98 99 #define _PIPE_A_CSC_PREOFF_HI 0x49030 100 #define _PIPE_A_CSC_PREOFF_ME 0x49034 101 #define _PIPE_A_CSC_PREOFF_LO 0x49038 102 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 103 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 104 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 105 106 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 107 #define _PIPE_B_CSC_COEFF_BY 0x49114 108 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 109 #define _PIPE_B_CSC_COEFF_BU 0x4911c 110 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 111 #define _PIPE_B_CSC_COEFF_BV 0x49124 112 #define _PIPE_B_CSC_MODE 0x49128 113 #define _PIPE_B_CSC_PREOFF_HI 0x49130 114 #define _PIPE_B_CSC_PREOFF_ME 0x49134 115 #define _PIPE_B_CSC_PREOFF_LO 0x49138 116 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 117 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 118 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 119 120 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 121 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 122 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 123 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 124 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 125 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 126 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 127 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 128 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 129 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 130 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 131 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 132 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 133 134 /* Pipe Output CSC */ 135 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 136 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 137 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 138 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 139 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 140 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 141 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 142 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 143 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 144 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 145 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 146 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 147 148 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 149 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 150 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 151 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 152 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 153 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 154 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 155 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 156 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 157 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 158 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 159 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 160 161 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 162 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 163 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 164 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 165 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 166 _PIPE_B_OUTPUT_CSC_COEFF_BY) 167 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 168 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 169 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 170 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 171 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 172 _PIPE_B_OUTPUT_CSC_COEFF_BU) 173 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 174 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 175 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 176 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 177 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 178 _PIPE_B_OUTPUT_CSC_COEFF_BV) 179 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 180 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 181 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 182 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 183 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 184 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 185 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 186 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 187 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 188 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 189 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 190 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 191 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 192 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 193 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 194 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 195 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 196 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 197 198 /* pipe degamma/gamma LUTs on IVB+ */ 199 #define _PAL_PREC_INDEX_A 0x4A400 200 #define _PAL_PREC_INDEX_B 0x4AC00 201 #define _PAL_PREC_INDEX_C 0x4B400 202 #define PAL_PREC_SPLIT_MODE REG_BIT(31) 203 #define PAL_PREC_AUTO_INCREMENT REG_BIT(15) 204 #define PAL_PREC_INDEX_VALUE_MASK REG_GENMASK(9, 0) 205 #define PAL_PREC_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_INDEX_VALUE_MASK, (x)) 206 #define _PAL_PREC_DATA_A 0x4A404 207 #define _PAL_PREC_DATA_B 0x4AC04 208 #define _PAL_PREC_DATA_C 0x4B404 209 /* see PREC_PALETTE_* for the bits */ 210 #define _PAL_PREC_GC_MAX_A 0x4A410 211 #define _PAL_PREC_GC_MAX_B 0x4AC10 212 #define _PAL_PREC_GC_MAX_C 0x4B410 213 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 214 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 215 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 216 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 217 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 218 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 219 220 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 221 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 222 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */ 223 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */ 224 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */ 225 226 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 227 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 228 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 229 #define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10) 230 #define PRE_CSC_GAMC_INDEX_VALUE_MASK REG_GENMASK(7, 0) 231 #define PRE_CSC_GAMC_INDEX_VALUE(x) REG_FIELD_PREP(PRE_CSC_GAMC_INDEX_VALUE_MASK, (x)) 232 #define _PRE_CSC_GAMC_DATA_A 0x4A488 233 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 234 #define _PRE_CSC_GAMC_DATA_C 0x4B488 235 236 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 237 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 238 239 /* ICL Multi segmented gamma */ 240 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 241 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 242 #define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15) 243 #define PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK REG_GENMASK(4, 0) 244 #define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x)) 245 246 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 247 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 248 /* see PREC_PALETTE_12P4_* for the bits */ 249 250 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 251 _PAL_PREC_MULTI_SEG_INDEX_A, \ 252 _PAL_PREC_MULTI_SEG_INDEX_B) 253 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 254 _PAL_PREC_MULTI_SEG_DATA_A, \ 255 _PAL_PREC_MULTI_SEG_DATA_B) 256 257 #define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */ 258 #define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */ 259 #define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */ 260 #define _PIPE_A_WGC_C12 0x600BC /* s2.10 */ 261 #define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */ 262 #define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */ 263 264 #define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00) 265 #define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02) 266 #define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10) 267 #define PIPE_WGC_C12(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12) 268 #define PIPE_WGC_C21_C20(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20) 269 #define PIPE_WGC_C22(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22) 270 271 /* pipe CSC & degamma/gamma LUTs on CHV */ 272 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 273 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 274 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 275 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 276 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 277 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 278 /* cgm degamma ldw */ 279 #define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16) 280 #define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0) 281 /* cgm degamma udw */ 282 #define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0) 283 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 284 /* cgm gamma ldw */ 285 #define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16) 286 #define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0) 287 /* cgm gamma udw */ 288 #define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0) 289 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 290 #define CGM_PIPE_MODE_GAMMA (1 << 2) 291 #define CGM_PIPE_MODE_CSC (1 << 1) 292 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 293 294 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 295 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 296 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 297 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 298 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 299 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 300 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 301 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 302 303 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 304 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 305 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 306 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 307 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 308 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 309 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 310 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 311 312 /* Skylake+ pipe bottom (background) color */ 313 #define _SKL_BOTTOM_COLOR_A 0x70034 314 #define _SKL_BOTTOM_COLOR_B 0x71034 315 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 316 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 317 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B) 318 319 #endif /* __INTEL_COLOR_REGS_H__ */ 320