1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ALPHA_PGTABLE_H
3 #define _ALPHA_PGTABLE_H
4
5 #include <asm-generic/pgtable-nopud.h>
6
7 /*
8 * This file contains the functions and defines necessary to modify and use
9 * the Alpha page table tree.
10 *
11 * This hopefully works with any standard Alpha page-size, as defined
12 * in <asm/page.h> (currently 8192).
13 */
14 #include <linux/mmzone.h>
15
16 #include <asm/page.h>
17 #include <asm/processor.h> /* For TASK_SIZE */
18 #include <asm/machvec.h>
19 #include <asm/setup.h>
20
21 struct mm_struct;
22 struct vm_area_struct;
23
24 /* Certain architectures need to do special things when PTEs
25 * within a page table are directly modified. Thus, the following
26 * hook is made available.
27 */
28 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
29
30 /* PMD_SHIFT determines the size of the area a second-level page table can map */
31 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
32 #define PMD_SIZE (1UL << PMD_SHIFT)
33 #define PMD_MASK (~(PMD_SIZE-1))
34
35 /* PGDIR_SHIFT determines what a third-level page table entry can map */
36 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
37 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
38 #define PGDIR_MASK (~(PGDIR_SIZE-1))
39
40 /*
41 * Entries per page directory level: the Alpha is three-level, with
42 * all levels having a one-page page table.
43 */
44 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
45 #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
46 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
47 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
48
49 /* Number of pointers that fit on a page: this will go away. */
50 #define PTRS_PER_PAGE (1UL << (PAGE_SHIFT-3))
51
52 #ifdef CONFIG_ALPHA_LARGE_VMALLOC
53 #define VMALLOC_START 0xfffffe0000000000
54 #else
55 #define VMALLOC_START (-2*PGDIR_SIZE)
56 #endif
57 #define VMALLOC_END (-PGDIR_SIZE)
58
59 /*
60 * OSF/1 PAL-code-imposed page table bits
61 */
62 #define _PAGE_VALID 0x0001
63 #define _PAGE_FOR 0x0002 /* used for page protection (fault on read) */
64 #define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */
65 #define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */
66 #define _PAGE_ASM 0x0010
67 #define _PAGE_KRE 0x0100 /* xxx - see below on the "accessed" bit */
68 #define _PAGE_URE 0x0200 /* xxx */
69 #define _PAGE_KWE 0x1000 /* used to do the dirty bit in software */
70 #define _PAGE_UWE 0x2000 /* used to do the dirty bit in software */
71
72 /* .. and these are ours ... */
73 #define _PAGE_DIRTY 0x20000
74 #define _PAGE_ACCESSED 0x40000
75
76 /* We borrow bit 39 to store the exclusive marker in swap PTEs. */
77 #define _PAGE_SWP_EXCLUSIVE 0x8000000000UL
78
79 /*
80 * NOTE! The "accessed" bit isn't necessarily exact: it can be kept exactly
81 * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
82 * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use
83 * the KRE/URE bits to watch for it. That way we don't need to overload the
84 * KWE/UWE bits with both handling dirty and accessed.
85 *
86 * Note that the kernel uses the accessed bit just to check whether to page
87 * out a page or not, so it doesn't have to be exact anyway.
88 */
89
90 #define __DIRTY_BITS (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
91 #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)
92
93 #define _PFN_MASK 0xFFFFFFFF00000000UL
94
95 #define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
96 #define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)
97
98 /*
99 * All the normal masks have the "page accessed" bits on, as any time they are used,
100 * the page is accessed. They are cleared only by the page-out routines
101 */
102 #define PAGE_NONE __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE)
103 #define PAGE_SHARED __pgprot(_PAGE_VALID | __ACCESS_BITS)
104 #define PAGE_COPY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
105 #define PAGE_READONLY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
106 #define PAGE_KERNEL __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE)
107
108 #define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x))
109
110 #define _PAGE_P(x) _PAGE_NORMAL((x) | _PAGE_FOW)
111 #define _PAGE_S(x) _PAGE_NORMAL(x)
112
113 /*
114 * The hardware can handle write-only mappings, but as the Alpha
115 * architecture does byte-wide writes with a read-modify-write
116 * sequence, it's not practical to have write-without-read privs.
117 * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in
118 * arch/alpha/mm/fault.c)
119 */
120 /* xwr */
121
122 /*
123 * pgprot_noncached() is only for infiniband pci support, and a real
124 * implementation for RAM would be more complicated.
125 */
126 #define pgprot_noncached(prot) (prot)
127
128 /*
129 * ZERO_PAGE is a global shared page that is always zero: used
130 * for zero-mapped memory areas etc..
131 */
132 #define ZERO_PAGE(vaddr) (virt_to_page(ZERO_PGE))
133
134 /*
135 * On certain platforms whose physical address space can overlap KSEG,
136 * namely EV6 and above, we must re-twiddle the physaddr to restore the
137 * correct high-order bits.
138 *
139 * This is extremely confusing until you realize that this is actually
140 * just working around a userspace bug. The X server was intending to
141 * provide the physical address but instead provided the KSEG address.
142 * Or tried to, except it's not representable.
143 *
144 * On Tsunami there's nothing meaningful at 0x40000000000, so this is
145 * a safe thing to do. Come the first core logic that does put something
146 * in this area -- memory or whathaveyou -- then this hack will have
147 * to go away. So be prepared!
148 */
149
150 #if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG)
151 #error "EV6-only feature in a generic kernel"
152 #endif
153 #if defined(CONFIG_ALPHA_GENERIC) || \
154 (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG))
155 #define KSEG_PFN (0xc0000000000UL >> PAGE_SHIFT)
156 #define PHYS_TWIDDLE(pfn) \
157 ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \
158 ? ((pfn) ^= KSEG_PFN) : (pfn))
159 #else
160 #define PHYS_TWIDDLE(pfn) (pfn)
161 #endif
162
163 /*
164 * Conversion functions: convert a page and protection to a page entry,
165 * and a page entry and page directory to the page they refer to.
166 */
167 #define page_to_pa(page) (page_to_pfn(page) << PAGE_SHIFT)
168 #define PFN_PTE_SHIFT 32
169 #define pte_pfn(pte) (pte_val(pte) >> PFN_PTE_SHIFT)
170
171 #define pte_page(pte) pfn_to_page(pte_pfn(pte))
172
pfn_pte(unsigned long physpfn,pgprot_t pgprot)173 extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot)
174 { pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; }
175
pte_modify(pte_t pte,pgprot_t newprot)176 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
177 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
178
pmd_set(pmd_t * pmdp,pte_t * ptep)179 extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
180 { pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
181
pud_set(pud_t * pudp,pmd_t * pmdp)182 extern inline void pud_set(pud_t * pudp, pmd_t * pmdp)
183 { pud_val(*pudp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
184
185
186 extern inline unsigned long
pmd_page_vaddr(pmd_t pmd)187 pmd_page_vaddr(pmd_t pmd)
188 {
189 return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET;
190 }
191
192 #define pmd_pfn(pmd) (pmd_val(pmd) >> 32)
193 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> 32))
194 #define pud_page(pud) (pfn_to_page(pud_val(pud) >> 32))
195
pud_pgtable(pud_t pgd)196 extern inline pmd_t *pud_pgtable(pud_t pgd)
197 {
198 return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)));
199 }
200
pte_none(pte_t pte)201 extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
pte_present(pte_t pte)202 extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; }
pte_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)203 extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
204 {
205 pte_val(*ptep) = 0;
206 }
207
pmd_none(pmd_t pmd)208 extern inline int pmd_none(pmd_t pmd) { return !pmd_val(pmd); }
pmd_bad(pmd_t pmd)209 extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; }
pmd_present(pmd_t pmd)210 extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _PAGE_VALID; }
pmd_clear(pmd_t * pmdp)211 extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; }
212
pud_none(pud_t pud)213 extern inline int pud_none(pud_t pud) { return !pud_val(pud); }
pud_bad(pud_t pud)214 extern inline int pud_bad(pud_t pud) { return (pud_val(pud) & ~_PFN_MASK) != _PAGE_TABLE; }
pud_present(pud_t pud)215 extern inline int pud_present(pud_t pud) { return pud_val(pud) & _PAGE_VALID; }
pud_clear(pud_t * pudp)216 extern inline void pud_clear(pud_t * pudp) { pud_val(*pudp) = 0; }
217
218 /*
219 * The following only work if pte_present() is true.
220 * Undefined behaviour if not..
221 */
pte_write(pte_t pte)222 extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_FOW); }
pte_dirty(pte_t pte)223 extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
pte_young(pte_t pte)224 extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
225
pte_wrprotect(pte_t pte)226 extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOW; return pte; }
pte_mkclean(pte_t pte)227 extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(__DIRTY_BITS); return pte; }
pte_mkold(pte_t pte)228 extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(__ACCESS_BITS); return pte; }
pte_mkwrite_novma(pte_t pte)229 extern inline pte_t pte_mkwrite_novma(pte_t pte){ pte_val(pte) &= ~_PAGE_FOW; return pte; }
pte_mkdirty(pte_t pte)230 extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; }
pte_mkyoung(pte_t pte)231 extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; }
232
233 /*
234 * The smp_rmb() in the following functions are required to order the load of
235 * *dir (the pointer in the top level page table) with any subsequent load of
236 * the returned pmd_t *ret (ret is data dependent on *dir).
237 *
238 * If this ordering is not enforced, the CPU might load an older value of
239 * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
240 * more details.
241 *
242 * Note that we never change the mm->pgd pointer after the task is running, so
243 * pgd_offset does not require such a barrier.
244 */
245
246 /* Find an entry in the second-level page table.. */
pmd_offset(pud_t * dir,unsigned long address)247 extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address)
248 {
249 pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
250 smp_rmb(); /* see above */
251 return ret;
252 }
253 #define pmd_offset pmd_offset
254
255 /* Find an entry in the third-level page table.. */
pte_offset_kernel(pmd_t * dir,unsigned long address)256 extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
257 {
258 pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
259 + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
260 smp_rmb(); /* see above */
261 return ret;
262 }
263 #define pte_offset_kernel pte_offset_kernel
264
265 extern pgd_t swapper_pg_dir[1024];
266
267 /*
268 * The Alpha doesn't have any external MMU info: the kernel page
269 * tables contain all the necessary information.
270 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)271 extern inline void update_mmu_cache(struct vm_area_struct * vma,
272 unsigned long address, pte_t *ptep)
273 {
274 }
275
update_mmu_cache_range(struct vm_fault * vmf,struct vm_area_struct * vma,unsigned long address,pte_t * ptep,unsigned int nr)276 static inline void update_mmu_cache_range(struct vm_fault *vmf,
277 struct vm_area_struct *vma, unsigned long address,
278 pte_t *ptep, unsigned int nr)
279 {
280 }
281
282 /*
283 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
284 * are !pte_none() && !pte_present().
285 *
286 * Format of swap PTEs:
287 *
288 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
289 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
290 * <------------------- offset ------------------> E <--- type -->
291 *
292 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
293 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
294 * <--------------------------- zeroes -------------------------->
295 *
296 * E is the exclusive marker that is not stored in swap entries.
297 */
mk_swap_pte(unsigned long type,unsigned long offset)298 extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
299 { pte_t pte; pte_val(pte) = ((type & 0x7f) << 32) | (offset << 40); return pte; }
300
301 #define __swp_type(x) (((x).val >> 32) & 0x7f)
302 #define __swp_offset(x) ((x).val >> 40)
303 #define __swp_entry(type, off) ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
304 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
305 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
306
pte_swp_exclusive(pte_t pte)307 static inline bool pte_swp_exclusive(pte_t pte)
308 {
309 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
310 }
311
pte_swp_mkexclusive(pte_t pte)312 static inline pte_t pte_swp_mkexclusive(pte_t pte)
313 {
314 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
315 return pte;
316 }
317
pte_swp_clear_exclusive(pte_t pte)318 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
319 {
320 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
321 return pte;
322 }
323
324 #define pte_ERROR(e) \
325 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
326 #define pmd_ERROR(e) \
327 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
328 #define pgd_ERROR(e) \
329 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
330
331 extern void paging_init(void);
332
333 /* We have our own get_unmapped_area */
334 #define HAVE_ARCH_UNMAPPED_AREA
335
336 #endif /* _ALPHA_PGTABLE_H */
337