xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h (revision 4db102dcb0396a4ccf89b1eac0f4eb3fd167a080)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2020-2022, Linaro Limited
4  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved
5  */
6 
7 #ifndef _DPU_HW_DSC_H
8 #define _DPU_HW_DSC_H
9 
10 #include <drm/display/drm_dsc.h>
11 
12 #define DSC_MODE_SPLIT_PANEL            BIT(0)
13 #define DSC_MODE_MULTIPLEX              BIT(1)
14 #define DSC_MODE_VIDEO                  BIT(2)
15 
16 struct dpu_hw_dsc;
17 
18 /**
19  * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
20  * Assumption is these functions will be called after clocks are enabled
21  */
22 struct dpu_hw_dsc_ops {
23 	/**
24 	 * dsc_disable - disable dsc
25 	 * @hw_dsc: Pointer to dsc context
26 	 */
27 	void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
28 
29 	/**
30 	 * dsc_config - configures dsc encoder
31 	 * @hw_dsc: Pointer to dsc context
32 	 * @dsc: panel dsc parameters
33 	 * @mode: dsc topology mode to be set
34 	 * @initial_lines: amount of initial lines to be used
35 	 */
36 	void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
37 			   struct drm_dsc_config *dsc,
38 			   u32 mode,
39 			   u32 initial_lines);
40 
41 	/**
42 	 * dsc_config_thresh - programs panel thresholds
43 	 * @hw_dsc: Pointer to dsc context
44 	 * @dsc: panel dsc parameters
45 	 */
46 	void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
47 				  struct drm_dsc_config *dsc);
48 
49 	void (*dsc_bind_pingpong_blk)(struct dpu_hw_dsc *hw_dsc,
50 				  enum dpu_pingpong pp);
51 };
52 
53 struct dpu_hw_dsc {
54 	struct dpu_hw_blk base;
55 	struct dpu_hw_blk_reg_map hw;
56 
57 	/* dsc */
58 	enum dpu_dsc idx;
59 	const struct dpu_dsc_cfg *caps;
60 
61 	/* ops */
62 	struct dpu_hw_dsc_ops ops;
63 };
64 
65 /**
66  * dpu_hw_dsc_init() - Initializes the DSC hw driver object.
67  * @dev:  Corresponding device for devres management
68  * @cfg:  DSC catalog entry for which driver object is required
69  * @addr: Mapped register io address of MDP
70  * Return: Error code or allocated dpu_hw_dsc context
71  */
72 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
73 				   const struct dpu_dsc_cfg *cfg,
74 				   void __iomem *addr);
75 
76 /**
77  * dpu_hw_dsc_init_1_2() - initializes the v1.2 DSC hw driver object
78  * @dev:  Corresponding device for devres management
79  * @cfg:  DSC catalog entry for which driver object is required
80  * @addr: Mapped register io address of MDP
81  * Returns: Error code or allocated dpu_hw_dsc context
82  */
83 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
84 				       const struct dpu_dsc_cfg *cfg,
85 				       void __iomem *addr);
86 
87 /**
88  * dpu_hw_dsc_destroy - destroys dsc driver context
89  * @dsc:   Pointer to dsc driver context returned by dpu_hw_dsc_init
90  */
91 void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
92 
to_dpu_hw_dsc(struct dpu_hw_blk * hw)93 static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
94 {
95 	return container_of(hw, struct dpu_hw_dsc, base);
96 }
97 
98 #endif /* _DPU_HW_DSC_H */
99