1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2024 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CURSOR_REGS_H__ 7 #define __INTEL_CURSOR_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define _CURACNTR 0x70080 12 #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR) 13 /* Old style CUR*CNTR flags (desktop 8xx) */ 14 #define CURSOR_ENABLE REG_BIT(31) 15 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 16 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 17 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 18 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 19 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 20 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 21 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 22 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 23 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 24 /* New style CUR*CNTR flags */ 25 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 26 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 27 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 28 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 29 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 30 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 31 #define MCURSOR_ROTATE_180 REG_BIT(15) 32 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 33 #define MCURSOR_MODE_MASK 0x27 34 #define MCURSOR_MODE_DISABLE 0x00 35 #define MCURSOR_MODE_128_32B_AX 0x02 36 #define MCURSOR_MODE_256_32B_AX 0x03 37 #define MCURSOR_MODE_64_2B 0x04 38 #define MCURSOR_MODE_64_32B_AX 0x07 39 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 40 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 41 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 42 43 #define _CURABASE 0x70084 44 #define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE) 45 46 #define _CURAPOS 0x70088 47 #define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS) 48 #define CURSOR_POS_Y_SIGN REG_BIT(31) 49 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 50 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 51 #define CURSOR_POS_X_SIGN REG_BIT(15) 52 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 53 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 54 55 #define _CURAPOS_ERLY_TPT 0x7008c 56 #define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT) 57 58 #define _CURASIZE 0x700a0 /* 845/865 */ 59 #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE) 60 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 61 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 62 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 63 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 64 65 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 66 #define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A) 67 #define CUR_FBC_EN REG_BIT(31) 68 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 69 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 70 71 #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ 72 #define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A) 73 74 #define _CURASURFLIVE 0x700ac /* g4x+ */ 75 #define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE) 76 77 /* skl+ */ 78 #define _CUR_WM_A_0 0x70140 79 #define _CUR_WM_B_0 0x71140 80 #define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4) 81 #define CUR_WM_EN REG_BIT(31) 82 #define CUR_WM_IGNORE_LINES REG_BIT(30) 83 #define CUR_WM_LINES_MASK REG_GENMASK(26, 14) 84 #define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0) 85 86 #define _CUR_WM_SAGV_A 0x70158 87 #define _CUR_WM_SAGV_B 0x71158 88 #define CUR_WM_SAGV(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) 89 90 #define _CUR_WM_SAGV_TRANS_A 0x7015C 91 #define _CUR_WM_SAGV_TRANS_B 0x7115C 92 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) 93 94 #define _CUR_WM_TRANS_A 0x70168 95 #define _CUR_WM_TRANS_B 0x71168 96 #define CUR_WM_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) 97 98 #define _CUR_BUF_CFG_A 0x7017c 99 #define _CUR_BUF_CFG_B 0x7117c 100 #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 101 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 102 #define CUR_BUF_END_MASK REG_GENMASK(27, 16) 103 #define CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end)) 104 #define CUR_BUF_START_MASK REG_GENMASK(11, 0) 105 #define CUR_BUF_START(start) REG_FIELD_PREP(CUR_BUF_START_MASK, (start)) 106 107 /* tgl+ */ 108 #define _SEL_FETCH_CUR_CTL_A 0x70880 109 #define _SEL_FETCH_CUR_CTL_B 0x71880 110 #define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_B) 111 112 #endif /* __INTEL_CURSOR_REGS_H__ */ 113