1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _ASM_RISCV_IMAGE_H 4 #define _ASM_RISCV_IMAGE_H 5 6 #define RISCV_IMAGE_MAGIC "RISCV\0\0\0" 7 #define RISCV_IMAGE_MAGIC2 "RSC\x05" 8 9 #define RISCV_IMAGE_FLAG_BE_SHIFT 0 10 #define RISCV_IMAGE_FLAG_BE_MASK 0x1 11 12 #define RISCV_IMAGE_FLAG_LE 0 13 #define RISCV_IMAGE_FLAG_BE 1 14 15 #ifdef CONFIG_CPU_BIG_ENDIAN 16 #error conversion of header fields to LE not yet implemented 17 #else 18 #define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE 19 #endif 20 21 #define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \ 22 RISCV_IMAGE_FLAG_##field##_SHIFT) 23 24 #define __HEAD_FLAGS (__HEAD_FLAG(BE)) 25 26 #define RISCV_HEADER_VERSION_MAJOR 0 27 #define RISCV_HEADER_VERSION_MINOR 2 28 29 #define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \ 30 RISCV_HEADER_VERSION_MINOR) 31 32 #ifndef __ASSEMBLY__ 33 #define riscv_image_flag_field(flags, field)\ 34 (((flags) >> field##_SHIFT) & field##_MASK) 35 /** 36 * struct riscv_image_header - riscv kernel image header 37 * @code0: Executable code 38 * @code1: Executable code 39 * @text_offset: Image load offset (little endian) 40 * @image_size: Effective Image size (little endian) 41 * @flags: kernel flags (little endian) 42 * @version: version 43 * @res1: reserved 44 * @res2: reserved 45 * @magic: Magic number (RISC-V specific; deprecated) 46 * @magic2: Magic number 2 (to match the ARM64 'magic' field pos) 47 * @res3: reserved (will be used for PE COFF offset) 48 * 49 * The intention is for this header format to be shared between multiple 50 * architectures to avoid a proliferation of image header formats. 51 */ 52 53 struct riscv_image_header { 54 u32 code0; 55 u32 code1; 56 u64 text_offset; 57 u64 image_size; 58 u64 flags; 59 u32 version; 60 u32 res1; 61 u64 res2; 62 u64 magic; 63 u32 magic2; 64 u32 res3; 65 }; 66 #endif /* __ASSEMBLY__ */ 67 #endif /* _ASM_RISCV_IMAGE_H */ 68