1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _ZL3073X_REGS_H 4 #define _ZL3073X_REGS_H 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 9 /* 10 * Hardware limits for ZL3073x chip family 11 */ 12 #define ZL3073X_MAX_CHANNELS 5 13 #define ZL3073X_NUM_REFS 10 14 #define ZL3073X_NUM_OUTS 10 15 #define ZL3073X_NUM_SYNTHS 5 16 #define ZL3073X_NUM_INPUT_PINS ZL3073X_NUM_REFS 17 #define ZL3073X_NUM_OUTPUT_PINS (ZL3073X_NUM_OUTS * 2) 18 #define ZL3073X_NUM_PINS (ZL3073X_NUM_INPUT_PINS + \ 19 ZL3073X_NUM_OUTPUT_PINS) 20 21 /* 22 * Register address structure: 23 * =========================== 24 * 25 19 18 16 15 7 6 0 25 * +------------------------------------------+ 26 * | max_offset | size | page | page_offset | 27 * +------------------------------------------+ 28 * 29 * page_offset ... <0x00..0x7F> 30 * page .......... HW page number 31 * size .......... register byte size (1, 2, 4 or 6) 32 * max_offset .... maximal offset for indexed registers 33 * (for non-indexed regs max_offset == page_offset) 34 */ 35 36 #define ZL_REG_OFFSET_MASK GENMASK(6, 0) 37 #define ZL_REG_PAGE_MASK GENMASK(15, 7) 38 #define ZL_REG_SIZE_MASK GENMASK(18, 16) 39 #define ZL_REG_MAX_OFFSET_MASK GENMASK(25, 19) 40 #define ZL_REG_ADDR_MASK GENMASK(15, 0) 41 42 #define ZL_REG_OFFSET(_reg) FIELD_GET(ZL_REG_OFFSET_MASK, _reg) 43 #define ZL_REG_PAGE(_reg) FIELD_GET(ZL_REG_PAGE_MASK, _reg) 44 #define ZL_REG_MAX_OFFSET(_reg) FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg) 45 #define ZL_REG_SIZE(_reg) FIELD_GET(ZL_REG_SIZE_MASK, _reg) 46 #define ZL_REG_ADDR(_reg) FIELD_GET(ZL_REG_ADDR_MASK, _reg) 47 48 /** 49 * ZL_REG_IDX - define indexed register 50 * @_idx: index of register to access 51 * @_page: register page 52 * @_offset: register offset in page 53 * @_size: register byte size (1, 2, 4 or 6) 54 * @_items: number of register indices 55 * @_stride: stride between items in bytes 56 * 57 * All parameters except @_idx should be constant. 58 */ 59 #define ZL_REG_IDX(_idx, _page, _offset, _size, _items, _stride) \ 60 (FIELD_PREP(ZL_REG_OFFSET_MASK, \ 61 (_offset) + (_idx) * (_stride)) | \ 62 FIELD_PREP_CONST(ZL_REG_PAGE_MASK, _page) | \ 63 FIELD_PREP_CONST(ZL_REG_SIZE_MASK, _size) | \ 64 FIELD_PREP_CONST(ZL_REG_MAX_OFFSET_MASK, \ 65 (_offset) + ((_items) - 1) * (_stride))) 66 67 /** 68 * ZL_REG - define simple (non-indexed) register 69 * @_page: register page 70 * @_offset: register offset in page 71 * @_size: register byte size (1, 2, 4 or 6) 72 * 73 * All parameters should be constant. 74 */ 75 #define ZL_REG(_page, _offset, _size) \ 76 ZL_REG_IDX(0, _page, _offset, _size, 1, 0) 77 78 /************************** 79 * Register Page 0, General 80 **************************/ 81 82 #define ZL_REG_INFO ZL_REG(0, 0x00, 1) 83 #define ZL_INFO_READY BIT(7) 84 85 #define ZL_REG_ID ZL_REG(0, 0x01, 2) 86 #define ZL_REG_REVISION ZL_REG(0, 0x03, 2) 87 #define ZL_REG_FW_VER ZL_REG(0, 0x05, 2) 88 #define ZL_REG_CUSTOM_CONFIG_VER ZL_REG(0, 0x07, 4) 89 90 #define ZL_REG_RESET_STATUS ZL_REG(0, 0x18, 1) 91 #define ZL_REG_RESET_STATUS_RESET BIT(0) 92 93 #define ZL_REG_DIE_TEMP_STATUS ZL_REG(0, 0x44, 2) 94 95 /************************* 96 * Register Page 2, Status 97 *************************/ 98 99 #define ZL_REG_REF_MON_STATUS(_idx) \ 100 ZL_REG_IDX(_idx, 2, 0x02, 1, ZL3073X_NUM_REFS, 1) 101 #define ZL_REF_MON_STATUS_OK 0 102 #define ZL_REF_MON_STATUS_LOS BIT(0) 103 #define ZL_REF_MON_STATUS_SCM BIT(1) 104 #define ZL_REF_MON_STATUS_CFM BIT(2) 105 #define ZL_REF_MON_STATUS_GST BIT(3) 106 #define ZL_REF_MON_STATUS_PFM BIT(4) 107 #define ZL_REF_MON_STATUS_ESYNC BIT(6) 108 #define ZL_REF_MON_STATUS_SPLIT_XO BIT(7) 109 110 #define ZL_REG_DPLL_MON_STATUS(_idx) \ 111 ZL_REG_IDX(_idx, 2, 0x10, 1, ZL3073X_MAX_CHANNELS, 1) 112 #define ZL_DPLL_MON_STATUS_STATE GENMASK(1, 0) 113 #define ZL_DPLL_MON_STATUS_STATE_ACQUIRING 0 114 #define ZL_DPLL_MON_STATUS_STATE_LOCK 1 115 #define ZL_DPLL_MON_STATUS_STATE_HOLDOVER 2 116 #define ZL_DPLL_MON_STATUS_HO_READY BIT(2) 117 118 #define ZL_REG_DPLL_REFSEL_STATUS(_idx) \ 119 ZL_REG_IDX(_idx, 2, 0x30, 1, ZL3073X_MAX_CHANNELS, 1) 120 #define ZL_DPLL_REFSEL_STATUS_REFSEL GENMASK(3, 0) 121 #define ZL_DPLL_REFSEL_STATUS_STATE GENMASK(6, 4) 122 #define ZL_DPLL_REFSEL_STATUS_STATE_LOCK 4 123 124 #define ZL_REG_REF_FREQ(_idx) \ 125 ZL_REG_IDX(_idx, 2, 0x44, 4, ZL3073X_NUM_REFS, 4) 126 127 /********************** 128 * Register Page 4, Ref 129 **********************/ 130 131 #define ZL_REG_REF_PHASE_ERR_READ_RQST ZL_REG(4, 0x0f, 1) 132 #define ZL_REF_PHASE_ERR_READ_RQST_RD BIT(0) 133 134 #define ZL_REG_REF_FREQ_MEAS_CTRL ZL_REG(4, 0x1c, 1) 135 #define ZL_REF_FREQ_MEAS_CTRL GENMASK(1, 0) 136 #define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ 1 137 #define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ_OFF 2 138 #define ZL_REF_FREQ_MEAS_CTRL_DPLL_FREQ_OFF 3 139 140 #define ZL_REG_REF_FREQ_MEAS_MASK_3_0 ZL_REG(4, 0x1d, 1) 141 #define ZL_REF_FREQ_MEAS_MASK_3_0(_ref) BIT(_ref) 142 143 #define ZL_REG_REF_FREQ_MEAS_MASK_4 ZL_REG(4, 0x1e, 1) 144 #define ZL_REF_FREQ_MEAS_MASK_4(_ref) BIT((_ref) - 8) 145 146 #define ZL_REG_DPLL_MEAS_REF_FREQ_CTRL ZL_REG(4, 0x1f, 1) 147 #define ZL_DPLL_MEAS_REF_FREQ_CTRL_EN BIT(0) 148 #define ZL_DPLL_MEAS_REF_FREQ_CTRL_IDX GENMASK(6, 4) 149 150 #define ZL_REG_REF_PHASE(_idx) \ 151 ZL_REG_IDX(_idx, 4, 0x20, 6, ZL3073X_NUM_REFS, 6) 152 153 /*********************** 154 * Register Page 5, DPLL 155 ***********************/ 156 157 #define ZL_REG_DPLL_MODE_REFSEL(_idx) \ 158 ZL_REG_IDX(_idx, 5, 0x04, 1, ZL3073X_MAX_CHANNELS, 4) 159 #define ZL_DPLL_MODE_REFSEL_MODE GENMASK(2, 0) 160 #define ZL_DPLL_MODE_REFSEL_MODE_FREERUN 0 161 #define ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER 1 162 #define ZL_DPLL_MODE_REFSEL_MODE_REFLOCK 2 163 #define ZL_DPLL_MODE_REFSEL_MODE_AUTO 3 164 #define ZL_DPLL_MODE_REFSEL_MODE_NCO 4 165 #define ZL_DPLL_MODE_REFSEL_REF GENMASK(7, 4) 166 167 #define ZL_REG_DPLL_DF_READ(_idx) \ 168 ZL_REG_IDX(_idx, 5, 0x28, 1, ZL3073X_MAX_CHANNELS, 1) 169 #define ZL_DPLL_DF_READ_SEM BIT(4) 170 #define ZL_DPLL_DF_READ_REF_OFST BIT(3) 171 172 #define ZL_REG_DPLL_MEAS_CTRL ZL_REG(5, 0x50, 1) 173 #define ZL_DPLL_MEAS_CTRL_EN BIT(0) 174 #define ZL_DPLL_MEAS_CTRL_AVG_FACTOR GENMASK(7, 4) 175 176 #define ZL_REG_DPLL_MEAS_IDX ZL_REG(5, 0x51, 1) 177 #define ZL_DPLL_MEAS_IDX GENMASK(2, 0) 178 179 #define ZL_REG_DPLL_PHASE_ERR_READ_MASK ZL_REG(5, 0x54, 1) 180 181 #define ZL_REG_DPLL_PHASE_ERR_DATA(_idx) \ 182 ZL_REG_IDX(_idx, 5, 0x55, 6, ZL3073X_MAX_CHANNELS, 6) 183 184 /******************************* 185 * Register Pages 6-7, DPLL Data 186 *******************************/ 187 188 #define ZL_REG_DPLL_DF_OFFSET_03(_idx) \ 189 ZL_REG_IDX(_idx, 6, 0x00, 6, 4, 0x20) 190 #define ZL_REG_DPLL_DF_OFFSET_4 ZL_REG(7, 0x00, 6) 191 #define ZL_REG_DPLL_DF_OFFSET(_idx) \ 192 ((_idx) < 4 ? ZL_REG_DPLL_DF_OFFSET_03(_idx) : ZL_REG_DPLL_DF_OFFSET_4) 193 194 /*********************************** 195 * Register Page 9, Synth and Output 196 ***********************************/ 197 198 #define ZL_REG_SYNTH_CTRL(_idx) \ 199 ZL_REG_IDX(_idx, 9, 0x00, 1, ZL3073X_NUM_SYNTHS, 1) 200 #define ZL_SYNTH_CTRL_EN BIT(0) 201 #define ZL_SYNTH_CTRL_DPLL_SEL GENMASK(6, 4) 202 203 #define ZL_REG_SYNTH_PHASE_SHIFT_CTRL ZL_REG(9, 0x1e, 1) 204 #define ZL_REG_SYNTH_PHASE_SHIFT_MASK ZL_REG(9, 0x1f, 1) 205 #define ZL_REG_SYNTH_PHASE_SHIFT_INTVL ZL_REG(9, 0x20, 1) 206 #define ZL_REG_SYNTH_PHASE_SHIFT_DATA ZL_REG(9, 0x21, 2) 207 208 #define ZL_REG_OUTPUT_CTRL(_idx) \ 209 ZL_REG_IDX(_idx, 9, 0x28, 1, ZL3073X_NUM_OUTS, 1) 210 #define ZL_OUTPUT_CTRL_EN BIT(0) 211 #define ZL_OUTPUT_CTRL_SYNTH_SEL GENMASK(6, 4) 212 213 /******************************* 214 * Register Page 10, Ref Mailbox 215 *******************************/ 216 217 #define ZL_REG_REF_MB_MASK ZL_REG(10, 0x02, 2) 218 219 #define ZL_REG_REF_MB_SEM ZL_REG(10, 0x04, 1) 220 #define ZL_REF_MB_SEM_WR BIT(0) 221 #define ZL_REF_MB_SEM_RD BIT(1) 222 223 #define ZL_REG_REF_FREQ_BASE ZL_REG(10, 0x05, 2) 224 #define ZL_REG_REF_FREQ_MULT ZL_REG(10, 0x07, 2) 225 #define ZL_REG_REF_RATIO_M ZL_REG(10, 0x09, 2) 226 #define ZL_REG_REF_RATIO_N ZL_REG(10, 0x0b, 2) 227 228 #define ZL_REG_REF_CONFIG ZL_REG(10, 0x0d, 1) 229 #define ZL_REF_CONFIG_ENABLE BIT(0) 230 #define ZL_REF_CONFIG_DIFF_EN BIT(2) 231 232 #define ZL_REG_REF_PHASE_OFFSET_COMP ZL_REG(10, 0x28, 6) 233 #define ZL_REG_REF_PHASE_OFFSET_COMP_32 ZL_REG(10, 0x28, 4) 234 235 #define ZL_REG_REF_SYNC_CTRL ZL_REG(10, 0x2e, 1) 236 #define ZL_REF_SYNC_CTRL_MODE GENMASK(2, 0) 237 #define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF 0 238 #define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR 1 239 #define ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75 2 240 #define ZL_REF_SYNC_CTRL_PAIR GENMASK(7, 4) 241 242 #define ZL_REG_REF_ESYNC_DIV ZL_REG(10, 0x30, 4) 243 #define ZL_REF_ESYNC_DIV_1HZ 0 244 245 /******************************** 246 * Register Page 12, DPLL Mailbox 247 ********************************/ 248 249 #define ZL_REG_DPLL_MB_MASK ZL_REG(12, 0x02, 2) 250 251 #define ZL_REG_DPLL_MB_SEM ZL_REG(12, 0x04, 1) 252 #define ZL_DPLL_MB_SEM_WR BIT(0) 253 #define ZL_DPLL_MB_SEM_RD BIT(1) 254 255 #define ZL_REG_DPLL_REF_PRIO(_idx) \ 256 ZL_REG_IDX(_idx, 12, 0x52, 1, ZL3073X_NUM_REFS / 2, 1) 257 #define ZL_DPLL_REF_PRIO_REF_P GENMASK(3, 0) 258 #define ZL_DPLL_REF_PRIO_REF_N GENMASK(7, 4) 259 #define ZL_DPLL_REF_PRIO_MAX 14 260 #define ZL_DPLL_REF_PRIO_NONE 15 261 262 /********************************* 263 * Register Page 13, Synth Mailbox 264 *********************************/ 265 266 #define ZL_REG_SYNTH_MB_MASK ZL_REG(13, 0x02, 2) 267 268 #define ZL_REG_SYNTH_MB_SEM ZL_REG(13, 0x04, 1) 269 #define ZL_SYNTH_MB_SEM_WR BIT(0) 270 #define ZL_SYNTH_MB_SEM_RD BIT(1) 271 272 #define ZL_REG_SYNTH_FREQ_BASE ZL_REG(13, 0x06, 2) 273 #define ZL_REG_SYNTH_FREQ_MULT ZL_REG(13, 0x08, 4) 274 #define ZL_REG_SYNTH_FREQ_M ZL_REG(13, 0x0c, 2) 275 #define ZL_REG_SYNTH_FREQ_N ZL_REG(13, 0x0e, 2) 276 277 /********************************** 278 * Register Page 14, Output Mailbox 279 **********************************/ 280 #define ZL_REG_OUTPUT_MB_MASK ZL_REG(14, 0x02, 2) 281 282 #define ZL_REG_OUTPUT_MB_SEM ZL_REG(14, 0x04, 1) 283 #define ZL_OUTPUT_MB_SEM_WR BIT(0) 284 #define ZL_OUTPUT_MB_SEM_RD BIT(1) 285 286 #define ZL_REG_OUTPUT_MODE ZL_REG(14, 0x05, 1) 287 #define ZL_OUTPUT_MODE_CLOCK_TYPE GENMASK(2, 0) 288 #define ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL 0 289 #define ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC 1 290 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT GENMASK(7, 4) 291 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DISABLED 0 292 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LVDS 1 293 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DIFF 2 294 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LOWVCM 3 295 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2 4 296 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1P 5 297 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1N 6 298 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_INV 7 299 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV 12 300 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV 15 301 302 #define ZL_REG_OUTPUT_DIV ZL_REG(14, 0x0c, 4) 303 #define ZL_REG_OUTPUT_WIDTH ZL_REG(14, 0x10, 4) 304 #define ZL_REG_OUTPUT_ESYNC_PERIOD ZL_REG(14, 0x14, 4) 305 #define ZL_REG_OUTPUT_ESYNC_WIDTH ZL_REG(14, 0x18, 4) 306 #define ZL_REG_OUTPUT_PHASE_COMP ZL_REG(14, 0x20, 4) 307 308 /* 309 * Register Page 255 - HW registers access 310 */ 311 #define ZL_REG_HWREG_OP ZL_REG(0xff, 0x00, 1) 312 #define ZL_HWREG_OP_WRITE 0x28 313 #define ZL_HWREG_OP_READ 0x29 314 #define ZL_HWREG_OP_PENDING BIT(1) 315 316 #define ZL_REG_HWREG_ADDR ZL_REG(0xff, 0x04, 4) 317 #define ZL_REG_HWREG_WRITE_DATA ZL_REG(0xff, 0x08, 4) 318 #define ZL_REG_HWREG_READ_DATA ZL_REG(0xff, 0x0c, 4) 319 320 /* 321 * Registers available in flash mode 322 */ 323 #define ZL_REG_FLASH_HASH ZL_REG(0, 0x78, 4) 324 #define ZL_REG_FLASH_FAMILY ZL_REG(0, 0x7c, 1) 325 #define ZL_REG_FLASH_RELEASE ZL_REG(0, 0x7d, 1) 326 327 #define ZL_REG_HOST_CONTROL ZL_REG(1, 0x02, 1) 328 #define ZL_HOST_CONTROL_ENABLE BIT(0) 329 330 #define ZL_REG_IMAGE_START_ADDR ZL_REG(1, 0x04, 4) 331 #define ZL_REG_IMAGE_SIZE ZL_REG(1, 0x08, 4) 332 #define ZL_REG_FLASH_INDEX_READ ZL_REG(1, 0x0c, 4) 333 #define ZL_REG_FLASH_INDEX_WRITE ZL_REG(1, 0x10, 4) 334 #define ZL_REG_FILL_PATTERN ZL_REG(1, 0x14, 4) 335 336 #define ZL_REG_WRITE_FLASH ZL_REG(1, 0x18, 1) 337 #define ZL_WRITE_FLASH_OP GENMASK(2, 0) 338 #define ZL_WRITE_FLASH_OP_DONE 0x0 339 #define ZL_WRITE_FLASH_OP_SECTORS 0x2 340 #define ZL_WRITE_FLASH_OP_PAGE 0x3 341 #define ZL_WRITE_FLASH_OP_COPY_PAGE 0x4 342 343 #define ZL_REG_FLASH_INFO ZL_REG(2, 0x00, 1) 344 #define ZL_FLASH_INFO_SECTOR_SIZE GENMASK(3, 0) 345 #define ZL_FLASH_INFO_SECTOR_4K 0 346 #define ZL_FLASH_INFO_SECTOR_64K 1 347 348 #define ZL_REG_ERROR_COUNT ZL_REG(2, 0x04, 4) 349 #define ZL_REG_ERROR_CAUSE ZL_REG(2, 0x08, 4) 350 351 #define ZL_REG_OP_STATE ZL_REG(2, 0x14, 1) 352 #define ZL_OP_STATE_NO_COMMAND 0 353 #define ZL_OP_STATE_PENDING 1 354 #define ZL_OP_STATE_DONE 2 355 356 #endif /* _ZL3073X_REGS_H */ 357