1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_ETH_H 8 #define AIROHA_ETH_H 9 10 #include <linux/debugfs.h> 11 #include <linux/etherdevice.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/reset.h> 16 #include <linux/soc/airoha/airoha_offload.h> 17 #include <net/dsa.h> 18 19 #define AIROHA_MAX_NUM_GDM_PORTS 4 20 #define AIROHA_MAX_NUM_GDM_DEVS 2 21 #define AIROHA_MAX_NUM_QDMA 2 22 #define AIROHA_MAX_NUM_IRQ_BANKS 4 23 #define AIROHA_MAX_DSA_PORTS 7 24 #define AIROHA_MAX_NUM_RSTS 3 25 #define AIROHA_MAX_MTU 9220 26 #define AIROHA_MAX_PACKET_SIZE 2048 27 #define AIROHA_NUM_QOS_CHANNELS 4 28 #define AIROHA_NUM_QOS_QUEUES 8 29 #define AIROHA_NUM_TX_RING 32 30 #define AIROHA_NUM_RX_RING 32 31 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \ 32 AIROHA_NUM_QOS_CHANNELS) 33 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64 34 #define AIROHA_FE_MC_MAX_VLAN_PORT 16 35 #define AIROHA_NUM_TX_IRQ 2 36 #define AIROHA_RX_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) 37 #define AIROHA_RX_LEN(_n) ((_n) - AIROHA_RX_HEADROOM) 38 #define HW_DSCP_NUM 2048 39 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048) 40 #define TX_DSCP_NUM 1024 41 #define RX_DSCP_NUM(_n) \ 42 ((_n) == 2 ? 128 : \ 43 (_n) == 11 ? 128 : \ 44 (_n) == 15 ? 128 : \ 45 (_n) == 0 ? 1024 : 16) 46 47 #define PSE_RSV_PAGES 128 48 #define PSE_QUEUE_RSV_PAGES 64 49 50 #define QDMA_METER_IDX(_n) ((_n) & 0xff) 51 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3) 52 53 #define PPE_SRAM_NUM_ENTRIES (8 * 1024) 54 #define PPE_STATS_NUM_ENTRIES (4 * 1024) 55 #define PPE_DRAM_NUM_ENTRIES (16 * 1024) 56 #define PPE_ENTRY_SIZE 80 57 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10)) 58 59 #define MTK_HDR_LEN 4 60 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1 61 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 62 63 enum { 64 QDMA_INT_REG_IDX0, 65 QDMA_INT_REG_IDX1, 66 QDMA_INT_REG_IDX2, 67 QDMA_INT_REG_IDX3, 68 QDMA_INT_REG_IDX4, 69 QDMA_INT_REG_MAX 70 }; 71 72 enum { 73 HSGMII_LAN_7581_PCIE0_SRCPORT = 0x16, 74 HSGMII_LAN_7581_PCIE1_SRCPORT, 75 HSGMII_LAN_7581_ETH_SRCPORT, 76 HSGMII_LAN_7581_USB_SRCPORT, 77 }; 78 79 enum { 80 HSGMII_LAN_7583_ETH_SRCPORT = 0x16, 81 HSGMII_LAN_7583_PCIE_SRCPORT = 0x18, 82 HSGMII_LAN_7583_USB_SRCPORT, 83 }; 84 85 enum { 86 XSI_PCIE0_VIP_PORT_MASK = BIT(22), 87 XSI_PCIE1_VIP_PORT_MASK = BIT(23), 88 XSI_USB_VIP_PORT_MASK = BIT(25), 89 XSI_ETH_VIP_PORT_MASK = BIT(24), 90 }; 91 92 enum { 93 DEV_STATE_INITIALIZED, 94 DEV_STATE_REGISTERED, 95 }; 96 97 enum { 98 CDM_CRSN_QSEL_Q1 = 1, 99 CDM_CRSN_QSEL_Q5 = 5, 100 CDM_CRSN_QSEL_Q6 = 6, 101 CDM_CRSN_QSEL_Q15 = 15, 102 }; 103 104 enum { 105 CRSN_08 = 0x8, 106 CRSN_21 = 0x15, /* KA */ 107 CRSN_22 = 0x16, /* hit bind and force route to CPU */ 108 CRSN_24 = 0x18, 109 CRSN_25 = 0x19, 110 }; 111 112 enum airoha_gdm_index { 113 AIROHA_GDM1_IDX = 1, 114 AIROHA_GDM2_IDX = 2, 115 AIROHA_GDM3_IDX = 3, 116 AIROHA_GDM4_IDX = 4, 117 }; 118 119 enum { 120 FE_PSE_PORT_CDM1, 121 FE_PSE_PORT_GDM1, 122 FE_PSE_PORT_GDM2, 123 FE_PSE_PORT_GDM3, 124 FE_PSE_PORT_PPE1, 125 FE_PSE_PORT_CDM2, 126 FE_PSE_PORT_CDM3, 127 FE_PSE_PORT_CDM4, 128 FE_PSE_PORT_PPE2, 129 FE_PSE_PORT_GDM4, 130 FE_PSE_PORT_CDM5, 131 FE_PSE_PORT_DROP = 0xf, 132 }; 133 134 enum tx_sched_mode { 135 TC_SCH_WRR8, 136 TC_SCH_SP, 137 TC_SCH_WRR7, 138 TC_SCH_WRR6, 139 TC_SCH_WRR5, 140 TC_SCH_WRR4, 141 TC_SCH_WRR3, 142 TC_SCH_WRR2, 143 }; 144 145 enum trtcm_unit_type { 146 TRTCM_BYTE_UNIT, 147 TRTCM_PACKET_UNIT, 148 }; 149 150 enum trtcm_param_type { 151 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */ 152 TRTCM_TOKEN_RATE_MODE, 153 TRTCM_BUCKETSIZE_SHIFT_MODE, 154 TRTCM_BUCKET_COUNTER_MODE, 155 }; 156 157 enum trtcm_mode_type { 158 TRTCM_COMMIT_MODE, 159 TRTCM_PEAK_MODE, 160 }; 161 162 enum trtcm_param { 163 TRTCM_TICK_SEL = BIT(0), 164 TRTCM_PKT_MODE = BIT(1), 165 TRTCM_METER_MODE = BIT(2), 166 }; 167 168 #define MIN_TOKEN_SIZE 4096 169 #define MAX_TOKEN_SIZE_OFFSET 17 170 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6) 171 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0) 172 173 struct airoha_queue_entry { 174 union { 175 void *buf; 176 struct { 177 struct list_head list; 178 struct sk_buff *skb; 179 }; 180 }; 181 dma_addr_t dma_addr; 182 u16 dma_len; 183 }; 184 185 struct airoha_queue { 186 struct airoha_qdma *qdma; 187 188 /* protect concurrent queue accesses */ 189 spinlock_t lock; 190 struct airoha_queue_entry *entry; 191 struct airoha_qdma_desc *desc; 192 u16 head; 193 u16 tail; 194 195 int queued; 196 int ndesc; 197 int free_thr; 198 int buf_size; 199 bool txq_stopped; 200 bool flushing; 201 202 struct napi_struct napi; 203 struct page_pool *page_pool; 204 struct sk_buff *skb; 205 206 struct list_head tx_list; 207 }; 208 209 struct airoha_tx_irq_queue { 210 struct airoha_qdma *qdma; 211 212 struct napi_struct napi; 213 214 int size; 215 u32 *q; 216 }; 217 218 struct airoha_hw_stats { 219 struct u64_stats_sync syncp; 220 221 /* get_stats64 */ 222 u64 rx_ok_pkts; 223 u64 tx_ok_pkts; 224 u64 rx_ok_bytes; 225 u64 tx_ok_bytes; 226 u64 rx_multicast; 227 u64 rx_errors; 228 u64 rx_drops; 229 u64 tx_drops; 230 u64 rx_crc_error; 231 u64 rx_over_errors; 232 /* ethtool stats */ 233 u64 tx_broadcast; 234 u64 tx_multicast; 235 u64 tx_len[7]; 236 u64 rx_broadcast; 237 u64 rx_fragment; 238 u64 rx_jabber; 239 u64 rx_len[7]; 240 }; 241 242 enum { 243 AIROHA_FOE_STATE_INVALID, 244 AIROHA_FOE_STATE_UNBIND, 245 AIROHA_FOE_STATE_BIND, 246 AIROHA_FOE_STATE_FIN 247 }; 248 249 enum { 250 PPE_PKT_TYPE_IPV4_HNAPT = 0, 251 PPE_PKT_TYPE_IPV4_ROUTE = 1, 252 PPE_PKT_TYPE_BRIDGE = 2, 253 PPE_PKT_TYPE_IPV4_DSLITE = 3, 254 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, 255 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, 256 PPE_PKT_TYPE_IPV6_6RD = 7, 257 }; 258 259 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16) 260 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0) 261 262 #define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12) 263 #define AIROHA_FOE_MAC_WDMA_BAND BIT(11) 264 #define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0) 265 266 struct airoha_foe_mac_info_common { 267 u16 vlan1; 268 u16 etype; 269 270 u32 dest_mac_hi; 271 272 u16 vlan2; 273 u16 dest_mac_lo; 274 275 u32 src_mac_hi; 276 }; 277 278 struct airoha_foe_mac_info { 279 struct airoha_foe_mac_info_common common; 280 281 u16 pppoe_id; 282 u16 src_mac_lo; 283 284 u32 meter; 285 }; 286 287 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24) 288 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) 289 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) 290 291 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31) 292 #define AIROHA_FOE_IB1_BIND_UDP BIT(30) 293 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28) 294 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25) 295 #define AIROHA_FOE_IB1_BIND_TTL BIT(24) 296 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) 297 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22) 298 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20) 299 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16) 300 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15) 301 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) 302 303 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24) 304 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13) 305 #define AIROHA_FOE_IB2_PCP BIT(12) 306 #define AIROHA_FOE_IB2_MULTICAST BIT(11) 307 #define AIROHA_FOE_IB2_FAST_PATH BIT(10) 308 #define AIROHA_FOE_IB2_PSE_QOS BIT(9) 309 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5) 310 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0) 311 312 #define AIROHA_FOE_ACTDP GENMASK(31, 24) 313 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16) 314 #define AIROHA_FOE_CHANNEL GENMASK(15, 11) 315 #define AIROHA_FOE_QID GENMASK(10, 8) 316 #define AIROHA_FOE_DPI BIT(7) 317 #define AIROHA_FOE_TUNNEL BIT(6) 318 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0) 319 320 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16) 321 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9) 322 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5) 323 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0) 324 325 struct airoha_foe_bridge { 326 u32 dest_mac_hi; 327 328 u16 src_mac_hi; 329 u16 dest_mac_lo; 330 331 u32 src_mac_lo; 332 333 u32 ib2; 334 335 u32 rsv[5]; 336 337 u32 data; 338 339 struct airoha_foe_mac_info l2; 340 }; 341 342 struct airoha_foe_ipv4_tuple { 343 u32 src_ip; 344 u32 dest_ip; 345 union { 346 struct { 347 u16 dest_port; 348 u16 src_port; 349 }; 350 struct { 351 u8 protocol; 352 u8 _pad[3]; /* fill with 0xa5a5a5 */ 353 }; 354 u32 ports; 355 }; 356 }; 357 358 struct airoha_foe_ipv4 { 359 struct airoha_foe_ipv4_tuple orig_tuple; 360 361 u32 ib2; 362 363 struct airoha_foe_ipv4_tuple new_tuple; 364 365 u32 rsv[2]; 366 367 u32 data; 368 369 struct airoha_foe_mac_info l2; 370 }; 371 372 struct airoha_foe_ipv4_dslite { 373 struct airoha_foe_ipv4_tuple ip4; 374 375 u32 ib2; 376 377 u8 flow_label[3]; 378 u8 priority; 379 380 u32 rsv[4]; 381 382 u32 data; 383 384 struct airoha_foe_mac_info l2; 385 }; 386 387 struct airoha_foe_ipv6 { 388 u32 src_ip[4]; 389 u32 dest_ip[4]; 390 391 union { 392 struct { 393 u16 dest_port; 394 u16 src_port; 395 }; 396 struct { 397 u8 protocol; 398 u8 pad[3]; 399 }; 400 u32 ports; 401 }; 402 403 u32 data; 404 405 u32 ib2; 406 407 struct airoha_foe_mac_info_common l2; 408 409 u32 meter; 410 }; 411 412 struct airoha_foe_entry { 413 union { 414 struct { 415 u32 ib1; 416 union { 417 struct airoha_foe_bridge bridge; 418 struct airoha_foe_ipv4 ipv4; 419 struct airoha_foe_ipv4_dslite dslite; 420 struct airoha_foe_ipv6 ipv6; 421 DECLARE_FLEX_ARRAY(u32, d); 422 }; 423 }; 424 u8 data[PPE_ENTRY_SIZE]; 425 }; 426 }; 427 428 struct airoha_foe_stats { 429 u32 bytes; 430 u32 packets; 431 }; 432 433 struct airoha_foe_stats64 { 434 u64 bytes; 435 u64 packets; 436 }; 437 438 struct airoha_flow_data { 439 struct ethhdr eth; 440 441 union { 442 struct { 443 __be32 src_addr; 444 __be32 dst_addr; 445 } v4; 446 447 struct { 448 struct in6_addr src_addr; 449 struct in6_addr dst_addr; 450 } v6; 451 }; 452 453 __be16 src_port; 454 __be16 dst_port; 455 456 struct { 457 struct { 458 u16 id; 459 __be16 proto; 460 } hdr[2]; 461 u8 num; 462 } vlan; 463 struct { 464 u16 sid; 465 u8 num; 466 } pppoe; 467 }; 468 469 enum airoha_flow_entry_type { 470 FLOW_TYPE_L4, 471 FLOW_TYPE_L2, 472 FLOW_TYPE_L2_SUBFLOW, 473 }; 474 475 struct airoha_flow_table_entry { 476 union { 477 struct hlist_node list; /* PPE L3 flow entry */ 478 struct { 479 struct rhash_head l2_node; /* L2 flow entry */ 480 struct hlist_head l2_flows; /* PPE L2 subflows list */ 481 }; 482 }; 483 484 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */ 485 u32 hash; 486 487 struct airoha_foe_stats64 stats; 488 enum airoha_flow_entry_type type; 489 490 struct rhash_head node; 491 unsigned long cookie; 492 493 /* Must be last --ends in a flexible-array member. */ 494 struct airoha_foe_entry data; 495 }; 496 497 struct airoha_wdma_info { 498 u8 idx; 499 u8 queue; 500 u16 wcid; 501 u8 bss; 502 }; 503 504 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */ 505 #define RX_IRQ0_BANK_PIN_MASK 0x839f 506 #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000 507 #define RX_IRQ2_BANK_PIN_MASK 0x20 508 #define RX_IRQ3_BANK_PIN_MASK 0x40 509 #define RX_IRQ_BANK_PIN_MASK(_n) \ 510 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \ 511 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \ 512 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \ 513 RX_IRQ0_BANK_PIN_MASK) 514 515 struct airoha_irq_bank { 516 struct airoha_qdma *qdma; 517 518 /* protect concurrent irqmask accesses */ 519 spinlock_t irq_lock; 520 u32 irqmask[QDMA_INT_REG_MAX]; 521 int irq; 522 }; 523 524 struct airoha_qdma { 525 struct airoha_eth *eth; 526 void __iomem *regs; 527 528 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS]; 529 530 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 531 532 struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; 533 struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; 534 535 DECLARE_BITMAP(qos_channel_map, AIROHA_NUM_QOS_CHANNELS); 536 }; 537 538 enum airoha_priv_flags { 539 AIROHA_PRIV_F_WAN = BIT(0), 540 }; 541 542 struct airoha_gdm_dev { 543 struct airoha_gdm_port *port; 544 struct airoha_qdma *qdma; 545 struct airoha_eth *eth; 546 547 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); 548 /* qos stats counters */ 549 u64 cpu_tx_packets; 550 u64 fwd_tx_packets; 551 552 u32 flags; 553 int nbq; 554 555 struct airoha_hw_stats stats; 556 }; 557 558 struct airoha_gdm_port { 559 struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS]; 560 int id; 561 int users; 562 563 /* protect concurrent hw_stats accesses */ 564 spinlock_t stats_lock; 565 566 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; 567 }; 568 569 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16) 570 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0) 571 572 struct airoha_ppe { 573 struct airoha_ppe_dev dev; 574 struct airoha_eth *eth; 575 576 void *foe; 577 dma_addr_t foe_dma; 578 579 struct rhashtable l2_flows; 580 581 struct hlist_head *foe_flow; 582 u16 *foe_check_time; 583 584 struct airoha_foe_stats *foe_stats; 585 dma_addr_t foe_stats_dma; 586 587 struct dentry *debugfs_dir; 588 }; 589 590 struct airoha_eth_soc_data { 591 u16 version; 592 const char * const *xsi_rsts_names; 593 int num_xsi_rsts; 594 int num_ppe; 595 struct { 596 int (*get_sport)(struct airoha_gdm_port *port, int nbq); 597 u32 (*get_vip_port)(struct airoha_gdm_port *port, int nbq); 598 int (*get_dev_from_sport)(struct airoha_qdma_desc *desc, 599 u16 *port, u16 *dev); 600 } ops; 601 }; 602 603 struct airoha_eth { 604 struct device *dev; 605 606 const struct airoha_eth_soc_data *soc; 607 608 unsigned long state; 609 void __iomem *fe_regs; 610 611 struct airoha_npu __rcu *npu; 612 613 struct airoha_ppe *ppe; 614 struct rhashtable flow_table; 615 616 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS]; 617 struct reset_control_bulk_data *xsi_rsts; 618 619 struct net_device *napi_dev; 620 621 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; 622 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; 623 }; 624 625 u32 airoha_rr(void __iomem *base, u32 offset); 626 void airoha_wr(void __iomem *base, u32 offset, u32 val); 627 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 628 629 #define airoha_fe_rr(eth, offset) \ 630 airoha_rr((eth)->fe_regs, (offset)) 631 #define airoha_fe_wr(eth, offset, val) \ 632 airoha_wr((eth)->fe_regs, (offset), (val)) 633 #define airoha_fe_rmw(eth, offset, mask, val) \ 634 airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) 635 #define airoha_fe_set(eth, offset, val) \ 636 airoha_rmw((eth)->fe_regs, (offset), 0, (val)) 637 #define airoha_fe_clear(eth, offset, val) \ 638 airoha_rmw((eth)->fe_regs, (offset), (val), 0) 639 #define airoha_fe_get(eth, offset, mask) \ 640 FIELD_GET((mask), airoha_fe_rr((eth), (offset))) 641 642 #define airoha_qdma_rr(qdma, offset) \ 643 airoha_rr((qdma)->regs, (offset)) 644 #define airoha_qdma_wr(qdma, offset, val) \ 645 airoha_wr((qdma)->regs, (offset), (val)) 646 #define airoha_qdma_rmw(qdma, offset, mask, val) \ 647 airoha_rmw((qdma)->regs, (offset), (mask), (val)) 648 #define airoha_qdma_set(qdma, offset, val) \ 649 airoha_rmw((qdma)->regs, (offset), 0, (val)) 650 #define airoha_qdma_clear(qdma, offset, val) \ 651 airoha_rmw((qdma)->regs, (offset), (val), 0) 652 #define airoha_qdma_get(qdma, offset, mask) \ 653 FIELD_GET((mask), airoha_qdma_rr((qdma), (offset))) 654 655 static inline u16 airoha_qdma_get_txq(struct airoha_qdma *qdma, u16 qid) 656 { 657 return qid % ARRAY_SIZE(qdma->q_tx); 658 } 659 660 static inline bool airoha_is_lan_gdm_dev(struct airoha_gdm_dev *dev) 661 { 662 return !(dev->flags & AIROHA_PRIV_F_WAN); 663 } 664 665 static inline bool airoha_is_7581(struct airoha_eth *eth) 666 { 667 return eth->soc->version == 0x7581; 668 } 669 670 static inline bool airoha_is_7583(struct airoha_eth *eth) 671 { 672 return eth->soc->version == 0x7583; 673 } 674 675 int airoha_get_fe_port(struct airoha_gdm_dev *dev); 676 bool airoha_is_valid_gdm_dev(struct airoha_eth *eth, 677 struct airoha_gdm_dev *dev); 678 679 void airoha_ppe_set_cpu_port(struct airoha_gdm_dev *dev, u8 ppe_id, u8 fport); 680 bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index); 681 void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb, 682 u16 hash, bool rx_wlan); 683 int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data); 684 int airoha_ppe_init(struct airoha_eth *eth); 685 void airoha_ppe_deinit(struct airoha_eth *eth); 686 void airoha_ppe_init_upd_mem(struct airoha_gdm_dev *dev, const u8 *addr); 687 u32 airoha_ppe_get_total_num_entries(struct airoha_ppe *ppe); 688 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe, 689 u32 hash); 690 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash, 691 struct airoha_foe_stats64 *stats); 692 693 #ifdef CONFIG_DEBUG_FS 694 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe); 695 #else 696 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) 697 { 698 return 0; 699 } 700 #endif 701 702 #endif /* AIROHA_ETH_H */ 703