1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Xilinx Zynq MPSoC Firmware layer 4 * 5 * Copyright (C) 2014-2021 Xilinx 6 * Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 * Davorin Mista <davorin.mista@aggios.com> 10 * Jolly Shah <jollys@xilinx.com> 11 * Rajan Vaja <rajanv@xilinx.com> 12 */ 13 14 #ifndef __FIRMWARE_ZYNQMP_H__ 15 #define __FIRMWARE_ZYNQMP_H__ 16 #include <linux/types.h> 17 18 #include <linux/err.h> 19 #include <linux/firmware/xlnx-zynqmp-ufs.h> 20 #include <linux/firmware/xlnx-zynqmp-crypto.h> 21 22 #define ZYNQMP_PM_VERSION_MAJOR 1 23 #define ZYNQMP_PM_VERSION_MINOR 0 24 25 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \ 26 ZYNQMP_PM_VERSION_MINOR) 27 28 #define ZYNQMP_TZ_VERSION_MAJOR 1 29 #define ZYNQMP_TZ_VERSION_MINOR 0 30 31 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ 32 ZYNQMP_TZ_VERSION_MINOR) 33 34 /* SMC SIP service Call Function Identifier Prefix */ 35 #define PM_SIP_SVC 0xC2000000 36 37 /* SMC function ID to get SiP SVC version */ 38 #define GET_SIP_SVC_VERSION (0x8200ff03U) 39 40 /* SiP Service Calls version numbers */ 41 #define SIP_SVC_VERSION_MAJOR (0U) 42 #define SIP_SVC_VERSION_MINOR (2U) 43 44 #define SIP_SVC_PASSTHROUGH_VERSION ((SIP_SVC_VERSION_MAJOR << 16) | \ 45 SIP_SVC_VERSION_MINOR) 46 47 /* Fixed ID for FW specific APIs */ 48 #define PASS_THROUGH_FW_CMD_ID GENMASK(11, 0) 49 50 /* PM API versions */ 51 #define PM_API_VERSION_1 1 52 #define PM_API_VERSION_2 2 53 54 #define PM_PINCTRL_PARAM_SET_VERSION 2 55 56 /* Family codes */ 57 #define PM_ZYNQMP_FAMILY_CODE 0x1 /* ZynqMP family code */ 58 #define PM_VERSAL_FAMILY_CODE 0x2 /* Versal family code */ 59 #define PM_VERSAL_NET_FAMILY_CODE 0x3 /* Versal NET family code */ 60 61 #define API_ID_MASK GENMASK(7, 0) 62 #define MODULE_ID_MASK GENMASK(11, 8) 63 #define PLM_MODULE_ID_MASK GENMASK(15, 8) 64 65 /* Firmware feature check version mask */ 66 #define FIRMWARE_VERSION_MASK 0xFFFFU 67 68 /* ATF only commands */ 69 #define TF_A_PM_REGISTER_SGI 0xa04 70 #define PM_GET_TRUSTZONE_VERSION 0xa03 71 #define PM_SET_SUSPEND_MODE 0xa02 72 #define GET_CALLBACK_DATA 0xa01 73 74 /* Number of 32bits values in payload */ 75 #define PAYLOAD_ARG_CNT 7U 76 77 /* Number of 64bits arguments for SMC call */ 78 #define SMC_ARG_CNT_64 8U 79 80 /* Number of 32bits arguments for SMC call */ 81 #define SMC_ARG_CNT_32 13U 82 83 /* Number of arguments for a callback */ 84 #define CB_ARG_CNT 4 85 86 /* Payload size (consists of callback API ID + arguments) */ 87 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1) 88 89 #define ZYNQMP_PM_MAX_QOS 100U 90 91 #define GSS_NUM_REGS (4) 92 93 /* Node capabilities */ 94 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U 95 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U 96 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U 97 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U 98 99 /* Loader commands */ 100 #define PM_LOAD_PDI 0x701 101 #define PDI_SRC_DDR 0xF 102 103 /* 104 * Firmware FPGA Manager flags 105 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration 106 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration 107 */ 108 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U 109 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) 110 111 /* FPGA Status Reg */ 112 #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U 113 #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U 114 115 /* 116 * Node IDs for the Error Events. 117 */ 118 #define VERSAL_EVENT_ERROR_PMC_ERR1 (0x28100000U) 119 #define VERSAL_EVENT_ERROR_PMC_ERR2 (0x28104000U) 120 #define VERSAL_EVENT_ERROR_PSM_ERR1 (0x28108000U) 121 #define VERSAL_EVENT_ERROR_PSM_ERR2 (0x2810C000U) 122 123 #define VERSAL_NET_EVENT_ERROR_PMC_ERR1 (0x28100000U) 124 #define VERSAL_NET_EVENT_ERROR_PMC_ERR2 (0x28104000U) 125 #define VERSAL_NET_EVENT_ERROR_PMC_ERR3 (0x28108000U) 126 #define VERSAL_NET_EVENT_ERROR_PSM_ERR1 (0x2810C000U) 127 #define VERSAL_NET_EVENT_ERROR_PSM_ERR2 (0x28110000U) 128 #define VERSAL_NET_EVENT_ERROR_PSM_ERR3 (0x28114000U) 129 #define VERSAL_NET_EVENT_ERROR_PSM_ERR4 (0x28118000U) 130 131 /* ZynqMP SD tap delay tuning */ 132 #define SD_ITAPDLY 0xFF180314 133 #define SD_OTAPDLYSEL 0xFF180318 134 135 /** 136 * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error. 137 */ 138 #define XPM_EVENT_ERROR_MASK_DDRMC_CR BIT(18) 139 140 /** 141 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error. 142 */ 143 #define XPM_EVENT_ERROR_MASK_DDRMC_NCR BIT(19) 144 #define XPM_EVENT_ERROR_MASK_NOC_NCR BIT(13) 145 #define XPM_EVENT_ERROR_MASK_NOC_CR BIT(12) 146 147 enum pm_module_id { 148 PM_MODULE_ID = 0x0, 149 XPM_MODULE_ID = 0x2, 150 XSEM_MODULE_ID = 0x3, 151 TF_A_MODULE_ID = 0xa, 152 }; 153 154 enum pm_api_cb_id { 155 PM_INIT_SUSPEND_CB = 30, 156 PM_ACKNOWLEDGE_CB = 31, 157 PM_NOTIFY_CB = 32, 158 }; 159 160 enum pm_api_id { 161 PM_API_FEATURES = 0, 162 PM_GET_API_VERSION = 1, 163 PM_GET_NODE_STATUS = 3, 164 PM_REGISTER_NOTIFIER = 5, 165 PM_FORCE_POWERDOWN = 8, 166 PM_REQUEST_WAKEUP = 10, 167 PM_SYSTEM_SHUTDOWN = 12, 168 PM_REQUEST_NODE = 13, 169 PM_RELEASE_NODE = 14, 170 PM_SET_REQUIREMENT = 15, 171 PM_RESET_ASSERT = 17, 172 PM_RESET_GET_STATUS = 18, 173 PM_MMIO_WRITE = 19, 174 PM_MMIO_READ = 20, 175 PM_PM_INIT_FINALIZE = 21, 176 PM_FPGA_LOAD = 22, 177 PM_FPGA_GET_STATUS = 23, 178 PM_GET_CHIPID = 24, 179 PM_SECURE_SHA = 26, 180 PM_PINCTRL_REQUEST = 28, 181 PM_PINCTRL_RELEASE = 29, 182 PM_PINCTRL_SET_FUNCTION = 31, 183 PM_PINCTRL_CONFIG_PARAM_GET = 32, 184 PM_PINCTRL_CONFIG_PARAM_SET = 33, 185 PM_IOCTL = 34, 186 PM_QUERY_DATA = 35, 187 PM_CLOCK_ENABLE = 36, 188 PM_CLOCK_DISABLE = 37, 189 PM_CLOCK_GETSTATE = 38, 190 PM_CLOCK_SETDIVIDER = 39, 191 PM_CLOCK_GETDIVIDER = 40, 192 PM_CLOCK_SETPARENT = 43, 193 PM_CLOCK_GETPARENT = 44, 194 PM_FPGA_READ = 46, 195 PM_SECURE_AES = 47, 196 PM_EFUSE_ACCESS = 53, 197 PM_FEATURE_CHECK = 63, 198 }; 199 200 /* PMU-FW return status codes */ 201 enum pm_ret_status { 202 XST_PM_SUCCESS = 0, 203 XST_PM_INVALID_VERSION = 4, 204 XST_PM_NO_FEATURE = 19, 205 XST_PM_INVALID_CRC = 301, 206 XST_PM_INTERNAL = 2000, 207 XST_PM_CONFLICT = 2001, 208 XST_PM_NO_ACCESS = 2002, 209 XST_PM_INVALID_NODE = 2003, 210 XST_PM_DOUBLE_REQ = 2004, 211 XST_PM_ABORT_SUSPEND = 2005, 212 XST_PM_MULT_USER = 2008, 213 }; 214 215 enum pm_ioctl_id { 216 IOCTL_GET_RPU_OPER_MODE = 0, 217 IOCTL_SET_RPU_OPER_MODE = 1, 218 IOCTL_RPU_BOOT_ADDR_CONFIG = 2, 219 IOCTL_TCM_COMB_CONFIG = 3, 220 IOCTL_SET_TAPDELAY_BYPASS = 4, 221 IOCTL_SD_DLL_RESET = 6, 222 IOCTL_SET_SD_TAPDELAY = 7, 223 IOCTL_SET_PLL_FRAC_MODE = 8, 224 IOCTL_GET_PLL_FRAC_MODE = 9, 225 IOCTL_SET_PLL_FRAC_DATA = 10, 226 IOCTL_GET_PLL_FRAC_DATA = 11, 227 IOCTL_WRITE_GGS = 12, 228 IOCTL_READ_GGS = 13, 229 IOCTL_WRITE_PGGS = 14, 230 IOCTL_READ_PGGS = 15, 231 /* Set healthy bit value */ 232 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 233 IOCTL_OSPI_MUX_SELECT = 21, 234 /* Register SGI to ATF */ 235 IOCTL_REGISTER_SGI = 25, 236 /* Runtime feature configuration */ 237 IOCTL_SET_FEATURE_CONFIG = 26, 238 IOCTL_GET_FEATURE_CONFIG = 27, 239 /* IOCTL for Secure Read/Write Interface */ 240 IOCTL_READ_REG = 28, 241 IOCTL_MASK_WRITE_REG = 29, 242 /* Dynamic SD/GEM configuration */ 243 IOCTL_SET_SD_CONFIG = 30, 244 IOCTL_SET_GEM_CONFIG = 31, 245 /* IOCTL to get default/current QoS */ 246 IOCTL_GET_QOS = 34, 247 }; 248 249 enum pm_query_id { 250 PM_QID_INVALID = 0, 251 PM_QID_CLOCK_GET_NAME = 1, 252 PM_QID_CLOCK_GET_TOPOLOGY = 2, 253 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, 254 PM_QID_CLOCK_GET_PARENTS = 4, 255 PM_QID_CLOCK_GET_ATTRIBUTES = 5, 256 PM_QID_PINCTRL_GET_NUM_PINS = 6, 257 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7, 258 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8, 259 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9, 260 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10, 261 PM_QID_PINCTRL_GET_PIN_GROUPS = 11, 262 PM_QID_CLOCK_GET_NUM_CLOCKS = 12, 263 PM_QID_CLOCK_GET_MAX_DIVISOR = 13, 264 PM_QID_PINCTRL_GET_ATTRIBUTES = 15, 265 }; 266 267 enum rpu_oper_mode { 268 PM_RPU_MODE_LOCKSTEP = 0, 269 PM_RPU_MODE_SPLIT = 1, 270 }; 271 272 enum rpu_boot_mem { 273 PM_RPU_BOOTMEM_LOVEC = 0, 274 PM_RPU_BOOTMEM_HIVEC = 1, 275 }; 276 277 enum rpu_tcm_comb { 278 PM_RPU_TCM_SPLIT = 0, 279 PM_RPU_TCM_COMB = 1, 280 }; 281 282 enum zynqmp_pm_reset_action { 283 PM_RESET_ACTION_RELEASE = 0, 284 PM_RESET_ACTION_ASSERT = 1, 285 PM_RESET_ACTION_PULSE = 2, 286 }; 287 288 enum zynqmp_pm_reset { 289 ZYNQMP_PM_RESET_START = 1000, 290 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, 291 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, 292 ZYNQMP_PM_RESET_PCIE_CTRL = 1002, 293 ZYNQMP_PM_RESET_DP = 1003, 294 ZYNQMP_PM_RESET_SWDT_CRF = 1004, 295 ZYNQMP_PM_RESET_AFI_FM5 = 1005, 296 ZYNQMP_PM_RESET_AFI_FM4 = 1006, 297 ZYNQMP_PM_RESET_AFI_FM3 = 1007, 298 ZYNQMP_PM_RESET_AFI_FM2 = 1008, 299 ZYNQMP_PM_RESET_AFI_FM1 = 1009, 300 ZYNQMP_PM_RESET_AFI_FM0 = 1010, 301 ZYNQMP_PM_RESET_GDMA = 1011, 302 ZYNQMP_PM_RESET_GPU_PP1 = 1012, 303 ZYNQMP_PM_RESET_GPU_PP0 = 1013, 304 ZYNQMP_PM_RESET_GPU = 1014, 305 ZYNQMP_PM_RESET_GT = 1015, 306 ZYNQMP_PM_RESET_SATA = 1016, 307 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, 308 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, 309 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, 310 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, 311 ZYNQMP_PM_RESET_APU_L2 = 1021, 312 ZYNQMP_PM_RESET_ACPU3 = 1022, 313 ZYNQMP_PM_RESET_ACPU2 = 1023, 314 ZYNQMP_PM_RESET_ACPU1 = 1024, 315 ZYNQMP_PM_RESET_ACPU0 = 1025, 316 ZYNQMP_PM_RESET_DDR = 1026, 317 ZYNQMP_PM_RESET_APM_FPD = 1027, 318 ZYNQMP_PM_RESET_SOFT = 1028, 319 ZYNQMP_PM_RESET_GEM0 = 1029, 320 ZYNQMP_PM_RESET_GEM1 = 1030, 321 ZYNQMP_PM_RESET_GEM2 = 1031, 322 ZYNQMP_PM_RESET_GEM3 = 1032, 323 ZYNQMP_PM_RESET_QSPI = 1033, 324 ZYNQMP_PM_RESET_UART0 = 1034, 325 ZYNQMP_PM_RESET_UART1 = 1035, 326 ZYNQMP_PM_RESET_SPI0 = 1036, 327 ZYNQMP_PM_RESET_SPI1 = 1037, 328 ZYNQMP_PM_RESET_SDIO0 = 1038, 329 ZYNQMP_PM_RESET_SDIO1 = 1039, 330 ZYNQMP_PM_RESET_CAN0 = 1040, 331 ZYNQMP_PM_RESET_CAN1 = 1041, 332 ZYNQMP_PM_RESET_I2C0 = 1042, 333 ZYNQMP_PM_RESET_I2C1 = 1043, 334 ZYNQMP_PM_RESET_TTC0 = 1044, 335 ZYNQMP_PM_RESET_TTC1 = 1045, 336 ZYNQMP_PM_RESET_TTC2 = 1046, 337 ZYNQMP_PM_RESET_TTC3 = 1047, 338 ZYNQMP_PM_RESET_SWDT_CRL = 1048, 339 ZYNQMP_PM_RESET_NAND = 1049, 340 ZYNQMP_PM_RESET_ADMA = 1050, 341 ZYNQMP_PM_RESET_GPIO = 1051, 342 ZYNQMP_PM_RESET_IOU_CC = 1052, 343 ZYNQMP_PM_RESET_TIMESTAMP = 1053, 344 ZYNQMP_PM_RESET_RPU_R50 = 1054, 345 ZYNQMP_PM_RESET_RPU_R51 = 1055, 346 ZYNQMP_PM_RESET_RPU_AMBA = 1056, 347 ZYNQMP_PM_RESET_OCM = 1057, 348 ZYNQMP_PM_RESET_RPU_PGE = 1058, 349 ZYNQMP_PM_RESET_USB0_CORERESET = 1059, 350 ZYNQMP_PM_RESET_USB1_CORERESET = 1060, 351 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, 352 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, 353 ZYNQMP_PM_RESET_USB0_APB = 1063, 354 ZYNQMP_PM_RESET_USB1_APB = 1064, 355 ZYNQMP_PM_RESET_IPI = 1065, 356 ZYNQMP_PM_RESET_APM_LPD = 1066, 357 ZYNQMP_PM_RESET_RTC = 1067, 358 ZYNQMP_PM_RESET_SYSMON = 1068, 359 ZYNQMP_PM_RESET_AFI_FM6 = 1069, 360 ZYNQMP_PM_RESET_LPD_SWDT = 1070, 361 ZYNQMP_PM_RESET_FPD = 1071, 362 ZYNQMP_PM_RESET_RPU_DBG1 = 1072, 363 ZYNQMP_PM_RESET_RPU_DBG0 = 1073, 364 ZYNQMP_PM_RESET_DBG_LPD = 1074, 365 ZYNQMP_PM_RESET_DBG_FPD = 1075, 366 ZYNQMP_PM_RESET_APLL = 1076, 367 ZYNQMP_PM_RESET_DPLL = 1077, 368 ZYNQMP_PM_RESET_VPLL = 1078, 369 ZYNQMP_PM_RESET_IOPLL = 1079, 370 ZYNQMP_PM_RESET_RPLL = 1080, 371 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, 372 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, 373 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, 374 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, 375 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, 376 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, 377 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, 378 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, 379 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, 380 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, 381 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, 382 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, 383 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, 384 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, 385 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, 386 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, 387 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, 388 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, 389 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, 390 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, 391 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, 392 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, 393 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, 394 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, 395 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, 396 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, 397 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, 398 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, 399 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, 400 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, 401 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, 402 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, 403 ZYNQMP_PM_RESET_RPU_LS = 1113, 404 ZYNQMP_PM_RESET_PS_ONLY = 1114, 405 ZYNQMP_PM_RESET_PL = 1115, 406 ZYNQMP_PM_RESET_PS_PL0 = 1116, 407 ZYNQMP_PM_RESET_PS_PL1 = 1117, 408 ZYNQMP_PM_RESET_PS_PL2 = 1118, 409 ZYNQMP_PM_RESET_PS_PL3 = 1119, 410 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 411 }; 412 413 enum zynqmp_pm_suspend_reason { 414 SUSPEND_POWER_REQUEST = 201, 415 SUSPEND_ALERT = 202, 416 SUSPEND_SYSTEM_SHUTDOWN = 203, 417 }; 418 419 enum zynqmp_pm_request_ack { 420 ZYNQMP_PM_REQUEST_ACK_NO = 1, 421 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2, 422 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3, 423 }; 424 425 enum pm_node_id { 426 NODE_SD_0 = 39, 427 NODE_SD_1 = 40, 428 }; 429 430 enum tap_delay_type { 431 PM_TAPDELAY_INPUT = 0, 432 PM_TAPDELAY_OUTPUT = 1, 433 }; 434 435 enum dll_reset_type { 436 PM_DLL_RESET_ASSERT = 0, 437 PM_DLL_RESET_RELEASE = 1, 438 PM_DLL_RESET_PULSE = 2, 439 }; 440 441 enum pm_pinctrl_config_param { 442 PM_PINCTRL_CONFIG_SLEW_RATE = 0, 443 PM_PINCTRL_CONFIG_BIAS_STATUS = 1, 444 PM_PINCTRL_CONFIG_PULL_CTRL = 2, 445 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3, 446 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4, 447 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5, 448 PM_PINCTRL_CONFIG_TRI_STATE = 6, 449 PM_PINCTRL_CONFIG_MAX = 7, 450 }; 451 452 enum pm_pinctrl_slew_rate { 453 PM_PINCTRL_SLEW_RATE_FAST = 0, 454 PM_PINCTRL_SLEW_RATE_SLOW = 1, 455 }; 456 457 enum pm_pinctrl_bias_status { 458 PM_PINCTRL_BIAS_DISABLE = 0, 459 PM_PINCTRL_BIAS_ENABLE = 1, 460 }; 461 462 enum pm_pinctrl_pull_ctrl { 463 PM_PINCTRL_BIAS_PULL_DOWN = 0, 464 PM_PINCTRL_BIAS_PULL_UP = 1, 465 }; 466 467 enum pm_pinctrl_schmitt_cmos { 468 PM_PINCTRL_INPUT_TYPE_CMOS = 0, 469 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1, 470 }; 471 472 enum pm_pinctrl_drive_strength { 473 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0, 474 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1, 475 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2, 476 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3, 477 }; 478 479 enum pm_pinctrl_tri_state { 480 PM_PINCTRL_TRI_STATE_DISABLE = 0, 481 PM_PINCTRL_TRI_STATE_ENABLE = 1, 482 }; 483 484 enum zynqmp_pm_shutdown_type { 485 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0, 486 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1, 487 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2, 488 }; 489 490 enum zynqmp_pm_shutdown_subtype { 491 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0, 492 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1, 493 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2, 494 }; 495 496 enum tap_delay_signal_type { 497 PM_TAPDELAY_NAND_DQS_IN = 0, 498 PM_TAPDELAY_NAND_DQS_OUT = 1, 499 PM_TAPDELAY_QSPI = 2, 500 PM_TAPDELAY_MAX = 3, 501 }; 502 503 enum tap_delay_bypass_ctrl { 504 PM_TAPDELAY_BYPASS_DISABLE = 0, 505 PM_TAPDELAY_BYPASS_ENABLE = 1, 506 }; 507 508 enum ospi_mux_select_type { 509 PM_OSPI_MUX_SEL_DMA = 0, 510 PM_OSPI_MUX_SEL_LINEAR = 1, 511 }; 512 513 enum pm_feature_config_id { 514 PM_FEATURE_INVALID = 0, 515 PM_FEATURE_OVERTEMP_STATUS = 1, 516 PM_FEATURE_OVERTEMP_VALUE = 2, 517 PM_FEATURE_EXTWDT_STATUS = 3, 518 PM_FEATURE_EXTWDT_VALUE = 4, 519 }; 520 521 /** 522 * enum pm_sd_config_type - PM SD configuration. 523 * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE 524 * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1 525 * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2 526 * @SD_CONFIG_FIXED: To set fixed config registers 527 */ 528 enum pm_sd_config_type { 529 SD_CONFIG_EMMC_SEL = 1, 530 SD_CONFIG_BASECLK = 2, 531 SD_CONFIG_8BIT = 3, 532 SD_CONFIG_FIXED = 4, 533 }; 534 535 /** 536 * enum pm_gem_config_type - PM GEM configuration. 537 * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register 538 * @GEM_CONFIG_FIXED: To set fixed config registers 539 */ 540 enum pm_gem_config_type { 541 GEM_CONFIG_SGMII_MODE = 1, 542 GEM_CONFIG_FIXED = 2, 543 }; 544 545 /** 546 * struct zynqmp_pm_query_data - PM query data 547 * @qid: query ID 548 * @arg1: Argument 1 of query data 549 * @arg2: Argument 2 of query data 550 * @arg3: Argument 3 of query data 551 */ 552 struct zynqmp_pm_query_data { 553 u32 qid; 554 u32 arg1; 555 u32 arg2; 556 u32 arg3; 557 }; 558 559 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...); 560 int zynqmp_pm_invoke_fw_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...); 561 562 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) 563 int zynqmp_pm_get_api_version(u32 *version); 564 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); 565 int zynqmp_pm_get_family_info(u32 *family); 566 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); 567 int zynqmp_pm_clock_enable(u32 clock_id); 568 int zynqmp_pm_clock_disable(u32 clock_id); 569 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); 570 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); 571 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); 572 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); 573 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); 574 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); 575 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); 576 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); 577 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); 578 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); 579 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); 580 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select); 581 int zynqmp_pm_reset_assert(const u32 reset, 582 const enum zynqmp_pm_reset_action assert_flag); 583 int zynqmp_pm_reset_get_status(const u32 reset, u32 *status); 584 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode); 585 int zynqmp_pm_bootmode_write(u32 ps_mode); 586 int zynqmp_pm_set_suspend_mode(u32 mode); 587 int zynqmp_pm_request_node(const u32 node, const u32 capabilities, 588 const u32 qos, const enum zynqmp_pm_request_ack ack); 589 int zynqmp_pm_release_node(const u32 node); 590 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, 591 const u32 qos, 592 const enum zynqmp_pm_request_ack ack); 593 int zynqmp_pm_efuse_access(const u64 address, u32 *out); 594 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); 595 int zynqmp_pm_fpga_get_status(u32 *value); 596 int zynqmp_pm_fpga_get_config_status(u32 *value); 597 int zynqmp_pm_write_ggs(u32 index, u32 value); 598 int zynqmp_pm_read_ggs(u32 index, u32 *value); 599 int zynqmp_pm_write_pggs(u32 index, u32 value); 600 int zynqmp_pm_read_pggs(u32 index, u32 *value); 601 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value); 602 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); 603 int zynqmp_pm_set_boot_health_status(u32 value); 604 int zynqmp_pm_pinctrl_request(const u32 pin); 605 int zynqmp_pm_pinctrl_release(const u32 pin); 606 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id); 607 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, 608 u32 *value); 609 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, 610 u32 value); 611 int zynqmp_pm_load_pdi(const u32 src, const u64 address); 612 int zynqmp_pm_register_notifier(const u32 node, const u32 event, 613 const u32 wake, const u32 enable); 614 int zynqmp_pm_feature(const u32 api_id); 615 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); 616 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); 617 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); 618 int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value); 619 int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, 620 u32 mask, u32 value); 621 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); 622 int zynqmp_pm_force_pwrdwn(const u32 target, 623 const enum zynqmp_pm_request_ack ack); 624 int zynqmp_pm_request_wake(const u32 node, 625 const bool set_addr, 626 const u64 address, 627 const enum zynqmp_pm_request_ack ack); 628 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode); 629 int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode); 630 int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode); 631 int zynqmp_pm_get_node_status(const u32 node, u32 *const status, 632 u32 *const requirements, u32 *const usage); 633 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); 634 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, 635 u32 value); 636 #else 637 static inline int zynqmp_pm_get_api_version(u32 *version) 638 { 639 return -ENODEV; 640 } 641 642 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) 643 { 644 return -ENODEV; 645 } 646 647 static inline int zynqmp_pm_get_family_info(u32 *family) 648 { 649 return -ENODEV; 650 } 651 652 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, 653 u32 *out) 654 { 655 return -ENODEV; 656 } 657 658 static inline int zynqmp_pm_clock_enable(u32 clock_id) 659 { 660 return -ENODEV; 661 } 662 663 static inline int zynqmp_pm_clock_disable(u32 clock_id) 664 { 665 return -ENODEV; 666 } 667 668 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) 669 { 670 return -ENODEV; 671 } 672 673 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) 674 { 675 return -ENODEV; 676 } 677 678 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) 679 { 680 return -ENODEV; 681 } 682 683 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) 684 { 685 return -ENODEV; 686 } 687 688 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) 689 { 690 return -ENODEV; 691 } 692 693 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) 694 { 695 return -ENODEV; 696 } 697 698 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) 699 { 700 return -ENODEV; 701 } 702 703 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) 704 { 705 return -ENODEV; 706 } 707 708 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) 709 { 710 return -ENODEV; 711 } 712 713 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) 714 { 715 return -ENODEV; 716 } 717 718 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) 719 { 720 return -ENODEV; 721 } 722 723 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select) 724 { 725 return -ENODEV; 726 } 727 728 static inline int zynqmp_pm_reset_assert(const u32 reset, 729 const enum zynqmp_pm_reset_action assert_flag) 730 { 731 return -ENODEV; 732 } 733 734 static inline int zynqmp_pm_reset_get_status(const u32 reset, u32 *status) 735 { 736 return -ENODEV; 737 } 738 739 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode) 740 { 741 return -ENODEV; 742 } 743 744 static inline int zynqmp_pm_bootmode_write(u32 ps_mode) 745 { 746 return -ENODEV; 747 } 748 749 static inline int zynqmp_pm_set_suspend_mode(u32 mode) 750 { 751 return -ENODEV; 752 } 753 754 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, 755 const u32 qos, 756 const enum zynqmp_pm_request_ack ack) 757 { 758 return -ENODEV; 759 } 760 761 static inline int zynqmp_pm_release_node(const u32 node) 762 { 763 return -ENODEV; 764 } 765 766 static inline int zynqmp_pm_set_requirement(const u32 node, 767 const u32 capabilities, 768 const u32 qos, 769 const enum zynqmp_pm_request_ack ack) 770 { 771 return -ENODEV; 772 } 773 774 static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) 775 { 776 return -ENODEV; 777 } 778 779 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, 780 const u32 flags) 781 { 782 return -ENODEV; 783 } 784 785 static inline int zynqmp_pm_fpga_get_status(u32 *value) 786 { 787 return -ENODEV; 788 } 789 790 static inline int zynqmp_pm_fpga_get_config_status(u32 *value) 791 { 792 return -ENODEV; 793 } 794 795 static inline int zynqmp_pm_write_ggs(u32 index, u32 value) 796 { 797 return -ENODEV; 798 } 799 800 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) 801 { 802 return -ENODEV; 803 } 804 805 static inline int zynqmp_pm_write_pggs(u32 index, u32 value) 806 { 807 return -ENODEV; 808 } 809 810 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) 811 { 812 return -ENODEV; 813 } 814 815 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value) 816 { 817 return -ENODEV; 818 } 819 820 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) 821 { 822 return -ENODEV; 823 } 824 825 static inline int zynqmp_pm_set_boot_health_status(u32 value) 826 { 827 return -ENODEV; 828 } 829 830 static inline int zynqmp_pm_pinctrl_request(const u32 pin) 831 { 832 return -ENODEV; 833 } 834 835 static inline int zynqmp_pm_pinctrl_release(const u32 pin) 836 { 837 return -ENODEV; 838 } 839 840 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) 841 { 842 return -ENODEV; 843 } 844 845 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id) 846 { 847 return -ENODEV; 848 } 849 850 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, 851 u32 *value) 852 { 853 return -ENODEV; 854 } 855 856 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, 857 u32 value) 858 { 859 return -ENODEV; 860 } 861 862 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address) 863 { 864 return -ENODEV; 865 } 866 867 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event, 868 const u32 wake, const u32 enable) 869 { 870 return -ENODEV; 871 } 872 873 static inline int zynqmp_pm_feature(const u32 api_id) 874 { 875 return -ENODEV; 876 } 877 878 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, 879 u32 value) 880 { 881 return -ENODEV; 882 } 883 884 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, 885 u32 *payload) 886 { 887 return -ENODEV; 888 } 889 890 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) 891 { 892 return -ENODEV; 893 } 894 895 static inline int zynqmp_pm_force_pwrdwn(const u32 target, 896 const enum zynqmp_pm_request_ack ack) 897 { 898 return -ENODEV; 899 } 900 901 static inline int zynqmp_pm_request_wake(const u32 node, 902 const bool set_addr, 903 const u64 address, 904 const enum zynqmp_pm_request_ack ack) 905 { 906 return -ENODEV; 907 } 908 909 static inline int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value) 910 { 911 return -ENODEV; 912 } 913 914 static inline int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, 915 u32 mask, u32 value) 916 { 917 return -ENODEV; 918 } 919 920 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) 921 { 922 return -ENODEV; 923 } 924 925 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode) 926 { 927 return -ENODEV; 928 } 929 930 static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode) 931 { 932 return -ENODEV; 933 } 934 935 static inline int zynqmp_pm_get_node_status(const u32 node, u32 *const status, 936 u32 *const requirements, 937 u32 *const usage) 938 { 939 return -ENODEV; 940 } 941 942 static inline int zynqmp_pm_set_sd_config(u32 node, 943 enum pm_sd_config_type config, 944 u32 value) 945 { 946 return -ENODEV; 947 } 948 949 static inline int zynqmp_pm_set_gem_config(u32 node, 950 enum pm_gem_config_type config, 951 u32 value) 952 { 953 return -ENODEV; 954 } 955 956 #endif 957 958 #endif /* __FIRMWARE_ZYNQMP_H__ */ 959