1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx ZynqMP DPDMA Engine driver
4 *
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
6 *
7 * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/dma/xilinx_dpdma.h>
16 #include <linux/dmaengine.h>
17 #include <linux/dmapool.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_dma.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/wait.h>
27
28 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
29
30 #include "../dmaengine.h"
31 #include "../virt-dma.h"
32
33 /* DPDMA registers */
34 #define XILINX_DPDMA_ERR_CTRL 0x000
35 #define XILINX_DPDMA_ISR 0x004
36 #define XILINX_DPDMA_IMR 0x008
37 #define XILINX_DPDMA_IEN 0x00c
38 #define XILINX_DPDMA_IDS 0x010
39 #define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0)
40 #define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0)
41 #define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6)
42 #define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6)
43 #define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12)
44 #define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12)
45 #define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16)
46 #define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18)
47 #define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24)
48 #define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25)
49 #define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26)
50 #define XILINX_DPDMA_INTR_VSYNC BIT(27)
51 #define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0x00041000
52 #define XILINX_DPDMA_INTR_CHAN_ERR 0x00fff000
53 #define XILINX_DPDMA_INTR_GLOBAL_ERR 0x07000000
54 #define XILINX_DPDMA_INTR_ERR_ALL 0x07fff000
55 #define XILINX_DPDMA_INTR_CHAN_MASK 0x00041041
56 #define XILINX_DPDMA_INTR_GLOBAL_MASK 0x0f000000
57 #define XILINX_DPDMA_INTR_ALL 0x0fffffff
58 #define XILINX_DPDMA_EISR 0x014
59 #define XILINX_DPDMA_EIMR 0x018
60 #define XILINX_DPDMA_EIEN 0x01c
61 #define XILINX_DPDMA_EIDS 0x020
62 #define XILINX_DPDMA_EINTR_INV_APB BIT(0)
63 #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1)
64 #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1)
65 #define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7)
66 #define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7)
67 #define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13)
68 #define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13)
69 #define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19)
70 #define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19)
71 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25)
72 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25)
73 #define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32)
74 #define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0x02082082
75 #define XILINX_DPDMA_EINTR_CHAN_ERR 0x7ffffffe
76 #define XILINX_DPDMA_EINTR_GLOBAL_ERR 0x80000001
77 #define XILINX_DPDMA_EINTR_ALL 0xffffffff
78 #define XILINX_DPDMA_CNTL 0x100
79 #define XILINX_DPDMA_GBL 0x104
80 #define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0)
81 #define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6)
82 #define XILINX_DPDMA_ALC0_CNTL 0x108
83 #define XILINX_DPDMA_ALC0_STATUS 0x10c
84 #define XILINX_DPDMA_ALC0_MAX 0x110
85 #define XILINX_DPDMA_ALC0_MIN 0x114
86 #define XILINX_DPDMA_ALC0_ACC 0x118
87 #define XILINX_DPDMA_ALC0_ACC_TRAN 0x11c
88 #define XILINX_DPDMA_ALC1_CNTL 0x120
89 #define XILINX_DPDMA_ALC1_STATUS 0x124
90 #define XILINX_DPDMA_ALC1_MAX 0x128
91 #define XILINX_DPDMA_ALC1_MIN 0x12c
92 #define XILINX_DPDMA_ALC1_ACC 0x130
93 #define XILINX_DPDMA_ALC1_ACC_TRAN 0x134
94
95 /* Channel register */
96 #define XILINX_DPDMA_CH_BASE 0x200
97 #define XILINX_DPDMA_CH_OFFSET 0x100
98 #define XILINX_DPDMA_CH_DESC_START_ADDRE 0x000
99 #define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0)
100 #define XILINX_DPDMA_CH_DESC_START_ADDR 0x004
101 #define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0x008
102 #define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0x00c
103 #define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0x010
104 #define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0x014
105 #define XILINX_DPDMA_CH_CNTL 0x018
106 #define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0)
107 #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1)
108 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2)
109 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6)
110 #define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10)
111 #define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11
112 #define XILINX_DPDMA_CH_STATUS 0x01c
113 #define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21)
114 #define XILINX_DPDMA_CH_VDO 0x020
115 #define XILINX_DPDMA_CH_PYLD_SZ 0x024
116 #define XILINX_DPDMA_CH_DESC_ID 0x028
117 #define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0)
118
119 /* DPDMA descriptor fields */
120 #define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5
121 #define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8)
122 #define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9)
123 #define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10)
124 #define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18)
125 #define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19)
126 #define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20)
127 #define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21)
128 #define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0)
129 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0)
130 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18)
131 #define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0)
132 #define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16)
133
134 #define XILINX_DPDMA_ALIGN_BYTES 256
135 #define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128
136
137 #define XILINX_DPDMA_NUM_CHAN 6
138
139 struct xilinx_dpdma_chan;
140
141 /**
142 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
143 * @control: control configuration field
144 * @desc_id: descriptor ID
145 * @xfer_size: transfer size
146 * @hsize_stride: horizontal size and stride
147 * @timestamp_lsb: LSB of time stamp
148 * @timestamp_msb: MSB of time stamp
149 * @addr_ext: upper 16 bit of 48 bit address (next_desc and src_addr)
150 * @next_desc: next descriptor 32 bit address
151 * @src_addr: payload source address (1st page, 32 LSB)
152 * @addr_ext_23: payload source address (2nd and 3rd pages, 16 LSBs)
153 * @addr_ext_45: payload source address (4th and 5th pages, 16 LSBs)
154 * @src_addr2: payload source address (2nd page, 32 LSB)
155 * @src_addr3: payload source address (3rd page, 32 LSB)
156 * @src_addr4: payload source address (4th page, 32 LSB)
157 * @src_addr5: payload source address (5th page, 32 LSB)
158 * @crc: descriptor CRC
159 */
160 struct xilinx_dpdma_hw_desc {
161 u32 control;
162 u32 desc_id;
163 u32 xfer_size;
164 u32 hsize_stride;
165 u32 timestamp_lsb;
166 u32 timestamp_msb;
167 u32 addr_ext;
168 u32 next_desc;
169 u32 src_addr;
170 u32 addr_ext_23;
171 u32 addr_ext_45;
172 u32 src_addr2;
173 u32 src_addr3;
174 u32 src_addr4;
175 u32 src_addr5;
176 u32 crc;
177 } __aligned(XILINX_DPDMA_ALIGN_BYTES);
178
179 /**
180 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
181 * @hw: DPDMA hardware descriptor
182 * @node: list node for software descriptors
183 * @dma_addr: DMA address of the software descriptor
184 */
185 struct xilinx_dpdma_sw_desc {
186 struct xilinx_dpdma_hw_desc hw;
187 struct list_head node;
188 dma_addr_t dma_addr;
189 };
190
191 /**
192 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor
193 * @vdesc: virtual DMA descriptor
194 * @chan: DMA channel
195 * @descriptors: list of software descriptors
196 * @error: an error has been detected with this descriptor
197 */
198 struct xilinx_dpdma_tx_desc {
199 struct virt_dma_desc vdesc;
200 struct xilinx_dpdma_chan *chan;
201 struct list_head descriptors;
202 bool error;
203 };
204
205 #define to_dpdma_tx_desc(_desc) \
206 container_of(_desc, struct xilinx_dpdma_tx_desc, vdesc)
207
208 /**
209 * struct xilinx_dpdma_chan - DPDMA channel
210 * @vchan: virtual DMA channel
211 * @reg: register base address
212 * @id: channel ID
213 * @wait_to_stop: queue to wait for outstanding transactions before stopping
214 * @running: true if the channel is running
215 * @first_frame: flag for the first frame of stream
216 * @video_group: flag if multi-channel operation is needed for video channels
217 * @lock: lock to access struct xilinx_dpdma_chan. Must be taken before
218 * @vchan.lock, if both are to be held.
219 * @desc_pool: descriptor allocation pool
220 * @err_task: error IRQ bottom half handler
221 * @desc: References to descriptors being processed
222 * @desc.pending: Descriptor schedule to the hardware, pending execution
223 * @desc.active: Descriptor being executed by the hardware
224 * @xdev: DPDMA device
225 */
226 struct xilinx_dpdma_chan {
227 struct virt_dma_chan vchan;
228 void __iomem *reg;
229 unsigned int id;
230
231 wait_queue_head_t wait_to_stop;
232 bool running;
233 bool first_frame;
234 bool video_group;
235
236 spinlock_t lock; /* lock to access struct xilinx_dpdma_chan */
237 struct dma_pool *desc_pool;
238 struct tasklet_struct err_task;
239
240 struct {
241 struct xilinx_dpdma_tx_desc *pending;
242 struct xilinx_dpdma_tx_desc *active;
243 } desc;
244
245 struct xilinx_dpdma_device *xdev;
246 };
247
248 #define to_xilinx_chan(_chan) \
249 container_of(_chan, struct xilinx_dpdma_chan, vchan.chan)
250
251 /**
252 * struct xilinx_dpdma_device - DPDMA device
253 * @common: generic dma device structure
254 * @reg: register base address
255 * @dev: generic device structure
256 * @irq: the interrupt number
257 * @axi_clk: axi clock
258 * @chan: DPDMA channels
259 * @ext_addr: flag for 64 bit system (48 bit addressing)
260 */
261 struct xilinx_dpdma_device {
262 struct dma_device common;
263 void __iomem *reg;
264 struct device *dev;
265 int irq;
266
267 struct clk *axi_clk;
268 struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN];
269
270 bool ext_addr;
271 };
272
273 /* -----------------------------------------------------------------------------
274 * DebugFS
275 */
276 #define XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE 32
277 #define XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR "65535"
278
279 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */
280 enum xilinx_dpdma_testcases {
281 DPDMA_TC_INTR_DONE,
282 DPDMA_TC_NONE
283 };
284
285 struct xilinx_dpdma_debugfs {
286 enum xilinx_dpdma_testcases testcase;
287 u16 xilinx_dpdma_irq_done_count;
288 unsigned int chan_id;
289 };
290
291 static struct xilinx_dpdma_debugfs dpdma_debugfs;
292 struct xilinx_dpdma_debugfs_request {
293 const char *name;
294 enum xilinx_dpdma_testcases tc;
295 ssize_t (*read)(char *buf);
296 int (*write)(char *args);
297 };
298
xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan * chan)299 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan)
300 {
301 if (IS_ENABLED(CONFIG_DEBUG_FS) && chan->id == dpdma_debugfs.chan_id)
302 dpdma_debugfs.xilinx_dpdma_irq_done_count++;
303 }
304
xilinx_dpdma_debugfs_desc_done_irq_read(char * buf)305 static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf)
306 {
307 size_t out_str_len;
308
309 dpdma_debugfs.testcase = DPDMA_TC_NONE;
310
311 out_str_len = strlen(XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR);
312 out_str_len = min_t(size_t, XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE,
313 out_str_len + 1);
314 snprintf(buf, out_str_len, "%d",
315 dpdma_debugfs.xilinx_dpdma_irq_done_count);
316
317 return 0;
318 }
319
xilinx_dpdma_debugfs_desc_done_irq_write(char * args)320 static int xilinx_dpdma_debugfs_desc_done_irq_write(char *args)
321 {
322 char *arg;
323 int ret;
324 u32 id;
325
326 arg = strsep(&args, " ");
327 if (!arg || strncasecmp(arg, "start", 5))
328 return -EINVAL;
329
330 arg = strsep(&args, " ");
331 if (!arg)
332 return -EINVAL;
333
334 ret = kstrtou32(arg, 0, &id);
335 if (ret < 0)
336 return ret;
337
338 if (id < ZYNQMP_DPDMA_VIDEO0 || id > ZYNQMP_DPDMA_AUDIO1)
339 return -EINVAL;
340
341 dpdma_debugfs.testcase = DPDMA_TC_INTR_DONE;
342 dpdma_debugfs.xilinx_dpdma_irq_done_count = 0;
343 dpdma_debugfs.chan_id = id;
344
345 return 0;
346 }
347
348 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */
349 static struct xilinx_dpdma_debugfs_request dpdma_debugfs_reqs[] = {
350 {
351 .name = "DESCRIPTOR_DONE_INTR",
352 .tc = DPDMA_TC_INTR_DONE,
353 .read = xilinx_dpdma_debugfs_desc_done_irq_read,
354 .write = xilinx_dpdma_debugfs_desc_done_irq_write,
355 },
356 };
357
xilinx_dpdma_debugfs_read(struct file * f,char __user * buf,size_t size,loff_t * pos)358 static ssize_t xilinx_dpdma_debugfs_read(struct file *f, char __user *buf,
359 size_t size, loff_t *pos)
360 {
361 enum xilinx_dpdma_testcases testcase;
362 char *kern_buff;
363 int ret = 0;
364
365 if (*pos != 0 || size <= 0)
366 return -EINVAL;
367
368 kern_buff = kzalloc(XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, GFP_KERNEL);
369 if (!kern_buff) {
370 dpdma_debugfs.testcase = DPDMA_TC_NONE;
371 return -ENOMEM;
372 }
373
374 testcase = READ_ONCE(dpdma_debugfs.testcase);
375 if (testcase != DPDMA_TC_NONE) {
376 ret = dpdma_debugfs_reqs[testcase].read(kern_buff);
377 if (ret < 0)
378 goto done;
379 } else {
380 strscpy(kern_buff, "No testcase executed",
381 XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE);
382 }
383
384 size = min(size, strlen(kern_buff));
385 if (copy_to_user(buf, kern_buff, size))
386 ret = -EFAULT;
387
388 done:
389 kfree(kern_buff);
390 if (ret)
391 return ret;
392
393 *pos = size + 1;
394 return size;
395 }
396
xilinx_dpdma_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)397 static ssize_t xilinx_dpdma_debugfs_write(struct file *f,
398 const char __user *buf, size_t size,
399 loff_t *pos)
400 {
401 char *kern_buff, *kern_buff_start;
402 char *testcase;
403 unsigned int i;
404 int ret;
405
406 if (*pos != 0 || size <= 0)
407 return -EINVAL;
408
409 /* Supporting single instance of test as of now. */
410 if (dpdma_debugfs.testcase != DPDMA_TC_NONE)
411 return -EBUSY;
412
413 kern_buff = kzalloc(size, GFP_KERNEL);
414 if (!kern_buff)
415 return -ENOMEM;
416 kern_buff_start = kern_buff;
417
418 ret = strncpy_from_user(kern_buff, buf, size);
419 if (ret < 0)
420 goto done;
421
422 /* Read the testcase name from a user request. */
423 testcase = strsep(&kern_buff, " ");
424
425 for (i = 0; i < ARRAY_SIZE(dpdma_debugfs_reqs); i++) {
426 if (!strcasecmp(testcase, dpdma_debugfs_reqs[i].name))
427 break;
428 }
429
430 if (i == ARRAY_SIZE(dpdma_debugfs_reqs)) {
431 ret = -EINVAL;
432 goto done;
433 }
434
435 ret = dpdma_debugfs_reqs[i].write(kern_buff);
436 if (ret < 0)
437 goto done;
438
439 ret = size;
440
441 done:
442 kfree(kern_buff_start);
443 return ret;
444 }
445
446 static const struct file_operations fops_xilinx_dpdma_dbgfs = {
447 .owner = THIS_MODULE,
448 .read = xilinx_dpdma_debugfs_read,
449 .write = xilinx_dpdma_debugfs_write,
450 };
451
xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device * xdev)452 static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev)
453 {
454 struct dentry *dent;
455
456 dpdma_debugfs.testcase = DPDMA_TC_NONE;
457
458 dent = debugfs_create_file("testcase", 0444, xdev->common.dbg_dev_root,
459 NULL, &fops_xilinx_dpdma_dbgfs);
460 if (IS_ERR(dent))
461 dev_err(xdev->dev, "Failed to create debugfs testcase file\n");
462 }
463
464 /* -----------------------------------------------------------------------------
465 * I/O Accessors
466 */
467
dpdma_read(void __iomem * base,u32 offset)468 static inline u32 dpdma_read(void __iomem *base, u32 offset)
469 {
470 return ioread32(base + offset);
471 }
472
dpdma_write(void __iomem * base,u32 offset,u32 val)473 static inline void dpdma_write(void __iomem *base, u32 offset, u32 val)
474 {
475 iowrite32(val, base + offset);
476 }
477
dpdma_clr(void __iomem * base,u32 offset,u32 clr)478 static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr)
479 {
480 dpdma_write(base, offset, dpdma_read(base, offset) & ~clr);
481 }
482
dpdma_set(void __iomem * base,u32 offset,u32 set)483 static inline void dpdma_set(void __iomem *base, u32 offset, u32 set)
484 {
485 dpdma_write(base, offset, dpdma_read(base, offset) | set);
486 }
487
488 /* -----------------------------------------------------------------------------
489 * Descriptor Operations
490 */
491
492 /**
493 * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor
494 * @xdev: DPDMA device
495 * @sw_desc: The software descriptor in which to set DMA addresses
496 * @prev: The previous descriptor
497 * @dma_addr: array of dma addresses
498 * @num_src_addr: number of addresses in @dma_addr
499 *
500 * Set all the DMA addresses in the hardware descriptor corresponding to @dev
501 * from @dma_addr. If a previous descriptor is specified in @prev, its next
502 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be
503 * identical to @sw_desc for cyclic transfers.
504 */
xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device * xdev,struct xilinx_dpdma_sw_desc * sw_desc,struct xilinx_dpdma_sw_desc * prev,dma_addr_t dma_addr[],unsigned int num_src_addr)505 static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev,
506 struct xilinx_dpdma_sw_desc *sw_desc,
507 struct xilinx_dpdma_sw_desc *prev,
508 dma_addr_t dma_addr[],
509 unsigned int num_src_addr)
510 {
511 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
512 unsigned int i;
513
514 hw_desc->src_addr = lower_32_bits(dma_addr[0]);
515 if (xdev->ext_addr)
516 hw_desc->addr_ext |=
517 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK,
518 upper_32_bits(dma_addr[0]));
519
520 for (i = 1; i < num_src_addr; i++) {
521 u32 *addr = &hw_desc->src_addr2;
522
523 addr[i - 1] = lower_32_bits(dma_addr[i]);
524
525 if (xdev->ext_addr) {
526 u32 *addr_ext = &hw_desc->addr_ext_23;
527 u32 addr_msb;
528
529 addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0);
530 addr_msb <<= 16 * ((i - 1) % 2);
531 addr_ext[(i - 1) / 2] |= addr_msb;
532 }
533 }
534
535 if (!prev)
536 return;
537
538 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
539 if (xdev->ext_addr)
540 prev->hw.addr_ext |=
541 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK,
542 upper_32_bits(sw_desc->dma_addr));
543 }
544
545 /**
546 * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor
547 * @chan: DPDMA channel
548 *
549 * Allocate a software descriptor from the channel's descriptor pool.
550 *
551 * Return: a software descriptor or NULL.
552 */
553 static struct xilinx_dpdma_sw_desc *
xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan * chan)554 xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan)
555 {
556 struct xilinx_dpdma_sw_desc *sw_desc;
557 dma_addr_t dma_addr;
558
559 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr);
560 if (!sw_desc)
561 return NULL;
562
563 sw_desc->dma_addr = dma_addr;
564
565 return sw_desc;
566 }
567
568 /**
569 * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor
570 * @chan: DPDMA channel
571 * @sw_desc: software descriptor to free
572 *
573 * Free a software descriptor from the channel's descriptor pool.
574 */
575 static void
xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan * chan,struct xilinx_dpdma_sw_desc * sw_desc)576 xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan,
577 struct xilinx_dpdma_sw_desc *sw_desc)
578 {
579 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr);
580 }
581
582 /**
583 * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor
584 * @chan: DPDMA channel
585 * @tx_desc: tx descriptor to dump
586 *
587 * Dump contents of a tx descriptor
588 */
xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan * chan,struct xilinx_dpdma_tx_desc * tx_desc)589 static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan,
590 struct xilinx_dpdma_tx_desc *tx_desc)
591 {
592 struct xilinx_dpdma_sw_desc *sw_desc;
593 struct device *dev = chan->xdev->dev;
594 unsigned int i = 0;
595
596 dev_dbg(dev, "------- TX descriptor dump start -------\n");
597 dev_dbg(dev, "------- channel ID = %d -------\n", chan->id);
598
599 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) {
600 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
601
602 dev_dbg(dev, "------- HW descriptor %d -------\n", i++);
603 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr);
604 dev_dbg(dev, "control: 0x%08x\n", hw_desc->control);
605 dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id);
606 dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size);
607 dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride);
608 dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb);
609 dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb);
610 dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext);
611 dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc);
612 dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr);
613 dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23);
614 dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45);
615 dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2);
616 dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3);
617 dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4);
618 dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5);
619 dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc);
620 }
621
622 dev_dbg(dev, "------- TX descriptor dump end -------\n");
623 }
624
625 /**
626 * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor
627 * @chan: DPDMA channel
628 *
629 * Allocate a tx descriptor.
630 *
631 * Return: a tx descriptor or NULL.
632 */
633 static struct xilinx_dpdma_tx_desc *
xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan * chan)634 xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan)
635 {
636 struct xilinx_dpdma_tx_desc *tx_desc;
637
638 tx_desc = kzalloc(sizeof(*tx_desc), GFP_NOWAIT);
639 if (!tx_desc)
640 return NULL;
641
642 INIT_LIST_HEAD(&tx_desc->descriptors);
643 tx_desc->chan = chan;
644 tx_desc->error = false;
645
646 return tx_desc;
647 }
648
649 /**
650 * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor
651 * @vdesc: virtual DMA descriptor
652 *
653 * Free the virtual DMA descriptor @vdesc including its software descriptors.
654 */
xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc * vdesc)655 static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc)
656 {
657 struct xilinx_dpdma_sw_desc *sw_desc, *next;
658 struct xilinx_dpdma_tx_desc *desc;
659
660 if (!vdesc)
661 return;
662
663 desc = to_dpdma_tx_desc(vdesc);
664
665 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) {
666 list_del(&sw_desc->node);
667 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc);
668 }
669
670 kfree(desc);
671 }
672
673 /**
674 * xilinx_dpdma_chan_prep_cyclic - Prepare a cyclic dma descriptor
675 * @chan: DPDMA channel
676 * @buf_addr: buffer address
677 * @buf_len: buffer length
678 * @period_len: number of periods
679 * @flags: tx flags argument passed in to prepare function
680 *
681 * Prepare a tx descriptor incudling internal software/hardware descriptors
682 * for the given cyclic transaction.
683 *
684 * Return: A dma async tx descriptor on success, or NULL.
685 */
686 static struct dma_async_tx_descriptor *
xilinx_dpdma_chan_prep_cyclic(struct xilinx_dpdma_chan * chan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,unsigned long flags)687 xilinx_dpdma_chan_prep_cyclic(struct xilinx_dpdma_chan *chan,
688 dma_addr_t buf_addr, size_t buf_len,
689 size_t period_len, unsigned long flags)
690 {
691 struct xilinx_dpdma_tx_desc *tx_desc;
692 struct xilinx_dpdma_sw_desc *sw_desc, *last = NULL;
693 unsigned int periods = buf_len / period_len;
694 unsigned int i;
695
696 tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan);
697 if (!tx_desc)
698 return NULL;
699
700 for (i = 0; i < periods; i++) {
701 struct xilinx_dpdma_hw_desc *hw_desc;
702
703 if (!IS_ALIGNED(buf_addr, XILINX_DPDMA_ALIGN_BYTES)) {
704 dev_err(chan->xdev->dev,
705 "buffer should be aligned at %d B\n",
706 XILINX_DPDMA_ALIGN_BYTES);
707 goto error;
708 }
709
710 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
711 if (!sw_desc)
712 goto error;
713
714 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, last,
715 &buf_addr, 1);
716 hw_desc = &sw_desc->hw;
717 hw_desc->xfer_size = period_len;
718 hw_desc->hsize_stride =
719 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK,
720 period_len) |
721 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK,
722 period_len);
723 hw_desc->control = XILINX_DPDMA_DESC_CONTROL_PREEMBLE |
724 XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE |
725 XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR;
726
727 list_add_tail(&sw_desc->node, &tx_desc->descriptors);
728
729 buf_addr += period_len;
730 last = sw_desc;
731 }
732
733 sw_desc = list_first_entry(&tx_desc->descriptors,
734 struct xilinx_dpdma_sw_desc, node);
735 last->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
736 if (chan->xdev->ext_addr)
737 last->hw.addr_ext |=
738 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK,
739 upper_32_bits(sw_desc->dma_addr));
740
741 last->hw.control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME;
742
743 return vchan_tx_prep(&chan->vchan, &tx_desc->vdesc, flags);
744
745 error:
746 xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc);
747
748 return NULL;
749 }
750
751 /**
752 * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma
753 * descriptor
754 * @chan: DPDMA channel
755 * @xt: dma interleaved template
756 *
757 * Prepare a tx descriptor including internal software/hardware descriptors
758 * based on @xt.
759 *
760 * Return: A DPDMA TX descriptor on success, or NULL.
761 */
762 static struct xilinx_dpdma_tx_desc *
xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan * chan,struct dma_interleaved_template * xt)763 xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan,
764 struct dma_interleaved_template *xt)
765 {
766 struct xilinx_dpdma_tx_desc *tx_desc;
767 struct xilinx_dpdma_sw_desc *sw_desc;
768 struct xilinx_dpdma_hw_desc *hw_desc;
769 size_t hsize = xt->sgl[0].size;
770 size_t stride = hsize + xt->sgl[0].icg;
771
772 if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) {
773 dev_err(chan->xdev->dev,
774 "chan%u: buffer should be aligned at %d B\n",
775 chan->id, XILINX_DPDMA_ALIGN_BYTES);
776 return NULL;
777 }
778
779 tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan);
780 if (!tx_desc)
781 return NULL;
782
783 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
784 if (!sw_desc) {
785 xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc);
786 return NULL;
787 }
788
789 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc,
790 &xt->src_start, 1);
791
792 hw_desc = &sw_desc->hw;
793 hsize = ALIGN(hsize, XILINX_DPDMA_LINESIZE_ALIGN_BITS / 8);
794 hw_desc->xfer_size = hsize * xt->numf;
795 hw_desc->hsize_stride =
796 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, hsize) |
797 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK,
798 stride / 16);
799 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE;
800 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR;
801 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE;
802 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME;
803
804 list_add_tail(&sw_desc->node, &tx_desc->descriptors);
805
806 return tx_desc;
807 }
808
809 /* -----------------------------------------------------------------------------
810 * DPDMA Channel Operations
811 */
812
813 /**
814 * xilinx_dpdma_chan_enable - Enable the channel
815 * @chan: DPDMA channel
816 *
817 * Enable the channel and its interrupts. Set the QoS values for video class.
818 */
xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan * chan)819 static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan)
820 {
821 u32 reg;
822
823 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id)
824 | XILINX_DPDMA_INTR_GLOBAL_MASK;
825 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
826 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)
827 | XILINX_DPDMA_INTR_GLOBAL_ERR;
828 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
829
830 reg = XILINX_DPDMA_CH_CNTL_ENABLE
831 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK,
832 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
833 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK,
834 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
835 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK,
836 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS);
837 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg);
838 }
839
840 /**
841 * xilinx_dpdma_chan_disable - Disable the channel
842 * @chan: DPDMA channel
843 *
844 * Disable the channel and its interrupts.
845 */
xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan * chan)846 static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan)
847 {
848 u32 reg;
849
850 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id;
851 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
852 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id;
853 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
854
855 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
856 }
857
858 /**
859 * xilinx_dpdma_chan_pause - Pause the channel
860 * @chan: DPDMA channel
861 *
862 * Pause the channel.
863 */
xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan * chan)864 static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan)
865 {
866 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
867 }
868
869 /**
870 * xilinx_dpdma_chan_unpause - Unpause the channel
871 * @chan: DPDMA channel
872 *
873 * Unpause the channel.
874 */
xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan * chan)875 static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan)
876 {
877 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
878 }
879
xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan * chan)880 static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan)
881 {
882 struct xilinx_dpdma_device *xdev = chan->xdev;
883 u32 channels = 0;
884 unsigned int i;
885
886 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
887 if (xdev->chan[i]->video_group && !xdev->chan[i]->running)
888 return 0;
889
890 if (xdev->chan[i]->video_group)
891 channels |= BIT(i);
892 }
893
894 return channels;
895 }
896
897 /**
898 * xilinx_dpdma_chan_queue_transfer - Queue the next transfer
899 * @chan: DPDMA channel
900 *
901 * Queue the next descriptor, if any, to the hardware. If the channel is
902 * stopped, start it first. Otherwise retrigger it with the next descriptor.
903 */
xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan * chan)904 static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
905 {
906 struct xilinx_dpdma_device *xdev = chan->xdev;
907 struct xilinx_dpdma_sw_desc *sw_desc;
908 struct xilinx_dpdma_tx_desc *desc;
909 struct virt_dma_desc *vdesc;
910 u32 reg, channels;
911 bool first_frame;
912
913 lockdep_assert_held(&chan->lock);
914
915 if (chan->desc.pending)
916 return;
917
918 if (!chan->running) {
919 xilinx_dpdma_chan_unpause(chan);
920 xilinx_dpdma_chan_enable(chan);
921 chan->first_frame = true;
922 chan->running = true;
923 }
924
925 vdesc = vchan_next_desc(&chan->vchan);
926 if (!vdesc)
927 return;
928
929 desc = to_dpdma_tx_desc(vdesc);
930 chan->desc.pending = desc;
931 list_del(&desc->vdesc.node);
932
933 /*
934 * Assign the cookie to descriptors in this transaction. Only 16 bit
935 * will be used, but it should be enough.
936 */
937 list_for_each_entry(sw_desc, &desc->descriptors, node)
938 sw_desc->hw.desc_id = desc->vdesc.tx.cookie
939 & XILINX_DPDMA_CH_DESC_ID_MASK;
940
941 sw_desc = list_first_entry(&desc->descriptors,
942 struct xilinx_dpdma_sw_desc, node);
943 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR,
944 lower_32_bits(sw_desc->dma_addr));
945 if (xdev->ext_addr)
946 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE,
947 FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK,
948 upper_32_bits(sw_desc->dma_addr)));
949
950 first_frame = chan->first_frame;
951 chan->first_frame = false;
952
953 if (chan->video_group) {
954 channels = xilinx_dpdma_chan_video_group_ready(chan);
955 /*
956 * Trigger the transfer only when all channels in the group are
957 * ready.
958 */
959 if (!channels)
960 return;
961 } else {
962 channels = BIT(chan->id);
963 }
964
965 if (first_frame)
966 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
967 else
968 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
969
970 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
971 }
972
973 /**
974 * xilinx_dpdma_chan_ostand - Number of outstanding transactions
975 * @chan: DPDMA channel
976 *
977 * Read and return the number of outstanding transactions from register.
978 *
979 * Return: Number of outstanding transactions from the status register.
980 */
xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan * chan)981 static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan)
982 {
983 return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK,
984 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS));
985 }
986
987 /**
988 * xilinx_dpdma_chan_notify_no_ostand - Notify no outstanding transaction event
989 * @chan: DPDMA channel
990 *
991 * Notify waiters for no outstanding event, so waiters can stop the channel
992 * safely. This function is supposed to be called when 'no outstanding'
993 * interrupt is generated. The 'no outstanding' interrupt is disabled and
994 * should be re-enabled when this event is handled. If the channel status
995 * register still shows some number of outstanding transactions, the interrupt
996 * remains enabled.
997 *
998 * Return: 0 on success. On failure, -EWOULDBLOCK if there's still outstanding
999 * transaction(s).
1000 */
xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan * chan)1001 static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan)
1002 {
1003 u32 cnt;
1004
1005 cnt = xilinx_dpdma_chan_ostand(chan);
1006 if (cnt) {
1007 dev_dbg(chan->xdev->dev,
1008 "chan%u: %d outstanding transactions\n",
1009 chan->id, cnt);
1010 return -EWOULDBLOCK;
1011 }
1012
1013 /* Disable 'no outstanding' interrupt */
1014 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS,
1015 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
1016 wake_up(&chan->wait_to_stop);
1017
1018 return 0;
1019 }
1020
1021 /**
1022 * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq
1023 * @chan: DPDMA channel
1024 *
1025 * Wait for the no outstanding transaction interrupt. This functions can sleep
1026 * for 50ms.
1027 *
1028 * Return: 0 on success. On failure, -ETIMEOUT for time out, or the error code
1029 * from wait_event_interruptible_timeout().
1030 */
xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan * chan)1031 static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan)
1032 {
1033 int ret;
1034
1035 /* Wait for a no outstanding transaction interrupt upto 50msec */
1036 ret = wait_event_interruptible_timeout(chan->wait_to_stop,
1037 !xilinx_dpdma_chan_ostand(chan),
1038 msecs_to_jiffies(50));
1039 if (ret > 0) {
1040 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
1041 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
1042 return 0;
1043 }
1044
1045 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n",
1046 chan->id, xilinx_dpdma_chan_ostand(chan));
1047
1048 if (ret == 0)
1049 return -ETIMEDOUT;
1050
1051 return ret;
1052 }
1053
1054 /**
1055 * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status
1056 * @chan: DPDMA channel
1057 *
1058 * Poll the outstanding transaction status, and return when there's no
1059 * outstanding transaction. This functions can be used in the interrupt context
1060 * or where the atomicity is required. Calling thread may wait more than 50ms.
1061 *
1062 * Return: 0 on success, or -ETIMEDOUT.
1063 */
xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan * chan)1064 static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan)
1065 {
1066 u32 cnt, loop = 50000;
1067
1068 /* Poll at least for 50ms (20 fps). */
1069 do {
1070 cnt = xilinx_dpdma_chan_ostand(chan);
1071 udelay(1);
1072 } while (loop-- > 0 && cnt);
1073
1074 if (loop) {
1075 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
1076 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
1077 return 0;
1078 }
1079
1080 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n",
1081 chan->id, xilinx_dpdma_chan_ostand(chan));
1082
1083 return -ETIMEDOUT;
1084 }
1085
1086 /**
1087 * xilinx_dpdma_chan_stop - Stop the channel
1088 * @chan: DPDMA channel
1089 *
1090 * Stop a previously paused channel by first waiting for completion of all
1091 * outstanding transaction and then disabling the channel.
1092 *
1093 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
1094 */
xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan * chan)1095 static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan)
1096 {
1097 unsigned long flags;
1098 int ret;
1099
1100 ret = xilinx_dpdma_chan_wait_no_ostand(chan);
1101 if (ret)
1102 return ret;
1103
1104 spin_lock_irqsave(&chan->lock, flags);
1105 xilinx_dpdma_chan_disable(chan);
1106 chan->running = false;
1107 spin_unlock_irqrestore(&chan->lock, flags);
1108
1109 return 0;
1110 }
1111
1112 /**
1113 * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion
1114 * @chan: DPDMA channel
1115 *
1116 * Handle completion of the currently active descriptor (@chan->desc.active). As
1117 * we currently support cyclic transfers only, this just invokes the cyclic
1118 * callback. The descriptor will be completed at the VSYNC interrupt when a new
1119 * descriptor replaces it.
1120 */
xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan * chan)1121 static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan)
1122 {
1123 struct xilinx_dpdma_tx_desc *active;
1124
1125 spin_lock(&chan->lock);
1126
1127 xilinx_dpdma_debugfs_desc_done_irq(chan);
1128
1129 active = chan->desc.active;
1130 if (active)
1131 vchan_cyclic_callback(&active->vdesc);
1132 else
1133 dev_warn(chan->xdev->dev,
1134 "chan%u: DONE IRQ with no active descriptor!\n",
1135 chan->id);
1136
1137 spin_unlock(&chan->lock);
1138 }
1139
1140 /**
1141 * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling
1142 * @chan: DPDMA channel
1143 *
1144 * At VSYNC the active descriptor may have been replaced by the pending
1145 * descriptor. Detect this through the DESC_ID and perform appropriate
1146 * bookkeeping.
1147 */
xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan * chan)1148 static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan)
1149 {
1150 struct xilinx_dpdma_tx_desc *pending;
1151 struct xilinx_dpdma_sw_desc *sw_desc;
1152 u32 desc_id;
1153
1154 spin_lock(&chan->lock);
1155
1156 pending = chan->desc.pending;
1157 if (!chan->running || !pending)
1158 goto out;
1159
1160 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)
1161 & XILINX_DPDMA_CH_DESC_ID_MASK;
1162
1163 /* If the retrigger raced with vsync, retry at the next frame. */
1164 sw_desc = list_first_entry(&pending->descriptors,
1165 struct xilinx_dpdma_sw_desc, node);
1166 if (sw_desc->hw.desc_id != desc_id) {
1167 dev_dbg(chan->xdev->dev,
1168 "chan%u: vsync race lost (%u != %u), retrying\n",
1169 chan->id, sw_desc->hw.desc_id, desc_id);
1170 goto out;
1171 }
1172
1173 /*
1174 * Complete the active descriptor, if any, promote the pending
1175 * descriptor to active, and queue the next transfer, if any.
1176 */
1177 spin_lock(&chan->vchan.lock);
1178 if (chan->desc.active)
1179 vchan_cookie_complete(&chan->desc.active->vdesc);
1180 chan->desc.active = pending;
1181 chan->desc.pending = NULL;
1182
1183 xilinx_dpdma_chan_queue_transfer(chan);
1184 spin_unlock(&chan->vchan.lock);
1185
1186 out:
1187 spin_unlock(&chan->lock);
1188 }
1189
1190 /**
1191 * xilinx_dpdma_chan_err - Detect any channel error
1192 * @chan: DPDMA channel
1193 * @isr: masked Interrupt Status Register
1194 * @eisr: Error Interrupt Status Register
1195 *
1196 * Return: true if any channel error occurs, or false otherwise.
1197 */
1198 static bool
xilinx_dpdma_chan_err(struct xilinx_dpdma_chan * chan,u32 isr,u32 eisr)1199 xilinx_dpdma_chan_err(struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr)
1200 {
1201 if (!chan)
1202 return false;
1203
1204 if (chan->running &&
1205 ((isr & (XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id)) ||
1206 (eisr & (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id))))
1207 return true;
1208
1209 return false;
1210 }
1211
1212 /**
1213 * xilinx_dpdma_chan_handle_err - DPDMA channel error handling
1214 * @chan: DPDMA channel
1215 *
1216 * This function is called when any channel error or any global error occurs.
1217 * The function disables the paused channel by errors and determines
1218 * if the current active descriptor can be rescheduled depending on
1219 * the descriptor status.
1220 */
xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan * chan)1221 static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan)
1222 {
1223 struct xilinx_dpdma_device *xdev = chan->xdev;
1224 struct xilinx_dpdma_tx_desc *active;
1225 unsigned long flags;
1226
1227 spin_lock_irqsave(&chan->lock, flags);
1228
1229 dev_dbg(xdev->dev, "chan%u: cur desc addr = 0x%04x%08x\n",
1230 chan->id,
1231 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
1232 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
1233 dev_dbg(xdev->dev, "chan%u: cur payload addr = 0x%04x%08x\n",
1234 chan->id,
1235 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
1236 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
1237
1238 xilinx_dpdma_chan_disable(chan);
1239 chan->running = false;
1240
1241 if (!chan->desc.active)
1242 goto out_unlock;
1243
1244 active = chan->desc.active;
1245 chan->desc.active = NULL;
1246
1247 xilinx_dpdma_chan_dump_tx_desc(chan, active);
1248
1249 if (active->error)
1250 dev_dbg(xdev->dev, "chan%u: repeated error on desc\n",
1251 chan->id);
1252
1253 /* Reschedule if there's no new descriptor */
1254 if (!chan->desc.pending &&
1255 list_empty(&chan->vchan.desc_issued)) {
1256 active->error = true;
1257 list_add_tail(&active->vdesc.node,
1258 &chan->vchan.desc_issued);
1259 } else {
1260 xilinx_dpdma_chan_free_tx_desc(&active->vdesc);
1261 }
1262
1263 out_unlock:
1264 spin_unlock_irqrestore(&chan->lock, flags);
1265 }
1266
1267 /* -----------------------------------------------------------------------------
1268 * DMA Engine Operations
1269 */
1270 static struct dma_async_tx_descriptor *
xilinx_dpdma_prep_dma_cyclic(struct dma_chan * dchan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)1271 xilinx_dpdma_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr,
1272 size_t buf_len, size_t period_len,
1273 enum dma_transfer_direction direction,
1274 unsigned long flags)
1275 {
1276 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1277
1278 if (direction != DMA_MEM_TO_DEV)
1279 return NULL;
1280
1281 if (buf_len % period_len)
1282 return NULL;
1283
1284 return xilinx_dpdma_chan_prep_cyclic(chan, buf_addr, buf_len,
1285 period_len, flags);
1286 }
1287
1288 static struct dma_async_tx_descriptor *
xilinx_dpdma_prep_interleaved_dma(struct dma_chan * dchan,struct dma_interleaved_template * xt,unsigned long flags)1289 xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan,
1290 struct dma_interleaved_template *xt,
1291 unsigned long flags)
1292 {
1293 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1294 struct xilinx_dpdma_tx_desc *desc;
1295
1296 if (xt->dir != DMA_MEM_TO_DEV)
1297 return NULL;
1298
1299 if (!xt->numf || !xt->sgl[0].size)
1300 return NULL;
1301
1302 if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT))
1303 return NULL;
1304
1305 desc = xilinx_dpdma_chan_prep_interleaved_dma(chan, xt);
1306 if (!desc)
1307 return NULL;
1308
1309 vchan_tx_prep(&chan->vchan, &desc->vdesc, flags | DMA_CTRL_ACK);
1310
1311 return &desc->vdesc.tx;
1312 }
1313
1314 /**
1315 * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel
1316 * @dchan: DMA channel
1317 *
1318 * Allocate a descriptor pool for the channel.
1319 *
1320 * Return: 0 on success, or -ENOMEM if failed to allocate a pool.
1321 */
xilinx_dpdma_alloc_chan_resources(struct dma_chan * dchan)1322 static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan)
1323 {
1324 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1325 size_t align = __alignof__(struct xilinx_dpdma_sw_desc);
1326
1327 chan->desc_pool = dma_pool_create(dev_name(chan->xdev->dev),
1328 chan->xdev->dev,
1329 sizeof(struct xilinx_dpdma_sw_desc),
1330 align, 0);
1331 if (!chan->desc_pool) {
1332 dev_err(chan->xdev->dev,
1333 "chan%u: failed to allocate a descriptor pool\n",
1334 chan->id);
1335 return -ENOMEM;
1336 }
1337
1338 return 0;
1339 }
1340
1341 /**
1342 * xilinx_dpdma_free_chan_resources - Free all resources for the channel
1343 * @dchan: DMA channel
1344 *
1345 * Free resources associated with the virtual DMA channel, and destroy the
1346 * descriptor pool.
1347 */
xilinx_dpdma_free_chan_resources(struct dma_chan * dchan)1348 static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan)
1349 {
1350 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1351
1352 vchan_free_chan_resources(&chan->vchan);
1353
1354 dma_pool_destroy(chan->desc_pool);
1355 chan->desc_pool = NULL;
1356 }
1357
xilinx_dpdma_issue_pending(struct dma_chan * dchan)1358 static void xilinx_dpdma_issue_pending(struct dma_chan *dchan)
1359 {
1360 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1361 unsigned long flags;
1362
1363 spin_lock_irqsave(&chan->lock, flags);
1364 spin_lock(&chan->vchan.lock);
1365 if (vchan_issue_pending(&chan->vchan))
1366 xilinx_dpdma_chan_queue_transfer(chan);
1367 spin_unlock(&chan->vchan.lock);
1368 spin_unlock_irqrestore(&chan->lock, flags);
1369 }
1370
xilinx_dpdma_config(struct dma_chan * dchan,struct dma_slave_config * config)1371 static int xilinx_dpdma_config(struct dma_chan *dchan,
1372 struct dma_slave_config *config)
1373 {
1374 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1375 struct xilinx_dpdma_peripheral_config *pconfig;
1376 unsigned long flags;
1377
1378 /*
1379 * The destination address doesn't need to be specified as the DPDMA is
1380 * hardwired to the destination (the DP controller). The transfer
1381 * width, burst size and port window size are thus meaningless, they're
1382 * fixed both on the DPDMA side and on the DP controller side.
1383 */
1384
1385 /*
1386 * Use the peripheral_config to indicate that the channel is part
1387 * of a video group. This requires matching use of the custom
1388 * structure in each driver.
1389 */
1390 pconfig = config->peripheral_config;
1391 if (WARN_ON(pconfig && config->peripheral_size != sizeof(*pconfig)))
1392 return -EINVAL;
1393
1394 spin_lock_irqsave(&chan->lock, flags);
1395 if (chan->id <= ZYNQMP_DPDMA_VIDEO2 && pconfig)
1396 chan->video_group = pconfig->video_group;
1397 spin_unlock_irqrestore(&chan->lock, flags);
1398
1399 return 0;
1400 }
1401
xilinx_dpdma_pause(struct dma_chan * dchan)1402 static int xilinx_dpdma_pause(struct dma_chan *dchan)
1403 {
1404 xilinx_dpdma_chan_pause(to_xilinx_chan(dchan));
1405
1406 return 0;
1407 }
1408
xilinx_dpdma_resume(struct dma_chan * dchan)1409 static int xilinx_dpdma_resume(struct dma_chan *dchan)
1410 {
1411 xilinx_dpdma_chan_unpause(to_xilinx_chan(dchan));
1412
1413 return 0;
1414 }
1415
1416 /**
1417 * xilinx_dpdma_terminate_all - Terminate the channel and descriptors
1418 * @dchan: DMA channel
1419 *
1420 * Pause the channel without waiting for ongoing transfers to complete. Waiting
1421 * for completion is performed by xilinx_dpdma_synchronize() that will disable
1422 * the channel to complete the stop.
1423 *
1424 * All the descriptors associated with the channel that are guaranteed not to
1425 * be touched by the hardware. The pending and active descriptor are not
1426 * touched, and will be freed either upon completion, or by
1427 * xilinx_dpdma_synchronize().
1428 *
1429 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
1430 */
xilinx_dpdma_terminate_all(struct dma_chan * dchan)1431 static int xilinx_dpdma_terminate_all(struct dma_chan *dchan)
1432 {
1433 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1434 struct xilinx_dpdma_device *xdev = chan->xdev;
1435 LIST_HEAD(descriptors);
1436 unsigned long flags;
1437 unsigned int i;
1438
1439 /* Pause the channel (including the whole video group if applicable). */
1440 if (chan->video_group) {
1441 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
1442 if (xdev->chan[i]->video_group &&
1443 xdev->chan[i]->running) {
1444 xilinx_dpdma_chan_pause(xdev->chan[i]);
1445 xdev->chan[i]->video_group = false;
1446 }
1447 }
1448 } else {
1449 xilinx_dpdma_chan_pause(chan);
1450 }
1451
1452 /* Gather all the descriptors we can free and free them. */
1453 spin_lock_irqsave(&chan->vchan.lock, flags);
1454 vchan_get_all_descriptors(&chan->vchan, &descriptors);
1455 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1456
1457 vchan_dma_desc_free_list(&chan->vchan, &descriptors);
1458
1459 return 0;
1460 }
1461
1462 /**
1463 * xilinx_dpdma_synchronize - Synchronize callback execution
1464 * @dchan: DMA channel
1465 *
1466 * Synchronizing callback execution ensures that all previously issued
1467 * transfers have completed and all associated callbacks have been called and
1468 * have returned.
1469 *
1470 * This function waits for the DMA channel to stop. It assumes it has been
1471 * paused by a previous call to dmaengine_terminate_async(), and that no new
1472 * pending descriptors have been issued with dma_async_issue_pending(). The
1473 * behaviour is undefined otherwise.
1474 */
xilinx_dpdma_synchronize(struct dma_chan * dchan)1475 static void xilinx_dpdma_synchronize(struct dma_chan *dchan)
1476 {
1477 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1478 unsigned long flags;
1479
1480 xilinx_dpdma_chan_stop(chan);
1481
1482 spin_lock_irqsave(&chan->vchan.lock, flags);
1483 if (chan->desc.pending) {
1484 vchan_terminate_vdesc(&chan->desc.pending->vdesc);
1485 chan->desc.pending = NULL;
1486 }
1487 if (chan->desc.active) {
1488 vchan_terminate_vdesc(&chan->desc.active->vdesc);
1489 chan->desc.active = NULL;
1490 }
1491 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1492
1493 vchan_synchronize(&chan->vchan);
1494 }
1495
1496 /* -----------------------------------------------------------------------------
1497 * Interrupt and Tasklet Handling
1498 */
1499
1500 /**
1501 * xilinx_dpdma_err - Detect any global error
1502 * @isr: Interrupt Status Register
1503 * @eisr: Error Interrupt Status Register
1504 *
1505 * Return: True if any global error occurs, or false otherwise.
1506 */
xilinx_dpdma_err(u32 isr,u32 eisr)1507 static bool xilinx_dpdma_err(u32 isr, u32 eisr)
1508 {
1509 if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR ||
1510 eisr & XILINX_DPDMA_EINTR_GLOBAL_ERR)
1511 return true;
1512
1513 return false;
1514 }
1515
1516 /**
1517 * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt
1518 * @xdev: DPDMA device
1519 * @isr: masked Interrupt Status Register
1520 * @eisr: Error Interrupt Status Register
1521 *
1522 * Handle if any error occurs based on @isr and @eisr. This function disables
1523 * corresponding error interrupts, and those should be re-enabled once handling
1524 * is done.
1525 */
xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device * xdev,u32 isr,u32 eisr)1526 static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev,
1527 u32 isr, u32 eisr)
1528 {
1529 bool err = xilinx_dpdma_err(isr, eisr);
1530 unsigned int i;
1531
1532 dev_dbg_ratelimited(xdev->dev,
1533 "error irq: isr = 0x%08x, eisr = 0x%08x\n",
1534 isr, eisr);
1535
1536 /* Disable channel error interrupts until errors are handled. */
1537 dpdma_write(xdev->reg, XILINX_DPDMA_IDS,
1538 isr & ~XILINX_DPDMA_INTR_GLOBAL_ERR);
1539 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS,
1540 eisr & ~XILINX_DPDMA_EINTR_GLOBAL_ERR);
1541
1542 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1543 if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr))
1544 tasklet_schedule(&xdev->chan[i]->err_task);
1545 }
1546
1547 /**
1548 * xilinx_dpdma_enable_irq - Enable interrupts
1549 * @xdev: DPDMA device
1550 *
1551 * Enable interrupts.
1552 */
xilinx_dpdma_enable_irq(struct xilinx_dpdma_device * xdev)1553 static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev)
1554 {
1555 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL);
1556 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL);
1557 }
1558
1559 /**
1560 * xilinx_dpdma_disable_irq - Disable interrupts
1561 * @xdev: DPDMA device
1562 *
1563 * Disable interrupts.
1564 */
xilinx_dpdma_disable_irq(struct xilinx_dpdma_device * xdev)1565 static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev)
1566 {
1567 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL);
1568 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL);
1569 }
1570
1571 /**
1572 * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling
1573 * @t: pointer to the tasklet associated with this handler
1574 *
1575 * Per channel error handling tasklet. This function waits for the outstanding
1576 * transaction to complete and triggers error handling. After error handling,
1577 * re-enable channel error interrupts, and restart the channel if needed.
1578 */
xilinx_dpdma_chan_err_task(struct tasklet_struct * t)1579 static void xilinx_dpdma_chan_err_task(struct tasklet_struct *t)
1580 {
1581 struct xilinx_dpdma_chan *chan = from_tasklet(chan, t, err_task);
1582 struct xilinx_dpdma_device *xdev = chan->xdev;
1583 unsigned long flags;
1584
1585 /* Proceed error handling even when polling fails. */
1586 xilinx_dpdma_chan_poll_no_ostand(chan);
1587
1588 xilinx_dpdma_chan_handle_err(chan);
1589
1590 dpdma_write(xdev->reg, XILINX_DPDMA_IEN,
1591 XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id);
1592 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN,
1593 XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id);
1594
1595 spin_lock_irqsave(&chan->lock, flags);
1596 spin_lock(&chan->vchan.lock);
1597 xilinx_dpdma_chan_queue_transfer(chan);
1598 spin_unlock(&chan->vchan.lock);
1599 spin_unlock_irqrestore(&chan->lock, flags);
1600 }
1601
xilinx_dpdma_irq_handler(int irq,void * data)1602 static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data)
1603 {
1604 struct xilinx_dpdma_device *xdev = data;
1605 unsigned long mask;
1606 unsigned int i;
1607 u32 status;
1608 u32 error;
1609
1610 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR);
1611 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR);
1612 if (!status && !error)
1613 return IRQ_NONE;
1614
1615 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status);
1616 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error);
1617
1618 if (status & XILINX_DPDMA_INTR_VSYNC) {
1619 /*
1620 * There's a single VSYNC interrupt that needs to be processed
1621 * by each running channel to update the active descriptor.
1622 */
1623 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
1624 struct xilinx_dpdma_chan *chan = xdev->chan[i];
1625
1626 if (chan)
1627 xilinx_dpdma_chan_vsync_irq(chan);
1628 }
1629 }
1630
1631 mask = FIELD_GET(XILINX_DPDMA_INTR_DESC_DONE_MASK, status);
1632 if (mask) {
1633 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
1634 xilinx_dpdma_chan_done_irq(xdev->chan[i]);
1635 }
1636
1637 mask = FIELD_GET(XILINX_DPDMA_INTR_NO_OSTAND_MASK, status);
1638 if (mask) {
1639 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
1640 xilinx_dpdma_chan_notify_no_ostand(xdev->chan[i]);
1641 }
1642
1643 mask = status & XILINX_DPDMA_INTR_ERR_ALL;
1644 if (mask || error)
1645 xilinx_dpdma_handle_err_irq(xdev, mask, error);
1646
1647 return IRQ_HANDLED;
1648 }
1649
1650 /* -----------------------------------------------------------------------------
1651 * Initialization & Cleanup
1652 */
1653
xilinx_dpdma_chan_init(struct xilinx_dpdma_device * xdev,unsigned int chan_id)1654 static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev,
1655 unsigned int chan_id)
1656 {
1657 struct xilinx_dpdma_chan *chan;
1658
1659 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
1660 if (!chan)
1661 return -ENOMEM;
1662
1663 chan->id = chan_id;
1664 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE
1665 + XILINX_DPDMA_CH_OFFSET * chan->id;
1666 chan->running = false;
1667 chan->xdev = xdev;
1668
1669 spin_lock_init(&chan->lock);
1670 init_waitqueue_head(&chan->wait_to_stop);
1671
1672 tasklet_setup(&chan->err_task, xilinx_dpdma_chan_err_task);
1673
1674 chan->vchan.desc_free = xilinx_dpdma_chan_free_tx_desc;
1675 vchan_init(&chan->vchan, &xdev->common);
1676
1677 xdev->chan[chan->id] = chan;
1678
1679 return 0;
1680 }
1681
xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan * chan)1682 static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan)
1683 {
1684 if (!chan)
1685 return;
1686
1687 tasklet_kill(&chan->err_task);
1688 list_del(&chan->vchan.chan.device_node);
1689 }
1690
of_dma_xilinx_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1691 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
1692 struct of_dma *ofdma)
1693 {
1694 struct xilinx_dpdma_device *xdev = ofdma->of_dma_data;
1695 u32 chan_id = dma_spec->args[0];
1696
1697 if (chan_id >= ARRAY_SIZE(xdev->chan))
1698 return NULL;
1699
1700 if (!xdev->chan[chan_id])
1701 return NULL;
1702
1703 return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan);
1704 }
1705
dpdma_hw_init(struct xilinx_dpdma_device * xdev)1706 static void dpdma_hw_init(struct xilinx_dpdma_device *xdev)
1707 {
1708 unsigned int i;
1709 void __iomem *reg;
1710
1711 /* Disable all interrupts */
1712 xilinx_dpdma_disable_irq(xdev);
1713
1714 /* Stop all channels */
1715 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
1716 reg = xdev->reg + XILINX_DPDMA_CH_BASE
1717 + XILINX_DPDMA_CH_OFFSET * i;
1718 dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
1719 }
1720
1721 /* Clear the interrupt status registers */
1722 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL);
1723 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL);
1724 }
1725
xilinx_dpdma_probe(struct platform_device * pdev)1726 static int xilinx_dpdma_probe(struct platform_device *pdev)
1727 {
1728 struct xilinx_dpdma_device *xdev;
1729 struct dma_device *ddev;
1730 unsigned int i;
1731 int ret;
1732
1733 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
1734 if (!xdev)
1735 return -ENOMEM;
1736
1737 xdev->dev = &pdev->dev;
1738 xdev->ext_addr = sizeof(dma_addr_t) > 4;
1739
1740 INIT_LIST_HEAD(&xdev->common.channels);
1741
1742 platform_set_drvdata(pdev, xdev);
1743
1744 xdev->axi_clk = devm_clk_get(xdev->dev, "axi_clk");
1745 if (IS_ERR(xdev->axi_clk))
1746 return PTR_ERR(xdev->axi_clk);
1747
1748 xdev->reg = devm_platform_ioremap_resource(pdev, 0);
1749 if (IS_ERR(xdev->reg))
1750 return PTR_ERR(xdev->reg);
1751
1752 dpdma_hw_init(xdev);
1753
1754 xdev->irq = platform_get_irq(pdev, 0);
1755 if (xdev->irq < 0)
1756 return xdev->irq;
1757
1758 ret = request_irq(xdev->irq, xilinx_dpdma_irq_handler, IRQF_SHARED,
1759 dev_name(xdev->dev), xdev);
1760 if (ret) {
1761 dev_err(xdev->dev, "failed to request IRQ\n");
1762 return ret;
1763 }
1764
1765 ddev = &xdev->common;
1766 ddev->dev = &pdev->dev;
1767
1768 dma_cap_set(DMA_SLAVE, ddev->cap_mask);
1769 dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
1770 dma_cap_set(DMA_CYCLIC, ddev->cap_mask);
1771 dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask);
1772 dma_cap_set(DMA_REPEAT, ddev->cap_mask);
1773 dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask);
1774 ddev->copy_align = fls(XILINX_DPDMA_ALIGN_BYTES - 1);
1775
1776 ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources;
1777 ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources;
1778 ddev->device_prep_dma_cyclic = xilinx_dpdma_prep_dma_cyclic;
1779 ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma;
1780 /* TODO: Can we achieve better granularity ? */
1781 ddev->device_tx_status = dma_cookie_status;
1782 ddev->device_issue_pending = xilinx_dpdma_issue_pending;
1783 ddev->device_config = xilinx_dpdma_config;
1784 ddev->device_pause = xilinx_dpdma_pause;
1785 ddev->device_resume = xilinx_dpdma_resume;
1786 ddev->device_terminate_all = xilinx_dpdma_terminate_all;
1787 ddev->device_synchronize = xilinx_dpdma_synchronize;
1788 ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED);
1789 ddev->directions = BIT(DMA_MEM_TO_DEV);
1790 ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1791
1792 for (i = 0; i < ARRAY_SIZE(xdev->chan); ++i) {
1793 ret = xilinx_dpdma_chan_init(xdev, i);
1794 if (ret < 0) {
1795 dev_err(xdev->dev, "failed to initialize channel %u\n",
1796 i);
1797 goto error;
1798 }
1799 }
1800
1801 ret = clk_prepare_enable(xdev->axi_clk);
1802 if (ret) {
1803 dev_err(xdev->dev, "failed to enable the axi clock\n");
1804 goto error;
1805 }
1806
1807 ret = dma_async_device_register(ddev);
1808 if (ret) {
1809 dev_err(xdev->dev, "failed to register the dma device\n");
1810 goto error_dma_async;
1811 }
1812
1813 ret = of_dma_controller_register(xdev->dev->of_node,
1814 of_dma_xilinx_xlate, ddev);
1815 if (ret) {
1816 dev_err(xdev->dev, "failed to register DMA to DT DMA helper\n");
1817 goto error_of_dma;
1818 }
1819
1820 xilinx_dpdma_enable_irq(xdev);
1821
1822 xilinx_dpdma_debugfs_init(xdev);
1823
1824 dev_info(&pdev->dev, "Xilinx DPDMA engine is probed\n");
1825
1826 return 0;
1827
1828 error_of_dma:
1829 dma_async_device_unregister(ddev);
1830 error_dma_async:
1831 clk_disable_unprepare(xdev->axi_clk);
1832 error:
1833 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1834 xilinx_dpdma_chan_remove(xdev->chan[i]);
1835
1836 free_irq(xdev->irq, xdev);
1837
1838 return ret;
1839 }
1840
xilinx_dpdma_remove(struct platform_device * pdev)1841 static void xilinx_dpdma_remove(struct platform_device *pdev)
1842 {
1843 struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev);
1844 unsigned int i;
1845
1846 /* Start by disabling the IRQ to avoid races during cleanup. */
1847 free_irq(xdev->irq, xdev);
1848
1849 xilinx_dpdma_disable_irq(xdev);
1850 of_dma_controller_free(pdev->dev.of_node);
1851 dma_async_device_unregister(&xdev->common);
1852 clk_disable_unprepare(xdev->axi_clk);
1853
1854 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1855 xilinx_dpdma_chan_remove(xdev->chan[i]);
1856 }
1857
1858 static const struct of_device_id xilinx_dpdma_of_match[] = {
1859 { .compatible = "xlnx,zynqmp-dpdma",},
1860 { /* end of table */ },
1861 };
1862 MODULE_DEVICE_TABLE(of, xilinx_dpdma_of_match);
1863
1864 static struct platform_driver xilinx_dpdma_driver = {
1865 .probe = xilinx_dpdma_probe,
1866 .remove_new = xilinx_dpdma_remove,
1867 .driver = {
1868 .name = "xilinx-zynqmp-dpdma",
1869 .of_match_table = xilinx_dpdma_of_match,
1870 },
1871 };
1872
1873 module_platform_driver(xilinx_dpdma_driver);
1874
1875 MODULE_AUTHOR("Xilinx, Inc.");
1876 MODULE_DESCRIPTION("Xilinx ZynqMP DPDMA driver");
1877 MODULE_LICENSE("GPL v2");
1878