1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 Broadcom
4 * Author: Jayachandran C <jchandra@broadcom.com>
5 * Copyright (C) 2016 Semihalf
6 * Author: Tomasz Nowicki <tn@semihalf.com>
7 */
8
9 #define pr_fmt(fmt) "ACPI: " fmt
10
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/pci-acpi.h>
14 #include <linux/pci-ecam.h>
15
16 /* Structure to hold entries from the MCFG table */
17 struct mcfg_entry {
18 struct list_head list;
19 phys_addr_t addr;
20 u16 segment;
21 u8 bus_start;
22 u8 bus_end;
23 };
24
25 #ifdef CONFIG_PCI_QUIRKS
26 struct mcfg_fixup {
27 char oem_id[ACPI_OEM_ID_SIZE + 1];
28 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
29 u32 oem_revision;
30 u16 segment;
31 struct resource bus_range;
32 const struct pci_ecam_ops *ops;
33 struct resource cfgres;
34 };
35
36 #define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
37 ((end) - (start) + 1), \
38 NULL, IORESOURCE_BUS)
39 #define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
40
41 static struct mcfg_fixup mcfg_quirks[] = {
42 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
43
44 #ifdef CONFIG_ARM64
45
46 #define AL_ECAM(table_id, rev, seg, ops) \
47 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
48
49 AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
50 AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
51 AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
52 AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
53 AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
54 AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
55 AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
56 AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
57
58 #define QCOM_ECAM32(seg) \
59 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
60
61 QCOM_ECAM32(0),
62 QCOM_ECAM32(1),
63 QCOM_ECAM32(2),
64 QCOM_ECAM32(3),
65 QCOM_ECAM32(4),
66 QCOM_ECAM32(5),
67 QCOM_ECAM32(6),
68 QCOM_ECAM32(7),
69
70 #define HISI_QUAD_DOM(table_id, seg, ops) \
71 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
72 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
73 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
74 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
75
76 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
77 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
78 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
79 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
80 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
81 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
82
83 #define THUNDER_PEM_RES(addr, node) \
84 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
85
86 #define THUNDER_PEM_QUIRK(rev, node) \
87 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
88 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
89 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
90 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
91 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
92 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
93 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
94 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
95 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
96 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
97 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
98 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
99
100 #define THUNDER_ECAM_QUIRK(rev, seg) \
101 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
102 &pci_thunder_ecam_ops }
103
104 /* SoC pass2.x */
105 THUNDER_PEM_QUIRK(1, 0),
106 THUNDER_PEM_QUIRK(1, 1),
107 THUNDER_ECAM_QUIRK(1, 10),
108
109 /* SoC pass1.x */
110 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
111 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
112 THUNDER_ECAM_QUIRK(2, 0),
113 THUNDER_ECAM_QUIRK(2, 1),
114 THUNDER_ECAM_QUIRK(2, 2),
115 THUNDER_ECAM_QUIRK(2, 3),
116 THUNDER_ECAM_QUIRK(2, 10),
117 THUNDER_ECAM_QUIRK(2, 11),
118 THUNDER_ECAM_QUIRK(2, 12),
119 THUNDER_ECAM_QUIRK(2, 13),
120
121 { "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops},
122 { "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops},
123 { "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops},
124 { "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops},
125 { "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops},
126 { "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops},
127
128 #define XGENE_V1_ECAM_MCFG(rev, seg) \
129 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
130 &xgene_v1_pcie_ecam_ops }
131
132 #define XGENE_V2_ECAM_MCFG(rev, seg) \
133 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
134 &xgene_v2_pcie_ecam_ops }
135
136 /* X-Gene SoC with v1 PCIe controller */
137 XGENE_V1_ECAM_MCFG(1, 0),
138 XGENE_V1_ECAM_MCFG(1, 1),
139 XGENE_V1_ECAM_MCFG(1, 2),
140 XGENE_V1_ECAM_MCFG(1, 3),
141 XGENE_V1_ECAM_MCFG(1, 4),
142 XGENE_V1_ECAM_MCFG(2, 0),
143 XGENE_V1_ECAM_MCFG(2, 1),
144 XGENE_V1_ECAM_MCFG(2, 2),
145 XGENE_V1_ECAM_MCFG(2, 3),
146 XGENE_V1_ECAM_MCFG(2, 4),
147 /* X-Gene SoC with v2.1 PCIe controller */
148 XGENE_V2_ECAM_MCFG(3, 0),
149 XGENE_V2_ECAM_MCFG(3, 1),
150 /* X-Gene SoC with v2.2 PCIe controller */
151 XGENE_V2_ECAM_MCFG(4, 0),
152 XGENE_V2_ECAM_MCFG(4, 1),
153 XGENE_V2_ECAM_MCFG(4, 2),
154
155 #define ALTRA_ECAM_QUIRK(rev, seg) \
156 { "Ampere", "Altra ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
157
158 ALTRA_ECAM_QUIRK(1, 0),
159 ALTRA_ECAM_QUIRK(1, 1),
160 ALTRA_ECAM_QUIRK(1, 2),
161 ALTRA_ECAM_QUIRK(1, 3),
162 ALTRA_ECAM_QUIRK(1, 4),
163 ALTRA_ECAM_QUIRK(1, 5),
164 ALTRA_ECAM_QUIRK(1, 6),
165 ALTRA_ECAM_QUIRK(1, 7),
166 ALTRA_ECAM_QUIRK(1, 8),
167 ALTRA_ECAM_QUIRK(1, 9),
168 ALTRA_ECAM_QUIRK(1, 10),
169 ALTRA_ECAM_QUIRK(1, 11),
170 ALTRA_ECAM_QUIRK(1, 12),
171 ALTRA_ECAM_QUIRK(1, 13),
172 ALTRA_ECAM_QUIRK(1, 14),
173 ALTRA_ECAM_QUIRK(1, 15),
174 #endif /* ARM64 */
175
176 #ifdef CONFIG_LOONGARCH
177 #define LOONGSON_ECAM_MCFG(table_id, seg) \
178 { "LOONGS", table_id, 1, seg, MCFG_BUS_ANY, &loongson_pci_ecam_ops }
179
180 LOONGSON_ECAM_MCFG("\0", 0),
181 LOONGSON_ECAM_MCFG("LOONGSON", 0),
182 LOONGSON_ECAM_MCFG("\0", 1),
183 LOONGSON_ECAM_MCFG("LOONGSON", 1),
184 LOONGSON_ECAM_MCFG("\0", 2),
185 LOONGSON_ECAM_MCFG("LOONGSON", 2),
186 LOONGSON_ECAM_MCFG("\0", 3),
187 LOONGSON_ECAM_MCFG("LOONGSON", 3),
188 LOONGSON_ECAM_MCFG("\0", 4),
189 LOONGSON_ECAM_MCFG("LOONGSON", 4),
190 LOONGSON_ECAM_MCFG("\0", 5),
191 LOONGSON_ECAM_MCFG("LOONGSON", 5),
192 LOONGSON_ECAM_MCFG("\0", 6),
193 LOONGSON_ECAM_MCFG("LOONGSON", 6),
194 LOONGSON_ECAM_MCFG("\0", 7),
195 LOONGSON_ECAM_MCFG("LOONGSON", 7),
196 #endif /* LOONGARCH */
197 };
198
199 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
200 static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
201 static u32 mcfg_oem_revision;
202
pci_mcfg_quirk_matches(struct mcfg_fixup * f,u16 segment,struct resource * bus_range)203 static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
204 struct resource *bus_range)
205 {
206 if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
207 !memcmp(f->oem_table_id, mcfg_oem_table_id,
208 ACPI_OEM_TABLE_ID_SIZE) &&
209 f->oem_revision == mcfg_oem_revision &&
210 f->segment == segment &&
211 resource_contains(&f->bus_range, bus_range))
212 return 1;
213
214 return 0;
215 }
216 #endif
217
pci_mcfg_apply_quirks(struct acpi_pci_root * root,struct resource * cfgres,const struct pci_ecam_ops ** ecam_ops)218 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
219 struct resource *cfgres,
220 const struct pci_ecam_ops **ecam_ops)
221 {
222 #ifdef CONFIG_PCI_QUIRKS
223 u16 segment = root->segment;
224 struct resource *bus_range = &root->secondary;
225 struct mcfg_fixup *f;
226 int i;
227
228 for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
229 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
230 if (f->cfgres.start)
231 *cfgres = f->cfgres;
232 if (f->ops)
233 *ecam_ops = f->ops;
234 dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
235 cfgres, bus_range, *ecam_ops);
236 return;
237 }
238 }
239 #endif
240 }
241
242 /* List to save MCFG entries */
243 static LIST_HEAD(pci_mcfg_list);
244
pci_mcfg_lookup(struct acpi_pci_root * root,struct resource * cfgres,const struct pci_ecam_ops ** ecam_ops)245 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
246 const struct pci_ecam_ops **ecam_ops)
247 {
248 const struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
249 struct resource *bus_res = &root->secondary;
250 u16 seg = root->segment;
251 struct mcfg_entry *e;
252 struct resource res;
253
254 /* Use address from _CBA if present, otherwise lookup MCFG */
255 if (root->mcfg_addr)
256 goto skip_lookup;
257
258 /*
259 * We expect the range in bus_res in the coverage of MCFG bus range.
260 */
261 list_for_each_entry(e, &pci_mcfg_list, list) {
262 if (e->segment == seg && e->bus_start <= bus_res->start &&
263 e->bus_end >= bus_res->end) {
264 root->mcfg_addr = e->addr;
265 }
266
267 }
268
269 skip_lookup:
270 memset(&res, 0, sizeof(res));
271 if (root->mcfg_addr) {
272 res.start = root->mcfg_addr + (bus_res->start << 20);
273 res.end = res.start + (resource_size(bus_res) << 20) - 1;
274 res.flags = IORESOURCE_MEM;
275 }
276
277 /*
278 * Allow quirks to override default ECAM ops and CFG resource
279 * range. This may even fabricate a CFG resource range in case
280 * MCFG does not have it. Invalid CFG start address means MCFG
281 * firmware bug or we need another quirk in array.
282 */
283 pci_mcfg_apply_quirks(root, &res, &ops);
284 if (!res.start)
285 return -ENXIO;
286
287 *cfgres = res;
288 *ecam_ops = ops;
289 return 0;
290 }
291
pci_mcfg_parse(struct acpi_table_header * header)292 static __init int pci_mcfg_parse(struct acpi_table_header *header)
293 {
294 struct acpi_table_mcfg *mcfg;
295 struct acpi_mcfg_allocation *mptr;
296 struct mcfg_entry *e, *arr;
297 int i, n;
298
299 if (header->length < sizeof(struct acpi_table_mcfg))
300 return -EINVAL;
301
302 n = (header->length - sizeof(struct acpi_table_mcfg)) /
303 sizeof(struct acpi_mcfg_allocation);
304 mcfg = (struct acpi_table_mcfg *)header;
305 mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
306
307 arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
308 if (!arr)
309 return -ENOMEM;
310
311 for (i = 0, e = arr; i < n; i++, mptr++, e++) {
312 e->segment = mptr->pci_segment;
313 e->addr = mptr->address;
314 e->bus_start = mptr->start_bus_number;
315 e->bus_end = mptr->end_bus_number;
316 list_add(&e->list, &pci_mcfg_list);
317 }
318
319 #ifdef CONFIG_PCI_QUIRKS
320 /* Save MCFG IDs and revision for quirks matching */
321 memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
322 memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
323 mcfg_oem_revision = header->oem_revision;
324 #endif
325
326 pr_info("MCFG table detected, %d entries\n", n);
327 return 0;
328 }
329
330 /* Interface called by ACPI - parse and save MCFG table */
pci_mmcfg_late_init(void)331 void __init pci_mmcfg_late_init(void)
332 {
333 int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
334 if (err)
335 pr_debug("Failed to parse MCFG (%d)\n", err);
336 }
337