1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #ifndef __XGBE_H__
9 #define __XGBE_H__
10
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/workqueue.h>
14 #include <linux/phy.h>
15 #include <linux/if_vlan.h>
16 #include <linux/bitops.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/timecounter.h>
19 #include <linux/net_tstamp.h>
20 #include <net/dcbnl.h>
21 #include <linux/completion.h>
22 #include <linux/cpumask.h>
23 #include <linux/interrupt.h>
24 #include <linux/dcache.h>
25 #include <linux/ethtool.h>
26 #include <linux/list.h>
27
28 #define XGBE_DRV_NAME "amd-xgbe"
29 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
30
31 /* Descriptor related defines */
32 #define XGBE_TX_DESC_CNT 512
33 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
34 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
35 #define XGBE_RX_DESC_CNT 512
36
37 #define XGBE_TX_DESC_CNT_MIN 64
38 #define XGBE_TX_DESC_CNT_MAX 4096
39 #define XGBE_RX_DESC_CNT_MIN 64
40 #define XGBE_RX_DESC_CNT_MAX 4096
41
42 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
43
44 /* Descriptors required for maximum contiguous TSO/GSO packet */
45 #define XGBE_TX_MAX_SPLIT \
46 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
47
48 /* Maximum possible descriptors needed for an SKB:
49 * - Maximum number of SKB frags
50 * - Maximum descriptors for contiguous TSO/GSO packet
51 * - Possible context descriptor
52 * - Possible TSO header descriptor
53 */
54 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
55
56 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
57 #define XGBE_RX_BUF_ALIGN 64
58 #define XGBE_SKB_ALLOC_SIZE 256
59 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
60
61 #define XGBE_MAX_DMA_CHANNELS 16
62 #define XGBE_MAX_QUEUES 16
63 #define XGBE_PRIORITY_QUEUES 8
64 #define XGBE_DMA_STOP_TIMEOUT 1
65
66 /* DMA cache settings - Outer sharable, write-back, write-allocate */
67 #define XGBE_DMA_OS_ARCR 0x002b2b2b
68 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f
69
70 /* DMA cache settings - System, no caches used */
71 #define XGBE_DMA_SYS_ARCR 0x00303030
72 #define XGBE_DMA_SYS_AWCR 0x30303030
73
74 /* DMA cache settings - PCI device */
75 #define XGBE_DMA_PCI_ARCR 0x000f0f0f
76 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f
77 #define XGBE_DMA_PCI_AWARCR 0x00000f0f
78
79 /* DMA channel interrupt modes */
80 #define XGBE_IRQ_MODE_EDGE 0
81 #define XGBE_IRQ_MODE_LEVEL 1
82
83 #define XGBE_ETH_FRAME_HDR (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
84 #define XGMAC_MIN_PACKET 60
85 #define XGMAC_STD_PACKET_MTU 1500
86 #define XGMAC_MAX_STD_PACKET 1518
87 #define XGMAC_JUMBO_PACKET_MTU 9000
88 #define XGMAC_MAX_JUMBO_PACKET 9018
89 #define XGMAC_GIANT_PACKET_MTU 16368
90 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
91
92 #define XGMAC_PFC_DATA_LEN 46
93 #define XGMAC_PFC_DELAYS 14000
94
95 #define XGMAC_PRIO_QUEUES(_cnt) \
96 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
97
98 /* Common property names */
99 #define XGBE_MAC_ADDR_PROPERTY "mac-address"
100 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
101 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
102 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
103
104 /* Device-tree clock names */
105 #define XGBE_DMA_CLOCK "dma_clk"
106 #define XGBE_PTP_CLOCK "ptp_clk"
107
108 /* ACPI property names */
109 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
110 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
111
112 /* PCI BAR mapping */
113 #define XGBE_XGMAC_BAR 0
114 #define XGBE_XPCS_BAR 1
115 #define XGBE_MAC_PROP_OFFSET 0x1d000
116 #define XGBE_I2C_CTRL_OFFSET 0x1e000
117
118 /* PCI MSI/MSIx support */
119 #define XGBE_MSI_BASE_COUNT 4
120 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1)
121
122 /* Initial PTP register values based on Link Speed. */
123 #define MAC_TICNR_1G_INITVAL 0x10
124 #define MAC_TECNR_1G_INITVAL 0x28
125
126 #define MAC_TICSNR_10G_INITVAL 0x33
127 #define MAC_TECNR_10G_INITVAL 0x14
128 #define MAC_TECSNR_10G_INITVAL 0xCC
129
130 /* PCI clock frequencies */
131 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
132 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
133
134 /* Timestamp support - values based on 50MHz PTP clock
135 * 50MHz => 20 nsec
136 */
137 #define XGBE_TSTAMP_SSINC 20
138 #define XGBE_TSTAMP_SNSINC 0
139 #define XGBE_PTP_ACT_CLK_FREQ 500000000
140
141 #define XGBE_V2_TSTAMP_SSINC 0xA
142 #define XGBE_V2_TSTAMP_SNSINC 0
143 #define XGBE_V2_PTP_ACT_CLK_FREQ 1000000000
144
145 /* Driver PMT macros */
146 #define XGMAC_DRIVER_CONTEXT 1
147 #define XGMAC_IOCTL_CONTEXT 2
148
149 #define XGMAC_FIFO_MIN_ALLOC 2048
150 #define XGMAC_FIFO_UNIT 256
151 #define XGMAC_FIFO_ALIGN(_x) \
152 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
153 #define XGMAC_FIFO_FC_OFF 2048
154 #define XGMAC_FIFO_FC_MIN 4096
155
156 #define XGBE_TC_MIN_QUANTUM 10
157
158 /* Helper macro for descriptor handling
159 * Always use XGBE_GET_DESC_DATA to access the descriptor data
160 * since the index is free-running and needs to be and-ed
161 * with the descriptor count value of the ring to index to
162 * the proper descriptor data.
163 */
164 #define XGBE_GET_DESC_DATA(_ring, _idx) \
165 ((_ring)->rdata + \
166 ((_idx) & ((_ring)->rdesc_count - 1)))
167
168 /* Default coalescing parameters */
169 #define XGMAC_INIT_DMA_TX_USECS 1000
170 #define XGMAC_INIT_DMA_TX_FRAMES 25
171
172 #define XGMAC_MAX_DMA_RIWT 0xff
173 #define XGMAC_INIT_DMA_RX_USECS 30
174 #define XGMAC_INIT_DMA_RX_FRAMES 25
175
176 /* Flow control queue count */
177 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
178
179 /* Flow control threshold units */
180 #define XGMAC_FLOW_CONTROL_UNIT 512
181 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \
182 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
183 #define XGMAC_FLOW_CONTROL_VALUE(_x) \
184 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
185 #define XGMAC_FLOW_CONTROL_MAX 33280
186
187 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
188 #define XGBE_MAC_HASH_TABLE_SIZE 8
189
190 /* Receive Side Scaling */
191 #define XGBE_RSS_HASH_KEY_SIZE 40
192 #define XGBE_RSS_MAX_TABLE_SIZE 256
193 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
194 #define XGBE_RSS_HASH_KEY_TYPE 1
195
196 /* Auto-negotiation */
197 #define XGBE_AN_MS_TIMEOUT 500
198 #define XGBE_LINK_TIMEOUT 5
199 #define XGBE_KR_TRAINING_WAIT_ITER 50
200
201 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(1)
202 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
203 #define XGBE_SGMII_AN_LINK_SPEED_10 0x00
204 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04
205 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
206 #define XGBE_SGMII_AN_LINK_STATUS BIT(4)
207
208 /* ECC correctable error notification window (seconds) */
209 #define XGBE_ECC_LIMIT 60
210
211 /* MDIO port types */
212 #define XGMAC_MAX_C22_PORT 3
213
214 /* Link mode bit operations */
215 #define XGBE_ZERO_SUP(_ls) \
216 ethtool_link_ksettings_zero_link_mode((_ls), supported)
217
218 #define XGBE_SET_SUP(_ls, _mode) \
219 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode)
220
221 #define XGBE_CLR_SUP(_ls, _mode) \
222 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode)
223
224 #define XGBE_IS_SUP(_ls, _mode) \
225 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode)
226
227 #define XGBE_ZERO_ADV(_ls) \
228 ethtool_link_ksettings_zero_link_mode((_ls), advertising)
229
230 #define XGBE_SET_ADV(_ls, _mode) \
231 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode)
232
233 #define XGBE_CLR_ADV(_ls, _mode) \
234 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode)
235
236 #define XGBE_ADV(_ls, _mode) \
237 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode)
238
239 #define XGBE_ZERO_LP_ADV(_ls) \
240 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising)
241
242 #define XGBE_SET_LP_ADV(_ls, _mode) \
243 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode)
244
245 #define XGBE_CLR_LP_ADV(_ls, _mode) \
246 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode)
247
248 #define XGBE_LP_ADV(_ls, _mode) \
249 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode)
250
251 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \
252 bitmap_copy((_dst)->link_modes._dname, \
253 (_src)->link_modes._sname, \
254 __ETHTOOL_LINK_MODE_MASK_NBITS)
255
256 /* XGBE PCI device id */
257 #define XGBE_RV_PCI_DEVICE_ID 0x15d0
258 #define XGBE_YC_PCI_DEVICE_ID 0x14b5
259 #define XGBE_RN_PCI_DEVICE_ID 0x1630
260
261 /* Generic low and high masks */
262 #define XGBE_GEN_HI_MASK GENMASK(31, 16)
263 #define XGBE_GEN_LO_MASK GENMASK(15, 0)
264
265 struct xgbe_prv_data;
266
267 struct xgbe_packet_data {
268 struct sk_buff *skb;
269
270 unsigned int attributes;
271
272 unsigned int errors;
273
274 unsigned int rdesc_count;
275 unsigned int length;
276
277 unsigned int header_len;
278 unsigned int tcp_header_len;
279 unsigned int tcp_payload_len;
280 unsigned short mss;
281
282 unsigned short vlan_ctag;
283
284 u64 rx_tstamp;
285
286 u32 rss_hash;
287 enum pkt_hash_types rss_hash_type;
288
289 unsigned int tx_packets;
290 unsigned int tx_bytes;
291 };
292
293 /* Common Rx and Tx descriptor mapping */
294 struct xgbe_ring_desc {
295 __le32 desc0;
296 __le32 desc1;
297 __le32 desc2;
298 __le32 desc3;
299 };
300
301 /* Page allocation related values */
302 struct xgbe_page_alloc {
303 struct page *pages;
304 unsigned int pages_len;
305 unsigned int pages_offset;
306
307 dma_addr_t pages_dma;
308 };
309
310 /* Ring entry buffer data */
311 struct xgbe_buffer_data {
312 struct xgbe_page_alloc pa;
313 struct xgbe_page_alloc pa_unmap;
314
315 dma_addr_t dma_base;
316 unsigned long dma_off;
317 unsigned int dma_len;
318 };
319
320 /* Tx-related ring data */
321 struct xgbe_tx_ring_data {
322 unsigned int packets; /* BQL packet count */
323 unsigned int bytes; /* BQL byte count */
324 };
325
326 /* Rx-related ring data */
327 struct xgbe_rx_ring_data {
328 struct xgbe_buffer_data hdr; /* Header locations */
329 struct xgbe_buffer_data buf; /* Payload locations */
330
331 unsigned short hdr_len; /* Length of received header */
332 unsigned short len; /* Length of received packet */
333 };
334
335 /* Structure used to hold information related to the descriptor
336 * and the packet associated with the descriptor (always use
337 * the XGBE_GET_DESC_DATA macro to access this data from the ring)
338 */
339 struct xgbe_ring_data {
340 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
341 dma_addr_t rdesc_dma; /* DMA address of descriptor */
342
343 struct sk_buff *skb; /* Virtual address of SKB */
344 dma_addr_t skb_dma; /* DMA address of SKB data */
345 unsigned int skb_dma_len; /* Length of SKB DMA area */
346
347 struct xgbe_tx_ring_data tx; /* Tx-related data */
348 struct xgbe_rx_ring_data rx; /* Rx-related data */
349
350 unsigned int mapped_as_page;
351
352 /* Incomplete receive save location. If the budget is exhausted
353 * or the last descriptor (last normal descriptor or a following
354 * context descriptor) has not been DMA'd yet the current state
355 * of the receive processing needs to be saved.
356 */
357 unsigned int state_saved;
358 struct {
359 struct sk_buff *skb;
360 unsigned int len;
361 unsigned int error;
362 } state;
363 };
364
365 struct xgbe_ring {
366 /* Ring lock - used just for TX rings at the moment */
367 spinlock_t lock;
368
369 /* Per packet related information */
370 struct xgbe_packet_data packet_data;
371
372 /* Virtual/DMA addresses and count of allocated descriptor memory */
373 struct xgbe_ring_desc *rdesc;
374 dma_addr_t rdesc_dma;
375 unsigned int rdesc_count;
376
377 /* Array of descriptor data corresponding the descriptor memory
378 * (always use the XGBE_GET_DESC_DATA macro to access this data)
379 */
380 struct xgbe_ring_data *rdata;
381
382 /* Page allocation for RX buffers */
383 struct xgbe_page_alloc rx_hdr_pa;
384 struct xgbe_page_alloc rx_buf_pa;
385 int node;
386
387 /* Ring index values
388 * cur - Tx: index of descriptor to be used for current transfer
389 * Rx: index of descriptor to check for packet availability
390 * dirty - Tx: index of descriptor to check for transfer complete
391 * Rx: index of descriptor to check for buffer reallocation
392 */
393 unsigned int cur;
394 unsigned int dirty;
395
396 /* Coalesce frame count used for interrupt bit setting */
397 unsigned int coalesce_count;
398
399 union {
400 struct {
401 unsigned int queue_stopped;
402 unsigned int xmit_more;
403 unsigned short cur_mss;
404 unsigned short cur_vlan_ctag;
405 } tx;
406 };
407 } ____cacheline_aligned;
408
409 /* Structure used to describe the descriptor rings associated with
410 * a DMA channel.
411 */
412 struct xgbe_channel {
413 char name[20];
414
415 /* Address of private data area for device */
416 struct xgbe_prv_data *pdata;
417
418 /* Queue index and base address of queue's DMA registers */
419 unsigned int queue_index;
420 void __iomem *dma_regs;
421
422 /* Per channel interrupt irq number */
423 int dma_irq;
424 char dma_irq_name[IFNAMSIZ + 32];
425
426 /* Netdev related settings */
427 struct napi_struct napi;
428
429 /* Per channel interrupt enablement tracker */
430 unsigned int curr_ier;
431 unsigned int saved_ier;
432
433 unsigned int tx_timer_active;
434 struct timer_list tx_timer;
435
436 struct xgbe_ring *tx_ring;
437 struct xgbe_ring *rx_ring;
438
439 int node;
440 cpumask_t affinity_mask;
441 } ____cacheline_aligned;
442
443 enum xgbe_state {
444 XGBE_DOWN,
445 XGBE_LINK_INIT,
446 XGBE_LINK_ERR,
447 XGBE_STOPPED,
448 };
449
450 enum xgbe_int {
451 XGMAC_INT_DMA_CH_SR_TI,
452 XGMAC_INT_DMA_CH_SR_TPS,
453 XGMAC_INT_DMA_CH_SR_TBU,
454 XGMAC_INT_DMA_CH_SR_RI,
455 XGMAC_INT_DMA_CH_SR_RBU,
456 XGMAC_INT_DMA_CH_SR_RPS,
457 XGMAC_INT_DMA_CH_SR_TI_RI,
458 XGMAC_INT_DMA_CH_SR_FBE,
459 XGMAC_INT_DMA_ALL,
460 };
461
462 enum xgbe_int_state {
463 XGMAC_INT_STATE_SAVE,
464 XGMAC_INT_STATE_RESTORE,
465 };
466
467 enum xgbe_ecc_sec {
468 XGBE_ECC_SEC_TX,
469 XGBE_ECC_SEC_RX,
470 XGBE_ECC_SEC_DESC,
471 };
472
473 enum xgbe_speed {
474 XGBE_SPEED_1000 = 0,
475 XGBE_SPEED_2500,
476 XGBE_SPEED_10000,
477 XGBE_SPEEDS,
478 };
479
480 enum xgbe_xpcs_access {
481 XGBE_XPCS_ACCESS_V1 = 0,
482 XGBE_XPCS_ACCESS_V2,
483 XGBE_XPCS_ACCESS_V3,
484 };
485
486 enum xgbe_an_mode {
487 XGBE_AN_MODE_CL73 = 0,
488 XGBE_AN_MODE_CL73_REDRV,
489 XGBE_AN_MODE_CL37,
490 XGBE_AN_MODE_CL37_SGMII,
491 XGBE_AN_MODE_NONE,
492 };
493
494 enum xgbe_an {
495 XGBE_AN_READY = 0,
496 XGBE_AN_PAGE_RECEIVED,
497 XGBE_AN_INCOMPAT_LINK,
498 XGBE_AN_COMPLETE,
499 XGBE_AN_NO_LINK,
500 XGBE_AN_ERROR,
501 };
502
503 enum xgbe_rx {
504 XGBE_RX_BPA = 0,
505 XGBE_RX_XNP,
506 XGBE_RX_COMPLETE,
507 XGBE_RX_ERROR,
508 };
509
510 enum xgbe_mode {
511 XGBE_MODE_KX_1000 = 0,
512 XGBE_MODE_KX_2500,
513 XGBE_MODE_KR,
514 XGBE_MODE_X,
515 XGBE_MODE_SGMII_10,
516 XGBE_MODE_SGMII_100,
517 XGBE_MODE_SGMII_1000,
518 XGBE_MODE_SFI,
519 XGBE_MODE_UNKNOWN,
520 };
521
522 enum xgbe_speedset {
523 XGBE_SPEEDSET_1000_10000 = 0,
524 XGBE_SPEEDSET_2500_10000,
525 };
526
527 enum xgbe_mdio_mode {
528 XGBE_MDIO_MODE_NONE = 0,
529 XGBE_MDIO_MODE_CL22,
530 XGBE_MDIO_MODE_CL45,
531 };
532
533 enum xgbe_mb_cmd {
534 XGBE_MB_CMD_POWER_OFF = 0,
535 XGBE_MB_CMD_SET_1G,
536 XGBE_MB_CMD_SET_2_5G,
537 XGBE_MB_CMD_SET_10G_SFI,
538 XGBE_MB_CMD_SET_10G_KR,
539 XGBE_MB_CMD_RRC
540 };
541
542 enum xgbe_mb_subcmd {
543 XGBE_MB_SUBCMD_NONE = 0,
544 XGBE_MB_SUBCMD_RX_ADAP,
545
546 /* 10GbE SFP subcommands */
547 XGBE_MB_SUBCMD_ACTIVE = 0,
548 XGBE_MB_SUBCMD_PASSIVE_1M,
549 XGBE_MB_SUBCMD_PASSIVE_3M,
550 XGBE_MB_SUBCMD_PASSIVE_OTHER,
551
552 /* 1GbE Mode subcommands */
553 XGBE_MB_SUBCMD_10MBITS = 0,
554 XGBE_MB_SUBCMD_100MBITS,
555 XGBE_MB_SUBCMD_1G_SGMII,
556 XGBE_MB_SUBCMD_1G_KX
557 };
558
559 struct xgbe_phy {
560 struct ethtool_link_ksettings lks;
561
562 int address;
563
564 int autoneg;
565 int speed;
566 int duplex;
567
568 int link;
569
570 int pause_autoneg;
571 int tx_pause;
572 int rx_pause;
573 };
574
575 enum xgbe_i2c_cmd {
576 XGBE_I2C_CMD_READ = 0,
577 XGBE_I2C_CMD_WRITE,
578 };
579
580 struct xgbe_i2c_op {
581 enum xgbe_i2c_cmd cmd;
582
583 unsigned int target;
584
585 void *buf;
586 unsigned int len;
587 };
588
589 struct xgbe_i2c_op_state {
590 struct xgbe_i2c_op *op;
591
592 unsigned int tx_len;
593 unsigned char *tx_buf;
594
595 unsigned int rx_len;
596 unsigned char *rx_buf;
597
598 unsigned int tx_abort_source;
599
600 int ret;
601 };
602
603 struct xgbe_i2c {
604 unsigned int started;
605 unsigned int max_speed_mode;
606 unsigned int rx_fifo_size;
607 unsigned int tx_fifo_size;
608
609 struct xgbe_i2c_op_state op_state;
610 };
611
612 struct xgbe_mmc_stats {
613 /* Tx Stats */
614 u64 txoctetcount_gb;
615 u64 txframecount_gb;
616 u64 txbroadcastframes_g;
617 u64 txmulticastframes_g;
618 u64 tx64octets_gb;
619 u64 tx65to127octets_gb;
620 u64 tx128to255octets_gb;
621 u64 tx256to511octets_gb;
622 u64 tx512to1023octets_gb;
623 u64 tx1024tomaxoctets_gb;
624 u64 txunicastframes_gb;
625 u64 txmulticastframes_gb;
626 u64 txbroadcastframes_gb;
627 u64 txunderflowerror;
628 u64 txoctetcount_g;
629 u64 txframecount_g;
630 u64 txpauseframes;
631 u64 txvlanframes_g;
632
633 /* Rx Stats */
634 u64 rxframecount_gb;
635 u64 rxoctetcount_gb;
636 u64 rxoctetcount_g;
637 u64 rxbroadcastframes_g;
638 u64 rxmulticastframes_g;
639 u64 rxcrcerror;
640 u64 rxrunterror;
641 u64 rxjabbererror;
642 u64 rxundersize_g;
643 u64 rxoversize_g;
644 u64 rx64octets_gb;
645 u64 rx65to127octets_gb;
646 u64 rx128to255octets_gb;
647 u64 rx256to511octets_gb;
648 u64 rx512to1023octets_gb;
649 u64 rx1024tomaxoctets_gb;
650 u64 rxunicastframes_g;
651 u64 rxlengtherror;
652 u64 rxoutofrangetype;
653 u64 rxpauseframes;
654 u64 rxfifooverflow;
655 u64 rxvlanframes_gb;
656 u64 rxwatchdogerror;
657 };
658
659 struct xgbe_ext_stats {
660 u64 tx_tso_packets;
661 u64 rx_split_header_packets;
662 u64 rx_buffer_unavailable;
663
664 u64 txq_packets[XGBE_MAX_DMA_CHANNELS];
665 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS];
666 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS];
667 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS];
668
669 u64 tx_vxlan_packets;
670 u64 rx_vxlan_packets;
671 u64 rx_csum_errors;
672 u64 rx_vxlan_csum_errors;
673 };
674
675 struct xgbe_hw_if {
676 int (*tx_complete)(struct xgbe_ring_desc *);
677
678 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr);
679 int (*config_rx_mode)(struct xgbe_prv_data *);
680
681 int (*enable_rx_csum)(struct xgbe_prv_data *);
682 int (*disable_rx_csum)(struct xgbe_prv_data *);
683
684 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
685 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
686 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
687 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
688 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
689
690 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
691 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
692 int (*set_speed)(struct xgbe_prv_data *, int);
693
694 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
695 enum xgbe_mdio_mode);
696 int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int);
697 int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16);
698 int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int);
699 int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int,
700 u16);
701
702 int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
703 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
704
705 void (*enable_tx)(struct xgbe_prv_data *);
706 void (*disable_tx)(struct xgbe_prv_data *);
707 void (*enable_rx)(struct xgbe_prv_data *);
708 void (*disable_rx)(struct xgbe_prv_data *);
709
710 void (*powerup_tx)(struct xgbe_prv_data *);
711 void (*powerdown_tx)(struct xgbe_prv_data *);
712 void (*powerup_rx)(struct xgbe_prv_data *);
713 void (*powerdown_rx)(struct xgbe_prv_data *);
714
715 int (*init)(struct xgbe_prv_data *);
716 int (*exit)(struct xgbe_prv_data *);
717
718 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
719 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
720 void (*dev_xmit)(struct xgbe_channel *);
721 int (*dev_read)(struct xgbe_channel *);
722 void (*tx_desc_init)(struct xgbe_channel *);
723 void (*rx_desc_init)(struct xgbe_channel *);
724 void (*tx_desc_reset)(struct xgbe_ring_data *);
725 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
726 unsigned int);
727 int (*is_last_desc)(struct xgbe_ring_desc *);
728 int (*is_context_desc)(struct xgbe_ring_desc *);
729 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
730
731 /* For FLOW ctrl */
732 int (*config_tx_flow_control)(struct xgbe_prv_data *);
733 int (*config_rx_flow_control)(struct xgbe_prv_data *);
734
735 /* For RX coalescing */
736 int (*config_rx_coalesce)(struct xgbe_prv_data *);
737 int (*config_tx_coalesce)(struct xgbe_prv_data *);
738 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
739 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
740
741 /* For RX and TX threshold config */
742 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
743 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
744
745 /* For RX and TX Store and Forward Mode config */
746 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
747 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
748
749 /* For TX DMA Operate on Second Frame config */
750 int (*config_osp_mode)(struct xgbe_prv_data *);
751
752 /* For MMC statistics */
753 void (*rx_mmc_int)(struct xgbe_prv_data *);
754 void (*tx_mmc_int)(struct xgbe_prv_data *);
755 void (*read_mmc_stats)(struct xgbe_prv_data *);
756
757 /* For Data Center Bridging config */
758 void (*config_tc)(struct xgbe_prv_data *);
759 void (*config_dcb_tc)(struct xgbe_prv_data *);
760 void (*config_dcb_pfc)(struct xgbe_prv_data *);
761
762 /* For Receive Side Scaling */
763 int (*enable_rss)(struct xgbe_prv_data *);
764 int (*disable_rss)(struct xgbe_prv_data *);
765 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
766 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
767
768 /* For ECC */
769 void (*disable_ecc_ded)(struct xgbe_prv_data *);
770 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
771
772 /* For VXLAN */
773 void (*enable_vxlan)(struct xgbe_prv_data *);
774 void (*disable_vxlan)(struct xgbe_prv_data *);
775 void (*set_vxlan_id)(struct xgbe_prv_data *);
776
777 /* For Split Header */
778 void (*enable_sph)(struct xgbe_prv_data *pdata);
779 void (*disable_sph)(struct xgbe_prv_data *pdata);
780 };
781
782 /* This structure represents implementation specific routines for an
783 * implementation of a PHY. All routines are required unless noted below.
784 * Optional routines:
785 * an_pre, an_post
786 * kr_training_pre, kr_training_post
787 * module_info, module_eeprom
788 */
789 struct xgbe_phy_impl_if {
790 /* Perform Setup/teardown actions */
791 int (*init)(struct xgbe_prv_data *);
792 void (*exit)(struct xgbe_prv_data *);
793
794 /* Perform start/stop specific actions */
795 int (*reset)(struct xgbe_prv_data *);
796 int (*start)(struct xgbe_prv_data *);
797 void (*stop)(struct xgbe_prv_data *);
798
799 /* Return the link status */
800 int (*link_status)(struct xgbe_prv_data *, int *);
801
802 /* Indicate if a particular speed is valid */
803 bool (*valid_speed)(struct xgbe_prv_data *, int);
804
805 /* Check if the specified mode can/should be used */
806 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
807 /* Switch the PHY into various modes */
808 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
809 /* Retrieve mode needed for a specific speed */
810 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
811 /* Retrieve new/next mode when trying to auto-negotiate */
812 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
813 /* Retrieve current mode */
814 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
815
816 /* Retrieve current auto-negotiation mode */
817 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
818
819 /* Configure auto-negotiation settings */
820 int (*an_config)(struct xgbe_prv_data *);
821
822 /* Set/override auto-negotiation advertisement settings */
823 void (*an_advertising)(struct xgbe_prv_data *,
824 struct ethtool_link_ksettings *);
825
826 /* Process results of auto-negotiation */
827 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
828
829 /* Pre/Post auto-negotiation support */
830 void (*an_pre)(struct xgbe_prv_data *);
831 void (*an_post)(struct xgbe_prv_data *);
832
833 /* Pre/Post KR training enablement support */
834 void (*kr_training_pre)(struct xgbe_prv_data *);
835 void (*kr_training_post)(struct xgbe_prv_data *);
836
837 /* SFP module related info */
838 int (*module_info)(struct xgbe_prv_data *pdata,
839 struct ethtool_modinfo *modinfo);
840 int (*module_eeprom)(struct xgbe_prv_data *pdata,
841 struct ethtool_eeprom *eeprom, u8 *data);
842 };
843
844 struct xgbe_phy_if {
845 /* For PHY setup/teardown */
846 int (*phy_init)(struct xgbe_prv_data *);
847 void (*phy_exit)(struct xgbe_prv_data *);
848
849 /* For PHY support when setting device up/down */
850 int (*phy_reset)(struct xgbe_prv_data *);
851 int (*phy_start)(struct xgbe_prv_data *);
852 void (*phy_stop)(struct xgbe_prv_data *);
853
854 /* For PHY support while device is up */
855 void (*phy_status)(struct xgbe_prv_data *);
856 int (*phy_config_aneg)(struct xgbe_prv_data *);
857
858 /* For PHY settings validation */
859 bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
860
861 /* For single interrupt support */
862 irqreturn_t (*an_isr)(struct xgbe_prv_data *);
863
864 /* For ethtool PHY support */
865 int (*module_info)(struct xgbe_prv_data *pdata,
866 struct ethtool_modinfo *modinfo);
867 int (*module_eeprom)(struct xgbe_prv_data *pdata,
868 struct ethtool_eeprom *eeprom, u8 *data);
869
870 /* PHY implementation specific services */
871 struct xgbe_phy_impl_if phy_impl;
872 };
873
874 struct xgbe_i2c_if {
875 /* For initial I2C setup */
876 int (*i2c_init)(struct xgbe_prv_data *);
877
878 /* For I2C support when setting device up/down */
879 int (*i2c_start)(struct xgbe_prv_data *);
880 void (*i2c_stop)(struct xgbe_prv_data *);
881
882 /* For performing I2C operations */
883 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
884
885 /* For single interrupt support */
886 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *);
887 };
888
889 struct xgbe_desc_if {
890 int (*alloc_ring_resources)(struct xgbe_prv_data *);
891 void (*free_ring_resources)(struct xgbe_prv_data *);
892 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
893 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
894 struct xgbe_ring_data *);
895 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
896 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
897 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
898 };
899
900 /* This structure contains flags that indicate what hardware features
901 * or configurations are present in the device.
902 */
903 struct xgbe_hw_features {
904 /* HW Version */
905 unsigned int version;
906
907 /* HW Feature Register0 */
908 unsigned int gmii; /* 1000 Mbps support */
909 unsigned int vlhash; /* VLAN Hash Filter */
910 unsigned int sma; /* SMA(MDIO) Interface */
911 unsigned int rwk; /* PMT remote wake-up packet */
912 unsigned int mgk; /* PMT magic packet */
913 unsigned int mmc; /* RMON module */
914 unsigned int aoe; /* ARP Offload */
915 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
916 unsigned int eee; /* Energy Efficient Ethernet */
917 unsigned int tx_coe; /* Tx Checksum Offload */
918 unsigned int rx_coe; /* Rx Checksum Offload */
919 unsigned int addn_mac; /* Additional MAC Addresses */
920 unsigned int ts_src; /* Timestamp Source */
921 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
922 unsigned int vxn; /* VXLAN/NVGRE */
923
924 /* HW Feature Register1 */
925 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
926 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
927 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
928 unsigned int dma_width; /* DMA width */
929 unsigned int dcb; /* DCB Feature */
930 unsigned int sph; /* Split Header Feature */
931 unsigned int tso; /* TCP Segmentation Offload */
932 unsigned int dma_debug; /* DMA Debug Registers */
933 unsigned int rss; /* Receive Side Scaling */
934 unsigned int tc_cnt; /* Number of Traffic Classes */
935 unsigned int hash_table_size; /* Hash Table Size */
936 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
937
938 /* HW Feature Register2 */
939 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
940 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
941 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
942 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
943 unsigned int pps_out_num; /* Number of PPS outputs */
944 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
945 };
946
947 struct xgbe_version_data {
948 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
949 enum xgbe_xpcs_access xpcs_access;
950 unsigned int mmc_64bit;
951 unsigned int tx_max_fifo_size;
952 unsigned int rx_max_fifo_size;
953 unsigned int tx_tstamp_workaround;
954 unsigned int tstamp_ptp_clock_freq;
955 unsigned int ecc_support;
956 unsigned int i2c_support;
957 unsigned int irq_reissue_support;
958 unsigned int tx_desc_prefetch;
959 unsigned int rx_desc_prefetch;
960 unsigned int an_cdr_workaround;
961 unsigned int enable_rrc;
962 };
963
964 struct xgbe_prv_data {
965 struct net_device *netdev;
966 struct pci_dev *pcidev;
967 struct platform_device *platdev;
968 struct acpi_device *adev;
969 struct device *dev;
970 struct platform_device *phy_platdev;
971 struct device *phy_dev;
972 unsigned int smn_base;
973
974 /* Version related data */
975 struct xgbe_version_data *vdata;
976
977 /* ACPI or DT flag */
978 unsigned int use_acpi;
979
980 /* XGMAC/XPCS related mmio registers */
981 void __iomem *xgmac_regs; /* XGMAC CSRs */
982 void __iomem *xpcs_regs; /* XPCS MMD registers */
983 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
984 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
985 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
986 void __iomem *xprop_regs; /* XGBE property registers */
987 void __iomem *xi2c_regs; /* XGBE I2C CSRs */
988
989 /* Port property registers */
990 unsigned int pp0;
991 unsigned int pp1;
992 unsigned int pp2;
993 unsigned int pp3;
994 unsigned int pp4;
995
996 /* Overall device lock */
997 spinlock_t lock;
998
999 /* XPCS indirect addressing lock */
1000 spinlock_t xpcs_lock;
1001 unsigned int xpcs_window_def_reg;
1002 unsigned int xpcs_window_sel_reg;
1003 unsigned int xpcs_window;
1004 unsigned int xpcs_window_size;
1005 unsigned int xpcs_window_mask;
1006
1007 /* RSS addressing mutex */
1008 struct mutex rss_mutex;
1009
1010 /* Flags representing xgbe_state */
1011 unsigned long dev_state;
1012
1013 /* ECC support */
1014 unsigned long tx_sec_period;
1015 unsigned long tx_ded_period;
1016 unsigned long rx_sec_period;
1017 unsigned long rx_ded_period;
1018 unsigned long desc_sec_period;
1019 unsigned long desc_ded_period;
1020
1021 unsigned int tx_sec_count;
1022 unsigned int tx_ded_count;
1023 unsigned int rx_sec_count;
1024 unsigned int rx_ded_count;
1025 unsigned int desc_ded_count;
1026 unsigned int desc_sec_count;
1027
1028 int dev_irq;
1029 int ecc_irq;
1030 int i2c_irq;
1031 int channel_irq[XGBE_MAX_DMA_CHANNELS];
1032
1033 unsigned int per_channel_irq;
1034 unsigned int irq_count;
1035 unsigned int channel_irq_count;
1036 unsigned int channel_irq_mode;
1037
1038 char ecc_name[IFNAMSIZ + 32];
1039
1040 struct xgbe_hw_if hw_if;
1041 struct xgbe_phy_if phy_if;
1042 struct xgbe_desc_if desc_if;
1043 struct xgbe_i2c_if i2c_if;
1044
1045 /* AXI DMA settings */
1046 unsigned int coherent;
1047 unsigned int arcr;
1048 unsigned int awcr;
1049 unsigned int awarcr;
1050
1051 /* Service routine support */
1052 struct workqueue_struct *dev_workqueue;
1053 struct work_struct service_work;
1054 struct timer_list service_timer;
1055
1056 /* Rings for Tx/Rx on a DMA channel */
1057 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS];
1058 unsigned int tx_max_channel_count;
1059 unsigned int rx_max_channel_count;
1060 unsigned int channel_count;
1061 unsigned int tx_ring_count;
1062 unsigned int tx_desc_count;
1063 unsigned int rx_ring_count;
1064 unsigned int rx_desc_count;
1065
1066 unsigned int new_tx_ring_count;
1067 unsigned int new_rx_ring_count;
1068
1069 unsigned int tx_max_q_count;
1070 unsigned int rx_max_q_count;
1071 unsigned int tx_q_count;
1072 unsigned int rx_q_count;
1073
1074 /* Tx/Rx common settings */
1075 unsigned int blen;
1076 unsigned int pbl;
1077 unsigned int aal;
1078 unsigned int rd_osr_limit;
1079 unsigned int wr_osr_limit;
1080
1081 /* Tx settings */
1082 unsigned int tx_sf_mode;
1083 unsigned int tx_threshold;
1084 unsigned int tx_osp_mode;
1085 unsigned int tx_max_fifo_size;
1086
1087 /* Rx settings */
1088 unsigned int rx_sf_mode;
1089 unsigned int rx_threshold;
1090 unsigned int rx_max_fifo_size;
1091
1092 /* Tx coalescing settings */
1093 unsigned int tx_usecs;
1094 unsigned int tx_frames;
1095
1096 /* Rx coalescing settings */
1097 unsigned int rx_riwt;
1098 unsigned int rx_usecs;
1099 unsigned int rx_frames;
1100
1101 /* Current Rx buffer size */
1102 unsigned int rx_buf_size;
1103
1104 /* Flow control settings */
1105 unsigned int pause_autoneg;
1106 unsigned int tx_pause;
1107 unsigned int rx_pause;
1108 unsigned int rx_rfa[XGBE_MAX_QUEUES];
1109 unsigned int rx_rfd[XGBE_MAX_QUEUES];
1110
1111 /* Receive Side Scaling settings */
1112 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
1113 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
1114 u32 rss_options;
1115
1116 /* VXLAN settings */
1117 u16 vxlan_port;
1118
1119 /* Netdev related settings */
1120 unsigned char mac_addr[ETH_ALEN];
1121 netdev_features_t netdev_features;
1122 struct napi_struct napi;
1123 struct xgbe_mmc_stats mmc_stats;
1124 struct xgbe_ext_stats ext_stats;
1125
1126 /* Filtering support */
1127 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1128
1129 /* Device clocks */
1130 struct clk *sysclk;
1131 unsigned long sysclk_rate;
1132 struct clk *ptpclk;
1133 unsigned long ptpclk_rate;
1134
1135 /* Timestamp support */
1136 spinlock_t tstamp_lock;
1137 struct ptp_clock_info ptp_clock_info;
1138 struct ptp_clock *ptp_clock;
1139 struct hwtstamp_config tstamp_config;
1140 unsigned int tstamp_addend;
1141 struct work_struct tx_tstamp_work;
1142 struct sk_buff *tx_tstamp_skb;
1143 u64 tx_tstamp;
1144
1145 /* DCB support */
1146 struct ieee_ets *ets;
1147 struct ieee_pfc *pfc;
1148 unsigned int q2tc_map[XGBE_MAX_QUEUES];
1149 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
1150 unsigned int pfcq[XGBE_MAX_QUEUES];
1151 unsigned int pfc_rfa;
1152 u8 num_tcs;
1153
1154 /* Hardware features of the device */
1155 struct xgbe_hw_features hw_feat;
1156
1157 /* Device work structures */
1158 struct work_struct restart_work;
1159 struct work_struct stopdev_work;
1160
1161 /* Keeps track of power mode */
1162 unsigned int power_down;
1163
1164 /* Network interface message level setting */
1165 u32 msg_enable;
1166
1167 /* Current PHY settings */
1168 phy_interface_t phy_mode;
1169 int phy_link;
1170 int phy_speed;
1171
1172 /* MDIO/PHY related settings */
1173 unsigned int phy_started;
1174 void *phy_data;
1175 struct xgbe_phy phy;
1176 int mdio_mmd;
1177 unsigned long link_check;
1178 struct completion mdio_complete;
1179
1180 unsigned int kr_redrv;
1181
1182 char an_name[IFNAMSIZ + 32];
1183 struct workqueue_struct *an_workqueue;
1184
1185 int an_irq;
1186 struct work_struct an_irq_work;
1187
1188 /* Auto-negotiation state machine support */
1189 unsigned int an_int;
1190 unsigned int an_status;
1191 struct mutex an_mutex;
1192 enum xgbe_an an_result;
1193 enum xgbe_an an_state;
1194 enum xgbe_rx kr_state;
1195 enum xgbe_rx kx_state;
1196 struct work_struct an_work;
1197 unsigned int an_again;
1198 unsigned int an_supported;
1199 unsigned int parallel_detect;
1200 unsigned int fec_ability;
1201 unsigned long an_start;
1202 unsigned long kr_start_time;
1203 enum xgbe_an_mode an_mode;
1204
1205 /* I2C support */
1206 struct xgbe_i2c i2c;
1207 struct mutex i2c_mutex;
1208 struct completion i2c_complete;
1209 char i2c_name[IFNAMSIZ + 32];
1210
1211 unsigned int lpm_ctrl; /* CTRL1 for resume */
1212
1213 unsigned int isr_as_bh_work;
1214 struct work_struct dev_bh_work;
1215 struct work_struct ecc_bh_work;
1216 struct work_struct i2c_bh_work;
1217 struct work_struct an_bh_work;
1218
1219 struct dentry *xgbe_debugfs;
1220
1221 unsigned int debugfs_xgmac_reg;
1222
1223 unsigned int debugfs_xpcs_mmd;
1224 unsigned int debugfs_xpcs_reg;
1225
1226 unsigned int debugfs_xprop_reg;
1227
1228 unsigned int debugfs_xi2c_reg;
1229
1230 bool debugfs_an_cdr_workaround;
1231 bool debugfs_an_cdr_track_early;
1232 bool en_rx_adap;
1233 int rx_adapt_retries;
1234 bool rx_adapt_done;
1235 bool mode_set;
1236 };
1237
1238 /* Function prototypes*/
1239 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *);
1240 void xgbe_free_pdata(struct xgbe_prv_data *);
1241 void xgbe_set_counts(struct xgbe_prv_data *);
1242 int xgbe_config_netdev(struct xgbe_prv_data *);
1243 void xgbe_deconfig_netdev(struct xgbe_prv_data *);
1244
1245 int xgbe_platform_init(void);
1246 void xgbe_platform_exit(void);
1247 #ifdef CONFIG_PCI
1248 int xgbe_pci_init(void);
1249 void xgbe_pci_exit(void);
1250 #else
xgbe_pci_init(void)1251 static inline int xgbe_pci_init(void) { return 0; }
xgbe_pci_exit(void)1252 static inline void xgbe_pci_exit(void) { }
1253 #endif
1254
1255 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
1256 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
1257 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
1258 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
1259 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
1260 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
1261 const struct net_device_ops *xgbe_get_netdev_ops(void);
1262 const struct ethtool_ops *xgbe_get_ethtool_ops(void);
1263 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void);
1264
1265 #ifdef CONFIG_AMD_XGBE_DCB
1266 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
1267 #endif
1268
1269 void xgbe_ptp_register(struct xgbe_prv_data *);
1270 void xgbe_ptp_unregister(struct xgbe_prv_data *);
1271 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1272 unsigned int, unsigned int, unsigned int);
1273 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
1274 unsigned int);
1275 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
1276 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
1277 int xgbe_powerup(struct net_device *, unsigned int);
1278 int xgbe_powerdown(struct net_device *, unsigned int);
1279 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
1280 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
1281 void xgbe_restart_dev(struct xgbe_prv_data *pdata);
1282 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata);
1283
1284 /* For Timestamp config */
1285 void xgbe_config_tstamp(struct xgbe_prv_data *pdata, unsigned int mac_tscr);
1286 u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata);
1287 u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata);
1288 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1289 struct xgbe_ring_desc *rdesc);
1290 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1291 struct xgbe_ring_desc *rdesc);
1292 void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1293 unsigned int addend);
1294 void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1295 unsigned int nsec);
1296 void xgbe_tx_tstamp(struct work_struct *work);
1297 int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1298 struct ifreq *ifreq);
1299 int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1300 struct ifreq *ifreq);
1301 void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1302 struct sk_buff *skb,
1303 struct xgbe_packet_data *packet);
1304 int xgbe_init_ptp(struct xgbe_prv_data *pdata);
1305 void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1306 unsigned int nsec);
1307 #ifdef CONFIG_DEBUG_FS
1308 void xgbe_debugfs_init(struct xgbe_prv_data *);
1309 void xgbe_debugfs_exit(struct xgbe_prv_data *);
1310 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata);
1311 #else
xgbe_debugfs_init(struct xgbe_prv_data * pdata)1312 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_exit(struct xgbe_prv_data * pdata)1313 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
xgbe_debugfs_rename(struct xgbe_prv_data * pdata)1314 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {}
1315 #endif /* CONFIG_DEBUG_FS */
1316
1317 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
1318 #if 0
1319 #define YDEBUG
1320 #define YDEBUG_MDIO
1321 #endif
1322
1323 /* For debug prints */
1324 #ifdef YDEBUG
1325 #define DBGPR(x...) pr_alert(x)
1326 #else
1327 #define DBGPR(x...) do { } while (0)
1328 #endif
1329
1330 #ifdef YDEBUG_MDIO
1331 #define DBGPR_MDIO(x...) pr_alert(x)
1332 #else
1333 #define DBGPR_MDIO(x...) do { } while (0)
1334 #endif
1335
1336 #endif
1337