xref: /linux/drivers/net/ethernet/wangxun/libwx/wx_type.h (revision 5abfdfd402699ce7c1e81d1a25bc37f60f7741ff)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3 
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6 
7 #include <linux/bitfield.h>
8 #include <linux/netdevice.h>
9 #include <linux/if_vlan.h>
10 #include <linux/phylink.h>
11 #include <net/ip.h>
12 
13 #define WX_NCSI_SUP                             0x8000
14 #define WX_NCSI_MASK                            0x8000
15 #define WX_WOL_SUP                              0x4000
16 #define WX_WOL_MASK                             0x4000
17 
18 /* MSI-X capability fields masks */
19 #define WX_PCIE_MSIX_TBL_SZ_MASK                0x7FF
20 #define WX_PCI_LINK_STATUS                      0xB2
21 
22 /**************** Global Registers ****************************/
23 /* chip control Registers */
24 #define WX_MIS_PWR                   0x10000
25 #define WX_MIS_RST                   0x1000C
26 #define WX_MIS_RST_LAN_RST(_i)       BIT((_i) + 1)
27 #define WX_MIS_RST_SW_RST            BIT(0)
28 #define WX_MIS_ST                    0x10028
29 #define WX_MIS_ST_MNG_INIT_DN        BIT(0)
30 #define WX_MIS_SWSM                  0x1002C
31 #define WX_MIS_SWSM_SMBI             BIT(0)
32 #define WX_MIS_RST_ST                0x10030
33 #define WX_MIS_RST_ST_RST_INI_SHIFT  8
34 #define WX_MIS_RST_ST_RST_INIT       (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
35 
36 /* FMGR Registers */
37 #define WX_SPI_CMD                   0x10104
38 #define WX_SPI_CMD_READ_DWORD        0x1
39 #define WX_SPI_CLK_DIV               0x3
40 #define WX_SPI_CMD_CMD(_v)           FIELD_PREP(GENMASK(30, 28), _v)
41 #define WX_SPI_CMD_CLK(_v)           FIELD_PREP(GENMASK(27, 25), _v)
42 #define WX_SPI_CMD_ADDR(_v)          FIELD_PREP(GENMASK(23, 0), _v)
43 #define WX_SPI_DATA                  0x10108
44 #define WX_SPI_DATA_BYPASS           BIT(31)
45 #define WX_SPI_DATA_OP_DONE          BIT(0)
46 #define WX_SPI_STATUS                0x1010C
47 #define WX_SPI_STATUS_OPDONE         BIT(0)
48 #define WX_SPI_STATUS_FLASH_BYPASS   BIT(31)
49 #define WX_SPI_ILDR_STATUS           0x10120
50 
51 /* Sensors for PVT(Process Voltage Temperature) */
52 #define WX_TS_EN                     0x10304
53 #define WX_TS_EN_ENA                 BIT(0)
54 #define WX_TS_ALARM_THRE             0x1030C
55 #define WX_TS_DALARM_THRE            0x10310
56 #define WX_TS_INT_EN                 0x10314
57 #define WX_TS_INT_EN_DALARM_INT_EN   BIT(1)
58 #define WX_TS_INT_EN_ALARM_INT_EN    BIT(0)
59 #define WX_TS_ALARM_ST               0x10318
60 #define WX_TS_ALARM_ST_DALARM        BIT(1)
61 #define WX_TS_ALARM_ST_ALARM         BIT(0)
62 
63 /* statistic */
64 #define WX_TX_FRAME_CNT_GOOD_BAD_L   0x1181C
65 #define WX_TX_BC_FRAMES_GOOD_L       0x11824
66 #define WX_TX_MC_FRAMES_GOOD_L       0x1182C
67 #define WX_RX_FRAME_CNT_GOOD_BAD_L   0x11900
68 #define WX_RX_BC_FRAMES_GOOD_L       0x11918
69 #define WX_RX_MC_FRAMES_GOOD_L       0x11920
70 #define WX_RX_CRC_ERROR_FRAMES_L     0x11928
71 #define WX_RX_LEN_ERROR_FRAMES_L     0x11978
72 #define WX_RX_UNDERSIZE_FRAMES_GOOD  0x11938
73 #define WX_RX_OVERSIZE_FRAMES_GOOD   0x1193C
74 #define WX_MAC_LXONOFFRXC            0x11E0C
75 
76 /*********************** Receive DMA registers **************************/
77 #define WX_RDM_DRP_PKT               0x12500
78 #define WX_RDM_PKT_CNT               0x12504
79 #define WX_RDM_BYTE_CNT_LSB          0x12508
80 #define WX_RDM_BMC2OS_CNT            0x12510
81 
82 /************************* Port Registers ************************************/
83 /* port cfg Registers */
84 #define WX_CFG_PORT_CTL              0x14400
85 #define WX_CFG_PORT_CTL_DRV_LOAD     BIT(3)
86 #define WX_CFG_PORT_CTL_QINQ         BIT(2)
87 #define WX_CFG_PORT_CTL_D_VLAN       BIT(0) /* double vlan*/
88 #define WX_CFG_TAG_TPID(_i)          (0x14430 + ((_i) * 4))
89 #define WX_CFG_PORT_CTL_NUM_VT_MASK  GENMASK(13, 12) /* number of TVs */
90 
91 
92 /* GPIO Registers */
93 #define WX_GPIO_DR                   0x14800
94 #define WX_GPIO_DR_0                 BIT(0) /* SDP0 Data Value */
95 #define WX_GPIO_DR_1                 BIT(1) /* SDP1 Data Value */
96 #define WX_GPIO_DDR                  0x14804
97 #define WX_GPIO_DDR_0                BIT(0) /* SDP0 IO direction */
98 #define WX_GPIO_DDR_1                BIT(1) /* SDP1 IO direction */
99 #define WX_GPIO_CTL                  0x14808
100 #define WX_GPIO_INTEN                0x14830
101 #define WX_GPIO_INTEN_0              BIT(0)
102 #define WX_GPIO_INTEN_1              BIT(1)
103 #define WX_GPIO_INTMASK              0x14834
104 #define WX_GPIO_INTTYPE_LEVEL        0x14838
105 #define WX_GPIO_POLARITY             0x1483C
106 #define WX_GPIO_INTSTATUS            0x14844
107 #define WX_GPIO_EOI                  0x1484C
108 #define WX_GPIO_EXT                  0x14850
109 
110 /*********************** Transmit DMA registers **************************/
111 /* transmit global control */
112 #define WX_TDM_CTL                   0x18000
113 /* TDM CTL BIT */
114 #define WX_TDM_CTL_TE                BIT(0) /* Transmit Enable */
115 #define WX_TDM_PB_THRE(_i)           (0x18020 + ((_i) * 4))
116 #define WX_TDM_RP_IDX                0x1820C
117 #define WX_TDM_PKT_CNT               0x18308
118 #define WX_TDM_BYTE_CNT_LSB          0x1830C
119 #define WX_TDM_OS2BMC_CNT            0x18314
120 #define WX_TDM_RP_RATE               0x18404
121 
122 /***************************** RDB registers *********************************/
123 /* receive packet buffer */
124 #define WX_RDB_PB_CTL                0x19000
125 #define WX_RDB_PB_CTL_RXEN           BIT(31) /* Enable Receiver */
126 #define WX_RDB_PB_CTL_DISABLED       BIT(0)
127 #define WX_RDB_PB_SZ(_i)             (0x19020 + ((_i) * 4))
128 #define WX_RDB_PB_SZ_SHIFT           10
129 /* statistic */
130 #define WX_RDB_PFCMACDAL             0x19210
131 #define WX_RDB_PFCMACDAH             0x19214
132 #define WX_RDB_LXOFFTXC              0x19218
133 #define WX_RDB_LXONTXC               0x1921C
134 /* Flow Control Registers */
135 #define WX_RDB_RFCV                  0x19200
136 #define WX_RDB_RFCL                  0x19220
137 #define WX_RDB_RFCL_XONE             BIT(31)
138 #define WX_RDB_RFCH                  0x19260
139 #define WX_RDB_RFCH_XOFFE            BIT(31)
140 #define WX_RDB_RFCRT                 0x192A0
141 #define WX_RDB_RFCC                  0x192A4
142 #define WX_RDB_RFCC_RFCE_802_3X      BIT(3)
143 /* ring assignment */
144 #define WX_RDB_PL_CFG(_i)            (0x19300 + ((_i) * 4))
145 #define WX_RDB_PL_CFG_L4HDR          BIT(1)
146 #define WX_RDB_PL_CFG_L3HDR          BIT(2)
147 #define WX_RDB_PL_CFG_L2HDR          BIT(3)
148 #define WX_RDB_PL_CFG_TUN_TUNHDR     BIT(4)
149 #define WX_RDB_PL_CFG_TUN_OUTL2HDR   BIT(5)
150 #define WX_RDB_RSSTBL(_i)            (0x19400 + ((_i) * 4))
151 #define WX_RDB_RSSRK(_i)             (0x19480 + ((_i) * 4))
152 #define WX_RDB_RA_CTL                0x194F4
153 #define WX_RDB_RA_CTL_RSS_EN         BIT(2) /* RSS Enable */
154 #define WX_RDB_RA_CTL_RSS_IPV4_TCP   BIT(16)
155 #define WX_RDB_RA_CTL_RSS_IPV4       BIT(17)
156 #define WX_RDB_RA_CTL_RSS_IPV6       BIT(20)
157 #define WX_RDB_RA_CTL_RSS_IPV6_TCP   BIT(21)
158 #define WX_RDB_RA_CTL_RSS_IPV4_UDP   BIT(22)
159 #define WX_RDB_RA_CTL_RSS_IPV6_UDP   BIT(23)
160 #define WX_RDB_FDIR_MATCH            0x19558
161 #define WX_RDB_FDIR_MISS             0x1955C
162 
163 /******************************* PSR Registers *******************************/
164 /* psr control */
165 #define WX_PSR_CTL                   0x15000
166 /* Header split receive */
167 #define WX_PSR_CTL_SW_EN             BIT(18)
168 #define WX_PSR_CTL_RSC_ACK           BIT(17)
169 #define WX_PSR_CTL_RSC_DIS           BIT(16)
170 #define WX_PSR_CTL_PCSD              BIT(13)
171 #define WX_PSR_CTL_IPPCSE            BIT(12)
172 #define WX_PSR_CTL_BAM               BIT(10)
173 #define WX_PSR_CTL_UPE               BIT(9)
174 #define WX_PSR_CTL_MPE               BIT(8)
175 #define WX_PSR_CTL_MFE               BIT(7)
176 #define WX_PSR_CTL_MO_SHIFT          5
177 #define WX_PSR_CTL_MO                (0x3 << WX_PSR_CTL_MO_SHIFT)
178 #define WX_PSR_CTL_TPE               BIT(4)
179 #define WX_PSR_MAX_SZ                0x15020
180 #define WX_PSR_VLAN_CTL              0x15088
181 #define WX_PSR_VLAN_CTL_CFIEN        BIT(29)  /* bit 29 */
182 #define WX_PSR_VLAN_CTL_VFE          BIT(30)  /* bit 30 */
183 /* mcasst/ucast overflow tbl */
184 #define WX_PSR_MC_TBL(_i)            (0x15200  + ((_i) * 4))
185 #define WX_PSR_UC_TBL(_i)            (0x15400 + ((_i) * 4))
186 
187 /* VM L2 contorl */
188 #define WX_PSR_VM_L2CTL(_i)          (0x15600 + ((_i) * 4))
189 #define WX_PSR_VM_L2CTL_UPE          BIT(4) /* unicast promiscuous */
190 #define WX_PSR_VM_L2CTL_VACC         BIT(6) /* accept nomatched vlan */
191 #define WX_PSR_VM_L2CTL_AUPE         BIT(8) /* accept untagged packets */
192 #define WX_PSR_VM_L2CTL_ROMPE        BIT(9) /* accept packets in MTA tbl */
193 #define WX_PSR_VM_L2CTL_ROPE         BIT(10) /* accept packets in UC tbl */
194 #define WX_PSR_VM_L2CTL_BAM          BIT(11) /* accept broadcast packets */
195 #define WX_PSR_VM_L2CTL_MPE          BIT(12) /* multicast promiscuous */
196 
197 /* Management */
198 #define WX_PSR_MNG_FLEX_SEL          0x1582C
199 #define WX_PSR_MNG_FLEX_DW_L(_i)     (0x15A00 + ((_i) * 16))
200 #define WX_PSR_MNG_FLEX_DW_H(_i)     (0x15A04 + ((_i) * 16))
201 #define WX_PSR_MNG_FLEX_MSK(_i)      (0x15A08 + ((_i) * 16))
202 #define WX_PSR_LAN_FLEX_SEL          0x15B8C
203 #define WX_PSR_LAN_FLEX_DW_L(_i)     (0x15C00 + ((_i) * 16))
204 #define WX_PSR_LAN_FLEX_DW_H(_i)     (0x15C04 + ((_i) * 16))
205 #define WX_PSR_LAN_FLEX_MSK(_i)      (0x15C08 + ((_i) * 16))
206 
207 #define WX_PSR_WKUP_CTL              0x15B80
208 /* Wake Up Filter Control Bit */
209 #define WX_PSR_WKUP_CTL_MAG          BIT(1) /* Magic Packet Wakeup Enable */
210 
211 /* vlan tbl */
212 #define WX_PSR_VLAN_TBL(_i)          (0x16000 + ((_i) * 4))
213 
214 /* mac switcher */
215 #define WX_PSR_MAC_SWC_AD_L          0x16200
216 #define WX_PSR_MAC_SWC_AD_H          0x16204
217 #define WX_PSR_MAC_SWC_AD_H_AD(v)       FIELD_PREP(U16_MAX, v)
218 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v)   FIELD_PREP(BIT(30), v)
219 #define WX_PSR_MAC_SWC_AD_H_AV       BIT(31)
220 #define WX_PSR_MAC_SWC_VM_L          0x16208
221 #define WX_PSR_MAC_SWC_VM_H          0x1620C
222 #define WX_PSR_MAC_SWC_IDX           0x16210
223 #define WX_CLEAR_VMDQ_ALL            0xFFFFFFFFU
224 
225 /* vlan switch */
226 #define WX_PSR_VLAN_SWC              0x16220
227 #define WX_PSR_VLAN_SWC_VM_L         0x16224
228 #define WX_PSR_VLAN_SWC_VM_H         0x16228
229 #define WX_PSR_VLAN_SWC_IDX          0x16230         /* 64 vlan entries */
230 /* VLAN pool filtering masks */
231 #define WX_PSR_VLAN_SWC_VIEN         BIT(31)  /* filter is valid */
232 #define WX_PSR_VLAN_SWC_ENTRIES      64
233 
234 /********************************* RSEC **************************************/
235 /* general rsec */
236 #define WX_RSC_CTL                   0x17000
237 #define WX_RSC_CTL_SAVE_MAC_ERR      BIT(6)
238 #define WX_RSC_CTL_CRC_STRIP         BIT(2)
239 #define WX_RSC_CTL_RX_DIS            BIT(1)
240 #define WX_RSC_ST                    0x17004
241 #define WX_RSC_ST_RSEC_RDY           BIT(0)
242 
243 /****************************** TDB ******************************************/
244 #define WX_TDB_PB_SZ(_i)             (0x1CC00 + ((_i) * 4))
245 #define WX_TXPKT_SIZE_MAX            0xA /* Max Tx Packet size */
246 
247 /****************************** TSEC *****************************************/
248 /* Security Control Registers */
249 #define WX_TSC_CTL                   0x1D000
250 #define WX_TSC_CTL_TX_DIS            BIT(1)
251 #define WX_TSC_CTL_TSEC_DIS          BIT(0)
252 #define WX_TSC_ST                    0x1D004
253 #define WX_TSC_ST_SECTX_RDY          BIT(0)
254 #define WX_TSC_BUF_AE                0x1D00C
255 #define WX_TSC_BUF_AE_THR            GENMASK(9, 0)
256 
257 /************************************** MNG ********************************/
258 #define WX_MNG_SWFW_SYNC             0x1E008
259 #define WX_MNG_SWFW_SYNC_SW_MB       BIT(2)
260 #define WX_MNG_SWFW_SYNC_SW_FLASH    BIT(3)
261 #define WX_MNG_MBOX                  0x1E100
262 #define WX_MNG_MBOX_CTL              0x1E044
263 #define WX_MNG_MBOX_CTL_SWRDY        BIT(0)
264 #define WX_MNG_MBOX_CTL_FWRDY        BIT(2)
265 #define WX_MNG_BMC2OS_CNT            0x1E090
266 #define WX_MNG_OS2BMC_CNT            0x1E094
267 
268 /************************************* ETH MAC *****************************/
269 #define WX_MAC_TX_CFG                0x11000
270 #define WX_MAC_TX_CFG_TE             BIT(0)
271 #define WX_MAC_TX_CFG_SPEED_MASK     GENMASK(30, 29)
272 #define WX_MAC_TX_CFG_SPEED_10G      FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
273 #define WX_MAC_TX_CFG_SPEED_1G       FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
274 #define WX_MAC_RX_CFG                0x11004
275 #define WX_MAC_RX_CFG_RE             BIT(0)
276 #define WX_MAC_RX_CFG_JE             BIT(8)
277 #define WX_MAC_PKT_FLT               0x11008
278 #define WX_MAC_PKT_FLT_PR            BIT(0) /* promiscuous mode */
279 #define WX_MAC_WDG_TIMEOUT           0x1100C
280 #define WX_MAC_RX_FLOW_CTRL          0x11090
281 #define WX_MAC_RX_FLOW_CTRL_RFE      BIT(0) /* receive fc enable */
282 /* MDIO Registers */
283 #define WX_MSCA                      0x11200
284 #define WX_MSCA_RA(v)                FIELD_PREP(U16_MAX, v)
285 #define WX_MSCA_PA(v)                FIELD_PREP(GENMASK(20, 16), v)
286 #define WX_MSCA_DA(v)                FIELD_PREP(GENMASK(25, 21), v)
287 #define WX_MSCC                      0x11204
288 #define WX_MSCC_CMD(v)               FIELD_PREP(GENMASK(17, 16), v)
289 
290 enum WX_MSCA_CMD_value {
291 	WX_MSCA_CMD_RSV = 0,
292 	WX_MSCA_CMD_WRITE,
293 	WX_MSCA_CMD_POST_READ,
294 	WX_MSCA_CMD_READ,
295 };
296 
297 #define WX_MSCC_SADDR                BIT(18)
298 #define WX_MSCC_BUSY                 BIT(22)
299 #define WX_MDIO_CLK(v)               FIELD_PREP(GENMASK(21, 19), v)
300 #define WX_MDIO_CLAUSE_SELECT        0x11220
301 #define WX_MMC_CONTROL               0x11800
302 #define WX_MMC_CONTROL_RSTONRD       BIT(2) /* reset on read */
303 
304 /********************************* BAR registers ***************************/
305 /* Interrupt Registers */
306 #define WX_BME_CTL                   0x12020
307 #define WX_PX_MISC_IC                0x100
308 #define WX_PX_MISC_ICS               0x104
309 #define WX_PX_MISC_IEN               0x108
310 #define WX_PX_INTA                   0x110
311 #define WX_PX_GPIE                   0x118
312 #define WX_PX_GPIE_MODEL             BIT(0)
313 #define WX_PX_IC(_i)                 (0x120 + (_i) * 4)
314 #define WX_PX_IMS(_i)                (0x140 + (_i) * 4)
315 #define WX_PX_IMC(_i)                (0x150 + (_i) * 4)
316 #define WX_PX_ISB_ADDR_L             0x160
317 #define WX_PX_ISB_ADDR_H             0x164
318 #define WX_PX_TRANSACTION_PENDING    0x168
319 #define WX_PX_ITRSEL                 0x180
320 #define WX_PX_ITR(_i)                (0x200 + (_i) * 4)
321 #define WX_PX_ITR_CNT_WDIS           BIT(31)
322 #define WX_PX_MISC_IVAR              0x4FC
323 #define WX_PX_IVAR(_i)               (0x500 + (_i) * 4)
324 
325 #define WX_PX_IVAR_ALLOC_VAL         0x80 /* Interrupt Allocation valid */
326 #define WX_7K_ITR                    595
327 #define WX_12K_ITR                   336
328 #define WX_20K_ITR                   200
329 #define WX_SP_MAX_EITR               0x00000FF8U
330 #define WX_EM_MAX_EITR               0x00007FFCU
331 
332 /* transmit DMA Registers */
333 #define WX_PX_TR_BAL(_i)             (0x03000 + ((_i) * 0x40))
334 #define WX_PX_TR_BAH(_i)             (0x03004 + ((_i) * 0x40))
335 #define WX_PX_TR_WP(_i)              (0x03008 + ((_i) * 0x40))
336 #define WX_PX_TR_RP(_i)              (0x0300C + ((_i) * 0x40))
337 #define WX_PX_TR_CFG(_i)             (0x03010 + ((_i) * 0x40))
338 /* Transmit Config masks */
339 #define WX_PX_TR_CFG_ENABLE          BIT(0) /* Ena specific Tx Queue */
340 #define WX_PX_TR_CFG_TR_SIZE_SHIFT   1 /* tx desc number per ring */
341 #define WX_PX_TR_CFG_SWFLSH          BIT(26) /* Tx Desc. wr-bk flushing */
342 #define WX_PX_TR_CFG_WTHRESH_SHIFT   16 /* shift to WTHRESH bits */
343 #define WX_PX_TR_CFG_THRE_SHIFT      8
344 
345 /* Receive DMA Registers */
346 #define WX_PX_RR_BAL(_i)             (0x01000 + ((_i) * 0x40))
347 #define WX_PX_RR_BAH(_i)             (0x01004 + ((_i) * 0x40))
348 #define WX_PX_RR_WP(_i)              (0x01008 + ((_i) * 0x40))
349 #define WX_PX_RR_RP(_i)              (0x0100C + ((_i) * 0x40))
350 #define WX_PX_RR_CFG(_i)             (0x01010 + ((_i) * 0x40))
351 #define WX_PX_MPRC(_i)               (0x01020 + ((_i) * 0x40))
352 /* PX_RR_CFG bit definitions */
353 #define WX_PX_RR_CFG_VLAN            BIT(31)
354 #define WX_PX_RR_CFG_DROP_EN         BIT(30)
355 #define WX_PX_RR_CFG_SPLIT_MODE      BIT(26)
356 #define WX_PX_RR_CFG_RR_THER_SHIFT   16
357 #define WX_PX_RR_CFG_RR_HDR_SZ       GENMASK(15, 12)
358 #define WX_PX_RR_CFG_RR_BUF_SZ       GENMASK(11, 8)
359 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT  6 /* 64byte resolution (>> 6)
360 					* + at bit 8 offset (<< 12)
361 					*  = (<< 6)
362 					*/
363 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT  2 /* so many KBs */
364 #define WX_PX_RR_CFG_RR_SIZE_SHIFT   1
365 #define WX_PX_RR_CFG_RR_EN           BIT(0)
366 
367 /* Number of 80 microseconds we wait for PCI Express master disable */
368 #define WX_PCI_MASTER_DISABLE_TIMEOUT        80000
369 
370 /****************** Manageablility Host Interface defines ********************/
371 #define WX_HI_MAX_BLOCK_BYTE_LENGTH  256 /* Num of bytes in range */
372 #define WX_HI_COMMAND_TIMEOUT        1000 /* Process HI command limit */
373 
374 #define FW_READ_SHADOW_RAM_CMD       0x31
375 #define FW_READ_SHADOW_RAM_LEN       0x6
376 #define FW_DEFAULT_CHECKSUM          0xFF /* checksum always 0xFF */
377 #define FW_NVM_DATA_OFFSET           3
378 #define FW_MAX_READ_BUFFER_SIZE      244
379 #define FW_RESET_CMD                 0xDF
380 #define FW_RESET_LEN                 0x2
381 #define FW_CEM_HDR_LEN               0x4
382 #define FW_CEM_CMD_RESERVED          0X0
383 #define FW_CEM_MAX_RETRIES           3
384 #define FW_CEM_RESP_STATUS_SUCCESS   0x1
385 
386 #define WX_SW_REGION_PTR             0x1C
387 
388 #define WX_MAC_STATE_DEFAULT         0x1
389 #define WX_MAC_STATE_MODIFIED        0x2
390 #define WX_MAC_STATE_IN_USE          0x4
391 
392 /* BitTimes (BT) conversion */
393 #define WX_BT2KB(BT)         (((BT) + (8 * 1024 - 1)) / (8 * 1024))
394 #define WX_B2BT(BT)          ((BT) * 8)
395 
396 /* Calculate Delay to respond to PFC */
397 #define WX_PFC_D     672
398 /* Calculate Cable Delay */
399 #define WX_CABLE_DC  5556 /* Delay Copper */
400 /* Calculate Delay incurred from higher layer */
401 #define WX_HD        6144
402 
403 /* Calculate Interface Delay */
404 #define WX_PHY_D     12800
405 #define WX_MAC_D     4096
406 #define WX_XAUI_D    (2 * 1024)
407 #define WX_ID        (WX_MAC_D + WX_XAUI_D + WX_PHY_D)
408 /* Calculate PCI Bus delay for low thresholds */
409 #define WX_PCI_DELAY 10000
410 
411 /* Calculate delay value in bit times */
412 #define WX_DV(_max_frame_link, _max_frame_tc) \
413 	((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \
414 		(2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \
415 	 2 * WX_B2BT(_max_frame_tc))
416 
417 /* Calculate low threshold delay values */
418 #define WX_LOW_DV(_max_frame_tc) \
419 	(2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))
420 
421 /* flow control */
422 #define WX_DEFAULT_FCPAUSE           0xFFFF
423 
424 #define WX_MAX_RXD                   8192
425 #define WX_MAX_TXD                   8192
426 #define WX_MIN_RXD                   128
427 #define WX_MIN_TXD                   128
428 
429 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */
430 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE   128
431 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE   128
432 
433 #define WX_MAX_JUMBO_FRAME_SIZE      9432 /* max payload 9414 */
434 #define VMDQ_P(p)                    p
435 
436 /* Supported Rx Buffer Sizes */
437 #define WX_RXBUFFER_256      256    /* Used for skb receive header */
438 #define WX_RXBUFFER_2K       2048
439 #define WX_MAX_RXBUFFER      16384  /* largest size for single descriptor */
440 
441 #if MAX_SKB_FRAGS < 8
442 #define WX_RX_BUFSZ      ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
443 #else
444 #define WX_RX_BUFSZ      WX_RXBUFFER_2K
445 #endif
446 
447 #define WX_RX_BUFFER_WRITE   16      /* Must be power of 2 */
448 
449 #define WX_MAX_DATA_PER_TXD  BIT(14)
450 /* Tx Descriptors needed, worst case */
451 #define TXD_USE_COUNT(S)     DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
452 #define DESC_NEEDED          (MAX_SKB_FRAGS + 4)
453 
454 #define WX_CFG_PORT_ST               0x14404
455 
456 /******************* Receive Descriptor bit definitions **********************/
457 #define WX_RXD_STAT_DD               BIT(0) /* Done */
458 #define WX_RXD_STAT_EOP              BIT(1) /* End of Packet */
459 #define WX_RXD_STAT_VP               BIT(5) /* IEEE VLAN Pkt */
460 #define WX_RXD_STAT_L4CS             BIT(7) /* L4 xsum calculated */
461 #define WX_RXD_STAT_IPCS             BIT(8) /* IP xsum calculated */
462 #define WX_RXD_STAT_OUTERIPCS        BIT(10) /* Cloud IP xsum calculated*/
463 
464 #define WX_RXD_ERR_OUTERIPER         BIT(26) /* CRC IP Header error */
465 #define WX_RXD_ERR_RXE               BIT(29) /* Any MAC Error */
466 #define WX_RXD_ERR_TCPE              BIT(30) /* TCP/UDP Checksum Error */
467 #define WX_RXD_ERR_IPE               BIT(31) /* IP Checksum Error */
468 
469 /* RSS Hash results */
470 #define WX_RXD_RSSTYPE_MASK          GENMASK(3, 0)
471 #define WX_RXD_RSSTYPE_IPV4_TCP      0x00000001U
472 #define WX_RXD_RSSTYPE_IPV6_TCP      0x00000003U
473 #define WX_RXD_RSSTYPE_IPV4_SCTP     0x00000004U
474 #define WX_RXD_RSSTYPE_IPV6_SCTP     0x00000006U
475 #define WX_RXD_RSSTYPE_IPV4_UDP      0x00000007U
476 #define WX_RXD_RSSTYPE_IPV6_UDP      0x00000008U
477 
478 #define WX_RSS_L4_TYPES_MASK \
479 	((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
480 	 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
481 	 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
482 	 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
483 	 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
484 	 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
485 /* TUN */
486 #define WX_PTYPE_TUN_IPV4            0x80
487 #define WX_PTYPE_TUN_IPV6            0xC0
488 
489 /* PKT for TUN */
490 #define WX_PTYPE_PKT_IPIP            0x00 /* IP+IP */
491 #define WX_PTYPE_PKT_IG              0x10 /* IP+GRE */
492 #define WX_PTYPE_PKT_IGM             0x20 /* IP+GRE+MAC */
493 #define WX_PTYPE_PKT_IGMV            0x30 /* IP+GRE+MAC+VLAN */
494 /* PKT for !TUN */
495 #define WX_PTYPE_PKT_MAC             0x10
496 #define WX_PTYPE_PKT_IP              0x20
497 
498 /* TYP for PKT=mac */
499 #define WX_PTYPE_TYP_MAC             0x01
500 /* TYP for PKT=ip */
501 #define WX_PTYPE_PKT_IPV6            0x08
502 #define WX_PTYPE_TYP_IPFRAG          0x01
503 #define WX_PTYPE_TYP_IP              0x02
504 #define WX_PTYPE_TYP_UDP             0x03
505 #define WX_PTYPE_TYP_TCP             0x04
506 #define WX_PTYPE_TYP_SCTP            0x05
507 
508 /* Packet type non-ip values */
509 enum wx_l2_ptypes {
510 	WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC),
511 	WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC),
512 
513 	WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG),
514 	WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP),
515 	WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP),
516 	WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP),
517 	WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP),
518 	WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
519 				 WX_PTYPE_TYP_IPFRAG),
520 	WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
521 			    WX_PTYPE_TYP_IP),
522 	WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
523 				WX_PTYPE_TYP_UDP),
524 	WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
525 				WX_PTYPE_TYP_TCP),
526 	WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
527 				 WX_PTYPE_TYP_SCTP),
528 
529 	WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM),
530 	WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM),
531 };
532 
533 #define WX_PTYPE_PKT(_pt)            ((_pt) & 0x30)
534 #define WX_PTYPE_TYPL4(_pt)          ((_pt) & 0x07)
535 
536 #define WX_RXD_PKTTYPE(_rxd) \
537 	((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
538 #define WX_RXD_IPV6EX(_rxd) \
539 	((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 6) & 0x1)
540 /*********************** Transmit Descriptor Config Masks ****************/
541 #define WX_TXD_STAT_DD               BIT(0)  /* Descriptor Done */
542 #define WX_TXD_DTYP_DATA             0       /* Adv Data Descriptor */
543 #define WX_TXD_PAYLEN_SHIFT          13      /* Desc PAYLEN shift */
544 #define WX_TXD_EOP                   BIT(24) /* End of Packet */
545 #define WX_TXD_IFCS                  BIT(25) /* Insert FCS */
546 #define WX_TXD_RS                    BIT(27) /* Report Status */
547 
548 /*********************** Adv Transmit Descriptor Config Masks ****************/
549 #define WX_TXD_MAC_TSTAMP            BIT(19) /* IEEE1588 time stamp */
550 #define WX_TXD_DTYP_CTXT             BIT(20) /* Adv Context Desc */
551 #define WX_TXD_LINKSEC               BIT(26) /* enable linksec */
552 #define WX_TXD_VLE                   BIT(30) /* VLAN pkt enable */
553 #define WX_TXD_TSE                   BIT(31) /* TCP Seg enable */
554 #define WX_TXD_CC                    BIT(7) /* Check Context */
555 #define WX_TXD_IPSEC                 BIT(8) /* enable ipsec esp */
556 #define WX_TXD_L4CS                  BIT(9)
557 #define WX_TXD_IIPCS                 BIT(10)
558 #define WX_TXD_EIPCS                 BIT(11)
559 #define WX_TXD_PAYLEN_SHIFT          13 /* Adv desc PAYLEN shift */
560 #define WX_TXD_MACLEN_SHIFT          9  /* Adv ctxt desc mac len shift */
561 #define WX_TXD_TAG_TPID_SEL_SHIFT    11
562 
563 #define WX_TXD_L4LEN_SHIFT           8  /* Adv ctxt L4LEN shift */
564 #define WX_TXD_MSS_SHIFT             16  /* Adv ctxt MSS shift */
565 
566 #define WX_TXD_OUTER_IPLEN_SHIFT     12 /* Adv ctxt OUTERIPLEN shift */
567 #define WX_TXD_TUNNEL_LEN_SHIFT      21 /* Adv ctxt TUNNELLEN shift */
568 #define WX_TXD_TUNNEL_TYPE_SHIFT     11 /* Adv Tx Desc Tunnel Type shift */
569 #define WX_TXD_TUNNEL_UDP            FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
570 #define WX_TXD_TUNNEL_GRE            FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
571 
572 enum wx_tx_flags {
573 	/* cmd_type flags */
574 	WX_TX_FLAGS_HW_VLAN	= 0x01,
575 	WX_TX_FLAGS_TSO		= 0x02,
576 	WX_TX_FLAGS_TSTAMP	= 0x04,
577 
578 	/* olinfo flags */
579 	WX_TX_FLAGS_CC		= 0x08,
580 	WX_TX_FLAGS_IPV4	= 0x10,
581 	WX_TX_FLAGS_CSUM	= 0x20,
582 	WX_TX_FLAGS_OUTER_IPV4	= 0x100,
583 	WX_TX_FLAGS_LINKSEC	= 0x200,
584 	WX_TX_FLAGS_IPSEC	= 0x400,
585 
586 	/* software defined flags */
587 	WX_TX_FLAGS_SW_VLAN	= 0x40,
588 };
589 
590 /* VLAN info */
591 #define WX_TX_FLAGS_VLAN_MASK			GENMASK(31, 16)
592 #define WX_TX_FLAGS_VLAN_SHIFT			16
593 
594 /* wx_dec_ptype.mac: outer mac */
595 enum wx_dec_ptype_mac {
596 	WX_DEC_PTYPE_MAC_IP	= 0,
597 	WX_DEC_PTYPE_MAC_L2	= 2,
598 	WX_DEC_PTYPE_MAC_FCOE	= 3,
599 };
600 
601 /* wx_dec_ptype.[e]ip: outer&encaped ip */
602 #define WX_DEC_PTYPE_IP_FRAG	0x4
603 enum wx_dec_ptype_ip {
604 	WX_DEC_PTYPE_IP_NONE = 0,
605 	WX_DEC_PTYPE_IP_IPV4 = 1,
606 	WX_DEC_PTYPE_IP_IPV6 = 2,
607 	WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
608 	WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
609 };
610 
611 /* wx_dec_ptype.etype: encaped type */
612 enum wx_dec_ptype_etype {
613 	WX_DEC_PTYPE_ETYPE_NONE	= 0,
614 	WX_DEC_PTYPE_ETYPE_IPIP	= 1,	/* IP+IP */
615 	WX_DEC_PTYPE_ETYPE_IG	= 2,	/* IP+GRE */
616 	WX_DEC_PTYPE_ETYPE_IGM	= 3,	/* IP+GRE+MAC */
617 	WX_DEC_PTYPE_ETYPE_IGMV	= 4,	/* IP+GRE+MAC+VLAN */
618 };
619 
620 /* wx_dec_ptype.proto: payload proto */
621 enum wx_dec_ptype_prot {
622 	WX_DEC_PTYPE_PROT_NONE	= 0,
623 	WX_DEC_PTYPE_PROT_UDP	= 1,
624 	WX_DEC_PTYPE_PROT_TCP	= 2,
625 	WX_DEC_PTYPE_PROT_SCTP	= 3,
626 	WX_DEC_PTYPE_PROT_ICMP	= 4,
627 	WX_DEC_PTYPE_PROT_TS	= 5,	/* time sync */
628 };
629 
630 /* wx_dec_ptype.layer: payload layer */
631 enum wx_dec_ptype_layer {
632 	WX_DEC_PTYPE_LAYER_NONE = 0,
633 	WX_DEC_PTYPE_LAYER_PAY2 = 1,
634 	WX_DEC_PTYPE_LAYER_PAY3 = 2,
635 	WX_DEC_PTYPE_LAYER_PAY4 = 3,
636 };
637 
638 struct wx_dec_ptype {
639 	u32 known:1;
640 	u32 mac:2;	/* outer mac */
641 	u32 ip:3;	/* outer ip*/
642 	u32 etype:3;	/* encaped type */
643 	u32 eip:3;	/* encaped ip */
644 	u32 prot:4;	/* payload proto */
645 	u32 layer:3;	/* payload layer */
646 };
647 
648 /* macro to make the table lines short */
649 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
650 	      {1, \
651 	       WX_DEC_PTYPE_MAC_##mac,		/* mac */\
652 	       WX_DEC_PTYPE_IP_##ip,		/* ip */ \
653 	       WX_DEC_PTYPE_ETYPE_##etype,	/* etype */\
654 	       WX_DEC_PTYPE_IP_##eip,		/* eip */\
655 	       WX_DEC_PTYPE_PROT_##proto,	/* proto */\
656 	       WX_DEC_PTYPE_LAYER_##layer	/* layer */}
657 
658 /* Host Interface Command Structures */
659 struct wx_hic_hdr {
660 	u8 cmd;
661 	u8 buf_len;
662 	union {
663 		u8 cmd_resv;
664 		u8 ret_status;
665 	} cmd_or_resp;
666 	u8 checksum;
667 };
668 
669 struct wx_hic_hdr2_req {
670 	u8 cmd;
671 	u8 buf_lenh;
672 	u8 buf_lenl;
673 	u8 checksum;
674 };
675 
676 struct wx_hic_hdr2_rsp {
677 	u8 cmd;
678 	u8 buf_lenl;
679 	u8 buf_lenh_status;     /* 7-5: high bits of buf_len, 4-0: status */
680 	u8 checksum;
681 };
682 
683 union wx_hic_hdr2 {
684 	struct wx_hic_hdr2_req req;
685 	struct wx_hic_hdr2_rsp rsp;
686 };
687 
688 /* These need to be dword aligned */
689 struct wx_hic_read_shadow_ram {
690 	union wx_hic_hdr2 hdr;
691 	u32 address;
692 	u16 length;
693 	u16 pad2;
694 	u16 data;
695 	u16 pad3;
696 };
697 
698 struct wx_hic_reset {
699 	struct wx_hic_hdr hdr;
700 	u16 lan_id;
701 	u16 reset_type;
702 };
703 
704 /* Bus parameters */
705 struct wx_bus_info {
706 	u8 func;
707 	u16 device;
708 };
709 
710 struct wx_thermal_sensor_data {
711 	s16 temp;
712 	s16 alarm_thresh;
713 	s16 dalarm_thresh;
714 };
715 
716 enum wx_mac_type {
717 	wx_mac_unknown = 0,
718 	wx_mac_sp,
719 	wx_mac_em
720 };
721 
722 enum sp_media_type {
723 	sp_media_unknown = 0,
724 	sp_media_fiber,
725 	sp_media_copper,
726 	sp_media_backplane
727 };
728 
729 enum em_mac_type {
730 	em_mac_type_unknown = 0,
731 	em_mac_type_mdi,
732 	em_mac_type_rgmii
733 };
734 
735 struct wx_mac_info {
736 	enum wx_mac_type type;
737 	bool set_lben;
738 	u8 addr[ETH_ALEN];
739 	u8 perm_addr[ETH_ALEN];
740 	u32 mta_shadow[128];
741 	s32 mc_filter_type;
742 	u32 mcft_size;
743 	u32 vft_shadow[128];
744 	u32 vft_size;
745 	u32 num_rar_entries;
746 	u32 rx_pb_size;
747 	u32 tx_pb_size;
748 	u32 max_tx_queues;
749 	u32 max_rx_queues;
750 
751 	u16 max_msix_vectors;
752 	struct wx_thermal_sensor_data sensor;
753 };
754 
755 enum wx_eeprom_type {
756 	wx_eeprom_uninitialized = 0,
757 	wx_eeprom_spi,
758 	wx_flash,
759 	wx_eeprom_none /* No NVM support */
760 };
761 
762 struct wx_eeprom_info {
763 	enum wx_eeprom_type type;
764 	u32 semaphore_delay;
765 	u16 word_size;
766 	u16 sw_region_offset;
767 };
768 
769 struct wx_addr_filter_info {
770 	u32 num_mc_addrs;
771 	u32 mta_in_use;
772 	bool user_set_promisc;
773 };
774 
775 struct wx_mac_addr {
776 	u8 addr[ETH_ALEN];
777 	u16 state; /* bitmask */
778 	u64 pools;
779 };
780 
781 enum wx_reset_type {
782 	WX_LAN_RESET = 0,
783 	WX_SW_RESET,
784 	WX_GLOBAL_RESET
785 };
786 
787 struct wx_cb {
788 	dma_addr_t dma;
789 	u16     append_cnt;      /* number of skb's appended */
790 	bool    page_released;
791 	bool    dma_released;
792 };
793 
794 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
795 
796 /* Transmit Descriptor */
797 union wx_tx_desc {
798 	struct {
799 		__le64 buffer_addr; /* Address of descriptor's data buf */
800 		__le32 cmd_type_len;
801 		__le32 olinfo_status;
802 	} read;
803 	struct {
804 		__le64 rsvd; /* Reserved */
805 		__le32 nxtseq_seed;
806 		__le32 status;
807 	} wb;
808 };
809 
810 /* Receive Descriptor */
811 union wx_rx_desc {
812 	struct {
813 		__le64 pkt_addr; /* Packet buffer address */
814 		__le64 hdr_addr; /* Header buffer address */
815 	} read;
816 	struct {
817 		struct {
818 			union {
819 				__le32 data;
820 				struct {
821 					__le16 pkt_info; /* RSS, Pkt type */
822 					__le16 hdr_info; /* Splithdr, hdrlen */
823 				} hs_rss;
824 			} lo_dword;
825 			union {
826 				__le32 rss; /* RSS Hash */
827 				struct {
828 					__le16 ip_id; /* IP id */
829 					__le16 csum; /* Packet Checksum */
830 				} csum_ip;
831 			} hi_dword;
832 		} lower;
833 		struct {
834 			__le32 status_error; /* ext status/error */
835 			__le16 length; /* Packet length */
836 			__le16 vlan; /* VLAN tag */
837 		} upper;
838 	} wb;  /* writeback */
839 };
840 
841 struct wx_tx_context_desc {
842 	__le32 vlan_macip_lens;
843 	__le32 seqnum_seed;
844 	__le32 type_tucmd_mlhl;
845 	__le32 mss_l4len_idx;
846 };
847 
848 /* if _flag is in _input, return _result */
849 #define WX_SET_FLAG(_input, _flag, _result) \
850 	(((_flag) <= (_result)) ? \
851 	 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
852 	 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
853 
854 #define WX_RX_DESC(R, i)     \
855 	(&(((union wx_rx_desc *)((R)->desc))[i]))
856 #define WX_TX_DESC(R, i)     \
857 	(&(((union wx_tx_desc *)((R)->desc))[i]))
858 #define WX_TX_CTXTDESC(R, i) \
859 	(&(((struct wx_tx_context_desc *)((R)->desc))[i]))
860 
861 /* wrapper around a pointer to a socket buffer,
862  * so a DMA handle can be stored along with the buffer
863  */
864 struct wx_tx_buffer {
865 	union wx_tx_desc *next_to_watch;
866 	struct sk_buff *skb;
867 	unsigned int bytecount;
868 	unsigned short gso_segs;
869 	DEFINE_DMA_UNMAP_ADDR(dma);
870 	DEFINE_DMA_UNMAP_LEN(len);
871 	__be16 protocol;
872 	u32 tx_flags;
873 };
874 
875 struct wx_rx_buffer {
876 	struct sk_buff *skb;
877 	dma_addr_t dma;
878 	dma_addr_t page_dma;
879 	struct page *page;
880 	unsigned int page_offset;
881 };
882 
883 struct wx_queue_stats {
884 	u64 packets;
885 	u64 bytes;
886 };
887 
888 struct wx_tx_queue_stats {
889 	u64 restart_queue;
890 	u64 tx_busy;
891 };
892 
893 struct wx_rx_queue_stats {
894 	u64 non_eop_descs;
895 	u64 csum_good_cnt;
896 	u64 csum_err;
897 	u64 alloc_rx_buff_failed;
898 };
899 
900 /* iterator for handling rings in ring container */
901 #define wx_for_each_ring(posm, headm) \
902 	for (posm = (headm).ring; posm; posm = posm->next)
903 
904 struct wx_ring_container {
905 	struct wx_ring *ring;           /* pointer to linked list of rings */
906 	unsigned int total_bytes;       /* total bytes processed this int */
907 	unsigned int total_packets;     /* total packets processed this int */
908 	u8 count;                       /* total number of rings in vector */
909 	u8 itr;                         /* current ITR setting for ring */
910 };
911 struct wx_ring {
912 	struct wx_ring *next;           /* pointer to next ring in q_vector */
913 	struct wx_q_vector *q_vector;   /* backpointer to host q_vector */
914 	struct net_device *netdev;      /* netdev ring belongs to */
915 	struct device *dev;             /* device for DMA mapping */
916 	struct page_pool *page_pool;
917 	void *desc;                     /* descriptor ring memory */
918 	union {
919 		struct wx_tx_buffer *tx_buffer_info;
920 		struct wx_rx_buffer *rx_buffer_info;
921 	};
922 	u8 __iomem *tail;
923 	dma_addr_t dma;                 /* phys. address of descriptor ring */
924 	unsigned int size;              /* length in bytes */
925 
926 	u16 count;                      /* amount of descriptors */
927 
928 	u8 queue_index; /* needed for multiqueue queue management */
929 	u8 reg_idx;                     /* holds the special value that gets
930 					 * the hardware register offset
931 					 * associated with this ring, which is
932 					 * different for DCB and RSS modes
933 					 */
934 	u16 next_to_use;
935 	u16 next_to_clean;
936 	union {
937 		u16 next_to_alloc;
938 		struct {
939 			u8 atr_sample_rate;
940 			u8 atr_count;
941 		};
942 	};
943 
944 	struct wx_queue_stats stats;
945 	struct u64_stats_sync syncp;
946 	union {
947 		struct wx_tx_queue_stats tx_stats;
948 		struct wx_rx_queue_stats rx_stats;
949 	};
950 } ____cacheline_internodealigned_in_smp;
951 
952 struct wx_q_vector {
953 	struct wx *wx;
954 	int cpu;        /* CPU for DCA */
955 	int numa_node;
956 	u16 v_idx;      /* index of q_vector within array, also used for
957 			 * finding the bit in EICR and friends that
958 			 * represents the vector for this ring
959 			 */
960 	u16 itr;        /* Interrupt throttle rate written to EITR */
961 	struct wx_ring_container rx, tx;
962 	struct napi_struct napi;
963 	struct rcu_head rcu;    /* to avoid race with update stats on free */
964 
965 	char name[IFNAMSIZ + 17];
966 
967 	/* for dynamic allocation of rings associated with this q_vector */
968 	struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
969 };
970 
971 struct wx_ring_feature {
972 	u16 limit;      /* upper limit on feature indices */
973 	u16 indices;    /* current value of indices */
974 	u16 mask;       /* Mask used for feature to ring mapping */
975 	u16 offset;     /* offset to start of feature */
976 };
977 
978 enum wx_ring_f_enum {
979 	RING_F_NONE = 0,
980 	RING_F_RSS,
981 	RING_F_FDIR,
982 	RING_F_ARRAY_SIZE  /* must be last in enum set */
983 };
984 
985 enum wx_isb_idx {
986 	WX_ISB_HEADER,
987 	WX_ISB_MISC,
988 	WX_ISB_VEC0,
989 	WX_ISB_VEC1,
990 	WX_ISB_MAX
991 };
992 
993 struct wx_fc_info {
994 	u32 high_water; /* Flow Ctrl High-water */
995 	u32 low_water; /* Flow Ctrl Low-water */
996 };
997 
998 /* Statistics counters collected by the MAC */
999 struct wx_hw_stats {
1000 	u64 gprc;
1001 	u64 gptc;
1002 	u64 gorc;
1003 	u64 gotc;
1004 	u64 tpr;
1005 	u64 tpt;
1006 	u64 bprc;
1007 	u64 bptc;
1008 	u64 mprc;
1009 	u64 mptc;
1010 	u64 roc;
1011 	u64 ruc;
1012 	u64 lxonoffrxc;
1013 	u64 lxontxc;
1014 	u64 lxofftxc;
1015 	u64 o2bgptc;
1016 	u64 b2ospc;
1017 	u64 o2bspc;
1018 	u64 b2ogprc;
1019 	u64 rdmdrop;
1020 	u64 crcerrs;
1021 	u64 rlec;
1022 	u64 qmprc;
1023 	u64 fdirmatch;
1024 	u64 fdirmiss;
1025 };
1026 
1027 enum wx_state {
1028 	WX_STATE_RESETTING,
1029 	WX_STATE_NBITS,		/* must be last */
1030 };
1031 
1032 enum wx_pf_flags {
1033 	WX_FLAG_FDIR_CAPABLE,
1034 	WX_FLAG_FDIR_HASH,
1035 	WX_FLAG_FDIR_PERFECT,
1036 	WX_PF_FLAGS_NBITS               /* must be last */
1037 };
1038 
1039 struct wx {
1040 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1041 	DECLARE_BITMAP(state, WX_STATE_NBITS);
1042 	DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS);
1043 
1044 	void *priv;
1045 	u8 __iomem *hw_addr;
1046 	struct pci_dev *pdev;
1047 	struct net_device *netdev;
1048 	struct wx_bus_info bus;
1049 	struct wx_mac_info mac;
1050 	enum em_mac_type mac_type;
1051 	enum sp_media_type media_type;
1052 	struct wx_eeprom_info eeprom;
1053 	struct wx_addr_filter_info addr_ctrl;
1054 	struct wx_fc_info fc;
1055 	struct wx_mac_addr *mac_table;
1056 	u16 device_id;
1057 	u16 vendor_id;
1058 	u16 subsystem_device_id;
1059 	u16 subsystem_vendor_id;
1060 	u8 revision_id;
1061 	u16 oem_ssid;
1062 	u16 oem_svid;
1063 	u16 msg_enable;
1064 	bool adapter_stopped;
1065 	u16 tpid[8];
1066 	char eeprom_id[32];
1067 	char *driver_name;
1068 	enum wx_reset_type reset_type;
1069 
1070 	/* PHY stuff */
1071 	unsigned int link;
1072 	int speed;
1073 	int duplex;
1074 	struct phy_device *phydev;
1075 	struct phylink *phylink;
1076 	struct phylink_config phylink_config;
1077 
1078 	bool wol_hw_supported;
1079 	bool ncsi_enabled;
1080 	bool gpio_ctrl;
1081 	raw_spinlock_t gpio_lock;
1082 
1083 	/* Tx fast path data */
1084 	int num_tx_queues;
1085 	u16 tx_itr_setting;
1086 	u16 tx_work_limit;
1087 
1088 	/* Rx fast path data */
1089 	int num_rx_queues;
1090 	u16 rx_itr_setting;
1091 	u16 rx_work_limit;
1092 
1093 	int num_q_vectors;      /* current number of q_vectors for device */
1094 	int max_q_vectors;      /* upper limit of q_vectors for device */
1095 
1096 	u32 tx_ring_count;
1097 	u32 rx_ring_count;
1098 
1099 	struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
1100 	struct wx_ring *rx_ring[64];
1101 	struct wx_q_vector *q_vector[64];
1102 
1103 	unsigned int queues_per_pool;
1104 	struct msix_entry *msix_q_entries;
1105 	struct msix_entry *msix_entry;
1106 	struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];
1107 
1108 	/* misc interrupt status block */
1109 	dma_addr_t isb_dma;
1110 	u32 *isb_mem;
1111 	u32 isb_tag[WX_ISB_MAX];
1112 	bool misc_irq_domain;
1113 
1114 #define WX_MAX_RETA_ENTRIES 128
1115 #define WX_RSS_INDIR_TBL_MAX 64
1116 	u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
1117 	bool rss_enabled;
1118 #define WX_RSS_KEY_SIZE     40  /* size of RSS Hash Key in bytes */
1119 	u32 *rss_key;
1120 	u32 wol;
1121 
1122 	u16 bd_number;
1123 
1124 	struct wx_hw_stats stats;
1125 	u64 tx_busy;
1126 	u64 non_eop_descs;
1127 	u64 restart_queue;
1128 	u64 hw_csum_rx_good;
1129 	u64 hw_csum_rx_error;
1130 	u64 alloc_rx_buff_failed;
1131 
1132 	u32 atr_sample_rate;
1133 	void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype);
1134 	void (*configure_fdir)(struct wx *wx);
1135 	void (*do_reset)(struct net_device *netdev);
1136 };
1137 
1138 #define WX_INTR_ALL (~0ULL)
1139 #define WX_INTR_Q(i) BIT((i) + 1)
1140 
1141 /* register operations */
1142 #define wr32(a, reg, value)	writel((value), ((a)->hw_addr + (reg)))
1143 #define rd32(a, reg)		readl((a)->hw_addr + (reg))
1144 #define rd32a(a, reg, offset) ( \
1145 	rd32((a), (reg) + ((offset) << 2)))
1146 #define wr32a(a, reg, off, val) \
1147 	wr32((a), (reg) + ((off) << 2), (val))
1148 
1149 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)1150 rd32m(struct wx *wx, u32 reg, u32 mask)
1151 {
1152 	u32 val;
1153 
1154 	val = rd32(wx, reg);
1155 	return val & mask;
1156 }
1157 
1158 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)1159 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
1160 {
1161 	u32 val;
1162 
1163 	val = rd32(wx, reg);
1164 	val = ((val & ~mask) | (field & mask));
1165 
1166 	wr32(wx, reg, val);
1167 }
1168 
1169 static inline u64
rd64(struct wx * wx,u32 reg)1170 rd64(struct wx *wx, u32 reg)
1171 {
1172 	u64 lsb, msb;
1173 
1174 	lsb = rd32(wx, reg);
1175 	msb = rd32(wx, reg + 4);
1176 
1177 	return (lsb | msb << 32);
1178 }
1179 
1180 /* On some domestic CPU platforms, sometimes IO is not synchronized with
1181  * flushing memory, here use readl() to flush PCI read and write.
1182  */
1183 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
1184 
1185 #define wx_err(wx, fmt, arg...) \
1186 	dev_err(&(wx)->pdev->dev, fmt, ##arg)
1187 
1188 #define wx_dbg(wx, fmt, arg...) \
1189 	dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
1190 
phylink_to_wx(struct phylink_config * config)1191 static inline struct wx *phylink_to_wx(struct phylink_config *config)
1192 {
1193 	return container_of(config, struct wx, phylink_config);
1194 }
1195 
wx_set_state_reset(struct wx * wx)1196 static inline int wx_set_state_reset(struct wx *wx)
1197 {
1198 	u8 timeout = 50;
1199 
1200 	while (test_and_set_bit(WX_STATE_RESETTING, wx->state)) {
1201 		timeout--;
1202 		if (!timeout)
1203 			return -EBUSY;
1204 
1205 		usleep_range(1000, 2000);
1206 	}
1207 
1208 	return 0;
1209 }
1210 
1211 #endif /* _WX_TYPE_H_ */
1212