1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6
7 #include <linux/ptp_clock_kernel.h>
8 #include <linux/timecounter.h>
9 #include <linux/bitfield.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/phylink.h>
13 #include <net/ip.h>
14
15 #define WX_NCSI_SUP 0x8000
16 #define WX_NCSI_MASK 0x8000
17 #define WX_WOL_SUP 0x4000
18 #define WX_WOL_MASK 0x4000
19
20 /* MSI-X capability fields masks */
21 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
22 #define WX_PCI_LINK_STATUS 0xB2
23 #define WX_MAX_PF_MACVLANS 15
24 #define WX_MAX_VF_MC_ENTRIES 30
25
26 /**************** Global Registers ****************************/
27 #define WX_VF_REG_OFFSET(_v) FIELD_GET(GENMASK(15, 5), (_v))
28 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))
29
30 /* chip control Registers */
31 #define WX_MIS_PWR 0x10000
32 #define WX_MIS_RST 0x1000C
33 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
34 #define WX_MIS_RST_SW_RST BIT(0)
35 #define WX_MIS_ST 0x10028
36 #define WX_MIS_ST_MNG_INIT_DN BIT(0)
37 #define WX_MIS_SWSM 0x1002C
38 #define WX_MIS_SWSM_SMBI BIT(0)
39 #define WX_MIS_RST_ST 0x10030
40 #define WX_MIS_RST_ST_RST_INI_SHIFT 8
41 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
42
43 /* FMGR Registers */
44 #define WX_SPI_CMD 0x10104
45 #define WX_SPI_CMD_READ_DWORD 0x1
46 #define WX_SPI_CLK_DIV 0x3
47 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
48 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
49 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
50 #define WX_SPI_DATA 0x10108
51 #define WX_SPI_DATA_BYPASS BIT(31)
52 #define WX_SPI_DATA_OP_DONE BIT(0)
53 #define WX_SPI_STATUS 0x1010C
54 #define WX_SPI_STATUS_OPDONE BIT(0)
55 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
56 #define WX_SPI_ILDR_STATUS 0x10120
57
58 /* Sensors for PVT(Process Voltage Temperature) */
59 #define WX_TS_EN 0x10304
60 #define WX_TS_EN_ENA BIT(0)
61 #define WX_TS_ALARM_THRE 0x1030C
62 #define WX_TS_DALARM_THRE 0x10310
63 #define WX_TS_INT_EN 0x10314
64 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
65 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
66 #define WX_TS_ALARM_ST 0x10318
67 #define WX_TS_ALARM_ST_DALARM BIT(1)
68 #define WX_TS_ALARM_ST_ALARM BIT(0)
69
70 /* statistic */
71 #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C
72 #define WX_TX_BC_FRAMES_GOOD_L 0x11824
73 #define WX_TX_MC_FRAMES_GOOD_L 0x1182C
74 #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900
75 #define WX_RX_BC_FRAMES_GOOD_L 0x11918
76 #define WX_RX_MC_FRAMES_GOOD_L 0x11920
77 #define WX_RX_CRC_ERROR_FRAMES_L 0x11928
78 #define WX_RX_LEN_ERROR_FRAMES_L 0x11978
79 #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938
80 #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C
81 #define WX_MAC_LXONOFFRXC 0x11E0C
82
83 /*********************** Receive DMA registers **************************/
84 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4))
85 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4))
86 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4))
87 #define WX_RDM_DRP_PKT 0x12500
88 #define WX_RDM_PKT_CNT 0x12504
89 #define WX_RDM_BYTE_CNT_LSB 0x12508
90 #define WX_RDM_BMC2OS_CNT 0x12510
91
92 /************************* Port Registers ************************************/
93 /* port cfg Registers */
94 #define WX_CFG_PORT_CTL 0x14400
95 #define WX_CFG_PORT_CTL_PFRSTD BIT(14)
96 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
97 #define WX_CFG_PORT_CTL_QINQ BIT(2)
98 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
99 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
100 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
101
102 #define WX_CFG_PORT_CTL_NUM_VT_NONE 0
103 #define WX_CFG_PORT_CTL_NUM_VT_8 FIELD_PREP(GENMASK(13, 12), 1)
104 #define WX_CFG_PORT_CTL_NUM_VT_32 FIELD_PREP(GENMASK(13, 12), 2)
105 #define WX_CFG_PORT_CTL_NUM_VT_64 FIELD_PREP(GENMASK(13, 12), 3)
106
107 /* GPIO Registers */
108 #define WX_GPIO_DR 0x14800
109 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
110 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
111 #define WX_GPIO_DDR 0x14804
112 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
113 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
114 #define WX_GPIO_CTL 0x14808
115 #define WX_GPIO_INTEN 0x14830
116 #define WX_GPIO_INTEN_0 BIT(0)
117 #define WX_GPIO_INTEN_1 BIT(1)
118 #define WX_GPIO_INTMASK 0x14834
119 #define WX_GPIO_INTTYPE_LEVEL 0x14838
120 #define WX_GPIO_POLARITY 0x1483C
121 #define WX_GPIO_INTSTATUS 0x14844
122 #define WX_GPIO_EOI 0x1484C
123 #define WX_GPIO_EXT 0x14850
124
125 /*********************** Transmit DMA registers **************************/
126 /* transmit global control */
127 #define WX_TDM_CTL 0x18000
128 #define WX_TDM_VF_TE(_i) (0x18004 + ((_i) * 4))
129 #define WX_TDM_MAC_AS(_i) (0x18060 + ((_i) * 4))
130 #define WX_TDM_VLAN_AS(_i) (0x18070 + ((_i) * 4))
131 #define WX_TDM_VFTE_CLR(_i) (0x180A0 + ((_i) * 4))
132
133 /* TDM CTL BIT */
134 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
135 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
136 #define WX_TDM_RP_IDX 0x1820C
137 #define WX_TDM_PKT_CNT 0x18308
138 #define WX_TDM_BYTE_CNT_LSB 0x1830C
139 #define WX_TDM_OS2BMC_CNT 0x18314
140 #define WX_TDM_RP_RATE 0x18404
141
142 /***************************** RDB registers *********************************/
143 /* receive packet buffer */
144 #define WX_RDB_PB_CTL 0x19000
145 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
146 #define WX_RDB_PB_CTL_DISABLED BIT(0)
147 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
148 #define WX_RDB_PB_SZ_SHIFT 10
149 /* statistic */
150 #define WX_RDB_PFCMACDAL 0x19210
151 #define WX_RDB_PFCMACDAH 0x19214
152 #define WX_RDB_LXOFFTXC 0x19218
153 #define WX_RDB_LXONTXC 0x1921C
154 /* Flow Control Registers */
155 #define WX_RDB_RFCV 0x19200
156 #define WX_RDB_RFCL 0x19220
157 #define WX_RDB_RFCL_XONE BIT(31)
158 #define WX_RDB_RFCH 0x19260
159 #define WX_RDB_RFCH_XOFFE BIT(31)
160 #define WX_RDB_RFCRT 0x192A0
161 #define WX_RDB_RFCC 0x192A4
162 #define WX_RDB_RFCC_RFCE_802_3X BIT(3)
163 /* ring assignment */
164 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
165 #define WX_RDB_PL_CFG_L4HDR BIT(1)
166 #define WX_RDB_PL_CFG_L3HDR BIT(2)
167 #define WX_RDB_PL_CFG_L2HDR BIT(3)
168 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
169 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
170 #define WX_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4))
171 #define WX_RDB_RSSRK(_i) (0x19480 + ((_i) * 4))
172 #define WX_RDB_RA_CTL 0x194F4
173 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
174 #define WX_RDB_RA_CTL_RSS_IPV4_TCP BIT(16)
175 #define WX_RDB_RA_CTL_RSS_IPV4 BIT(17)
176 #define WX_RDB_RA_CTL_RSS_IPV6 BIT(20)
177 #define WX_RDB_RA_CTL_RSS_IPV6_TCP BIT(21)
178 #define WX_RDB_RA_CTL_RSS_IPV4_UDP BIT(22)
179 #define WX_RDB_RA_CTL_RSS_IPV6_UDP BIT(23)
180 #define WX_RDB_FDIR_MATCH 0x19558
181 #define WX_RDB_FDIR_MISS 0x1955C
182
183 /******************************* PSR Registers *******************************/
184 /* psr control */
185 #define WX_PSR_CTL 0x15000
186 #define WX_PSR_VM_CTL 0x151B0
187 /* Header split receive */
188 #define WX_PSR_CTL_SW_EN BIT(18)
189 #define WX_PSR_CTL_RSC_ACK BIT(17)
190 #define WX_PSR_CTL_RSC_DIS BIT(16)
191 #define WX_PSR_CTL_PCSD BIT(13)
192 #define WX_PSR_CTL_IPPCSE BIT(12)
193 #define WX_PSR_CTL_BAM BIT(10)
194 #define WX_PSR_CTL_UPE BIT(9)
195 #define WX_PSR_CTL_MPE BIT(8)
196 #define WX_PSR_CTL_MFE BIT(7)
197 #define WX_PSR_CTL_MO_SHIFT 5
198 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
199 #define WX_PSR_CTL_TPE BIT(4)
200 #define WX_PSR_MAX_SZ 0x15020
201 #define WX_PSR_VLAN_CTL 0x15088
202 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
203 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
204 /* EType Queue Filter */
205 #define WX_PSR_ETYPE_SWC(_i) (0x15128 + ((_i) * 4))
206 #define WX_PSR_ETYPE_SWC_FILTER_1588 3
207 #define WX_PSR_ETYPE_SWC_FILTER_EN BIT(31)
208 #define WX_PSR_ETYPE_SWC_1588 BIT(30)
209 /* 1588 */
210 #define WX_PSR_1588_MSG 0x15120
211 #define WX_PSR_1588_MSG_V1_SYNC FIELD_PREP(GENMASK(7, 0), 0)
212 #define WX_PSR_1588_MSG_V1_DELAY_REQ FIELD_PREP(GENMASK(7, 0), 1)
213 #define WX_PSR_1588_STMPL 0x151E8
214 #define WX_PSR_1588_STMPH 0x151A4
215 #define WX_PSR_1588_CTL 0x15188
216 #define WX_PSR_1588_CTL_ENABLED BIT(4)
217 #define WX_PSR_1588_CTL_TYPE_MASK GENMASK(3, 1)
218 #define WX_PSR_1588_CTL_TYPE_L4_V1 FIELD_PREP(GENMASK(3, 1), 1)
219 #define WX_PSR_1588_CTL_TYPE_EVENT_V2 FIELD_PREP(GENMASK(3, 1), 5)
220 #define WX_PSR_1588_CTL_VALID BIT(0)
221 /* mcasst/ucast overflow tbl */
222 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
223 #define WX_PSR_MC_TBL_REG(_i) FIELD_GET(GENMASK(11, 5), (_i))
224 #define WX_PSR_MC_TBL_BIT(_i) FIELD_GET(GENMASK(4, 0), (_i))
225 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
226 #define WX_PSR_VM_CTL_REPLEN BIT(30) /* replication enabled */
227 #define WX_PSR_VM_CTL_POOL_MASK GENMASK(12, 7)
228
229 /* VM L2 contorl */
230 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
231 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
232 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
233 #define WX_PSR_VM_L2CTL_VPE BIT(7) /* vlan promiscuous mode */
234 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
235 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
236 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
237 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
238 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
239
240 /* Management */
241 #define WX_PSR_MNG_FLEX_SEL 0x1582C
242 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
243 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
244 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
245 #define WX_PSR_LAN_FLEX_SEL 0x15B8C
246 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
247 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
248 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
249
250 #define WX_PSR_WKUP_CTL 0x15B80
251 /* Wake Up Filter Control Bit */
252 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
253
254 /* vlan tbl */
255 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
256
257 /* mac switcher */
258 #define WX_PSR_MAC_SWC_AD_L 0x16200
259 #define WX_PSR_MAC_SWC_AD_H 0x16204
260 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
261 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
262 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
263 #define WX_PSR_MAC_SWC_VM_L 0x16208
264 #define WX_PSR_MAC_SWC_VM_H 0x1620C
265 #define WX_PSR_MAC_SWC_IDX 0x16210
266 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
267
268 /* vlan switch */
269 #define WX_PSR_VLAN_SWC 0x16220
270 #define WX_PSR_VLAN_SWC_VM_L 0x16224
271 #define WX_PSR_VLAN_SWC_VM_H 0x16228
272 #define WX_PSR_VLAN_SWC_VM(_i) (0x16224 + ((_i) * 4))
273 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
274 /* VLAN pool filtering masks */
275 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
276 #define WX_PSR_VLAN_SWC_ENTRIES 64
277 #define WX_PSR_VLAN_SWC_VLANID_MASK GENMASK(11, 0)
278
279 /********************************* RSEC **************************************/
280 /* general rsec */
281 #define WX_RSC_CTL 0x17000
282 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
283 #define WX_RSC_CTL_CRC_STRIP BIT(2)
284 #define WX_RSC_CTL_RX_DIS BIT(1)
285 #define WX_RSC_ST 0x17004
286 #define WX_RSC_ST_RSEC_RDY BIT(0)
287
288 /*********************** Transmit DMA registers **************************/
289 /* transmit global control */
290 #define WX_TDM_ETYPE_AS(_i) (0x18058 + ((_i) * 4))
291 #define WX_TDM_VLAN_INS(_i) (0x18100 + ((_i) * 4))
292 /* Per VF Port VLAN insertion rules */
293 #define WX_TDM_VLAN_INS_VLANA_DEFAULT BIT(30) /* Always use default VLAN*/
294
295 /****************************** TDB ******************************************/
296 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
297 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
298
299 /****************************** TSEC *****************************************/
300 /* Security Control Registers */
301 #define WX_TSC_CTL 0x1D000
302 #define WX_TSC_CTL_TX_DIS BIT(1)
303 #define WX_TSC_CTL_TSEC_DIS BIT(0)
304 #define WX_TSC_ST 0x1D004
305 #define WX_TSC_ST_SECTX_RDY BIT(0)
306 #define WX_TSC_BUF_AE 0x1D00C
307 #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
308 /* 1588 */
309 #define WX_TSC_1588_CTL 0x11F00
310 #define WX_TSC_1588_CTL_ENABLED BIT(4)
311 #define WX_TSC_1588_CTL_VALID BIT(0)
312 #define WX_TSC_1588_STMPL 0x11F04
313 #define WX_TSC_1588_STMPH 0x11F08
314 #define WX_TSC_1588_SYSTIML 0x11F0C
315 #define WX_TSC_1588_SYSTIMH 0x11F10
316 #define WX_TSC_1588_INC 0x11F14
317 #define WX_TSC_1588_INT_ST 0x11F20
318 #define WX_TSC_1588_INT_ST_TT1 BIT(5)
319 #define WX_TSC_1588_INT_EN 0x11F24
320 #define WX_TSC_1588_INT_EN_TT1 BIT(5)
321 #define WX_TSC_1588_AUX_CTL 0x11F28
322 #define WX_TSC_1588_AUX_CTL_EN_TS0 BIT(8)
323 #define WX_TSC_1588_AUX_CTL_EN_TT1 BIT(2)
324 #define WX_TSC_1588_AUX_CTL_PLSG BIT(1)
325 #define WX_TSC_1588_AUX_CTL_EN_TT0 BIT(0)
326 #define WX_TSC_1588_TRGT_L(i) (0x11F2C + ((i) * 8)) /* [0,1] */
327 #define WX_TSC_1588_TRGT_H(i) (0x11F30 + ((i) * 8)) /* [0,1] */
328 #define WX_TSC_1588_SDP(i) (0x11F5C + ((i) * 4)) /* [0,3] */
329 #define WX_TSC_1588_SDP_OUT_LEVEL_H FIELD_PREP(BIT(4), 0)
330 #define WX_TSC_1588_SDP_OUT_LEVEL_L FIELD_PREP(BIT(4), 1)
331 #define WX_TSC_1588_SDP_FUN_SEL_MASK GENMASK(2, 0)
332 #define WX_TSC_1588_SDP_FUN_SEL_TT0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 1)
333 #define WX_TSC_1588_SDP_FUN_SEL_TS0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 5)
334
335 /************************************** MNG ********************************/
336 #define WX_MNG_SWFW_SYNC 0x1E008
337 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
338 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
339 #define WX_MNG_MBOX 0x1E100
340 #define WX_MNG_MBOX_CTL 0x1E044
341 #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
342 #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
343 #define WX_MNG_BMC2OS_CNT 0x1E090
344 #define WX_MNG_OS2BMC_CNT 0x1E094
345 #define WX_SW2FW_MBOX_CMD 0x1E0A0
346 #define WX_SW2FW_MBOX_CMD_VLD BIT(31)
347 #define WX_SW2FW_MBOX 0x1E200
348 #define WX_FW2SW_MBOX 0x1E300
349
350 /************************************* ETH MAC *****************************/
351 #define WX_MAC_TX_CFG 0x11000
352 #define WX_MAC_TX_CFG_TE BIT(0)
353 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
354 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
355 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
356 #define WX_MAC_RX_CFG 0x11004
357 #define WX_MAC_RX_CFG_RE BIT(0)
358 #define WX_MAC_RX_CFG_JE BIT(8)
359 #define WX_MAC_PKT_FLT 0x11008
360 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
361 #define WX_MAC_WDG_TIMEOUT 0x1100C
362 #define WX_MAC_RX_FLOW_CTRL 0x11090
363 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
364
365 #define WX_MAC_WDG_TIMEOUT_WTO_MASK GENMASK(3, 0)
366 #define WX_MAC_WDG_TIMEOUT_WTO_DELTA 2
367 /* MDIO Registers */
368 #define WX_MSCA 0x11200
369 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
370 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
371 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
372 #define WX_MSCC 0x11204
373 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
374
375 enum WX_MSCA_CMD_value {
376 WX_MSCA_CMD_RSV = 0,
377 WX_MSCA_CMD_WRITE,
378 WX_MSCA_CMD_POST_READ,
379 WX_MSCA_CMD_READ,
380 };
381
382 #define WX_MSCC_SADDR BIT(18)
383 #define WX_MSCC_BUSY BIT(22)
384 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
385 #define WX_MDIO_CLAUSE_SELECT 0x11220
386 #define WX_MMC_CONTROL 0x11800
387 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
388
389 /********************************* BAR registers ***************************/
390 /* Interrupt Registers */
391 #define WX_BME_CTL 0x12020
392 #define WX_PX_MISC_IC 0x100
393 #define WX_PX_MISC_ICS 0x104
394 #define WX_PX_MISC_IEN 0x108
395 #define WX_PX_INTA 0x110
396 #define WX_PX_GPIE 0x118
397 #define WX_PX_GPIE_MODEL BIT(0)
398 #define WX_PX_IC(_i) (0x120 + (_i) * 4)
399 #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
400 #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
401 #define WX_PX_ISB_ADDR_L 0x160
402 #define WX_PX_ISB_ADDR_H 0x164
403 #define WX_PX_TRANSACTION_PENDING 0x168
404 #define WX_PX_ITRSEL 0x180
405 #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
406 #define WX_PX_ITR_CNT_WDIS BIT(31)
407 #define WX_PX_MISC_IVAR 0x4FC
408 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
409
410 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
411 #define WX_7K_ITR 595
412 #define WX_12K_ITR 336
413 #define WX_20K_ITR 200
414 #define WX_SP_MAX_EITR 0x00000FF8U
415 #define WX_AML_MAX_EITR 0x00000FFFU
416 #define WX_EM_MAX_EITR 0x00007FFCU
417
418 /* transmit DMA Registers */
419 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
420 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
421 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
422 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
423 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
424 /* Transmit Config masks */
425 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
426 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
427 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
428 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
429 #define WX_PX_TR_CFG_THRE_SHIFT 8
430
431 /* Receive DMA Registers */
432 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
433 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
434 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
435 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
436 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
437 #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40))
438 /* PX_RR_CFG bit definitions */
439 #define WX_PX_RR_CFG_VLAN BIT(31)
440 #define WX_PX_RR_CFG_DROP_EN BIT(30)
441 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
442 #define WX_PX_RR_CFG_RR_THER_SHIFT 16
443 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
444 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
445 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
446 * + at bit 8 offset (<< 12)
447 * = (<< 6)
448 */
449 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
450 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
451 #define WX_PX_RR_CFG_RR_EN BIT(0)
452
453 /* Number of 80 microseconds we wait for PCI Express master disable */
454 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
455
456 #define WX_RSS_64Q_MASK 0x3F
457 #define WX_RSS_8Q_MASK 0x7
458 #define WX_RSS_4Q_MASK 0x3
459 #define WX_RSS_2Q_MASK 0x1
460 #define WX_RSS_DISABLED_MASK 0x0
461
462 #define WX_VMDQ_4Q_MASK 0x7C
463 #define WX_VMDQ_2Q_MASK 0x7E
464
465 /****************** Manageablility Host Interface defines ********************/
466 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
467 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
468 #define WX_HIC_HDR_INDEX_MAX 255
469
470 #define FW_READ_SHADOW_RAM_CMD 0x31
471 #define FW_READ_SHADOW_RAM_LEN 0x6
472 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
473 #define FW_NVM_DATA_OFFSET 3
474 #define FW_MAX_READ_BUFFER_SIZE 244
475 #define FW_RESET_CMD 0xDF
476 #define FW_RESET_LEN 0x2
477 #define FW_CEM_HDR_LEN 0x4
478 #define FW_CEM_CMD_RESERVED 0X0
479 #define FW_CEM_MAX_RETRIES 3
480 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
481 #define FW_PPS_SET_CMD 0xF6
482 #define FW_PPS_SET_LEN 0x14
483
484 #define WX_SW_REGION_PTR 0x1C
485
486 #define WX_MAC_STATE_DEFAULT 0x1
487 #define WX_MAC_STATE_MODIFIED 0x2
488 #define WX_MAC_STATE_IN_USE 0x4
489
490 /* BitTimes (BT) conversion */
491 #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
492 #define WX_B2BT(BT) ((BT) * 8)
493
494 /* Calculate Delay to respond to PFC */
495 #define WX_PFC_D 672
496 /* Calculate Cable Delay */
497 #define WX_CABLE_DC 5556 /* Delay Copper */
498 /* Calculate Delay incurred from higher layer */
499 #define WX_HD 6144
500
501 /* Calculate Interface Delay */
502 #define WX_PHY_D 12800
503 #define WX_MAC_D 4096
504 #define WX_XAUI_D (2 * 1024)
505 #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D)
506 /* Calculate PCI Bus delay for low thresholds */
507 #define WX_PCI_DELAY 10000
508
509 /* Calculate delay value in bit times */
510 #define WX_DV(_max_frame_link, _max_frame_tc) \
511 ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \
512 (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \
513 2 * WX_B2BT(_max_frame_tc))
514
515 /* Calculate low threshold delay values */
516 #define WX_LOW_DV(_max_frame_tc) \
517 (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))
518
519 /* flow control */
520 #define WX_DEFAULT_FCPAUSE 0xFFFF
521
522 #define WX_MAX_RXD 8192
523 #define WX_MAX_TXD 8192
524 #define WX_MIN_RXD 128
525 #define WX_MIN_TXD 128
526
527 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */
528 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
529 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
530
531 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
532 #define VMDQ_P(p) ((p) + wx->ring_feature[RING_F_VMDQ].offset)
533
534 /* Supported Rx Buffer Sizes */
535 #define WX_RXBUFFER_256 256 /* Used for skb receive header */
536 #define WX_RXBUFFER_2K 2048
537 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
538
539 #if MAX_SKB_FRAGS < 8
540 #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
541 #else
542 #define WX_RX_BUFSZ WX_RXBUFFER_2K
543 #endif
544
545 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
546
547 #define WX_MAX_DATA_PER_TXD BIT(14)
548 /* Tx Descriptors needed, worst case */
549 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
550 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
551
552 #define WX_CFG_PORT_ST 0x14404
553
554 /******************* Receive Descriptor bit definitions **********************/
555 #define WX_RXD_STAT_DD BIT(0) /* Done */
556 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
557 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
558 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
559 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
560 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
561 #define WX_RXD_STAT_IPV6EX BIT(12) /* IPv6 Dest Header */
562 #define WX_RXD_STAT_TS BIT(14) /* IEEE1588 Time Stamp */
563
564 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
565 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
566 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
567 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
568
569 /* RSS Hash results */
570 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
571 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
572 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
573 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
574 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
575 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
576 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
577
578 #define WX_RSS_L4_TYPES_MASK \
579 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
580 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
581 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
582 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
583 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
584 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
585 /* TUN */
586 #define WX_PTYPE_TUN_IPV4 0x80
587 #define WX_PTYPE_TUN_IPV6 0xC0
588
589 /* PKT for TUN */
590 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
591 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
592 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
593 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
594 /* PKT for !TUN */
595 #define WX_PTYPE_PKT_MAC 0x10
596 #define WX_PTYPE_PKT_IP 0x20
597
598 /* TYP for PKT=mac */
599 #define WX_PTYPE_TYP_MAC 0x01
600 /* TYP for PKT=ip */
601 #define WX_PTYPE_PKT_IPV6 0x08
602 #define WX_PTYPE_TYP_IPFRAG 0x01
603 #define WX_PTYPE_TYP_IP 0x02
604 #define WX_PTYPE_TYP_UDP 0x03
605 #define WX_PTYPE_TYP_TCP 0x04
606 #define WX_PTYPE_TYP_SCTP 0x05
607
608 /* Packet type non-ip values */
609 enum wx_l2_ptypes {
610 WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC),
611 WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC),
612
613 WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG),
614 WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP),
615 WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP),
616 WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP),
617 WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP),
618 WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
619 WX_PTYPE_TYP_IPFRAG),
620 WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
621 WX_PTYPE_TYP_IP),
622 WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
623 WX_PTYPE_TYP_UDP),
624 WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
625 WX_PTYPE_TYP_TCP),
626 WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
627 WX_PTYPE_TYP_SCTP),
628
629 WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM),
630 WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM),
631 };
632
633 #define WX_PTYPE_PKT(_pt) ((_pt) & 0x30)
634 #define WX_PTYPE_TYPL4(_pt) ((_pt) & 0x07)
635
636 #define WX_RXD_PKTTYPE(_rxd) \
637 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
638 /*********************** Transmit Descriptor Config Masks ****************/
639 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
640 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
641 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
642 #define WX_TXD_EOP BIT(24) /* End of Packet */
643 #define WX_TXD_IFCS BIT(25) /* Insert FCS */
644 #define WX_TXD_RS BIT(27) /* Report Status */
645
646 /*********************** Adv Transmit Descriptor Config Masks ****************/
647 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
648 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
649 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
650 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
651 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
652 #define WX_TXD_CC BIT(7) /* Check Context */
653 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
654 #define WX_TXD_L4CS BIT(9)
655 #define WX_TXD_IIPCS BIT(10)
656 #define WX_TXD_EIPCS BIT(11)
657 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
658 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
659 #define WX_TXD_TAG_TPID_SEL_SHIFT 11
660
661 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
662 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
663
664 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
665 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
666 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
667 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
668 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
669
670 enum wx_tx_flags {
671 /* cmd_type flags */
672 WX_TX_FLAGS_HW_VLAN = 0x01,
673 WX_TX_FLAGS_TSO = 0x02,
674 WX_TX_FLAGS_TSTAMP = 0x04,
675
676 /* olinfo flags */
677 WX_TX_FLAGS_CC = 0x08,
678 WX_TX_FLAGS_IPV4 = 0x10,
679 WX_TX_FLAGS_CSUM = 0x20,
680 WX_TX_FLAGS_OUTER_IPV4 = 0x100,
681 WX_TX_FLAGS_LINKSEC = 0x200,
682 WX_TX_FLAGS_IPSEC = 0x400,
683
684 /* software defined flags */
685 WX_TX_FLAGS_SW_VLAN = 0x40,
686 };
687
688 /* VLAN info */
689 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
690 #define WX_TX_FLAGS_VLAN_SHIFT 16
691
692 /* wx_dec_ptype.mac: outer mac */
693 enum wx_dec_ptype_mac {
694 WX_DEC_PTYPE_MAC_IP = 0,
695 WX_DEC_PTYPE_MAC_L2 = 2,
696 WX_DEC_PTYPE_MAC_FCOE = 3,
697 };
698
699 /* wx_dec_ptype.[e]ip: outer&encaped ip */
700 #define WX_DEC_PTYPE_IP_FRAG 0x4
701 enum wx_dec_ptype_ip {
702 WX_DEC_PTYPE_IP_NONE = 0,
703 WX_DEC_PTYPE_IP_IPV4 = 1,
704 WX_DEC_PTYPE_IP_IPV6 = 2,
705 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
706 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
707 };
708
709 /* wx_dec_ptype.etype: encaped type */
710 enum wx_dec_ptype_etype {
711 WX_DEC_PTYPE_ETYPE_NONE = 0,
712 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
713 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
714 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
715 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
716 };
717
718 /* wx_dec_ptype.proto: payload proto */
719 enum wx_dec_ptype_prot {
720 WX_DEC_PTYPE_PROT_NONE = 0,
721 WX_DEC_PTYPE_PROT_UDP = 1,
722 WX_DEC_PTYPE_PROT_TCP = 2,
723 WX_DEC_PTYPE_PROT_SCTP = 3,
724 WX_DEC_PTYPE_PROT_ICMP = 4,
725 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
726 };
727
728 /* wx_dec_ptype.layer: payload layer */
729 enum wx_dec_ptype_layer {
730 WX_DEC_PTYPE_LAYER_NONE = 0,
731 WX_DEC_PTYPE_LAYER_PAY2 = 1,
732 WX_DEC_PTYPE_LAYER_PAY3 = 2,
733 WX_DEC_PTYPE_LAYER_PAY4 = 3,
734 };
735
736 struct wx_dec_ptype {
737 u32 known:1;
738 u32 mac:2; /* outer mac */
739 u32 ip:3; /* outer ip*/
740 u32 etype:3; /* encaped type */
741 u32 eip:3; /* encaped ip */
742 u32 prot:4; /* payload proto */
743 u32 layer:3; /* payload layer */
744 };
745
746 /* macro to make the table lines short */
747 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
748 {1, \
749 WX_DEC_PTYPE_MAC_##mac, /* mac */\
750 WX_DEC_PTYPE_IP_##ip, /* ip */ \
751 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
752 WX_DEC_PTYPE_IP_##eip, /* eip */\
753 WX_DEC_PTYPE_PROT_##proto, /* proto */\
754 WX_DEC_PTYPE_LAYER_##layer /* layer */}
755
756 /* Host Interface Command Structures */
757 struct wx_hic_hdr {
758 u8 cmd;
759 u8 buf_len;
760 union {
761 u8 cmd_resv;
762 u8 ret_status;
763 } cmd_or_resp;
764 union {
765 u8 checksum;
766 u8 index;
767 };
768 };
769
770 struct wx_hic_hdr2_req {
771 u8 cmd;
772 u8 buf_lenh;
773 u8 buf_lenl;
774 union {
775 u8 checksum;
776 u8 index;
777 };
778 };
779
780 struct wx_hic_hdr2_rsp {
781 u8 cmd;
782 u8 buf_lenl;
783 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
784 union {
785 u8 checksum;
786 u8 index;
787 };
788 };
789
790 union wx_hic_hdr2 {
791 struct wx_hic_hdr2_req req;
792 struct wx_hic_hdr2_rsp rsp;
793 };
794
795 /* These need to be dword aligned */
796 struct wx_hic_read_shadow_ram {
797 union wx_hic_hdr2 hdr;
798 u32 address;
799 u16 length;
800 u16 pad2;
801 u16 data;
802 u16 pad3;
803 };
804
805 struct wx_hic_reset {
806 struct wx_hic_hdr hdr;
807 u16 lan_id;
808 u16 reset_type;
809 };
810
811 struct wx_hic_set_pps {
812 struct wx_hic_hdr hdr;
813 u8 lan_id;
814 u8 enable;
815 u16 pad2;
816 u64 nsec;
817 u64 cycles;
818 };
819
820 /* Bus parameters */
821 struct wx_bus_info {
822 u8 func;
823 u16 device;
824 };
825
826 struct wx_mbx_info {
827 u16 size;
828 u32 mailbox;
829 u32 udelay;
830 u32 timeout;
831 /* lock mbx access */
832 spinlock_t mbx_lock;
833 };
834
835 struct wx_thermal_sensor_data {
836 s16 temp;
837 s16 alarm_thresh;
838 s16 dalarm_thresh;
839 };
840
841 enum wx_mac_type {
842 wx_mac_unknown = 0,
843 wx_mac_sp,
844 wx_mac_em,
845 wx_mac_aml,
846 wx_mac_aml40,
847 };
848
849 enum wx_media_type {
850 wx_media_unknown = 0,
851 wx_media_fiber,
852 wx_media_copper,
853 wx_media_backplane
854 };
855
856 enum em_mac_type {
857 em_mac_type_unknown = 0,
858 em_mac_type_mdi,
859 em_mac_type_rgmii
860 };
861
862 struct wx_mac_info {
863 enum wx_mac_type type;
864 bool set_lben;
865 u8 addr[ETH_ALEN];
866 u8 perm_addr[ETH_ALEN];
867 u32 mta_shadow[128];
868 s32 mc_filter_type;
869 u32 mcft_size;
870 u32 vft_shadow[128];
871 u32 vft_size;
872 u32 num_rar_entries;
873 u32 rx_pb_size;
874 u32 tx_pb_size;
875 u32 max_tx_queues;
876 u32 max_rx_queues;
877
878 u16 max_msix_vectors;
879 struct wx_thermal_sensor_data sensor;
880 };
881
882 enum wx_eeprom_type {
883 wx_eeprom_uninitialized = 0,
884 wx_eeprom_spi,
885 wx_flash,
886 wx_eeprom_none /* No NVM support */
887 };
888
889 struct wx_eeprom_info {
890 enum wx_eeprom_type type;
891 u32 semaphore_delay;
892 u16 word_size;
893 u16 sw_region_offset;
894 };
895
896 struct wx_addr_filter_info {
897 u32 num_mc_addrs;
898 u32 mta_in_use;
899 bool user_set_promisc;
900 };
901
902 struct wx_mac_addr {
903 u8 addr[ETH_ALEN];
904 u16 state; /* bitmask */
905 u64 pools;
906 };
907
908 enum wx_reset_type {
909 WX_LAN_RESET = 0,
910 WX_SW_RESET,
911 WX_GLOBAL_RESET
912 };
913
914 struct wx_cb {
915 dma_addr_t dma;
916 u16 append_cnt; /* number of skb's appended */
917 bool dma_released;
918 };
919
920 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
921
922 /* Transmit Descriptor */
923 union wx_tx_desc {
924 struct {
925 __le64 buffer_addr; /* Address of descriptor's data buf */
926 __le32 cmd_type_len;
927 __le32 olinfo_status;
928 } read;
929 struct {
930 __le64 rsvd; /* Reserved */
931 __le32 nxtseq_seed;
932 __le32 status;
933 } wb;
934 };
935
936 /* Receive Descriptor */
937 union wx_rx_desc {
938 struct {
939 __le64 pkt_addr; /* Packet buffer address */
940 __le64 hdr_addr; /* Header buffer address */
941 } read;
942 struct {
943 struct {
944 union {
945 __le32 data;
946 struct {
947 __le16 pkt_info; /* RSS, Pkt type */
948 __le16 hdr_info; /* Splithdr, hdrlen */
949 } hs_rss;
950 } lo_dword;
951 union {
952 __le32 rss; /* RSS Hash */
953 struct {
954 __le16 ip_id; /* IP id */
955 __le16 csum; /* Packet Checksum */
956 } csum_ip;
957 } hi_dword;
958 } lower;
959 struct {
960 __le32 status_error; /* ext status/error */
961 __le16 length; /* Packet length */
962 __le16 vlan; /* VLAN tag */
963 } upper;
964 } wb; /* writeback */
965 };
966
967 struct wx_tx_context_desc {
968 __le32 vlan_macip_lens;
969 __le32 seqnum_seed;
970 __le32 type_tucmd_mlhl;
971 __le32 mss_l4len_idx;
972 };
973
974 /* if _flag is in _input, return _result */
975 #define WX_SET_FLAG(_input, _flag, _result) \
976 (((_flag) <= (_result)) ? \
977 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
978 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
979
980 #define WX_RX_DESC(R, i) \
981 (&(((union wx_rx_desc *)((R)->desc))[i]))
982 #define WX_TX_DESC(R, i) \
983 (&(((union wx_tx_desc *)((R)->desc))[i]))
984 #define WX_TX_CTXTDESC(R, i) \
985 (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
986
987 /* wrapper around a pointer to a socket buffer,
988 * so a DMA handle can be stored along with the buffer
989 */
990 struct wx_tx_buffer {
991 union wx_tx_desc *next_to_watch;
992 unsigned long time_stamp;
993 struct sk_buff *skb;
994 unsigned int bytecount;
995 unsigned short gso_segs;
996 DEFINE_DMA_UNMAP_ADDR(dma);
997 DEFINE_DMA_UNMAP_LEN(len);
998 __be16 protocol;
999 u32 tx_flags;
1000 };
1001
1002 struct wx_rx_buffer {
1003 struct sk_buff *skb;
1004 dma_addr_t dma;
1005 struct page *page;
1006 unsigned int page_offset;
1007 };
1008
1009 struct wx_queue_stats {
1010 u64 packets;
1011 u64 bytes;
1012 };
1013
1014 struct wx_tx_queue_stats {
1015 u64 restart_queue;
1016 u64 tx_busy;
1017 };
1018
1019 struct wx_rx_queue_stats {
1020 u64 non_eop_descs;
1021 u64 csum_good_cnt;
1022 u64 csum_err;
1023 u64 alloc_rx_buff_failed;
1024 };
1025
1026 /* iterator for handling rings in ring container */
1027 #define wx_for_each_ring(posm, headm) \
1028 for (posm = (headm).ring; posm; posm = posm->next)
1029
1030 struct wx_ring_container {
1031 struct wx_ring *ring; /* pointer to linked list of rings */
1032 unsigned int total_bytes; /* total bytes processed this int */
1033 unsigned int total_packets; /* total packets processed this int */
1034 u8 count; /* total number of rings in vector */
1035 u8 itr; /* current ITR setting for ring */
1036 };
1037 struct wx_ring {
1038 struct wx_ring *next; /* pointer to next ring in q_vector */
1039 struct wx_q_vector *q_vector; /* backpointer to host q_vector */
1040 struct net_device *netdev; /* netdev ring belongs to */
1041 struct device *dev; /* device for DMA mapping */
1042 struct page_pool *page_pool;
1043 void *desc; /* descriptor ring memory */
1044 union {
1045 struct wx_tx_buffer *tx_buffer_info;
1046 struct wx_rx_buffer *rx_buffer_info;
1047 };
1048 u8 __iomem *tail;
1049 dma_addr_t dma; /* phys. address of descriptor ring */
1050 unsigned int size; /* length in bytes */
1051
1052 u16 count; /* amount of descriptors */
1053 unsigned long last_rx_timestamp;
1054
1055 u8 queue_index; /* needed for multiqueue queue management */
1056 u8 reg_idx; /* holds the special value that gets
1057 * the hardware register offset
1058 * associated with this ring, which is
1059 * different for DCB and RSS modes
1060 */
1061 u16 next_to_use;
1062 u16 next_to_clean;
1063 union {
1064 u16 next_to_alloc;
1065 struct {
1066 u8 atr_sample_rate;
1067 u8 atr_count;
1068 };
1069 };
1070
1071 struct wx_queue_stats stats;
1072 struct u64_stats_sync syncp;
1073 union {
1074 struct wx_tx_queue_stats tx_stats;
1075 struct wx_rx_queue_stats rx_stats;
1076 };
1077 } ____cacheline_internodealigned_in_smp;
1078
1079 struct wx_q_vector {
1080 struct wx *wx;
1081 int cpu; /* CPU for DCA */
1082 int numa_node;
1083 u16 v_idx; /* index of q_vector within array, also used for
1084 * finding the bit in EICR and friends that
1085 * represents the vector for this ring
1086 */
1087 u16 itr; /* Interrupt throttle rate written to EITR */
1088 struct wx_ring_container rx, tx;
1089 struct napi_struct napi;
1090 struct rcu_head rcu; /* to avoid race with update stats on free */
1091
1092 char name[IFNAMSIZ + 17];
1093
1094 /* for dynamic allocation of rings associated with this q_vector */
1095 struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
1096 };
1097
1098 struct wx_ring_feature {
1099 u16 limit; /* upper limit on feature indices */
1100 u16 indices; /* current value of indices */
1101 u16 mask; /* Mask used for feature to ring mapping */
1102 u16 offset; /* offset to start of feature */
1103 };
1104
1105 enum wx_ring_f_enum {
1106 RING_F_NONE = 0,
1107 RING_F_VMDQ,
1108 RING_F_RSS,
1109 RING_F_FDIR,
1110 RING_F_ARRAY_SIZE /* must be last in enum set */
1111 };
1112
1113 enum wx_isb_idx {
1114 WX_ISB_HEADER,
1115 WX_ISB_MISC,
1116 WX_ISB_VEC0,
1117 WX_ISB_VEC1,
1118 WX_ISB_MAX
1119 };
1120
1121 struct wx_fc_info {
1122 u32 high_water; /* Flow Ctrl High-water */
1123 u32 low_water; /* Flow Ctrl Low-water */
1124 };
1125
1126 /* Statistics counters collected by the MAC */
1127 struct wx_hw_stats {
1128 u64 gprc;
1129 u64 gptc;
1130 u64 gorc;
1131 u64 gotc;
1132 u64 tpr;
1133 u64 tpt;
1134 u64 bprc;
1135 u64 bptc;
1136 u64 mprc;
1137 u64 mptc;
1138 u64 roc;
1139 u64 ruc;
1140 u64 lxonoffrxc;
1141 u64 lxontxc;
1142 u64 lxofftxc;
1143 u64 o2bgptc;
1144 u64 b2ospc;
1145 u64 o2bspc;
1146 u64 b2ogprc;
1147 u64 rdmdrop;
1148 u64 crcerrs;
1149 u64 rlec;
1150 u64 qmprc;
1151 u64 fdirmatch;
1152 u64 fdirmiss;
1153 };
1154
1155 enum wx_state {
1156 WX_STATE_RESETTING,
1157 WX_STATE_SWFW_BUSY,
1158 WX_STATE_PTP_RUNNING,
1159 WX_STATE_PTP_TX_IN_PROGRESS,
1160 WX_STATE_SERVICE_SCHED,
1161 WX_STATE_NBITS /* must be last */
1162 };
1163
1164 struct vf_data_storage {
1165 struct pci_dev *vfdev;
1166 unsigned char vf_mac_addr[ETH_ALEN];
1167 bool spoofchk_enabled;
1168 bool link_enable;
1169 bool trusted;
1170 int xcast_mode;
1171 unsigned int vf_api;
1172 bool clear_to_send;
1173 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
1174 u16 pf_qos;
1175 bool pf_set_mac;
1176
1177 u16 vf_mc_hashes[WX_MAX_VF_MC_ENTRIES];
1178 u16 num_vf_mc_hashes;
1179 u16 vlan_count;
1180 int link_state;
1181 };
1182
1183 struct vf_macvlans {
1184 struct list_head mvlist;
1185 int vf;
1186 bool free;
1187 bool is_macvlan;
1188 u8 vf_macvlan[ETH_ALEN];
1189 };
1190
1191 enum wx_pf_flags {
1192 WX_FLAG_MULTI_64_FUNC,
1193 WX_FLAG_SWFW_RING,
1194 WX_FLAG_VMDQ_ENABLED,
1195 WX_FLAG_VLAN_PROMISC,
1196 WX_FLAG_SRIOV_ENABLED,
1197 WX_FLAG_IRQ_VECTOR_SHARED,
1198 WX_FLAG_FDIR_CAPABLE,
1199 WX_FLAG_FDIR_HASH,
1200 WX_FLAG_FDIR_PERFECT,
1201 WX_FLAG_RSC_CAPABLE,
1202 WX_FLAG_RX_HWTSTAMP_ENABLED,
1203 WX_FLAG_RX_HWTSTAMP_IN_REGISTER,
1204 WX_FLAG_PTP_PPS_ENABLED,
1205 WX_FLAG_NEED_LINK_CONFIG,
1206 WX_FLAG_NEED_SFP_RESET,
1207 WX_FLAG_NEED_UPDATE_LINK,
1208 WX_FLAG_NEED_DO_RESET,
1209 WX_PF_FLAGS_NBITS /* must be last */
1210 };
1211
1212 struct wx {
1213 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1214 DECLARE_BITMAP(state, WX_STATE_NBITS);
1215 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS);
1216
1217 void *priv;
1218 u8 __iomem *hw_addr;
1219 u8 __iomem *b4_addr; /* vf only */
1220 struct pci_dev *pdev;
1221 struct net_device *netdev;
1222 struct wx_bus_info bus;
1223 struct wx_mbx_info mbx;
1224 struct wx_mac_info mac;
1225 enum em_mac_type mac_type;
1226 enum wx_media_type media_type;
1227 struct wx_eeprom_info eeprom;
1228 struct wx_addr_filter_info addr_ctrl;
1229 struct wx_fc_info fc;
1230 struct wx_mac_addr *mac_table;
1231 u16 device_id;
1232 u16 vendor_id;
1233 u16 subsystem_device_id;
1234 u16 subsystem_vendor_id;
1235 u8 revision_id;
1236 u16 oem_ssid;
1237 u16 oem_svid;
1238 u16 msg_enable;
1239 bool adapter_stopped;
1240 u16 tpid[8];
1241 char eeprom_id[32];
1242 char *driver_name;
1243 enum wx_reset_type reset_type;
1244 u8 swfw_index;
1245
1246 /* PHY stuff */
1247 bool notify_down;
1248 int adv_speed;
1249 int adv_duplex;
1250 unsigned int link;
1251 int speed;
1252 int duplex;
1253 struct phy_device *phydev;
1254 struct phylink *phylink;
1255 struct phylink_config phylink_config;
1256
1257 bool wol_hw_supported;
1258 bool ncsi_enabled;
1259 bool gpio_ctrl;
1260 raw_spinlock_t gpio_lock;
1261
1262 /* Tx fast path data */
1263 int num_tx_queues;
1264 u16 tx_itr_setting;
1265 u16 tx_work_limit;
1266
1267 /* Rx fast path data */
1268 int num_rx_queues;
1269 u16 rx_itr_setting;
1270 u16 rx_work_limit;
1271
1272 int num_q_vectors; /* current number of q_vectors for device */
1273 int max_q_vectors; /* upper limit of q_vectors for device */
1274
1275 u32 tx_ring_count;
1276 u32 rx_ring_count;
1277
1278 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
1279 struct wx_ring *rx_ring[64];
1280 struct wx_q_vector *q_vector[64];
1281 int num_rx_pools;
1282 int num_rx_queues_per_pool;
1283
1284 unsigned int queues_per_pool;
1285 struct msix_entry *msix_q_entries;
1286 struct msix_entry *msix_entry;
1287 struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];
1288
1289 /* misc interrupt status block */
1290 dma_addr_t isb_dma;
1291 u32 *isb_mem;
1292 u32 isb_tag[WX_ISB_MAX];
1293 bool misc_irq_domain;
1294 u32 eims_other;
1295 u32 eims_enable_mask;
1296
1297 #define WX_MAX_RETA_ENTRIES 128
1298 #define WX_RSS_INDIR_TBL_MAX 64
1299 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
1300 bool rss_enabled;
1301 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
1302 u32 *rss_key;
1303 u32 wol;
1304
1305 u16 bd_number;
1306 bool default_up;
1307
1308 struct wx_hw_stats stats;
1309 u64 tx_busy;
1310 u64 non_eop_descs;
1311 u64 restart_queue;
1312 u64 hw_csum_rx_good;
1313 u64 hw_csum_rx_error;
1314 u64 alloc_rx_buff_failed;
1315 unsigned int num_vfs;
1316 struct vf_data_storage *vfinfo;
1317 struct vf_macvlans vf_mvs;
1318 struct vf_macvlans *mv_list;
1319 unsigned long fwd_bitmask;
1320
1321 u32 atr_sample_rate;
1322 void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype);
1323 void (*configure_fdir)(struct wx *wx);
1324 int (*setup_tc)(struct net_device *netdev, u8 tc);
1325 void (*do_reset)(struct net_device *netdev);
1326 int (*ptp_setup_sdp)(struct wx *wx);
1327 void (*set_num_queues)(struct wx *wx);
1328
1329 bool pps_enabled;
1330 u64 pps_width;
1331 u64 pps_edge_start;
1332 u64 pps_edge_end;
1333 u64 sec_to_cc;
1334 u32 base_incval;
1335 u32 tx_hwtstamp_pkts;
1336 u32 tx_hwtstamp_timeouts;
1337 u32 tx_hwtstamp_skipped;
1338 u32 tx_hwtstamp_errors;
1339 u32 rx_hwtstamp_cleared;
1340 unsigned long last_overflow_check;
1341 unsigned long last_rx_ptp_check;
1342 unsigned long ptp_tx_start;
1343 seqlock_t hw_tc_lock; /* seqlock for ptp */
1344 struct cyclecounter hw_cc;
1345 struct timecounter hw_tc;
1346 struct ptp_clock *ptp_clock;
1347 struct ptp_clock_info ptp_caps;
1348 struct kernel_hwtstamp_config tstamp_config;
1349 struct sk_buff *ptp_tx_skb;
1350
1351 struct timer_list service_timer;
1352 struct work_struct service_task;
1353 };
1354
1355 #define WX_INTR_ALL (~0ULL)
1356 #define WX_INTR_Q(i) BIT((i))
1357
1358 /* register operations */
1359 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
1360 #define rd32(a, reg) readl((a)->hw_addr + (reg))
1361 #define rd32a(a, reg, offset) ( \
1362 rd32((a), (reg) + ((offset) << 2)))
1363 #define wr32a(a, reg, off, val) \
1364 wr32((a), (reg) + ((off) << 2), (val))
1365
1366 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)1367 rd32m(struct wx *wx, u32 reg, u32 mask)
1368 {
1369 u32 val;
1370
1371 val = rd32(wx, reg);
1372 return val & mask;
1373 }
1374
1375 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)1376 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
1377 {
1378 u32 val;
1379
1380 val = rd32(wx, reg);
1381 val = ((val & ~mask) | (field & mask));
1382
1383 wr32(wx, reg, val);
1384 }
1385
1386 static inline u64
rd64(struct wx * wx,u32 reg)1387 rd64(struct wx *wx, u32 reg)
1388 {
1389 u64 lsb, msb;
1390
1391 lsb = rd32(wx, reg);
1392 msb = rd32(wx, reg + 4);
1393
1394 return (lsb | msb << 32);
1395 }
1396
1397 static inline u32
rd32ptp(struct wx * wx,u32 reg)1398 rd32ptp(struct wx *wx, u32 reg)
1399 {
1400 if (wx->mac.type == wx_mac_em)
1401 return rd32(wx, reg);
1402
1403 return rd32(wx, reg + 0xB500);
1404 }
1405
1406 static inline void
wr32ptp(struct wx * wx,u32 reg,u32 value)1407 wr32ptp(struct wx *wx, u32 reg, u32 value)
1408 {
1409 if (wx->mac.type == wx_mac_em)
1410 return wr32(wx, reg, value);
1411
1412 return wr32(wx, reg + 0xB500, value);
1413 }
1414
1415 /* On some domestic CPU platforms, sometimes IO is not synchronized with
1416 * flushing memory, here use readl() to flush PCI read and write.
1417 */
1418 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
1419
1420 #define wx_err(wx, fmt, arg...) \
1421 dev_err(&(wx)->pdev->dev, fmt, ##arg)
1422
1423 #define wx_dbg(wx, fmt, arg...) \
1424 dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
1425
phylink_to_wx(struct phylink_config * config)1426 static inline struct wx *phylink_to_wx(struct phylink_config *config)
1427 {
1428 return container_of(config, struct wx, phylink_config);
1429 }
1430
wx_set_state_reset(struct wx * wx)1431 static inline int wx_set_state_reset(struct wx *wx)
1432 {
1433 u8 timeout = 50;
1434
1435 while (test_and_set_bit(WX_STATE_RESETTING, wx->state)) {
1436 timeout--;
1437 if (!timeout)
1438 return -EBUSY;
1439
1440 usleep_range(1000, 2000);
1441 }
1442
1443 return 0;
1444 }
1445
1446 #endif /* _WX_TYPE_H_ */
1447