1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/device.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/hwmon.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/printk.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/reset.h>
18 #include <linux/slab.h>
19 #include <linux/soundwire/sdw.h>
20 #include <linux/soundwire/sdw_registers.h>
21 #include <linux/soundwire/sdw_type.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc-dapm.h>
25 #include <sound/soc.h>
26 #include <sound/tlv.h>
27
28 #define WSA883X_BASE 0x3000
29 #define WSA883X_ANA_BG_TSADC_BASE (WSA883X_BASE + 0x00000001)
30 #define WSA883X_REF_CTRL (WSA883X_ANA_BG_TSADC_BASE + 0x0000)
31 #define WSA883X_TEST_CTL_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0001)
32 #define WSA883X_BIAS_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0002)
33 #define WSA883X_OP_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0003)
34 #define WSA883X_IREF_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0004)
35 #define WSA883X_ISENS_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0005)
36 #define WSA883X_CLK_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0006)
37 #define WSA883X_TEST_CTL_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0007)
38 #define WSA883X_BIAS_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0008)
39 #define WSA883X_ADC_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0009)
40 #define WSA883X_DOUT_MSB (WSA883X_ANA_BG_TSADC_BASE + 0x000A)
41 #define WSA883X_DOUT_LSB (WSA883X_ANA_BG_TSADC_BASE + 0x000B)
42 #define WSA883X_VBAT_SNS (WSA883X_ANA_BG_TSADC_BASE + 0x000C)
43 #define WSA883X_ITRIM_CODE (WSA883X_ANA_BG_TSADC_BASE + 0x000D)
44
45 #define WSA883X_ANA_IVSENSE_BASE (WSA883X_BASE + 0x0000000F)
46 #define WSA883X_EN (WSA883X_ANA_IVSENSE_BASE + 0x0000)
47 #define WSA883X_OVERRIDE1 (WSA883X_ANA_IVSENSE_BASE + 0x0001)
48 #define WSA883X_OVERRIDE2 (WSA883X_ANA_IVSENSE_BASE + 0x0002)
49 #define WSA883X_VSENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0003)
50 #define WSA883X_ISENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0004)
51 #define WSA883X_ISENSE2 (WSA883X_ANA_IVSENSE_BASE + 0x0005)
52 #define WSA883X_ISENSE_CAL (WSA883X_ANA_IVSENSE_BASE + 0x0006)
53 #define WSA883X_MISC (WSA883X_ANA_IVSENSE_BASE + 0x0007)
54 #define WSA883X_ADC_0 (WSA883X_ANA_IVSENSE_BASE + 0x0008)
55 #define WSA883X_ADC_1 (WSA883X_ANA_IVSENSE_BASE + 0x0009)
56 #define WSA883X_ADC_2 (WSA883X_ANA_IVSENSE_BASE + 0x000A)
57 #define WSA883X_ADC_3 (WSA883X_ANA_IVSENSE_BASE + 0x000B)
58 #define WSA883X_ADC_4 (WSA883X_ANA_IVSENSE_BASE + 0x000C)
59 #define WSA883X_ADC_5 (WSA883X_ANA_IVSENSE_BASE + 0x000D)
60 #define WSA883X_ADC_6 (WSA883X_ANA_IVSENSE_BASE + 0x000E)
61 #define WSA883X_ADC_7 (WSA883X_ANA_IVSENSE_BASE + 0x000F)
62 #define WSA883X_STATUS (WSA883X_ANA_IVSENSE_BASE + 0x0010)
63
64 #define WSA883X_ANA_SPK_TOP_BASE (WSA883X_BASE + 0x00000025)
65 #define WSA883X_DAC_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0000)
66 #define WSA883X_DAC_EN_DEBUG_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0001)
67 #define WSA883X_DAC_OPAMP_BIAS1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0002)
68 #define WSA883X_DAC_OPAMP_BIAS2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0003)
69 #define WSA883X_DAC_VCM_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0004)
70 #define WSA883X_DAC_VOLTAGE_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0005)
71 #define WSA883X_ATEST1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0006)
72 #define WSA883X_ATEST2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0007)
73 #define WSA883X_SPKR_TOP_BIAS_REG1 (WSA883X_ANA_SPK_TOP_BASE + 0x0008)
74 #define WSA883X_SPKR_TOP_BIAS_REG2 (WSA883X_ANA_SPK_TOP_BASE + 0x0009)
75 #define WSA883X_SPKR_TOP_BIAS_REG3 (WSA883X_ANA_SPK_TOP_BASE + 0x000A)
76 #define WSA883X_SPKR_TOP_BIAS_REG4 (WSA883X_ANA_SPK_TOP_BASE + 0x000B)
77 #define WSA883X_SPKR_CLIP_DET_REG (WSA883X_ANA_SPK_TOP_BASE + 0x000C)
78 #define WSA883X_SPKR_DRV_LF_BLK_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000D)
79 #define WSA883X_SPKR_DRV_LF_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000E)
80 #define WSA883X_SPKR_DRV_LF_MASK_DCC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x000F)
81 #define WSA883X_SPKR_DRV_LF_MISC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0010)
82 #define WSA883X_SPKR_DRV_LF_REG_GAIN (WSA883X_ANA_SPK_TOP_BASE + 0x0011)
83 #define WSA883X_SPKR_DRV_OS_CAL_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0012)
84 #define WSA883X_SPKR_DRV_OS_CAL_CTL1 (WSA883X_ANA_SPK_TOP_BASE + 0x0013)
85 #define WSA883X_SPKR_PWM_CLK_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0014)
86 #define WSA883X_SPKR_PWM_FREQ_SEL_MASK BIT(3)
87 #define WSA883X_SPKR_PWM_FREQ_F300KHZ 0
88 #define WSA883X_SPKR_PWM_FREQ_F600KHZ 1
89 #define WSA883X_SPKR_PDRV_HS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0015)
90 #define WSA883X_SPKR_PDRV_LS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0016)
91 #define WSA883X_SPKR_PWRSTG_DBG (WSA883X_ANA_SPK_TOP_BASE + 0x0017)
92 #define WSA883X_SPKR_OCP_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0018)
93 #define WSA883X_SPKR_BBM_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0019)
94 #define WSA883X_PA_STATUS0 (WSA883X_ANA_SPK_TOP_BASE + 0x001A)
95 #define WSA883X_PA_STATUS1 (WSA883X_ANA_SPK_TOP_BASE + 0x001B)
96 #define WSA883X_PA_STATUS2 (WSA883X_ANA_SPK_TOP_BASE + 0x001C)
97
98 #define WSA883X_ANA_BOOST_BASE (WSA883X_BASE + 0x00000043)
99 #define WSA883X_EN_CTRL (WSA883X_ANA_BOOST_BASE + 0x0000)
100 #define WSA883X_CURRENT_LIMIT (WSA883X_ANA_BOOST_BASE + 0x0001)
101 #define WSA883X_IBIAS1 (WSA883X_ANA_BOOST_BASE + 0x0002)
102 #define WSA883X_IBIAS2 (WSA883X_ANA_BOOST_BASE + 0x0003)
103 #define WSA883X_IBIAS3 (WSA883X_ANA_BOOST_BASE + 0x0004)
104 #define WSA883X_LDO_PROG (WSA883X_ANA_BOOST_BASE + 0x0005)
105 #define WSA883X_STABILITY_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0006)
106 #define WSA883X_STABILITY_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0007)
107 #define WSA883X_PWRSTAGE_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0008)
108 #define WSA883X_PWRSTAGE_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0009)
109 #define WSA883X_BYPASS_1 (WSA883X_ANA_BOOST_BASE + 0x000A)
110 #define WSA883X_BYPASS_2 (WSA883X_ANA_BOOST_BASE + 0x000B)
111 #define WSA883X_ZX_CTRL_1 (WSA883X_ANA_BOOST_BASE + 0x000C)
112 #define WSA883X_ZX_CTRL_2 (WSA883X_ANA_BOOST_BASE + 0x000D)
113 #define WSA883X_MISC1 (WSA883X_ANA_BOOST_BASE + 0x000E)
114 #define WSA883X_MISC2 (WSA883X_ANA_BOOST_BASE + 0x000F)
115 #define WSA883X_GMAMP_SUP1 (WSA883X_ANA_BOOST_BASE + 0x0010)
116 #define WSA883X_PWRSTAGE_CTRL3 (WSA883X_ANA_BOOST_BASE + 0x0011)
117 #define WSA883X_PWRSTAGE_CTRL4 (WSA883X_ANA_BOOST_BASE + 0x0012)
118 #define WSA883X_TEST1 (WSA883X_ANA_BOOST_BASE + 0x0013)
119 #define WSA883X_SPARE1 (WSA883X_ANA_BOOST_BASE + 0x0014)
120 #define WSA883X_SPARE2 (WSA883X_ANA_BOOST_BASE + 0x0015)
121
122 #define WSA883X_ANA_PON_LDOL_BASE (WSA883X_BASE + 0x00000059)
123 #define WSA883X_PON_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0000)
124 #define WSA883X_PON_CLT_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0001)
125 #define WSA883X_PON_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0002)
126 #define WSA883X_PON_CTL_3 (WSA883X_ANA_PON_LDOL_BASE + 0x0003)
127 #define WSA883X_CKWD_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0004)
128 #define WSA883X_CKWD_CTL_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0005)
129 #define WSA883X_CKWD_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0006)
130 #define WSA883X_CKSK_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0007)
131 #define WSA883X_PADSW_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0008)
132 #define WSA883X_TEST_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0009)
133 #define WSA883X_TEST_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000A)
134 #define WSA883X_STATUS_0 (WSA883X_ANA_PON_LDOL_BASE + 0x000B)
135 #define WSA883X_STATUS_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000C)
136
137 #define WSA883X_DIG_CTRL_BASE (WSA883X_BASE + 0x00000400)
138 #define WSA883X_CHIP_ID0 (WSA883X_DIG_CTRL_BASE + 0x0001)
139 #define WSA883X_CHIP_ID1 (WSA883X_DIG_CTRL_BASE + 0x0002)
140 #define WSA883X_CHIP_ID2 (WSA883X_DIG_CTRL_BASE + 0x0003)
141 #define WSA883X_CHIP_ID3 (WSA883X_DIG_CTRL_BASE + 0x0004)
142 #define WSA883X_BUS_ID (WSA883X_DIG_CTRL_BASE + 0x0005)
143 #define WSA883X_CDC_RST_CTL (WSA883X_DIG_CTRL_BASE + 0x0006)
144 #define WSA883X_TOP_CLK_CFG (WSA883X_DIG_CTRL_BASE + 0x0007)
145 #define WSA883X_CDC_PATH_MODE (WSA883X_DIG_CTRL_BASE + 0x0008)
146 #define WSA883X_RXD_MODE_MASK BIT(1)
147 #define WSA883X_RXD_MODE_NORMAL 0
148 #define WSA883X_RXD_MODE_HIFI 1
149 #define WSA883X_CDC_CLK_CTL (WSA883X_DIG_CTRL_BASE + 0x0009)
150 #define WSA883X_SWR_RESET_EN (WSA883X_DIG_CTRL_BASE + 0x000A)
151 #define WSA883X_RESET_CTL (WSA883X_DIG_CTRL_BASE + 0x000B)
152 #define WSA883X_PA_FSM_CTL (WSA883X_DIG_CTRL_BASE + 0x0010)
153 #define WSA883X_GLOBAL_PA_EN_MASK BIT(0)
154 #define WSA883X_GLOBAL_PA_ENABLE 1
155 #define WSA883X_PA_FSM_TIMER0 (WSA883X_DIG_CTRL_BASE + 0x0011)
156 #define WSA883X_PA_FSM_TIMER1 (WSA883X_DIG_CTRL_BASE + 0x0012)
157 #define WSA883X_PA_FSM_STA (WSA883X_DIG_CTRL_BASE + 0x0013)
158 #define WSA883X_PA_FSM_ERR_COND (WSA883X_DIG_CTRL_BASE + 0x0014)
159 #define WSA883X_PA_FSM_MSK (WSA883X_DIG_CTRL_BASE + 0x0015)
160 #define WSA883X_PA_FSM_BYP (WSA883X_DIG_CTRL_BASE + 0x0016)
161 #define WSA883X_PA_FSM_BYP_DC_CAL_EN_MASK 0x01
162 #define WSA883X_PA_FSM_BYP_DC_CAL_EN_SHIFT 0
163 #define WSA883X_PA_FSM_BYP_CLK_WD_EN_MASK 0x02
164 #define WSA883X_PA_FSM_BYP_CLK_WD_EN_SHIFT 1
165 #define WSA883X_PA_FSM_BYP_BG_EN_MASK 0x04
166 #define WSA883X_PA_FSM_BYP_BG_EN_SHIFT 2
167 #define WSA883X_PA_FSM_BYP_BOOST_EN_MASK 0x08
168 #define WSA883X_PA_FSM_BYP_BOOST_EN_SHIFT 3
169 #define WSA883X_PA_FSM_BYP_PA_EN_MASK 0x10
170 #define WSA883X_PA_FSM_BYP_PA_EN_SHIFT 4
171 #define WSA883X_PA_FSM_BYP_D_UNMUTE_MASK 0x20
172 #define WSA883X_PA_FSM_BYP_D_UNMUTE_SHIFT 5
173 #define WSA883X_PA_FSM_BYP_SPKR_PROT_EN_MASK 0x40
174 #define WSA883X_PA_FSM_BYP_SPKR_PROT_EN_SHIFT 6
175 #define WSA883X_PA_FSM_BYP_TSADC_EN_MASK 0x80
176 #define WSA883X_PA_FSM_BYP_TSADC_EN_SHIFT 7
177 #define WSA883X_PA_FSM_DBG (WSA883X_DIG_CTRL_BASE + 0x0017)
178 #define WSA883X_TADC_VALUE_CTL (WSA883X_DIG_CTRL_BASE + 0x0020)
179 #define WSA883X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK 0x01
180 #define WSA883X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_SHIFT 0
181 #define WSA883X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_MASK 0x02
182 #define WSA883X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_SHIFT 1
183 #define WSA883X_TEMP_DETECT_CTL (WSA883X_DIG_CTRL_BASE + 0x0021)
184 #define WSA883X_TEMP_MSB (WSA883X_DIG_CTRL_BASE + 0x0022)
185 #define WSA883X_TEMP_LSB (WSA883X_DIG_CTRL_BASE + 0x0023)
186 #define WSA883X_TEMP_CONFIG0 (WSA883X_DIG_CTRL_BASE + 0x0024)
187 #define WSA883X_TEMP_CONFIG1 (WSA883X_DIG_CTRL_BASE + 0x0025)
188 #define WSA883X_VBAT_ADC_FLT_CTL (WSA883X_DIG_CTRL_BASE + 0x0026)
189 #define WSA883X_VBAT_ADC_FLT_EN_MASK BIT(0)
190 #define WSA883X_VBAT_ADC_COEF_SEL_MASK GENMASK(3, 1)
191 #define WSA883X_VBAT_ADC_COEF_F_1DIV2 0x0
192 #define WSA883X_VBAT_ADC_COEF_F_1DIV16 0x3
193 #define WSA883X_VBAT_DIN_MSB (WSA883X_DIG_CTRL_BASE + 0x0027)
194 #define WSA883X_VBAT_DIN_LSB (WSA883X_DIG_CTRL_BASE + 0x0028)
195 #define WSA883X_VBAT_DOUT (WSA883X_DIG_CTRL_BASE + 0x0029)
196 #define WSA883X_SDM_PDM9_LSB (WSA883X_DIG_CTRL_BASE + 0x002A)
197 #define WSA883X_SDM_PDM9_MSB (WSA883X_DIG_CTRL_BASE + 0x002B)
198 #define WSA883X_CDC_RX_CTL (WSA883X_DIG_CTRL_BASE + 0x0030)
199 #define WSA883X_CDC_SPK_DSM_A1_0 (WSA883X_DIG_CTRL_BASE + 0x0031)
200 #define WSA883X_CDC_SPK_DSM_A1_1 (WSA883X_DIG_CTRL_BASE + 0x0032)
201 #define WSA883X_CDC_SPK_DSM_A2_0 (WSA883X_DIG_CTRL_BASE + 0x0033)
202 #define WSA883X_CDC_SPK_DSM_A2_1 (WSA883X_DIG_CTRL_BASE + 0x0034)
203 #define WSA883X_CDC_SPK_DSM_A3_0 (WSA883X_DIG_CTRL_BASE + 0x0035)
204 #define WSA883X_CDC_SPK_DSM_A3_1 (WSA883X_DIG_CTRL_BASE + 0x0036)
205 #define WSA883X_CDC_SPK_DSM_A4_0 (WSA883X_DIG_CTRL_BASE + 0x0037)
206 #define WSA883X_CDC_SPK_DSM_A4_1 (WSA883X_DIG_CTRL_BASE + 0x0038)
207 #define WSA883X_CDC_SPK_DSM_A5_0 (WSA883X_DIG_CTRL_BASE + 0x0039)
208 #define WSA883X_CDC_SPK_DSM_A5_1 (WSA883X_DIG_CTRL_BASE + 0x003A)
209 #define WSA883X_CDC_SPK_DSM_A6_0 (WSA883X_DIG_CTRL_BASE + 0x003B)
210 #define WSA883X_CDC_SPK_DSM_A7_0 (WSA883X_DIG_CTRL_BASE + 0x003C)
211 #define WSA883X_CDC_SPK_DSM_C_0 (WSA883X_DIG_CTRL_BASE + 0x003D)
212 #define WSA883X_CDC_SPK_DSM_C_1 (WSA883X_DIG_CTRL_BASE + 0x003E)
213 #define WSA883X_CDC_SPK_DSM_C_2 (WSA883X_DIG_CTRL_BASE + 0x003F)
214 #define WSA883X_CDC_SPK_DSM_C_3 (WSA883X_DIG_CTRL_BASE + 0x0040)
215 #define WSA883X_CDC_SPK_DSM_R1 (WSA883X_DIG_CTRL_BASE + 0x0041)
216 #define WSA883X_CDC_SPK_DSM_R2 (WSA883X_DIG_CTRL_BASE + 0x0042)
217 #define WSA883X_CDC_SPK_DSM_R3 (WSA883X_DIG_CTRL_BASE + 0x0043)
218 #define WSA883X_CDC_SPK_DSM_R4 (WSA883X_DIG_CTRL_BASE + 0x0044)
219 #define WSA883X_CDC_SPK_DSM_R5 (WSA883X_DIG_CTRL_BASE + 0x0045)
220 #define WSA883X_CDC_SPK_DSM_R6 (WSA883X_DIG_CTRL_BASE + 0x0046)
221 #define WSA883X_CDC_SPK_DSM_R7 (WSA883X_DIG_CTRL_BASE + 0x0047)
222 #define WSA883X_CDC_SPK_GAIN_PDM_0 (WSA883X_DIG_CTRL_BASE + 0x0048)
223 #define WSA883X_CDC_SPK_GAIN_PDM_1 (WSA883X_DIG_CTRL_BASE + 0x0049)
224 #define WSA883X_CDC_SPK_GAIN_PDM_2 (WSA883X_DIG_CTRL_BASE + 0x004A)
225 #define WSA883X_PDM_WD_CTL (WSA883X_DIG_CTRL_BASE + 0x004B)
226 #define WSA883X_PDM_EN_MASK BIT(0)
227 #define WSA883X_PDM_ENABLE BIT(0)
228 #define WSA883X_DEM_BYPASS_DATA0 (WSA883X_DIG_CTRL_BASE + 0x004C)
229 #define WSA883X_DEM_BYPASS_DATA1 (WSA883X_DIG_CTRL_BASE + 0x004D)
230 #define WSA883X_DEM_BYPASS_DATA2 (WSA883X_DIG_CTRL_BASE + 0x004E)
231 #define WSA883X_DEM_BYPASS_DATA3 (WSA883X_DIG_CTRL_BASE + 0x004F)
232 #define WSA883X_WAVG_CTL (WSA883X_DIG_CTRL_BASE + 0x0050)
233 #define WSA883X_WAVG_LRA_PER_0 (WSA883X_DIG_CTRL_BASE + 0x0051)
234 #define WSA883X_WAVG_LRA_PER_1 (WSA883X_DIG_CTRL_BASE + 0x0052)
235 #define WSA883X_WAVG_DELTA_THETA_0 (WSA883X_DIG_CTRL_BASE + 0x0053)
236 #define WSA883X_WAVG_DELTA_THETA_1 (WSA883X_DIG_CTRL_BASE + 0x0054)
237 #define WSA883X_WAVG_DIRECT_AMP_0 (WSA883X_DIG_CTRL_BASE + 0x0055)
238 #define WSA883X_WAVG_DIRECT_AMP_1 (WSA883X_DIG_CTRL_BASE + 0x0056)
239 #define WSA883X_WAVG_PTRN_AMP0_0 (WSA883X_DIG_CTRL_BASE + 0x0057)
240 #define WSA883X_WAVG_PTRN_AMP0_1 (WSA883X_DIG_CTRL_BASE + 0x0058)
241 #define WSA883X_WAVG_PTRN_AMP1_0 (WSA883X_DIG_CTRL_BASE + 0x0059)
242 #define WSA883X_WAVG_PTRN_AMP1_1 (WSA883X_DIG_CTRL_BASE + 0x005A)
243 #define WSA883X_WAVG_PTRN_AMP2_0 (WSA883X_DIG_CTRL_BASE + 0x005B)
244 #define WSA883X_WAVG_PTRN_AMP2_1 (WSA883X_DIG_CTRL_BASE + 0x005C)
245 #define WSA883X_WAVG_PTRN_AMP3_0 (WSA883X_DIG_CTRL_BASE + 0x005D)
246 #define WSA883X_WAVG_PTRN_AMP3_1 (WSA883X_DIG_CTRL_BASE + 0x005E)
247 #define WSA883X_WAVG_PTRN_AMP4_0 (WSA883X_DIG_CTRL_BASE + 0x005F)
248 #define WSA883X_WAVG_PTRN_AMP4_1 (WSA883X_DIG_CTRL_BASE + 0x0060)
249 #define WSA883X_WAVG_PTRN_AMP5_0 (WSA883X_DIG_CTRL_BASE + 0x0061)
250 #define WSA883X_WAVG_PTRN_AMP5_1 (WSA883X_DIG_CTRL_BASE + 0x0062)
251 #define WSA883X_WAVG_PTRN_AMP6_0 (WSA883X_DIG_CTRL_BASE + 0x0063)
252 #define WSA883X_WAVG_PTRN_AMP6_1 (WSA883X_DIG_CTRL_BASE + 0x0064)
253 #define WSA883X_WAVG_PTRN_AMP7_0 (WSA883X_DIG_CTRL_BASE + 0x0065)
254 #define WSA883X_WAVG_PTRN_AMP7_1 (WSA883X_DIG_CTRL_BASE + 0x0066)
255 #define WSA883X_WAVG_PER_0_1 (WSA883X_DIG_CTRL_BASE + 0x0067)
256 #define WSA883X_WAVG_PER_2_3 (WSA883X_DIG_CTRL_BASE + 0x0068)
257 #define WSA883X_WAVG_PER_4_5 (WSA883X_DIG_CTRL_BASE + 0x0069)
258 #define WSA883X_WAVG_PER_6_7 (WSA883X_DIG_CTRL_BASE + 0x006A)
259 #define WSA883X_WAVG_STA (WSA883X_DIG_CTRL_BASE + 0x006B)
260 #define WSA883X_DRE_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x006C)
261 #define WSA883X_DRE_OFFSET_MASK GENMASK(2, 0)
262 #define WSA883X_DRE_PROG_DELAY_MASK GENMASK(7, 4)
263 #define WSA883X_DRE_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x006D)
264 #define WSA883X_DRE_GAIN_EN_MASK BIT(0)
265 #define WSA883X_DRE_GAIN_FROM_CSR 1
266 #define WSA883X_DRE_IDLE_DET_CTL (WSA883X_DIG_CTRL_BASE + 0x006E)
267 #define WSA883X_CLSH_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x0070)
268 #define WSA883X_CLSH_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x0071)
269 #define WSA883X_CLSH_V_HD_PA (WSA883X_DIG_CTRL_BASE + 0x0072)
270 #define WSA883X_CLSH_V_PA_MIN (WSA883X_DIG_CTRL_BASE + 0x0073)
271 #define WSA883X_CLSH_OVRD_VAL (WSA883X_DIG_CTRL_BASE + 0x0074)
272 #define WSA883X_CLSH_HARD_MAX (WSA883X_DIG_CTRL_BASE + 0x0075)
273 #define WSA883X_CLSH_SOFT_MAX (WSA883X_DIG_CTRL_BASE + 0x0076)
274 #define WSA883X_CLSH_SIG_DP (WSA883X_DIG_CTRL_BASE + 0x0077)
275 #define WSA883X_TAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x0078)
276 #define WSA883X_TAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x0079)
277 #define WSA883X_TAGC_E2E_GAIN (WSA883X_DIG_CTRL_BASE + 0x007A)
278 #define WSA883X_TAGC_FORCE_VAL (WSA883X_DIG_CTRL_BASE + 0x007B)
279 #define WSA883X_VAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x007C)
280 #define WSA883X_VAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x007D)
281 #define WSA883X_VAGC_ATTN_LVL_1_2 (WSA883X_DIG_CTRL_BASE + 0x007E)
282 #define WSA883X_VAGC_ATTN_LVL_3 (WSA883X_DIG_CTRL_BASE + 0x007F)
283 #define WSA883X_INTR_MODE (WSA883X_DIG_CTRL_BASE + 0x0080)
284 #define WSA883X_INTR_MASK0 (WSA883X_DIG_CTRL_BASE + 0x0081)
285 #define WSA883X_INTR_MASK1 (WSA883X_DIG_CTRL_BASE + 0x0082)
286 #define WSA883X_INTR_STATUS0 (WSA883X_DIG_CTRL_BASE + 0x0083)
287 #define WSA883X_INTR_STATUS1 (WSA883X_DIG_CTRL_BASE + 0x0084)
288 #define WSA883X_INTR_CLEAR0 (WSA883X_DIG_CTRL_BASE + 0x0085)
289 #define WSA883X_INTR_CLEAR1 (WSA883X_DIG_CTRL_BASE + 0x0086)
290 #define WSA883X_INTR_LEVEL0 (WSA883X_DIG_CTRL_BASE + 0x0087)
291 #define WSA883X_INTR_LEVEL1 (WSA883X_DIG_CTRL_BASE + 0x0088)
292 #define WSA883X_INTR_SET0 (WSA883X_DIG_CTRL_BASE + 0x0089)
293 #define WSA883X_INTR_SET1 (WSA883X_DIG_CTRL_BASE + 0x008A)
294 #define WSA883X_INTR_TEST0 (WSA883X_DIG_CTRL_BASE + 0x008B)
295 #define WSA883X_INTR_TEST1 (WSA883X_DIG_CTRL_BASE + 0x008C)
296 #define WSA883X_OTP_CTRL0 (WSA883X_DIG_CTRL_BASE + 0x0090)
297 #define WSA883X_OTP_CTRL1 (WSA883X_DIG_CTRL_BASE + 0x0091)
298 #define WSA883X_HDRIVE_CTL_GROUP1 (WSA883X_DIG_CTRL_BASE + 0x0092)
299 #define WSA883X_PIN_CTL (WSA883X_DIG_CTRL_BASE + 0x0093)
300 #define WSA883X_PIN_CTL_OE (WSA883X_DIG_CTRL_BASE + 0x0094)
301 #define WSA883X_PIN_WDATA_IOPAD (WSA883X_DIG_CTRL_BASE + 0x0095)
302 #define WSA883X_PIN_STATUS (WSA883X_DIG_CTRL_BASE + 0x0096)
303 #define WSA883X_I2C_SLAVE_CTL (WSA883X_DIG_CTRL_BASE + 0x0097)
304 #define WSA883X_PDM_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A0)
305 #define WSA883X_ATE_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A1)
306 #define WSA883X_DIG_DEBUG_MODE (WSA883X_DIG_CTRL_BASE + 0x00A3)
307 #define WSA883X_DIG_DEBUG_SEL (WSA883X_DIG_CTRL_BASE + 0x00A4)
308 #define WSA883X_DIG_DEBUG_EN (WSA883X_DIG_CTRL_BASE + 0x00A5)
309 #define WSA883X_SWR_HM_TEST0 (WSA883X_DIG_CTRL_BASE + 0x00A6)
310 #define WSA883X_SWR_HM_TEST1 (WSA883X_DIG_CTRL_BASE + 0x00A7)
311 #define WSA883X_SWR_PAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00A8)
312 #define WSA883X_TADC_DETECT_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00A9)
313 #define WSA883X_TADC_DEBUG_MSB (WSA883X_DIG_CTRL_BASE + 0x00AA)
314 #define WSA883X_TADC_DEBUG_LSB (WSA883X_DIG_CTRL_BASE + 0x00AB)
315 #define WSA883X_SAMPLE_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AC)
316 #define WSA883X_SWR_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AD)
317 #define WSA883X_TEST_MODE_CTL (WSA883X_DIG_CTRL_BASE + 0x00AE)
318 #define WSA883X_IOPAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00AF)
319 #define WSA883X_ANA_CSR_DBG_ADD (WSA883X_DIG_CTRL_BASE + 0x00B0)
320 #define WSA883X_ANA_CSR_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00B1)
321 #define WSA883X_SPARE_R (WSA883X_DIG_CTRL_BASE + 0x00BC)
322 #define WSA883X_SPARE_0 (WSA883X_DIG_CTRL_BASE + 0x00BD)
323 #define WSA883X_SPARE_1 (WSA883X_DIG_CTRL_BASE + 0x00BE)
324 #define WSA883X_SPARE_2 (WSA883X_DIG_CTRL_BASE + 0x00BF)
325 #define WSA883X_SCODE (WSA883X_DIG_CTRL_BASE + 0x00C0)
326
327 #define WSA883X_DIG_TRIM_BASE (WSA883X_BASE + 0x00000500)
328 #define WSA883X_OTP_REG_0 (WSA883X_DIG_TRIM_BASE + 0x0080)
329 #define WSA883X_ID_MASK GENMASK(3, 0)
330 #define WSA883X_OTP_REG_1 (WSA883X_DIG_TRIM_BASE + 0x0081)
331 #define WSA883X_OTP_REG_2 (WSA883X_DIG_TRIM_BASE + 0x0082)
332 #define WSA883X_OTP_REG_3 (WSA883X_DIG_TRIM_BASE + 0x0083)
333 #define WSA883X_OTP_REG_4 (WSA883X_DIG_TRIM_BASE + 0x0084)
334 #define WSA883X_OTP_REG_5 (WSA883X_DIG_TRIM_BASE + 0x0085)
335 #define WSA883X_OTP_REG_6 (WSA883X_DIG_TRIM_BASE + 0x0086)
336 #define WSA883X_OTP_REG_7 (WSA883X_DIG_TRIM_BASE + 0x0087)
337 #define WSA883X_OTP_REG_8 (WSA883X_DIG_TRIM_BASE + 0x0088)
338 #define WSA883X_OTP_REG_9 (WSA883X_DIG_TRIM_BASE + 0x0089)
339 #define WSA883X_OTP_REG_10 (WSA883X_DIG_TRIM_BASE + 0x008A)
340 #define WSA883X_OTP_REG_11 (WSA883X_DIG_TRIM_BASE + 0x008B)
341 #define WSA883X_OTP_REG_12 (WSA883X_DIG_TRIM_BASE + 0x008C)
342 #define WSA883X_OTP_REG_13 (WSA883X_DIG_TRIM_BASE + 0x008D)
343 #define WSA883X_OTP_REG_14 (WSA883X_DIG_TRIM_BASE + 0x008E)
344 #define WSA883X_OTP_REG_15 (WSA883X_DIG_TRIM_BASE + 0x008F)
345 #define WSA883X_OTP_REG_16 (WSA883X_DIG_TRIM_BASE + 0x0090)
346 #define WSA883X_OTP_REG_17 (WSA883X_DIG_TRIM_BASE + 0x0091)
347 #define WSA883X_OTP_REG_18 (WSA883X_DIG_TRIM_BASE + 0x0092)
348 #define WSA883X_OTP_REG_19 (WSA883X_DIG_TRIM_BASE + 0x0093)
349 #define WSA883X_OTP_REG_20 (WSA883X_DIG_TRIM_BASE + 0x0094)
350 #define WSA883X_OTP_REG_21 (WSA883X_DIG_TRIM_BASE + 0x0095)
351 #define WSA883X_OTP_REG_22 (WSA883X_DIG_TRIM_BASE + 0x0096)
352 #define WSA883X_OTP_REG_23 (WSA883X_DIG_TRIM_BASE + 0x0097)
353 #define WSA883X_OTP_REG_24 (WSA883X_DIG_TRIM_BASE + 0x0098)
354 #define WSA883X_OTP_REG_25 (WSA883X_DIG_TRIM_BASE + 0x0099)
355 #define WSA883X_OTP_REG_26 (WSA883X_DIG_TRIM_BASE + 0x009A)
356 #define WSA883X_OTP_REG_27 (WSA883X_DIG_TRIM_BASE + 0x009B)
357 #define WSA883X_OTP_REG_28 (WSA883X_DIG_TRIM_BASE + 0x009C)
358 #define WSA883X_OTP_REG_29 (WSA883X_DIG_TRIM_BASE + 0x009D)
359 #define WSA883X_OTP_REG_30 (WSA883X_DIG_TRIM_BASE + 0x009E)
360 #define WSA883X_OTP_REG_31 (WSA883X_DIG_TRIM_BASE + 0x009F)
361 #define WSA883X_OTP_REG_32 (WSA883X_DIG_TRIM_BASE + 0x00A0)
362 #define WSA883X_OTP_REG_33 (WSA883X_DIG_TRIM_BASE + 0x00A1)
363 #define WSA883X_OTP_REG_34 (WSA883X_DIG_TRIM_BASE + 0x00A2)
364 #define WSA883X_OTP_REG_35 (WSA883X_DIG_TRIM_BASE + 0x00A3)
365 #define WSA883X_OTP_REG_63 (WSA883X_DIG_TRIM_BASE + 0x00BF)
366
367 #define WSA883X_DIG_EMEM_BASE (WSA883X_BASE + 0x000005C0)
368 #define WSA883X_EMEM_0 (WSA883X_DIG_EMEM_BASE + 0x0000)
369 #define WSA883X_EMEM_1 (WSA883X_DIG_EMEM_BASE + 0x0001)
370 #define WSA883X_EMEM_2 (WSA883X_DIG_EMEM_BASE + 0x0002)
371 #define WSA883X_EMEM_3 (WSA883X_DIG_EMEM_BASE + 0x0003)
372 #define WSA883X_EMEM_4 (WSA883X_DIG_EMEM_BASE + 0x0004)
373 #define WSA883X_EMEM_5 (WSA883X_DIG_EMEM_BASE + 0x0005)
374 #define WSA883X_EMEM_6 (WSA883X_DIG_EMEM_BASE + 0x0006)
375 #define WSA883X_EMEM_7 (WSA883X_DIG_EMEM_BASE + 0x0007)
376 #define WSA883X_EMEM_8 (WSA883X_DIG_EMEM_BASE + 0x0008)
377 #define WSA883X_EMEM_9 (WSA883X_DIG_EMEM_BASE + 0x0009)
378 #define WSA883X_EMEM_10 (WSA883X_DIG_EMEM_BASE + 0x000A)
379 #define WSA883X_EMEM_11 (WSA883X_DIG_EMEM_BASE + 0x000B)
380 #define WSA883X_EMEM_12 (WSA883X_DIG_EMEM_BASE + 0x000C)
381 #define WSA883X_EMEM_13 (WSA883X_DIG_EMEM_BASE + 0x000D)
382 #define WSA883X_EMEM_14 (WSA883X_DIG_EMEM_BASE + 0x000E)
383 #define WSA883X_EMEM_15 (WSA883X_DIG_EMEM_BASE + 0x000F)
384 #define WSA883X_EMEM_16 (WSA883X_DIG_EMEM_BASE + 0x0010)
385 #define WSA883X_EMEM_17 (WSA883X_DIG_EMEM_BASE + 0x0011)
386 #define WSA883X_EMEM_18 (WSA883X_DIG_EMEM_BASE + 0x0012)
387 #define WSA883X_EMEM_19 (WSA883X_DIG_EMEM_BASE + 0x0013)
388 #define WSA883X_EMEM_20 (WSA883X_DIG_EMEM_BASE + 0x0014)
389 #define WSA883X_EMEM_21 (WSA883X_DIG_EMEM_BASE + 0x0015)
390 #define WSA883X_EMEM_22 (WSA883X_DIG_EMEM_BASE + 0x0016)
391 #define WSA883X_EMEM_23 (WSA883X_DIG_EMEM_BASE + 0x0017)
392 #define WSA883X_EMEM_24 (WSA883X_DIG_EMEM_BASE + 0x0018)
393 #define WSA883X_EMEM_25 (WSA883X_DIG_EMEM_BASE + 0x0019)
394 #define WSA883X_EMEM_26 (WSA883X_DIG_EMEM_BASE + 0x001A)
395 #define WSA883X_EMEM_27 (WSA883X_DIG_EMEM_BASE + 0x001B)
396 #define WSA883X_EMEM_28 (WSA883X_DIG_EMEM_BASE + 0x001C)
397 #define WSA883X_EMEM_29 (WSA883X_DIG_EMEM_BASE + 0x001D)
398 #define WSA883X_EMEM_30 (WSA883X_DIG_EMEM_BASE + 0x001E)
399 #define WSA883X_EMEM_31 (WSA883X_DIG_EMEM_BASE + 0x001F)
400 #define WSA883X_EMEM_32 (WSA883X_DIG_EMEM_BASE + 0x0020)
401 #define WSA883X_EMEM_33 (WSA883X_DIG_EMEM_BASE + 0x0021)
402 #define WSA883X_EMEM_34 (WSA883X_DIG_EMEM_BASE + 0x0022)
403 #define WSA883X_EMEM_35 (WSA883X_DIG_EMEM_BASE + 0x0023)
404 #define WSA883X_EMEM_36 (WSA883X_DIG_EMEM_BASE + 0x0024)
405 #define WSA883X_EMEM_37 (WSA883X_DIG_EMEM_BASE + 0x0025)
406 #define WSA883X_EMEM_38 (WSA883X_DIG_EMEM_BASE + 0x0026)
407 #define WSA883X_EMEM_39 (WSA883X_DIG_EMEM_BASE + 0x0027)
408 #define WSA883X_EMEM_40 (WSA883X_DIG_EMEM_BASE + 0x0028)
409 #define WSA883X_EMEM_41 (WSA883X_DIG_EMEM_BASE + 0x0029)
410 #define WSA883X_EMEM_42 (WSA883X_DIG_EMEM_BASE + 0x002A)
411 #define WSA883X_EMEM_43 (WSA883X_DIG_EMEM_BASE + 0x002B)
412 #define WSA883X_EMEM_44 (WSA883X_DIG_EMEM_BASE + 0x002C)
413 #define WSA883X_EMEM_45 (WSA883X_DIG_EMEM_BASE + 0x002D)
414 #define WSA883X_EMEM_46 (WSA883X_DIG_EMEM_BASE + 0x002E)
415 #define WSA883X_EMEM_47 (WSA883X_DIG_EMEM_BASE + 0x002F)
416 #define WSA883X_EMEM_48 (WSA883X_DIG_EMEM_BASE + 0x0030)
417 #define WSA883X_EMEM_49 (WSA883X_DIG_EMEM_BASE + 0x0031)
418 #define WSA883X_EMEM_50 (WSA883X_DIG_EMEM_BASE + 0x0032)
419 #define WSA883X_EMEM_51 (WSA883X_DIG_EMEM_BASE + 0x0033)
420 #define WSA883X_EMEM_52 (WSA883X_DIG_EMEM_BASE + 0x0034)
421 #define WSA883X_EMEM_53 (WSA883X_DIG_EMEM_BASE + 0x0035)
422 #define WSA883X_EMEM_54 (WSA883X_DIG_EMEM_BASE + 0x0036)
423 #define WSA883X_EMEM_55 (WSA883X_DIG_EMEM_BASE + 0x0037)
424 #define WSA883X_EMEM_56 (WSA883X_DIG_EMEM_BASE + 0x0038)
425 #define WSA883X_EMEM_57 (WSA883X_DIG_EMEM_BASE + 0x0039)
426 #define WSA883X_EMEM_58 (WSA883X_DIG_EMEM_BASE + 0x003A)
427 #define WSA883X_EMEM_59 (WSA883X_DIG_EMEM_BASE + 0x003B)
428 #define WSA883X_EMEM_60 (WSA883X_DIG_EMEM_BASE + 0x003C)
429 #define WSA883X_EMEM_61 (WSA883X_DIG_EMEM_BASE + 0x003D)
430 #define WSA883X_EMEM_62 (WSA883X_DIG_EMEM_BASE + 0x003E)
431 #define WSA883X_EMEM_63 (WSA883X_DIG_EMEM_BASE + 0x003F)
432
433 #define WSA883X_NUM_REGISTERS (WSA883X_EMEM_63 + 1)
434 #define WSA883X_MAX_REGISTER (WSA883X_NUM_REGISTERS - 1)
435
436 #define WSA883X_VERSION_1_0 0
437 #define WSA883X_VERSION_1_1 1
438
439 #define WSA883X_MAX_SWR_PORTS 4
440 #define WSA883X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
441 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
442 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
443 SNDRV_PCM_RATE_384000)
444 /* Fractional Rates */
445 #define WSA883X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
446 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
447
448 #define WSA883X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
449 SNDRV_PCM_FMTBIT_S24_LE |\
450 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
451
452 /* Two-point trimming for temperature calibration */
453 #define WSA883X_T1_TEMP -10L
454 #define WSA883X_T2_TEMP 150L
455
456 /*
457 * Device will report senseless data in many cases, so discard any measurements
458 * outside of valid range.
459 */
460 #define WSA883X_LOW_TEMP_THRESHOLD 5
461 #define WSA883X_HIGH_TEMP_THRESHOLD 45
462
463 struct wsa883x_priv {
464 struct regmap *regmap;
465 struct device *dev;
466 struct regulator *vdd;
467 struct sdw_slave *slave;
468 struct sdw_stream_config sconfig;
469 struct sdw_stream_runtime *sruntime;
470 struct sdw_port_config port_config[WSA883X_MAX_SWR_PORTS];
471 struct gpio_desc *sd_n;
472 struct reset_control *sd_reset;
473 bool port_prepared[WSA883X_MAX_SWR_PORTS];
474 bool port_enable[WSA883X_MAX_SWR_PORTS];
475 int active_ports;
476 int dev_mode;
477 int comp_offset;
478 bool hw_init;
479 /*
480 * Protects temperature reading code (related to speaker protection) and
481 * fields: temperature and pa_on.
482 */
483 struct mutex sp_lock;
484 unsigned int temperature;
485 bool pa_on;
486 };
487
488 enum {
489 WSA8830 = 0,
490 WSA8835,
491 WSA8832,
492 WSA8835_V2 = 5,
493 };
494
495 enum {
496 COMP_OFFSET0,
497 COMP_OFFSET1,
498 COMP_OFFSET2,
499 COMP_OFFSET3,
500 COMP_OFFSET4,
501 };
502
503 enum wsa_port_ids {
504 WSA883X_PORT_DAC,
505 WSA883X_PORT_COMP,
506 WSA883X_PORT_BOOST,
507 WSA883X_PORT_VISENSE,
508 };
509
510 static const char * const wsa_dev_mode_text[] = {
511 "Speaker", "Receiver", "Ultrasound"
512 };
513
514 enum {
515 SPEAKER,
516 RECEIVER,
517 ULTRASOUND,
518 };
519
520 static const struct soc_enum wsa_dev_mode_enum =
521 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
522
523 /* 4 ports */
524 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA883X_MAX_SWR_PORTS] = {
525 [WSA883X_PORT_DAC] = {
526 .num = WSA883X_PORT_DAC + 1,
527 .type = SDW_DPN_SIMPLE,
528 .min_ch = 1,
529 .max_ch = 1,
530 .simple_ch_prep_sm = true,
531 .read_only_wordlength = true,
532 },
533 [WSA883X_PORT_COMP] = {
534 .num = WSA883X_PORT_COMP + 1,
535 .type = SDW_DPN_SIMPLE,
536 .min_ch = 1,
537 .max_ch = 1,
538 .simple_ch_prep_sm = true,
539 .read_only_wordlength = true,
540 },
541 [WSA883X_PORT_BOOST] = {
542 .num = WSA883X_PORT_BOOST + 1,
543 .type = SDW_DPN_SIMPLE,
544 .min_ch = 1,
545 .max_ch = 1,
546 .simple_ch_prep_sm = true,
547 .read_only_wordlength = true,
548 },
549 [WSA883X_PORT_VISENSE] = {
550 .num = WSA883X_PORT_VISENSE + 1,
551 .type = SDW_DPN_SIMPLE,
552 .min_ch = 1,
553 .max_ch = 1,
554 .simple_ch_prep_sm = true,
555 .read_only_wordlength = true,
556 }
557 };
558
559 static const struct sdw_port_config wsa883x_pconfig[WSA883X_MAX_SWR_PORTS] = {
560 [WSA883X_PORT_DAC] = {
561 .num = WSA883X_PORT_DAC + 1,
562 .ch_mask = 0x1,
563 },
564 [WSA883X_PORT_COMP] = {
565 .num = WSA883X_PORT_COMP + 1,
566 .ch_mask = 0xf,
567 },
568 [WSA883X_PORT_BOOST] = {
569 .num = WSA883X_PORT_BOOST + 1,
570 .ch_mask = 0x3,
571 },
572 [WSA883X_PORT_VISENSE] = {
573 .num = WSA883X_PORT_VISENSE + 1,
574 .ch_mask = 0x1,
575 },
576 };
577
578 static const struct reg_default wsa883x_defaults[] = {
579 { WSA883X_REF_CTRL, 0xD5 },
580 { WSA883X_TEST_CTL_0, 0x06 },
581 { WSA883X_BIAS_0, 0xD2 },
582 { WSA883X_OP_CTL, 0xE0 },
583 { WSA883X_IREF_CTL, 0x57 },
584 { WSA883X_ISENS_CTL, 0x47 },
585 { WSA883X_CLK_CTL, 0x87 },
586 { WSA883X_TEST_CTL_1, 0x00 },
587 { WSA883X_BIAS_1, 0x51 },
588 { WSA883X_ADC_CTL, 0x01 },
589 { WSA883X_DOUT_MSB, 0x00 },
590 { WSA883X_DOUT_LSB, 0x00 },
591 { WSA883X_VBAT_SNS, 0x40 },
592 { WSA883X_ITRIM_CODE, 0x9F },
593 { WSA883X_EN, 0x20 },
594 { WSA883X_OVERRIDE1, 0x00 },
595 { WSA883X_OVERRIDE2, 0x08 },
596 { WSA883X_VSENSE1, 0xD3 },
597 { WSA883X_ISENSE1, 0xD4 },
598 { WSA883X_ISENSE2, 0x20 },
599 { WSA883X_ISENSE_CAL, 0x00 },
600 { WSA883X_MISC, 0x08 },
601 { WSA883X_ADC_0, 0x00 },
602 { WSA883X_ADC_1, 0x00 },
603 { WSA883X_ADC_2, 0x40 },
604 { WSA883X_ADC_3, 0x80 },
605 { WSA883X_ADC_4, 0x25 },
606 { WSA883X_ADC_5, 0x25 },
607 { WSA883X_ADC_6, 0x08 },
608 { WSA883X_ADC_7, 0x81 },
609 { WSA883X_STATUS, 0x00 },
610 { WSA883X_DAC_CTRL_REG, 0x53 },
611 { WSA883X_DAC_EN_DEBUG_REG, 0x00 },
612 { WSA883X_DAC_OPAMP_BIAS1_REG, 0x48 },
613 { WSA883X_DAC_OPAMP_BIAS2_REG, 0x48 },
614 { WSA883X_DAC_VCM_CTRL_REG, 0x88 },
615 { WSA883X_DAC_VOLTAGE_CTRL_REG, 0xA5 },
616 { WSA883X_ATEST1_REG, 0x00 },
617 { WSA883X_ATEST2_REG, 0x00 },
618 { WSA883X_SPKR_TOP_BIAS_REG1, 0x6A },
619 { WSA883X_SPKR_TOP_BIAS_REG2, 0x65 },
620 { WSA883X_SPKR_TOP_BIAS_REG3, 0x55 },
621 { WSA883X_SPKR_TOP_BIAS_REG4, 0xA9 },
622 { WSA883X_SPKR_CLIP_DET_REG, 0x9C },
623 { WSA883X_SPKR_DRV_LF_BLK_EN, 0x0F },
624 { WSA883X_SPKR_DRV_LF_EN, 0x0A },
625 { WSA883X_SPKR_DRV_LF_MASK_DCC_CTL, 0x00 },
626 { WSA883X_SPKR_DRV_LF_MISC_CTL, 0x3A },
627 { WSA883X_SPKR_DRV_LF_REG_GAIN, 0x00 },
628 { WSA883X_SPKR_DRV_OS_CAL_CTL, 0x00 },
629 { WSA883X_SPKR_DRV_OS_CAL_CTL1, 0x90 },
630 { WSA883X_SPKR_PWM_CLK_CTL, 0x00 },
631 { WSA883X_SPKR_PDRV_HS_CTL, 0x52 },
632 { WSA883X_SPKR_PDRV_LS_CTL, 0x48 },
633 { WSA883X_SPKR_PWRSTG_DBG, 0x08 },
634 { WSA883X_SPKR_OCP_CTL, 0xE2 },
635 { WSA883X_SPKR_BBM_CTL, 0x92 },
636 { WSA883X_PA_STATUS0, 0x00 },
637 { WSA883X_PA_STATUS1, 0x00 },
638 { WSA883X_PA_STATUS2, 0x80 },
639 { WSA883X_EN_CTRL, 0x44 },
640 { WSA883X_CURRENT_LIMIT, 0xCC },
641 { WSA883X_IBIAS1, 0x00 },
642 { WSA883X_IBIAS2, 0x00 },
643 { WSA883X_IBIAS3, 0x00 },
644 { WSA883X_LDO_PROG, 0x02 },
645 { WSA883X_STABILITY_CTRL1, 0x8E },
646 { WSA883X_STABILITY_CTRL2, 0x10 },
647 { WSA883X_PWRSTAGE_CTRL1, 0x06 },
648 { WSA883X_PWRSTAGE_CTRL2, 0x00 },
649 { WSA883X_BYPASS_1, 0x19 },
650 { WSA883X_BYPASS_2, 0x13 },
651 { WSA883X_ZX_CTRL_1, 0xF0 },
652 { WSA883X_ZX_CTRL_2, 0x04 },
653 { WSA883X_MISC1, 0x06 },
654 { WSA883X_MISC2, 0xA0 },
655 { WSA883X_GMAMP_SUP1, 0x82 },
656 { WSA883X_PWRSTAGE_CTRL3, 0x39 },
657 { WSA883X_PWRSTAGE_CTRL4, 0x5F },
658 { WSA883X_TEST1, 0x00 },
659 { WSA883X_SPARE1, 0x00 },
660 { WSA883X_SPARE2, 0x00 },
661 { WSA883X_PON_CTL_0, 0x10 },
662 { WSA883X_PON_CLT_1, 0xE0 },
663 { WSA883X_PON_CTL_2, 0x90 },
664 { WSA883X_PON_CTL_3, 0x70 },
665 { WSA883X_CKWD_CTL_0, 0x34 },
666 { WSA883X_CKWD_CTL_1, 0x0F },
667 { WSA883X_CKWD_CTL_2, 0x00 },
668 { WSA883X_CKSK_CTL_0, 0x00 },
669 { WSA883X_PADSW_CTL_0, 0x00 },
670 { WSA883X_TEST_0, 0x00 },
671 { WSA883X_TEST_1, 0x00 },
672 { WSA883X_STATUS_0, 0x00 },
673 { WSA883X_STATUS_1, 0x00 },
674 { WSA883X_CHIP_ID0, 0x00 },
675 { WSA883X_CHIP_ID1, 0x00 },
676 { WSA883X_CHIP_ID2, 0x02 },
677 { WSA883X_CHIP_ID3, 0x02 },
678 { WSA883X_BUS_ID, 0x00 },
679 { WSA883X_CDC_RST_CTL, 0x01 },
680 { WSA883X_TOP_CLK_CFG, 0x00 },
681 { WSA883X_CDC_PATH_MODE, 0x00 },
682 { WSA883X_CDC_CLK_CTL, 0xFF },
683 { WSA883X_SWR_RESET_EN, 0x00 },
684 { WSA883X_RESET_CTL, 0x00 },
685 { WSA883X_PA_FSM_CTL, 0x00 },
686 { WSA883X_PA_FSM_TIMER0, 0x80 },
687 { WSA883X_PA_FSM_TIMER1, 0x80 },
688 { WSA883X_PA_FSM_STA, 0x00 },
689 { WSA883X_PA_FSM_ERR_COND, 0x00 },
690 { WSA883X_PA_FSM_MSK, 0x00 },
691 { WSA883X_PA_FSM_BYP, 0x01 },
692 { WSA883X_PA_FSM_DBG, 0x00 },
693 { WSA883X_TADC_VALUE_CTL, 0x03 },
694 { WSA883X_TEMP_DETECT_CTL, 0x01 },
695 { WSA883X_TEMP_MSB, 0x00 },
696 { WSA883X_TEMP_LSB, 0x00 },
697 { WSA883X_TEMP_CONFIG0, 0x00 },
698 { WSA883X_TEMP_CONFIG1, 0x00 },
699 { WSA883X_VBAT_ADC_FLT_CTL, 0x00 },
700 { WSA883X_VBAT_DIN_MSB, 0x00 },
701 { WSA883X_VBAT_DIN_LSB, 0x00 },
702 { WSA883X_VBAT_DOUT, 0x00 },
703 { WSA883X_SDM_PDM9_LSB, 0x00 },
704 { WSA883X_SDM_PDM9_MSB, 0x00 },
705 { WSA883X_CDC_RX_CTL, 0xFE },
706 { WSA883X_CDC_SPK_DSM_A1_0, 0x00 },
707 { WSA883X_CDC_SPK_DSM_A1_1, 0x01 },
708 { WSA883X_CDC_SPK_DSM_A2_0, 0x96 },
709 { WSA883X_CDC_SPK_DSM_A2_1, 0x09 },
710 { WSA883X_CDC_SPK_DSM_A3_0, 0xAB },
711 { WSA883X_CDC_SPK_DSM_A3_1, 0x05 },
712 { WSA883X_CDC_SPK_DSM_A4_0, 0x1C },
713 { WSA883X_CDC_SPK_DSM_A4_1, 0x02 },
714 { WSA883X_CDC_SPK_DSM_A5_0, 0x17 },
715 { WSA883X_CDC_SPK_DSM_A5_1, 0x02 },
716 { WSA883X_CDC_SPK_DSM_A6_0, 0xAA },
717 { WSA883X_CDC_SPK_DSM_A7_0, 0xE3 },
718 { WSA883X_CDC_SPK_DSM_C_0, 0x69 },
719 { WSA883X_CDC_SPK_DSM_C_1, 0x54 },
720 { WSA883X_CDC_SPK_DSM_C_2, 0x02 },
721 { WSA883X_CDC_SPK_DSM_C_3, 0x15 },
722 { WSA883X_CDC_SPK_DSM_R1, 0xA4 },
723 { WSA883X_CDC_SPK_DSM_R2, 0xB5 },
724 { WSA883X_CDC_SPK_DSM_R3, 0x86 },
725 { WSA883X_CDC_SPK_DSM_R4, 0x85 },
726 { WSA883X_CDC_SPK_DSM_R5, 0xAA },
727 { WSA883X_CDC_SPK_DSM_R6, 0xE2 },
728 { WSA883X_CDC_SPK_DSM_R7, 0x62 },
729 { WSA883X_CDC_SPK_GAIN_PDM_0, 0x00 },
730 { WSA883X_CDC_SPK_GAIN_PDM_1, 0xFC },
731 { WSA883X_CDC_SPK_GAIN_PDM_2, 0x05 },
732 { WSA883X_PDM_WD_CTL, 0x00 },
733 { WSA883X_DEM_BYPASS_DATA0, 0x00 },
734 { WSA883X_DEM_BYPASS_DATA1, 0x00 },
735 { WSA883X_DEM_BYPASS_DATA2, 0x00 },
736 { WSA883X_DEM_BYPASS_DATA3, 0x00 },
737 { WSA883X_WAVG_CTL, 0x06 },
738 { WSA883X_WAVG_LRA_PER_0, 0xD1 },
739 { WSA883X_WAVG_LRA_PER_1, 0x00 },
740 { WSA883X_WAVG_DELTA_THETA_0, 0xE6 },
741 { WSA883X_WAVG_DELTA_THETA_1, 0x04 },
742 { WSA883X_WAVG_DIRECT_AMP_0, 0x50 },
743 { WSA883X_WAVG_DIRECT_AMP_1, 0x00 },
744 { WSA883X_WAVG_PTRN_AMP0_0, 0x50 },
745 { WSA883X_WAVG_PTRN_AMP0_1, 0x00 },
746 { WSA883X_WAVG_PTRN_AMP1_0, 0x50 },
747 { WSA883X_WAVG_PTRN_AMP1_1, 0x00 },
748 { WSA883X_WAVG_PTRN_AMP2_0, 0x50 },
749 { WSA883X_WAVG_PTRN_AMP2_1, 0x00 },
750 { WSA883X_WAVG_PTRN_AMP3_0, 0x50 },
751 { WSA883X_WAVG_PTRN_AMP3_1, 0x00 },
752 { WSA883X_WAVG_PTRN_AMP4_0, 0x50 },
753 { WSA883X_WAVG_PTRN_AMP4_1, 0x00 },
754 { WSA883X_WAVG_PTRN_AMP5_0, 0x50 },
755 { WSA883X_WAVG_PTRN_AMP5_1, 0x00 },
756 { WSA883X_WAVG_PTRN_AMP6_0, 0x50 },
757 { WSA883X_WAVG_PTRN_AMP6_1, 0x00 },
758 { WSA883X_WAVG_PTRN_AMP7_0, 0x50 },
759 { WSA883X_WAVG_PTRN_AMP7_1, 0x00 },
760 { WSA883X_WAVG_PER_0_1, 0x88 },
761 { WSA883X_WAVG_PER_2_3, 0x88 },
762 { WSA883X_WAVG_PER_4_5, 0x88 },
763 { WSA883X_WAVG_PER_6_7, 0x88 },
764 { WSA883X_WAVG_STA, 0x00 },
765 { WSA883X_DRE_CTL_0, 0x70 },
766 { WSA883X_DRE_CTL_1, 0x08 },
767 { WSA883X_DRE_IDLE_DET_CTL, 0x1F },
768 { WSA883X_CLSH_CTL_0, 0x37 },
769 { WSA883X_CLSH_CTL_1, 0x81 },
770 { WSA883X_CLSH_V_HD_PA, 0x0F },
771 { WSA883X_CLSH_V_PA_MIN, 0x00 },
772 { WSA883X_CLSH_OVRD_VAL, 0x00 },
773 { WSA883X_CLSH_HARD_MAX, 0xFF },
774 { WSA883X_CLSH_SOFT_MAX, 0xF5 },
775 { WSA883X_CLSH_SIG_DP, 0x00 },
776 { WSA883X_TAGC_CTL, 0x10 },
777 { WSA883X_TAGC_TIME, 0x20 },
778 { WSA883X_TAGC_E2E_GAIN, 0x02 },
779 { WSA883X_TAGC_FORCE_VAL, 0x00 },
780 { WSA883X_VAGC_CTL, 0x00 },
781 { WSA883X_VAGC_TIME, 0x08 },
782 { WSA883X_VAGC_ATTN_LVL_1_2, 0x21 },
783 { WSA883X_VAGC_ATTN_LVL_3, 0x03 },
784 { WSA883X_INTR_MODE, 0x00 },
785 { WSA883X_INTR_MASK0, 0x90 },
786 { WSA883X_INTR_MASK1, 0x00 },
787 { WSA883X_INTR_STATUS0, 0x00 },
788 { WSA883X_INTR_STATUS1, 0x00 },
789 { WSA883X_INTR_CLEAR0, 0x00 },
790 { WSA883X_INTR_CLEAR1, 0x00 },
791 { WSA883X_INTR_LEVEL0, 0x00 },
792 { WSA883X_INTR_LEVEL1, 0x00 },
793 { WSA883X_INTR_SET0, 0x00 },
794 { WSA883X_INTR_SET1, 0x00 },
795 { WSA883X_INTR_TEST0, 0x00 },
796 { WSA883X_INTR_TEST1, 0x00 },
797 { WSA883X_OTP_CTRL0, 0x00 },
798 { WSA883X_OTP_CTRL1, 0x00 },
799 { WSA883X_HDRIVE_CTL_GROUP1, 0x00 },
800 { WSA883X_PIN_CTL, 0x04 },
801 { WSA883X_PIN_CTL_OE, 0x00 },
802 { WSA883X_PIN_WDATA_IOPAD, 0x00 },
803 { WSA883X_PIN_STATUS, 0x00 },
804 { WSA883X_I2C_SLAVE_CTL, 0x00 },
805 { WSA883X_PDM_TEST_MODE, 0x00 },
806 { WSA883X_ATE_TEST_MODE, 0x00 },
807 { WSA883X_DIG_DEBUG_MODE, 0x00 },
808 { WSA883X_DIG_DEBUG_SEL, 0x00 },
809 { WSA883X_DIG_DEBUG_EN, 0x00 },
810 { WSA883X_SWR_HM_TEST0, 0x08 },
811 { WSA883X_SWR_HM_TEST1, 0x00 },
812 { WSA883X_SWR_PAD_CTL, 0x37 },
813 { WSA883X_TADC_DETECT_DBG_CTL, 0x00 },
814 { WSA883X_TADC_DEBUG_MSB, 0x00 },
815 { WSA883X_TADC_DEBUG_LSB, 0x00 },
816 { WSA883X_SAMPLE_EDGE_SEL, 0x7F },
817 { WSA883X_SWR_EDGE_SEL, 0x00 },
818 { WSA883X_TEST_MODE_CTL, 0x04 },
819 { WSA883X_IOPAD_CTL, 0x00 },
820 { WSA883X_ANA_CSR_DBG_ADD, 0x00 },
821 { WSA883X_ANA_CSR_DBG_CTL, 0x12 },
822 { WSA883X_SPARE_R, 0x00 },
823 { WSA883X_SPARE_0, 0x00 },
824 { WSA883X_SPARE_1, 0x00 },
825 { WSA883X_SPARE_2, 0x00 },
826 { WSA883X_SCODE, 0x00 },
827 { WSA883X_OTP_REG_0, 0x05 },
828 { WSA883X_OTP_REG_1, 0xFF },
829 { WSA883X_OTP_REG_2, 0xC0 },
830 { WSA883X_OTP_REG_3, 0xFF },
831 { WSA883X_OTP_REG_4, 0xC0 },
832 { WSA883X_OTP_REG_5, 0xFF },
833 { WSA883X_OTP_REG_6, 0xFF },
834 { WSA883X_OTP_REG_7, 0xFF },
835 { WSA883X_OTP_REG_8, 0xFF },
836 { WSA883X_OTP_REG_9, 0xFF },
837 { WSA883X_OTP_REG_10, 0xFF },
838 { WSA883X_OTP_REG_11, 0xFF },
839 { WSA883X_OTP_REG_12, 0xFF },
840 { WSA883X_OTP_REG_13, 0xFF },
841 { WSA883X_OTP_REG_14, 0xFF },
842 { WSA883X_OTP_REG_15, 0xFF },
843 { WSA883X_OTP_REG_16, 0xFF },
844 { WSA883X_OTP_REG_17, 0xFF },
845 { WSA883X_OTP_REG_18, 0xFF },
846 { WSA883X_OTP_REG_19, 0xFF },
847 { WSA883X_OTP_REG_20, 0xFF },
848 { WSA883X_OTP_REG_21, 0xFF },
849 { WSA883X_OTP_REG_22, 0xFF },
850 { WSA883X_OTP_REG_23, 0xFF },
851 { WSA883X_OTP_REG_24, 0x37 },
852 { WSA883X_OTP_REG_25, 0x3F },
853 { WSA883X_OTP_REG_26, 0x03 },
854 { WSA883X_OTP_REG_27, 0x00 },
855 { WSA883X_OTP_REG_28, 0x00 },
856 { WSA883X_OTP_REG_29, 0x00 },
857 { WSA883X_OTP_REG_30, 0x00 },
858 { WSA883X_OTP_REG_31, 0x03 },
859 { WSA883X_OTP_REG_32, 0x00 },
860 { WSA883X_OTP_REG_33, 0xFF },
861 { WSA883X_OTP_REG_34, 0x00 },
862 { WSA883X_OTP_REG_35, 0x00 },
863 { WSA883X_OTP_REG_63, 0x40 },
864 { WSA883X_EMEM_0, 0x00 },
865 { WSA883X_EMEM_1, 0x00 },
866 { WSA883X_EMEM_2, 0x00 },
867 { WSA883X_EMEM_3, 0x00 },
868 { WSA883X_EMEM_4, 0x00 },
869 { WSA883X_EMEM_5, 0x00 },
870 { WSA883X_EMEM_6, 0x00 },
871 { WSA883X_EMEM_7, 0x00 },
872 { WSA883X_EMEM_8, 0x00 },
873 { WSA883X_EMEM_9, 0x00 },
874 { WSA883X_EMEM_10, 0x00 },
875 { WSA883X_EMEM_11, 0x00 },
876 { WSA883X_EMEM_12, 0x00 },
877 { WSA883X_EMEM_13, 0x00 },
878 { WSA883X_EMEM_14, 0x00 },
879 { WSA883X_EMEM_15, 0x00 },
880 { WSA883X_EMEM_16, 0x00 },
881 { WSA883X_EMEM_17, 0x00 },
882 { WSA883X_EMEM_18, 0x00 },
883 { WSA883X_EMEM_19, 0x00 },
884 { WSA883X_EMEM_20, 0x00 },
885 { WSA883X_EMEM_21, 0x00 },
886 { WSA883X_EMEM_22, 0x00 },
887 { WSA883X_EMEM_23, 0x00 },
888 { WSA883X_EMEM_24, 0x00 },
889 { WSA883X_EMEM_25, 0x00 },
890 { WSA883X_EMEM_26, 0x00 },
891 { WSA883X_EMEM_27, 0x00 },
892 { WSA883X_EMEM_28, 0x00 },
893 { WSA883X_EMEM_29, 0x00 },
894 { WSA883X_EMEM_30, 0x00 },
895 { WSA883X_EMEM_31, 0x00 },
896 { WSA883X_EMEM_32, 0x00 },
897 { WSA883X_EMEM_33, 0x00 },
898 { WSA883X_EMEM_34, 0x00 },
899 { WSA883X_EMEM_35, 0x00 },
900 { WSA883X_EMEM_36, 0x00 },
901 { WSA883X_EMEM_37, 0x00 },
902 { WSA883X_EMEM_38, 0x00 },
903 { WSA883X_EMEM_39, 0x00 },
904 { WSA883X_EMEM_40, 0x00 },
905 { WSA883X_EMEM_41, 0x00 },
906 { WSA883X_EMEM_42, 0x00 },
907 { WSA883X_EMEM_43, 0x00 },
908 { WSA883X_EMEM_44, 0x00 },
909 { WSA883X_EMEM_45, 0x00 },
910 { WSA883X_EMEM_46, 0x00 },
911 { WSA883X_EMEM_47, 0x00 },
912 { WSA883X_EMEM_48, 0x00 },
913 { WSA883X_EMEM_49, 0x00 },
914 { WSA883X_EMEM_50, 0x00 },
915 { WSA883X_EMEM_51, 0x00 },
916 { WSA883X_EMEM_52, 0x00 },
917 { WSA883X_EMEM_53, 0x00 },
918 { WSA883X_EMEM_54, 0x00 },
919 { WSA883X_EMEM_55, 0x00 },
920 { WSA883X_EMEM_56, 0x00 },
921 { WSA883X_EMEM_57, 0x00 },
922 { WSA883X_EMEM_58, 0x00 },
923 { WSA883X_EMEM_59, 0x00 },
924 { WSA883X_EMEM_60, 0x00 },
925 { WSA883X_EMEM_61, 0x00 },
926 { WSA883X_EMEM_62, 0x00 },
927 { WSA883X_EMEM_63, 0x00 },
928 };
929
wsa883x_readonly_register(struct device * dev,unsigned int reg)930 static bool wsa883x_readonly_register(struct device *dev, unsigned int reg)
931 {
932 switch (reg) {
933 case WSA883X_DOUT_MSB:
934 case WSA883X_DOUT_LSB:
935 case WSA883X_STATUS:
936 case WSA883X_PA_STATUS0:
937 case WSA883X_PA_STATUS1:
938 case WSA883X_PA_STATUS2:
939 case WSA883X_STATUS_0:
940 case WSA883X_STATUS_1:
941 case WSA883X_CHIP_ID0:
942 case WSA883X_CHIP_ID1:
943 case WSA883X_CHIP_ID2:
944 case WSA883X_CHIP_ID3:
945 case WSA883X_BUS_ID:
946 case WSA883X_PA_FSM_STA:
947 case WSA883X_PA_FSM_ERR_COND:
948 case WSA883X_TEMP_MSB:
949 case WSA883X_TEMP_LSB:
950 case WSA883X_VBAT_DIN_MSB:
951 case WSA883X_VBAT_DIN_LSB:
952 case WSA883X_VBAT_DOUT:
953 case WSA883X_SDM_PDM9_LSB:
954 case WSA883X_SDM_PDM9_MSB:
955 case WSA883X_WAVG_STA:
956 case WSA883X_INTR_STATUS0:
957 case WSA883X_INTR_STATUS1:
958 case WSA883X_OTP_CTRL1:
959 case WSA883X_PIN_STATUS:
960 case WSA883X_ATE_TEST_MODE:
961 case WSA883X_SWR_HM_TEST1:
962 case WSA883X_SPARE_R:
963 case WSA883X_OTP_REG_0:
964 return true;
965 }
966 return false;
967 }
968
wsa883x_writeable_register(struct device * dev,unsigned int reg)969 static bool wsa883x_writeable_register(struct device *dev, unsigned int reg)
970 {
971 return !wsa883x_readonly_register(dev, reg);
972 }
973
wsa883x_volatile_register(struct device * dev,unsigned int reg)974 static bool wsa883x_volatile_register(struct device *dev, unsigned int reg)
975 {
976 return wsa883x_readonly_register(dev, reg);
977 }
978
979 static const struct regmap_config wsa883x_regmap_config = {
980 .reg_bits = 32,
981 .val_bits = 8,
982 .cache_type = REGCACHE_MAPLE,
983 .reg_defaults = wsa883x_defaults,
984 .max_register = WSA883X_MAX_REGISTER,
985 .num_reg_defaults = ARRAY_SIZE(wsa883x_defaults),
986 .volatile_reg = wsa883x_volatile_register,
987 .writeable_reg = wsa883x_writeable_register,
988 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
989 .val_format_endian = REGMAP_ENDIAN_NATIVE,
990 .use_single_read = true,
991 };
992
993 static const struct reg_sequence reg_init[] = {
994 {WSA883X_PA_FSM_BYP, 0x00},
995 {WSA883X_ADC_6, 0x02},
996 {WSA883X_CDC_SPK_DSM_A2_0, 0x0A},
997 {WSA883X_CDC_SPK_DSM_A2_1, 0x08},
998 {WSA883X_CDC_SPK_DSM_A3_0, 0xF3},
999 {WSA883X_CDC_SPK_DSM_A3_1, 0x07},
1000 {WSA883X_CDC_SPK_DSM_A4_0, 0x79},
1001 {WSA883X_CDC_SPK_DSM_A4_1, 0x02},
1002 {WSA883X_CDC_SPK_DSM_A5_0, 0x0B},
1003 {WSA883X_CDC_SPK_DSM_A5_1, 0x02},
1004 {WSA883X_CDC_SPK_DSM_A6_0, 0x8A},
1005 {WSA883X_CDC_SPK_DSM_A7_0, 0x9B},
1006 {WSA883X_CDC_SPK_DSM_C_0, 0x68},
1007 {WSA883X_CDC_SPK_DSM_C_1, 0x54},
1008 {WSA883X_CDC_SPK_DSM_C_2, 0xF2},
1009 {WSA883X_CDC_SPK_DSM_C_3, 0x20},
1010 {WSA883X_CDC_SPK_DSM_R1, 0x83},
1011 {WSA883X_CDC_SPK_DSM_R2, 0x7F},
1012 {WSA883X_CDC_SPK_DSM_R3, 0x9D},
1013 {WSA883X_CDC_SPK_DSM_R4, 0x82},
1014 {WSA883X_CDC_SPK_DSM_R5, 0x8B},
1015 {WSA883X_CDC_SPK_DSM_R6, 0x9B},
1016 {WSA883X_CDC_SPK_DSM_R7, 0x3F},
1017 {WSA883X_VBAT_SNS, 0x20},
1018 {WSA883X_DRE_CTL_0, 0x92},
1019 {WSA883X_DRE_IDLE_DET_CTL, 0x0F},
1020 {WSA883X_CURRENT_LIMIT, 0xC4},
1021 {WSA883X_VAGC_TIME, 0x0F},
1022 {WSA883X_VAGC_ATTN_LVL_1_2, 0x00},
1023 {WSA883X_VAGC_ATTN_LVL_3, 0x01},
1024 {WSA883X_VAGC_CTL, 0x01},
1025 {WSA883X_TAGC_CTL, 0x1A},
1026 {WSA883X_TAGC_TIME, 0x2C},
1027 {WSA883X_TEMP_CONFIG0, 0x02},
1028 {WSA883X_TEMP_CONFIG1, 0x02},
1029 {WSA883X_OTP_REG_1, 0x49},
1030 {WSA883X_OTP_REG_2, 0x80},
1031 {WSA883X_OTP_REG_3, 0xC9},
1032 {WSA883X_OTP_REG_4, 0x40},
1033 {WSA883X_TAGC_CTL, 0x1B},
1034 {WSA883X_ADC_2, 0x00},
1035 {WSA883X_ADC_7, 0x85},
1036 {WSA883X_ADC_7, 0x87},
1037 {WSA883X_CKWD_CTL_0, 0x14},
1038 {WSA883X_CKWD_CTL_1, 0x1B},
1039 {WSA883X_GMAMP_SUP1, 0xE2},
1040 };
1041
wsa883x_init(struct wsa883x_priv * wsa883x)1042 static int wsa883x_init(struct wsa883x_priv *wsa883x)
1043 {
1044 struct regmap *regmap = wsa883x->regmap;
1045 int variant, version, ret;
1046
1047 if (wsa883x->hw_init)
1048 return 0;
1049
1050 ret = regmap_read(regmap, WSA883X_OTP_REG_0, &variant);
1051 if (ret)
1052 return ret;
1053 variant = variant & WSA883X_ID_MASK;
1054
1055 ret = regmap_read(regmap, WSA883X_CHIP_ID0, &version);
1056 if (ret)
1057 return ret;
1058
1059 switch (variant) {
1060 case WSA8830:
1061 dev_dbg(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8830\n",
1062 version);
1063 break;
1064 case WSA8835:
1065 dev_dbg(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835\n",
1066 version);
1067 break;
1068 case WSA8832:
1069 dev_dbg(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8832\n",
1070 version);
1071 break;
1072 case WSA8835_V2:
1073 dev_dbg(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835_V2\n",
1074 version);
1075 break;
1076 default:
1077 dev_warn(wsa883x->dev, "unknown variant: %d\n", variant);
1078 break;
1079 }
1080
1081 wsa883x->comp_offset = COMP_OFFSET2;
1082
1083 /* Initial settings */
1084 regmap_multi_reg_write(regmap, reg_init, ARRAY_SIZE(reg_init));
1085
1086 if (variant == WSA8830 || variant == WSA8832) {
1087 wsa883x->comp_offset = COMP_OFFSET3;
1088 regmap_update_bits(regmap, WSA883X_DRE_CTL_0,
1089 WSA883X_DRE_OFFSET_MASK,
1090 wsa883x->comp_offset);
1091 }
1092
1093 wsa883x->hw_init = true;
1094
1095 return 0;
1096 }
1097
wsa883x_update_status(struct sdw_slave * slave,enum sdw_slave_status status)1098 static int wsa883x_update_status(struct sdw_slave *slave,
1099 enum sdw_slave_status status)
1100 {
1101 struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
1102
1103 if (status == SDW_SLAVE_UNATTACHED)
1104 wsa883x->hw_init = false;
1105
1106 if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1107 return wsa883x_init(wsa883x);
1108
1109 return 0;
1110 }
1111
wsa883x_port_prep(struct sdw_slave * slave,struct sdw_prepare_ch * prepare_ch,enum sdw_port_prep_ops state)1112 static int wsa883x_port_prep(struct sdw_slave *slave,
1113 struct sdw_prepare_ch *prepare_ch,
1114 enum sdw_port_prep_ops state)
1115 {
1116 struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
1117
1118 if (state == SDW_OPS_PORT_POST_PREP)
1119 wsa883x->port_prepared[prepare_ch->num - 1] = true;
1120 else
1121 wsa883x->port_prepared[prepare_ch->num - 1] = false;
1122
1123 return 0;
1124 }
1125
1126 static const struct sdw_slave_ops wsa883x_slave_ops = {
1127 .update_status = wsa883x_update_status,
1128 .port_prep = wsa883x_port_prep,
1129 };
1130
wsa_dev_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1131 static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
1132 struct snd_ctl_elem_value *ucontrol)
1133 {
1134 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1135 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1136
1137 ucontrol->value.enumerated.item[0] = wsa883x->dev_mode;
1138
1139 return 0;
1140 }
1141
wsa_dev_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1142 static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
1143 struct snd_ctl_elem_value *ucontrol)
1144 {
1145 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1146 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1147
1148 if (wsa883x->dev_mode == ucontrol->value.enumerated.item[0])
1149 return 0;
1150
1151 wsa883x->dev_mode = ucontrol->value.enumerated.item[0];
1152
1153 return 1;
1154 }
1155
1156 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(pa_gain,
1157 0, 14, TLV_DB_SCALE_ITEM(-300, 0, 0),
1158 15, 29, TLV_DB_SCALE_ITEM(-300, 150, 0),
1159 30, 31, TLV_DB_SCALE_ITEM(1800, 0, 0),
1160 );
1161
wsa883x_get_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1162 static int wsa883x_get_swr_port(struct snd_kcontrol *kcontrol,
1163 struct snd_ctl_elem_value *ucontrol)
1164 {
1165 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
1166 struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
1167 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1168 int portidx = mixer->reg;
1169
1170 ucontrol->value.integer.value[0] = data->port_enable[portidx];
1171
1172 return 0;
1173 }
1174
wsa883x_set_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1175 static int wsa883x_set_swr_port(struct snd_kcontrol *kcontrol,
1176 struct snd_ctl_elem_value *ucontrol)
1177 {
1178 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
1179 struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
1180 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1181 int portidx = mixer->reg;
1182
1183 if (ucontrol->value.integer.value[0]) {
1184 if (data->port_enable[portidx])
1185 return 0;
1186
1187 data->port_enable[portidx] = true;
1188 } else {
1189 if (!data->port_enable[portidx])
1190 return 0;
1191
1192 data->port_enable[portidx] = false;
1193 }
1194
1195 return 1;
1196 }
1197
wsa883x_get_comp_offset(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1198 static int wsa883x_get_comp_offset(struct snd_kcontrol *kcontrol,
1199 struct snd_ctl_elem_value *ucontrol)
1200 {
1201 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1202 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1203
1204 ucontrol->value.integer.value[0] = wsa883x->comp_offset;
1205
1206 return 0;
1207 }
1208
wsa883x_set_comp_offset(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1209 static int wsa883x_set_comp_offset(struct snd_kcontrol *kcontrol,
1210 struct snd_ctl_elem_value *ucontrol)
1211 {
1212 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1213 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1214
1215 if (wsa883x->comp_offset == ucontrol->value.integer.value[0])
1216 return 0;
1217
1218 wsa883x->comp_offset = ucontrol->value.integer.value[0];
1219
1220 return 1;
1221 }
1222
wsa883x_codec_probe(struct snd_soc_component * comp)1223 static int wsa883x_codec_probe(struct snd_soc_component *comp)
1224 {
1225 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(comp);
1226
1227 snd_soc_component_init_regmap(comp, wsa883x->regmap);
1228
1229 return 0;
1230 }
1231
wsa883x_spkr_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1232 static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
1233 struct snd_kcontrol *kcontrol, int event)
1234 {
1235 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1236 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1237
1238 switch (event) {
1239 case SND_SOC_DAPM_POST_PMU:
1240 mutex_lock(&wsa883x->sp_lock);
1241 wsa883x->pa_on = true;
1242 mutex_unlock(&wsa883x->sp_lock);
1243
1244 switch (wsa883x->dev_mode) {
1245 case RECEIVER:
1246 snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
1247 WSA883X_RXD_MODE_MASK,
1248 WSA883X_RXD_MODE_HIFI);
1249 snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
1250 WSA883X_SPKR_PWM_FREQ_SEL_MASK,
1251 WSA883X_SPKR_PWM_FREQ_F600KHZ);
1252 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1253 WSA883X_DRE_PROG_DELAY_MASK, 0x0);
1254 break;
1255 case SPEAKER:
1256 snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
1257 WSA883X_RXD_MODE_MASK,
1258 WSA883X_RXD_MODE_NORMAL);
1259 snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
1260 WSA883X_SPKR_PWM_FREQ_SEL_MASK,
1261 WSA883X_SPKR_PWM_FREQ_F300KHZ);
1262 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1263 WSA883X_DRE_PROG_DELAY_MASK, 0x9);
1264 break;
1265 default:
1266 break;
1267 }
1268
1269 if (wsa883x->port_enable[WSA883X_PORT_COMP])
1270 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1271 WSA883X_DRE_OFFSET_MASK,
1272 wsa883x->comp_offset);
1273 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1274 WSA883X_VBAT_ADC_COEF_SEL_MASK,
1275 WSA883X_VBAT_ADC_COEF_F_1DIV16);
1276 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1277 WSA883X_VBAT_ADC_FLT_EN_MASK, 0x1);
1278 snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
1279 WSA883X_PDM_EN_MASK,
1280 WSA883X_PDM_ENABLE);
1281
1282 break;
1283 case SND_SOC_DAPM_PRE_PMD:
1284 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1285 WSA883X_VBAT_ADC_FLT_EN_MASK, 0x0);
1286 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1287 WSA883X_VBAT_ADC_COEF_SEL_MASK,
1288 WSA883X_VBAT_ADC_COEF_F_1DIV2);
1289 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1290 WSA883X_GLOBAL_PA_EN_MASK, 0);
1291 snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
1292 WSA883X_PDM_EN_MASK, 0);
1293 mutex_lock(&wsa883x->sp_lock);
1294 wsa883x->pa_on = false;
1295 mutex_unlock(&wsa883x->sp_lock);
1296 break;
1297 }
1298 return 0;
1299 }
1300
1301 static const struct snd_soc_dapm_widget wsa883x_dapm_widgets[] = {
1302 SND_SOC_DAPM_INPUT("IN"),
1303 SND_SOC_DAPM_SPK("SPKR", wsa883x_spkr_event),
1304 };
1305
1306 static const struct snd_kcontrol_new wsa883x_snd_controls[] = {
1307 SOC_SINGLE_RANGE_TLV("PA Volume", WSA883X_DRE_CTL_1, 1,
1308 0x0, 0x1f, 1, pa_gain),
1309 SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
1310 wsa_dev_mode_get, wsa_dev_mode_put),
1311 SOC_SINGLE_EXT("COMP Offset", SND_SOC_NOPM, 0, 4, 0,
1312 wsa883x_get_comp_offset, wsa883x_set_comp_offset),
1313 SOC_SINGLE_EXT("DAC Switch", WSA883X_PORT_DAC, 0, 1, 0,
1314 wsa883x_get_swr_port, wsa883x_set_swr_port),
1315 SOC_SINGLE_EXT("COMP Switch", WSA883X_PORT_COMP, 0, 1, 0,
1316 wsa883x_get_swr_port, wsa883x_set_swr_port),
1317 SOC_SINGLE_EXT("BOOST Switch", WSA883X_PORT_BOOST, 0, 1, 0,
1318 wsa883x_get_swr_port, wsa883x_set_swr_port),
1319 SOC_SINGLE_EXT("VISENSE Switch", WSA883X_PORT_VISENSE, 0, 1, 0,
1320 wsa883x_get_swr_port, wsa883x_set_swr_port),
1321 };
1322
1323 static const struct snd_soc_dapm_route wsa883x_audio_map[] = {
1324 {"SPKR", NULL, "IN"},
1325 };
1326
1327 static const struct snd_soc_component_driver wsa883x_component_drv = {
1328 .name = "WSA883x",
1329 .probe = wsa883x_codec_probe,
1330 .controls = wsa883x_snd_controls,
1331 .num_controls = ARRAY_SIZE(wsa883x_snd_controls),
1332 .dapm_widgets = wsa883x_dapm_widgets,
1333 .num_dapm_widgets = ARRAY_SIZE(wsa883x_dapm_widgets),
1334 .dapm_routes = wsa883x_audio_map,
1335 .num_dapm_routes = ARRAY_SIZE(wsa883x_audio_map),
1336 };
1337
wsa883x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1338 static int wsa883x_hw_params(struct snd_pcm_substream *substream,
1339 struct snd_pcm_hw_params *params,
1340 struct snd_soc_dai *dai)
1341 {
1342 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1343 int i;
1344
1345 wsa883x->active_ports = 0;
1346 for (i = 0; i < WSA883X_MAX_SWR_PORTS; i++) {
1347 if (!wsa883x->port_enable[i])
1348 continue;
1349
1350 wsa883x->port_config[wsa883x->active_ports] = wsa883x_pconfig[i];
1351 wsa883x->active_ports++;
1352 }
1353
1354 wsa883x->sconfig.frame_rate = params_rate(params);
1355
1356 return sdw_stream_add_slave(wsa883x->slave, &wsa883x->sconfig,
1357 wsa883x->port_config, wsa883x->active_ports,
1358 wsa883x->sruntime);
1359 }
1360
wsa883x_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1361 static int wsa883x_hw_free(struct snd_pcm_substream *substream,
1362 struct snd_soc_dai *dai)
1363 {
1364 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1365
1366 sdw_stream_remove_slave(wsa883x->slave, wsa883x->sruntime);
1367
1368 return 0;
1369 }
1370
wsa883x_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)1371 static int wsa883x_set_sdw_stream(struct snd_soc_dai *dai,
1372 void *stream, int direction)
1373 {
1374 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1375
1376 wsa883x->sruntime = stream;
1377
1378 return 0;
1379 }
1380
wsa883x_digital_mute(struct snd_soc_dai * dai,int mute,int stream)1381 static int wsa883x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1382 {
1383 struct snd_soc_component *component = dai->component;
1384
1385 if (mute) {
1386 snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1387 WSA883X_DRE_GAIN_EN_MASK, 0);
1388 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1389 WSA883X_GLOBAL_PA_EN_MASK, 0);
1390
1391 } else {
1392 snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1393 WSA883X_DRE_GAIN_EN_MASK,
1394 WSA883X_DRE_GAIN_FROM_CSR);
1395 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1396 WSA883X_GLOBAL_PA_EN_MASK,
1397 WSA883X_GLOBAL_PA_ENABLE);
1398
1399 }
1400
1401 return 0;
1402 }
1403
1404 static const struct snd_soc_dai_ops wsa883x_dai_ops = {
1405 .hw_params = wsa883x_hw_params,
1406 .hw_free = wsa883x_hw_free,
1407 .mute_stream = wsa883x_digital_mute,
1408 .set_stream = wsa883x_set_sdw_stream,
1409 .mute_unmute_on_trigger = true,
1410 };
1411
1412 static struct snd_soc_dai_driver wsa883x_dais[] = {
1413 {
1414 .name = "SPKR",
1415 .playback = {
1416 .stream_name = "SPKR Playback",
1417 .rates = WSA883X_RATES | WSA883X_FRAC_RATES,
1418 .formats = WSA883X_FORMATS,
1419 .rate_min = 8000,
1420 .rate_max = 352800,
1421 .channels_min = 1,
1422 .channels_max = 1,
1423 },
1424 .ops = &wsa883x_dai_ops,
1425 },
1426 };
1427
wsa883x_get_temp(struct wsa883x_priv * wsa883x,long * temp)1428 static int wsa883x_get_temp(struct wsa883x_priv *wsa883x, long *temp)
1429 {
1430 unsigned int d1_msb = 0, d1_lsb = 0, d2_msb = 0, d2_lsb = 0;
1431 unsigned int dmeas_msb = 0, dmeas_lsb = 0;
1432 int d1, d2, dmeas;
1433 unsigned int mask;
1434 int ret, range;
1435 long val;
1436
1437 guard(mutex)(&wsa883x->sp_lock);
1438
1439 if (wsa883x->pa_on) {
1440 /*
1441 * Reading temperature is possible only when Power Amplifier is
1442 * off. Report last cached data.
1443 */
1444 *temp = wsa883x->temperature * 1000;
1445 return 0;
1446 }
1447
1448 ret = pm_runtime_resume_and_get(wsa883x->dev);
1449 if (ret < 0)
1450 return ret;
1451
1452 mask = WSA883X_PA_FSM_BYP_DC_CAL_EN_MASK |
1453 WSA883X_PA_FSM_BYP_CLK_WD_EN_MASK |
1454 WSA883X_PA_FSM_BYP_BG_EN_MASK |
1455 WSA883X_PA_FSM_BYP_D_UNMUTE_MASK |
1456 WSA883X_PA_FSM_BYP_SPKR_PROT_EN_MASK |
1457 WSA883X_PA_FSM_BYP_TSADC_EN_MASK;
1458
1459 /*
1460 * Here and further do not care about read or update failures.
1461 * For example, before turning the amplifier on for the first
1462 * time, reading WSA883X_TEMP_DIN_MSB will always return 0.
1463 * Instead, check if returned value is within reasonable
1464 * thresholds.
1465 */
1466 regmap_update_bits(wsa883x->regmap, WSA883X_PA_FSM_BYP, mask, mask);
1467
1468 regmap_update_bits(wsa883x->regmap, WSA883X_TADC_VALUE_CTL,
1469 WSA883X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK,
1470 FIELD_PREP(WSA883X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK, 0x0));
1471
1472 regmap_read(wsa883x->regmap, WSA883X_TEMP_MSB, &dmeas_msb);
1473 regmap_read(wsa883x->regmap, WSA883X_TEMP_LSB, &dmeas_lsb);
1474
1475 regmap_update_bits(wsa883x->regmap, WSA883X_TADC_VALUE_CTL,
1476 WSA883X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK,
1477 FIELD_PREP(WSA883X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK, 0x1));
1478
1479 regmap_read(wsa883x->regmap, WSA883X_OTP_REG_1, &d1_msb);
1480 regmap_read(wsa883x->regmap, WSA883X_OTP_REG_2, &d1_lsb);
1481 regmap_read(wsa883x->regmap, WSA883X_OTP_REG_3, &d2_msb);
1482 regmap_read(wsa883x->regmap, WSA883X_OTP_REG_4, &d2_lsb);
1483
1484 regmap_update_bits(wsa883x->regmap, WSA883X_PA_FSM_BYP, mask, 0x0);
1485
1486 dmeas = (((dmeas_msb & 0xff) << 0x8) | (dmeas_lsb & 0xff)) >> 0x6;
1487 d1 = (((d1_msb & 0xff) << 0x8) | (d1_lsb & 0xff)) >> 0x6;
1488 d2 = (((d2_msb & 0xff) << 0x8) | (d2_lsb & 0xff)) >> 0x6;
1489
1490 if (d1 == d2) {
1491 /* Incorrect data in OTP? */
1492 ret = -EINVAL;
1493 goto out;
1494 }
1495
1496 val = WSA883X_T1_TEMP + (((dmeas - d1) * (WSA883X_T2_TEMP - WSA883X_T1_TEMP)) / (d2 - d1));
1497 range = WSA883X_HIGH_TEMP_THRESHOLD - WSA883X_LOW_TEMP_THRESHOLD;
1498 if (in_range(val, WSA883X_LOW_TEMP_THRESHOLD, range)) {
1499 wsa883x->temperature = val;
1500 *temp = val * 1000;
1501 ret = 0;
1502 } else {
1503 ret = -EAGAIN;
1504 }
1505 out:
1506 pm_runtime_put_autosuspend(wsa883x->dev);
1507
1508 return ret;
1509 }
1510
wsa883x_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)1511 static umode_t wsa883x_hwmon_is_visible(const void *data,
1512 enum hwmon_sensor_types type, u32 attr,
1513 int channel)
1514 {
1515 if (type != hwmon_temp)
1516 return 0;
1517
1518 switch (attr) {
1519 case hwmon_temp_input:
1520 return 0444;
1521 default:
1522 break;
1523 }
1524
1525 return 0;
1526 }
1527
wsa883x_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * temp)1528 static int wsa883x_hwmon_read(struct device *dev,
1529 enum hwmon_sensor_types type,
1530 u32 attr, int channel, long *temp)
1531 {
1532 int ret;
1533
1534 switch (attr) {
1535 case hwmon_temp_input:
1536 ret = wsa883x_get_temp(dev_get_drvdata(dev), temp);
1537 break;
1538 default:
1539 ret = -EOPNOTSUPP;
1540 break;
1541 }
1542
1543 return ret;
1544 }
1545
1546 static const struct hwmon_channel_info *const wsa883x_hwmon_info[] = {
1547 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
1548 NULL
1549 };
1550
1551 static const struct hwmon_ops wsa883x_hwmon_ops = {
1552 .is_visible = wsa883x_hwmon_is_visible,
1553 .read = wsa883x_hwmon_read,
1554 };
1555
1556 static const struct hwmon_chip_info wsa883x_hwmon_chip_info = {
1557 .ops = &wsa883x_hwmon_ops,
1558 .info = wsa883x_hwmon_info,
1559 };
1560
wsa883x_reset_assert(void * data)1561 static void wsa883x_reset_assert(void *data)
1562 {
1563 struct wsa883x_priv *wsa883x = data;
1564
1565 if (wsa883x->sd_reset)
1566 reset_control_assert(wsa883x->sd_reset);
1567 else
1568 gpiod_direction_output(wsa883x->sd_n, 1);
1569 }
1570
wsa883x_reset_deassert(struct wsa883x_priv * wsa883x)1571 static void wsa883x_reset_deassert(struct wsa883x_priv *wsa883x)
1572 {
1573 if (wsa883x->sd_reset)
1574 reset_control_deassert(wsa883x->sd_reset);
1575 else
1576 gpiod_direction_output(wsa883x->sd_n, 0);
1577 }
1578
wsa883x_get_reset(struct device * dev,struct wsa883x_priv * wsa883x)1579 static int wsa883x_get_reset(struct device *dev, struct wsa883x_priv *wsa883x)
1580 {
1581 wsa883x->sd_reset = devm_reset_control_get_optional_shared(dev, NULL);
1582 if (IS_ERR(wsa883x->sd_reset))
1583 return dev_err_probe(dev, PTR_ERR(wsa883x->sd_reset),
1584 "Failed to get reset\n");
1585
1586 /* if sd_reset: NULL, so use the backwards compatible way for powerdown-gpios */
1587 if (!wsa883x->sd_reset) {
1588 wsa883x->sd_n = devm_gpiod_get_optional(dev, "powerdown",
1589 GPIOD_OUT_HIGH);
1590 if (IS_ERR(wsa883x->sd_n))
1591 return dev_err_probe(dev, PTR_ERR(wsa883x->sd_n),
1592 "Shutdown Control GPIO not found\n");
1593 }
1594
1595 return 0;
1596 }
1597
wsa883x_probe(struct sdw_slave * pdev,const struct sdw_device_id * id)1598 static int wsa883x_probe(struct sdw_slave *pdev,
1599 const struct sdw_device_id *id)
1600 {
1601 struct wsa883x_priv *wsa883x;
1602 struct device *dev = &pdev->dev;
1603 int ret;
1604
1605 wsa883x = devm_kzalloc(dev, sizeof(*wsa883x), GFP_KERNEL);
1606 if (!wsa883x)
1607 return -ENOMEM;
1608
1609 wsa883x->vdd = devm_regulator_get(dev, "vdd");
1610 if (IS_ERR(wsa883x->vdd))
1611 return dev_err_probe(dev, PTR_ERR(wsa883x->vdd),
1612 "No vdd regulator found\n");
1613
1614 ret = regulator_enable(wsa883x->vdd);
1615 if (ret)
1616 return dev_err_probe(dev, ret, "Failed to enable vdd regulator\n");
1617
1618 ret = wsa883x_get_reset(dev, wsa883x);
1619 if (ret)
1620 goto err;
1621
1622 dev_set_drvdata(dev, wsa883x);
1623 wsa883x->slave = pdev;
1624 wsa883x->dev = dev;
1625 wsa883x->sconfig.ch_count = 1;
1626 wsa883x->sconfig.bps = 1;
1627 wsa883x->sconfig.direction = SDW_DATA_DIR_RX;
1628 wsa883x->sconfig.type = SDW_STREAM_PDM;
1629 mutex_init(&wsa883x->sp_lock);
1630
1631 /*
1632 * Port map index starts with 0, however the data port for this codec
1633 * are from index 1
1634 */
1635 if (of_property_read_u32_array(dev->of_node, "qcom,port-mapping", &pdev->m_port_map[1],
1636 WSA883X_MAX_SWR_PORTS))
1637 dev_dbg(dev, "Static Port mapping not specified\n");
1638
1639 pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS - 1, 0);
1640 pdev->prop.simple_clk_stop_capable = true;
1641 pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1642 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1643
1644 wsa883x_reset_deassert(wsa883x);
1645 ret = devm_add_action_or_reset(dev, wsa883x_reset_assert, wsa883x);
1646 if (ret)
1647 return ret;
1648
1649 wsa883x->regmap = devm_regmap_init_sdw(pdev, &wsa883x_regmap_config);
1650 if (IS_ERR(wsa883x->regmap)) {
1651 ret = dev_err_probe(dev, PTR_ERR(wsa883x->regmap),
1652 "regmap_init failed\n");
1653 goto err;
1654 }
1655
1656 if (IS_REACHABLE(CONFIG_HWMON)) {
1657 struct device *hwmon;
1658
1659 hwmon = devm_hwmon_device_register_with_info(dev, "wsa883x",
1660 wsa883x,
1661 &wsa883x_hwmon_chip_info,
1662 NULL);
1663 if (IS_ERR(hwmon))
1664 return dev_err_probe(dev, PTR_ERR(hwmon),
1665 "Failed to register hwmon sensor\n");
1666 }
1667
1668 pm_runtime_set_autosuspend_delay(dev, 3000);
1669 pm_runtime_use_autosuspend(dev);
1670 pm_runtime_mark_last_busy(dev);
1671 pm_runtime_set_active(dev);
1672 pm_runtime_enable(dev);
1673
1674 ret = devm_snd_soc_register_component(dev,
1675 &wsa883x_component_drv,
1676 wsa883x_dais,
1677 ARRAY_SIZE(wsa883x_dais));
1678 err:
1679 if (ret)
1680 regulator_disable(wsa883x->vdd);
1681
1682 return ret;
1683
1684 }
1685
wsa883x_runtime_suspend(struct device * dev)1686 static int wsa883x_runtime_suspend(struct device *dev)
1687 {
1688 struct regmap *regmap = dev_get_regmap(dev, NULL);
1689
1690 regcache_cache_only(regmap, true);
1691 regcache_mark_dirty(regmap);
1692
1693 return 0;
1694 }
1695
wsa883x_runtime_resume(struct device * dev)1696 static int wsa883x_runtime_resume(struct device *dev)
1697 {
1698 struct regmap *regmap = dev_get_regmap(dev, NULL);
1699
1700 regcache_cache_only(regmap, false);
1701 regcache_sync(regmap);
1702
1703 return 0;
1704 }
1705
1706 static const struct dev_pm_ops wsa883x_pm_ops = {
1707 RUNTIME_PM_OPS(wsa883x_runtime_suspend, wsa883x_runtime_resume, NULL)
1708 };
1709
1710 static const struct sdw_device_id wsa883x_swr_id[] = {
1711 SDW_SLAVE_ENTRY(0x0217, 0x0202, 0),
1712 {},
1713 };
1714
1715 MODULE_DEVICE_TABLE(sdw, wsa883x_swr_id);
1716
1717 static struct sdw_driver wsa883x_codec_driver = {
1718 .driver = {
1719 .name = "wsa883x-codec",
1720 .pm = pm_ptr(&wsa883x_pm_ops),
1721 .suppress_bind_attrs = true,
1722 },
1723 .probe = wsa883x_probe,
1724 .ops = &wsa883x_slave_ops,
1725 .id_table = wsa883x_swr_id,
1726 };
1727
1728 module_sdw_driver(wsa883x_codec_driver);
1729
1730 MODULE_DESCRIPTION("WSA883x codec driver");
1731 MODULE_LICENSE("GPL");
1732