1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2017, The Linux Foundation.
3 // Copyright (c) 2019, Linaro Limited
4
5 #include <linux/bitops.h>
6 #include <linux/gpio.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/module.h>
9 #include <linux/regmap.h>
10 #include <linux/slab.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/soundwire/sdw.h>
13 #include <linux/soundwire/sdw_registers.h>
14 #include <linux/soundwire/sdw_type.h>
15 #include <sound/soc.h>
16 #include <sound/tlv.h>
17
18 #define WSA881X_DIGITAL_BASE 0x3000
19 #define WSA881X_ANALOG_BASE 0x3100
20
21 /* Digital register address space */
22 #define WSA881X_CHIP_ID0 (WSA881X_DIGITAL_BASE + 0x0000)
23 #define WSA881X_CHIP_ID1 (WSA881X_DIGITAL_BASE + 0x0001)
24 #define WSA881X_CHIP_ID2 (WSA881X_DIGITAL_BASE + 0x0002)
25 #define WSA881X_CHIP_ID3 (WSA881X_DIGITAL_BASE + 0x0003)
26 #define WSA881X_BUS_ID (WSA881X_DIGITAL_BASE + 0x0004)
27 #define WSA881X_CDC_RST_CTL (WSA881X_DIGITAL_BASE + 0x0005)
28 #define WSA881X_CDC_TOP_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0006)
29 #define WSA881X_CDC_ANA_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0007)
30 #define WSA881X_CDC_DIG_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0008)
31 #define WSA881X_CLOCK_CONFIG (WSA881X_DIGITAL_BASE + 0x0009)
32 #define WSA881X_ANA_CTL (WSA881X_DIGITAL_BASE + 0x000A)
33 #define WSA881X_SWR_RESET_EN (WSA881X_DIGITAL_BASE + 0x000B)
34 #define WSA881X_RESET_CTL (WSA881X_DIGITAL_BASE + 0x000C)
35 #define WSA881X_TADC_VALUE_CTL (WSA881X_DIGITAL_BASE + 0x000F)
36 #define WSA881X_TEMP_DETECT_CTL (WSA881X_DIGITAL_BASE + 0x0010)
37 #define WSA881X_TEMP_MSB (WSA881X_DIGITAL_BASE + 0x0011)
38 #define WSA881X_TEMP_LSB (WSA881X_DIGITAL_BASE + 0x0012)
39 #define WSA881X_TEMP_CONFIG0 (WSA881X_DIGITAL_BASE + 0x0013)
40 #define WSA881X_TEMP_CONFIG1 (WSA881X_DIGITAL_BASE + 0x0014)
41 #define WSA881X_CDC_CLIP_CTL (WSA881X_DIGITAL_BASE + 0x0015)
42 #define WSA881X_SDM_PDM9_LSB (WSA881X_DIGITAL_BASE + 0x0016)
43 #define WSA881X_SDM_PDM9_MSB (WSA881X_DIGITAL_BASE + 0x0017)
44 #define WSA881X_CDC_RX_CTL (WSA881X_DIGITAL_BASE + 0x0018)
45 #define WSA881X_DEM_BYPASS_DATA0 (WSA881X_DIGITAL_BASE + 0x0019)
46 #define WSA881X_DEM_BYPASS_DATA1 (WSA881X_DIGITAL_BASE + 0x001A)
47 #define WSA881X_DEM_BYPASS_DATA2 (WSA881X_DIGITAL_BASE + 0x001B)
48 #define WSA881X_DEM_BYPASS_DATA3 (WSA881X_DIGITAL_BASE + 0x001C)
49 #define WSA881X_OTP_CTRL0 (WSA881X_DIGITAL_BASE + 0x001D)
50 #define WSA881X_OTP_CTRL1 (WSA881X_DIGITAL_BASE + 0x001E)
51 #define WSA881X_HDRIVE_CTL_GROUP1 (WSA881X_DIGITAL_BASE + 0x001F)
52 #define WSA881X_INTR_MODE (WSA881X_DIGITAL_BASE + 0x0020)
53 #define WSA881X_INTR_MASK (WSA881X_DIGITAL_BASE + 0x0021)
54 #define WSA881X_INTR_STATUS (WSA881X_DIGITAL_BASE + 0x0022)
55 #define WSA881X_INTR_CLEAR (WSA881X_DIGITAL_BASE + 0x0023)
56 #define WSA881X_INTR_LEVEL (WSA881X_DIGITAL_BASE + 0x0024)
57 #define WSA881X_INTR_SET (WSA881X_DIGITAL_BASE + 0x0025)
58 #define WSA881X_INTR_TEST (WSA881X_DIGITAL_BASE + 0x0026)
59 #define WSA881X_PDM_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0030)
60 #define WSA881X_ATE_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0031)
61 #define WSA881X_PIN_CTL_MODE (WSA881X_DIGITAL_BASE + 0x0032)
62 #define WSA881X_PIN_CTL_OE (WSA881X_DIGITAL_BASE + 0x0033)
63 #define WSA881X_PIN_WDATA_IOPAD (WSA881X_DIGITAL_BASE + 0x0034)
64 #define WSA881X_PIN_STATUS (WSA881X_DIGITAL_BASE + 0x0035)
65 #define WSA881X_DIG_DEBUG_MODE (WSA881X_DIGITAL_BASE + 0x0037)
66 #define WSA881X_DIG_DEBUG_SEL (WSA881X_DIGITAL_BASE + 0x0038)
67 #define WSA881X_DIG_DEBUG_EN (WSA881X_DIGITAL_BASE + 0x0039)
68 #define WSA881X_SWR_HM_TEST1 (WSA881X_DIGITAL_BASE + 0x003B)
69 #define WSA881X_SWR_HM_TEST2 (WSA881X_DIGITAL_BASE + 0x003C)
70 #define WSA881X_TEMP_DETECT_DBG_CTL (WSA881X_DIGITAL_BASE + 0x003D)
71 #define WSA881X_TEMP_DEBUG_MSB (WSA881X_DIGITAL_BASE + 0x003E)
72 #define WSA881X_TEMP_DEBUG_LSB (WSA881X_DIGITAL_BASE + 0x003F)
73 #define WSA881X_SAMPLE_EDGE_SEL (WSA881X_DIGITAL_BASE + 0x0044)
74 #define WSA881X_IOPAD_CTL (WSA881X_DIGITAL_BASE + 0x0045)
75 #define WSA881X_SPARE_0 (WSA881X_DIGITAL_BASE + 0x0050)
76 #define WSA881X_SPARE_1 (WSA881X_DIGITAL_BASE + 0x0051)
77 #define WSA881X_SPARE_2 (WSA881X_DIGITAL_BASE + 0x0052)
78 #define WSA881X_OTP_REG_0 (WSA881X_DIGITAL_BASE + 0x0080)
79 #define WSA881X_OTP_REG_1 (WSA881X_DIGITAL_BASE + 0x0081)
80 #define WSA881X_OTP_REG_2 (WSA881X_DIGITAL_BASE + 0x0082)
81 #define WSA881X_OTP_REG_3 (WSA881X_DIGITAL_BASE + 0x0083)
82 #define WSA881X_OTP_REG_4 (WSA881X_DIGITAL_BASE + 0x0084)
83 #define WSA881X_OTP_REG_5 (WSA881X_DIGITAL_BASE + 0x0085)
84 #define WSA881X_OTP_REG_6 (WSA881X_DIGITAL_BASE + 0x0086)
85 #define WSA881X_OTP_REG_7 (WSA881X_DIGITAL_BASE + 0x0087)
86 #define WSA881X_OTP_REG_8 (WSA881X_DIGITAL_BASE + 0x0088)
87 #define WSA881X_OTP_REG_9 (WSA881X_DIGITAL_BASE + 0x0089)
88 #define WSA881X_OTP_REG_10 (WSA881X_DIGITAL_BASE + 0x008A)
89 #define WSA881X_OTP_REG_11 (WSA881X_DIGITAL_BASE + 0x008B)
90 #define WSA881X_OTP_REG_12 (WSA881X_DIGITAL_BASE + 0x008C)
91 #define WSA881X_OTP_REG_13 (WSA881X_DIGITAL_BASE + 0x008D)
92 #define WSA881X_OTP_REG_14 (WSA881X_DIGITAL_BASE + 0x008E)
93 #define WSA881X_OTP_REG_15 (WSA881X_DIGITAL_BASE + 0x008F)
94 #define WSA881X_OTP_REG_16 (WSA881X_DIGITAL_BASE + 0x0090)
95 #define WSA881X_OTP_REG_17 (WSA881X_DIGITAL_BASE + 0x0091)
96 #define WSA881X_OTP_REG_18 (WSA881X_DIGITAL_BASE + 0x0092)
97 #define WSA881X_OTP_REG_19 (WSA881X_DIGITAL_BASE + 0x0093)
98 #define WSA881X_OTP_REG_20 (WSA881X_DIGITAL_BASE + 0x0094)
99 #define WSA881X_OTP_REG_21 (WSA881X_DIGITAL_BASE + 0x0095)
100 #define WSA881X_OTP_REG_22 (WSA881X_DIGITAL_BASE + 0x0096)
101 #define WSA881X_OTP_REG_23 (WSA881X_DIGITAL_BASE + 0x0097)
102 #define WSA881X_OTP_REG_24 (WSA881X_DIGITAL_BASE + 0x0098)
103 #define WSA881X_OTP_REG_25 (WSA881X_DIGITAL_BASE + 0x0099)
104 #define WSA881X_OTP_REG_26 (WSA881X_DIGITAL_BASE + 0x009A)
105 #define WSA881X_OTP_REG_27 (WSA881X_DIGITAL_BASE + 0x009B)
106 #define WSA881X_OTP_REG_28 (WSA881X_DIGITAL_BASE + 0x009C)
107 #define WSA881X_OTP_REG_29 (WSA881X_DIGITAL_BASE + 0x009D)
108 #define WSA881X_OTP_REG_30 (WSA881X_DIGITAL_BASE + 0x009E)
109 #define WSA881X_OTP_REG_31 (WSA881X_DIGITAL_BASE + 0x009F)
110 #define WSA881X_OTP_REG_63 (WSA881X_DIGITAL_BASE + 0x00BF)
111
112 /* Analog Register address space */
113 #define WSA881X_BIAS_REF_CTRL (WSA881X_ANALOG_BASE + 0x0000)
114 #define WSA881X_BIAS_TEST (WSA881X_ANALOG_BASE + 0x0001)
115 #define WSA881X_BIAS_BIAS (WSA881X_ANALOG_BASE + 0x0002)
116 #define WSA881X_TEMP_OP (WSA881X_ANALOG_BASE + 0x0003)
117 #define WSA881X_TEMP_IREF_CTRL (WSA881X_ANALOG_BASE + 0x0004)
118 #define WSA881X_TEMP_ISENS_CTRL (WSA881X_ANALOG_BASE + 0x0005)
119 #define WSA881X_TEMP_CLK_CTRL (WSA881X_ANALOG_BASE + 0x0006)
120 #define WSA881X_TEMP_TEST (WSA881X_ANALOG_BASE + 0x0007)
121 #define WSA881X_TEMP_BIAS (WSA881X_ANALOG_BASE + 0x0008)
122 #define WSA881X_TEMP_ADC_CTRL (WSA881X_ANALOG_BASE + 0x0009)
123 #define WSA881X_TEMP_DOUT_MSB (WSA881X_ANALOG_BASE + 0x000A)
124 #define WSA881X_TEMP_DOUT_LSB (WSA881X_ANALOG_BASE + 0x000B)
125 #define WSA881X_ADC_EN_MODU_V (WSA881X_ANALOG_BASE + 0x0010)
126 #define WSA881X_ADC_EN_MODU_I (WSA881X_ANALOG_BASE + 0x0011)
127 #define WSA881X_ADC_EN_DET_TEST_V (WSA881X_ANALOG_BASE + 0x0012)
128 #define WSA881X_ADC_EN_DET_TEST_I (WSA881X_ANALOG_BASE + 0x0013)
129 #define WSA881X_ADC_SEL_IBIAS (WSA881X_ANALOG_BASE + 0x0014)
130 #define WSA881X_ADC_EN_SEL_IBAIS (WSA881X_ANALOG_BASE + 0x0015)
131 #define WSA881X_SPKR_DRV_EN (WSA881X_ANALOG_BASE + 0x001A)
132 #define WSA881X_SPKR_DRV_GAIN (WSA881X_ANALOG_BASE + 0x001B)
133 #define WSA881X_PA_GAIN_SEL_MASK BIT(3)
134 #define WSA881X_PA_GAIN_SEL_REG BIT(3)
135 #define WSA881X_PA_GAIN_SEL_DRE 0
136 #define WSA881X_SPKR_PAG_GAIN_MASK GENMASK(7, 4)
137 #define WSA881X_SPKR_DAC_CTL (WSA881X_ANALOG_BASE + 0x001C)
138 #define WSA881X_SPKR_DRV_DBG (WSA881X_ANALOG_BASE + 0x001D)
139 #define WSA881X_SPKR_PWRSTG_DBG (WSA881X_ANALOG_BASE + 0x001E)
140 #define WSA881X_SPKR_OCP_CTL (WSA881X_ANALOG_BASE + 0x001F)
141 #define WSA881X_SPKR_OCP_MASK GENMASK(7, 6)
142 #define WSA881X_SPKR_OCP_EN BIT(7)
143 #define WSA881X_SPKR_OCP_HOLD BIT(6)
144 #define WSA881X_SPKR_CLIP_CTL (WSA881X_ANALOG_BASE + 0x0020)
145 #define WSA881X_SPKR_BBM_CTL (WSA881X_ANALOG_BASE + 0x0021)
146 #define WSA881X_SPKR_MISC_CTL1 (WSA881X_ANALOG_BASE + 0x0022)
147 #define WSA881X_SPKR_MISC_CTL2 (WSA881X_ANALOG_BASE + 0x0023)
148 #define WSA881X_SPKR_BIAS_INT (WSA881X_ANALOG_BASE + 0x0024)
149 #define WSA881X_SPKR_PA_INT (WSA881X_ANALOG_BASE + 0x0025)
150 #define WSA881X_SPKR_BIAS_CAL (WSA881X_ANALOG_BASE + 0x0026)
151 #define WSA881X_SPKR_BIAS_PSRR (WSA881X_ANALOG_BASE + 0x0027)
152 #define WSA881X_SPKR_STATUS1 (WSA881X_ANALOG_BASE + 0x0028)
153 #define WSA881X_SPKR_STATUS2 (WSA881X_ANALOG_BASE + 0x0029)
154 #define WSA881X_BOOST_EN_CTL (WSA881X_ANALOG_BASE + 0x002A)
155 #define WSA881X_BOOST_EN_MASK BIT(7)
156 #define WSA881X_BOOST_EN BIT(7)
157 #define WSA881X_BOOST_CURRENT_LIMIT (WSA881X_ANALOG_BASE + 0x002B)
158 #define WSA881X_BOOST_PS_CTL (WSA881X_ANALOG_BASE + 0x002C)
159 #define WSA881X_BOOST_PRESET_OUT1 (WSA881X_ANALOG_BASE + 0x002D)
160 #define WSA881X_BOOST_PRESET_OUT2 (WSA881X_ANALOG_BASE + 0x002E)
161 #define WSA881X_BOOST_FORCE_OUT (WSA881X_ANALOG_BASE + 0x002F)
162 #define WSA881X_BOOST_LDO_PROG (WSA881X_ANALOG_BASE + 0x0030)
163 #define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB (WSA881X_ANALOG_BASE + 0x0031)
164 #define WSA881X_BOOST_RON_CTL (WSA881X_ANALOG_BASE + 0x0032)
165 #define WSA881X_BOOST_LOOP_STABILITY (WSA881X_ANALOG_BASE + 0x0033)
166 #define WSA881X_BOOST_ZX_CTL (WSA881X_ANALOG_BASE + 0x0034)
167 #define WSA881X_BOOST_START_CTL (WSA881X_ANALOG_BASE + 0x0035)
168 #define WSA881X_BOOST_MISC1_CTL (WSA881X_ANALOG_BASE + 0x0036)
169 #define WSA881X_BOOST_MISC2_CTL (WSA881X_ANALOG_BASE + 0x0037)
170 #define WSA881X_BOOST_MISC3_CTL (WSA881X_ANALOG_BASE + 0x0038)
171 #define WSA881X_BOOST_ATEST_CTL (WSA881X_ANALOG_BASE + 0x0039)
172 #define WSA881X_SPKR_PROT_FE_GAIN (WSA881X_ANALOG_BASE + 0x003A)
173 #define WSA881X_SPKR_PROT_FE_CM_LDO_SET (WSA881X_ANALOG_BASE + 0x003B)
174 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x003C)
175 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2 (WSA881X_ANALOG_BASE + 0x003D)
176 #define WSA881X_SPKR_PROT_ATEST1 (WSA881X_ANALOG_BASE + 0x003E)
177 #define WSA881X_SPKR_PROT_ATEST2 (WSA881X_ANALOG_BASE + 0x003F)
178 #define WSA881X_SPKR_PROT_FE_VSENSE_VCM (WSA881X_ANALOG_BASE + 0x0040)
179 #define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x0041)
180 #define WSA881X_BONGO_RESRV_REG1 (WSA881X_ANALOG_BASE + 0x0042)
181 #define WSA881X_BONGO_RESRV_REG2 (WSA881X_ANALOG_BASE + 0x0043)
182 #define WSA881X_SPKR_PROT_SAR (WSA881X_ANALOG_BASE + 0x0044)
183 #define WSA881X_SPKR_STATUS3 (WSA881X_ANALOG_BASE + 0x0045)
184
185 #define SWRS_SCP_FRAME_CTRL_BANK(m) (0x60 + 0x10 * (m))
186 #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (0xE0 + 0x10 * (m))
187 #define SWR_SLV_MAX_REG_ADDR 0x390
188 #define SWR_SLV_START_REG_ADDR 0x40
189 #define SWR_SLV_MAX_BUF_LEN 20
190 #define BYTES_PER_LINE 12
191 #define SWR_SLV_RD_BUF_LEN 8
192 #define SWR_SLV_WR_BUF_LEN 32
193 #define SWR_SLV_MAX_DEVICES 2
194 #define WSA881X_MAX_SWR_PORTS 4
195 #define WSA881X_VERSION_ENTRY_SIZE 27
196 #define WSA881X_OCP_CTL_TIMER_SEC 2
197 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25
198 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60
199 #define WSA881X_PROBE_TIMEOUT 1000
200
201 #define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
202 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
203 snd_soc_get_volsw, wsa881x_put_pa_gain, tlv_array)
204
205 static const struct reg_default wsa881x_defaults[] = {
206 { WSA881X_CHIP_ID0, 0x00 },
207 { WSA881X_CHIP_ID1, 0x00 },
208 { WSA881X_CHIP_ID2, 0x00 },
209 { WSA881X_CHIP_ID3, 0x02 },
210 { WSA881X_BUS_ID, 0x00 },
211 { WSA881X_CDC_RST_CTL, 0x00 },
212 { WSA881X_CDC_TOP_CLK_CTL, 0x03 },
213 { WSA881X_CDC_ANA_CLK_CTL, 0x00 },
214 { WSA881X_CDC_DIG_CLK_CTL, 0x00 },
215 { WSA881X_CLOCK_CONFIG, 0x00 },
216 { WSA881X_ANA_CTL, 0x08 },
217 { WSA881X_SWR_RESET_EN, 0x00 },
218 { WSA881X_TEMP_DETECT_CTL, 0x01 },
219 { WSA881X_TEMP_MSB, 0x00 },
220 { WSA881X_TEMP_LSB, 0x00 },
221 { WSA881X_TEMP_CONFIG0, 0x00 },
222 { WSA881X_TEMP_CONFIG1, 0x00 },
223 { WSA881X_CDC_CLIP_CTL, 0x03 },
224 { WSA881X_SDM_PDM9_LSB, 0x00 },
225 { WSA881X_SDM_PDM9_MSB, 0x00 },
226 { WSA881X_CDC_RX_CTL, 0x7E },
227 { WSA881X_DEM_BYPASS_DATA0, 0x00 },
228 { WSA881X_DEM_BYPASS_DATA1, 0x00 },
229 { WSA881X_DEM_BYPASS_DATA2, 0x00 },
230 { WSA881X_DEM_BYPASS_DATA3, 0x00 },
231 { WSA881X_OTP_CTRL0, 0x00 },
232 { WSA881X_OTP_CTRL1, 0x00 },
233 { WSA881X_HDRIVE_CTL_GROUP1, 0x00 },
234 { WSA881X_INTR_MODE, 0x00 },
235 { WSA881X_INTR_STATUS, 0x00 },
236 { WSA881X_INTR_CLEAR, 0x00 },
237 { WSA881X_INTR_LEVEL, 0x00 },
238 { WSA881X_INTR_SET, 0x00 },
239 { WSA881X_INTR_TEST, 0x00 },
240 { WSA881X_PDM_TEST_MODE, 0x00 },
241 { WSA881X_ATE_TEST_MODE, 0x00 },
242 { WSA881X_PIN_CTL_MODE, 0x00 },
243 { WSA881X_PIN_CTL_OE, 0x00 },
244 { WSA881X_PIN_WDATA_IOPAD, 0x00 },
245 { WSA881X_PIN_STATUS, 0x00 },
246 { WSA881X_DIG_DEBUG_MODE, 0x00 },
247 { WSA881X_DIG_DEBUG_SEL, 0x00 },
248 { WSA881X_DIG_DEBUG_EN, 0x00 },
249 { WSA881X_SWR_HM_TEST1, 0x08 },
250 { WSA881X_SWR_HM_TEST2, 0x00 },
251 { WSA881X_TEMP_DETECT_DBG_CTL, 0x00 },
252 { WSA881X_TEMP_DEBUG_MSB, 0x00 },
253 { WSA881X_TEMP_DEBUG_LSB, 0x00 },
254 { WSA881X_SAMPLE_EDGE_SEL, 0x0C },
255 { WSA881X_SPARE_0, 0x00 },
256 { WSA881X_SPARE_1, 0x00 },
257 { WSA881X_SPARE_2, 0x00 },
258 { WSA881X_OTP_REG_0, 0x01 },
259 { WSA881X_OTP_REG_1, 0xFF },
260 { WSA881X_OTP_REG_2, 0xC0 },
261 { WSA881X_OTP_REG_3, 0xFF },
262 { WSA881X_OTP_REG_4, 0xC0 },
263 { WSA881X_OTP_REG_5, 0xFF },
264 { WSA881X_OTP_REG_6, 0xFF },
265 { WSA881X_OTP_REG_7, 0xFF },
266 { WSA881X_OTP_REG_8, 0xFF },
267 { WSA881X_OTP_REG_9, 0xFF },
268 { WSA881X_OTP_REG_10, 0xFF },
269 { WSA881X_OTP_REG_11, 0xFF },
270 { WSA881X_OTP_REG_12, 0xFF },
271 { WSA881X_OTP_REG_13, 0xFF },
272 { WSA881X_OTP_REG_14, 0xFF },
273 { WSA881X_OTP_REG_15, 0xFF },
274 { WSA881X_OTP_REG_16, 0xFF },
275 { WSA881X_OTP_REG_17, 0xFF },
276 { WSA881X_OTP_REG_18, 0xFF },
277 { WSA881X_OTP_REG_19, 0xFF },
278 { WSA881X_OTP_REG_20, 0xFF },
279 { WSA881X_OTP_REG_21, 0xFF },
280 { WSA881X_OTP_REG_22, 0xFF },
281 { WSA881X_OTP_REG_23, 0xFF },
282 { WSA881X_OTP_REG_24, 0x03 },
283 { WSA881X_OTP_REG_25, 0x01 },
284 { WSA881X_OTP_REG_26, 0x03 },
285 { WSA881X_OTP_REG_27, 0x11 },
286 { WSA881X_OTP_REG_63, 0x40 },
287 /* WSA881x Analog registers */
288 { WSA881X_BIAS_REF_CTRL, 0x6C },
289 { WSA881X_BIAS_TEST, 0x16 },
290 { WSA881X_BIAS_BIAS, 0xF0 },
291 { WSA881X_TEMP_OP, 0x00 },
292 { WSA881X_TEMP_IREF_CTRL, 0x56 },
293 { WSA881X_TEMP_ISENS_CTRL, 0x47 },
294 { WSA881X_TEMP_CLK_CTRL, 0x87 },
295 { WSA881X_TEMP_TEST, 0x00 },
296 { WSA881X_TEMP_BIAS, 0x51 },
297 { WSA881X_TEMP_DOUT_MSB, 0x00 },
298 { WSA881X_TEMP_DOUT_LSB, 0x00 },
299 { WSA881X_ADC_EN_MODU_V, 0x00 },
300 { WSA881X_ADC_EN_MODU_I, 0x00 },
301 { WSA881X_ADC_EN_DET_TEST_V, 0x00 },
302 { WSA881X_ADC_EN_DET_TEST_I, 0x00 },
303 { WSA881X_ADC_EN_SEL_IBAIS, 0x10 },
304 { WSA881X_SPKR_DRV_EN, 0x74 },
305 { WSA881X_SPKR_DRV_DBG, 0x15 },
306 { WSA881X_SPKR_PWRSTG_DBG, 0x00 },
307 { WSA881X_SPKR_OCP_CTL, 0xD4 },
308 { WSA881X_SPKR_CLIP_CTL, 0x90 },
309 { WSA881X_SPKR_PA_INT, 0x54 },
310 { WSA881X_SPKR_BIAS_CAL, 0xAC },
311 { WSA881X_SPKR_STATUS1, 0x00 },
312 { WSA881X_SPKR_STATUS2, 0x00 },
313 { WSA881X_BOOST_EN_CTL, 0x18 },
314 { WSA881X_BOOST_CURRENT_LIMIT, 0x7A },
315 { WSA881X_BOOST_PRESET_OUT2, 0x70 },
316 { WSA881X_BOOST_FORCE_OUT, 0x0E },
317 { WSA881X_BOOST_LDO_PROG, 0x16 },
318 { WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 },
319 { WSA881X_BOOST_RON_CTL, 0x0F },
320 { WSA881X_BOOST_ZX_CTL, 0x34 },
321 { WSA881X_BOOST_START_CTL, 0x23 },
322 { WSA881X_BOOST_MISC1_CTL, 0x80 },
323 { WSA881X_BOOST_MISC2_CTL, 0x00 },
324 { WSA881X_BOOST_MISC3_CTL, 0x00 },
325 { WSA881X_BOOST_ATEST_CTL, 0x00 },
326 { WSA881X_SPKR_PROT_FE_GAIN, 0x46 },
327 { WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B },
328 { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D },
329 { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D },
330 { WSA881X_SPKR_PROT_ATEST1, 0x01 },
331 { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D },
332 { WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D },
333 { WSA881X_SPKR_PROT_SAR, 0x00 },
334 { WSA881X_SPKR_STATUS3, 0x00 },
335 };
336
337 static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = {
338 { WSA881X_SPKR_DRV_GAIN, 0x41, 0 },
339 { WSA881X_SPKR_MISC_CTL1, 0x87, 0 },
340 };
341
342 static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = {
343 { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 },
344 { WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 },
345 { WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 },
346 };
347
348 /* Default register reset values for WSA881x rev 2.0 */
349 static const struct reg_sequence wsa881x_rev_2_0[] = {
350 { WSA881X_RESET_CTL, 0x00, 0x00 },
351 { WSA881X_TADC_VALUE_CTL, 0x01, 0x00 },
352 { WSA881X_INTR_MASK, 0x1B, 0x00 },
353 { WSA881X_IOPAD_CTL, 0x00, 0x00 },
354 { WSA881X_OTP_REG_28, 0x3F, 0x00 },
355 { WSA881X_OTP_REG_29, 0x3F, 0x00 },
356 { WSA881X_OTP_REG_30, 0x01, 0x00 },
357 { WSA881X_OTP_REG_31, 0x01, 0x00 },
358 { WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 },
359 { WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 },
360 { WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 },
361 { WSA881X_SPKR_DAC_CTL, 0x42, 0x00 },
362 { WSA881X_SPKR_BBM_CTL, 0x02, 0x00 },
363 { WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 },
364 { WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 },
365 { WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 },
366 { WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 },
367 { WSA881X_BOOST_PS_CTL, 0xA0, 0x00 },
368 { WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 },
369 { WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 },
370 { WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 },
371 { WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 },
372 { WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 },
373 };
374
375 enum wsa_port_ids {
376 WSA881X_PORT_DAC,
377 WSA881X_PORT_COMP,
378 WSA881X_PORT_BOOST,
379 WSA881X_PORT_VISENSE,
380 };
381
382 /* 4 ports */
383 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
384 [WSA881X_PORT_DAC] = {
385 .num = WSA881X_PORT_DAC + 1,
386 .type = SDW_DPN_SIMPLE,
387 .min_ch = 1,
388 .max_ch = 1,
389 .simple_ch_prep_sm = true,
390 .read_only_wordlength = true,
391 },
392 [WSA881X_PORT_COMP] = {
393 .num = WSA881X_PORT_COMP + 1,
394 .type = SDW_DPN_SIMPLE,
395 .min_ch = 1,
396 .max_ch = 1,
397 .simple_ch_prep_sm = true,
398 .read_only_wordlength = true,
399 },
400 [WSA881X_PORT_BOOST] = {
401 .num = WSA881X_PORT_BOOST + 1,
402 .type = SDW_DPN_SIMPLE,
403 .min_ch = 1,
404 .max_ch = 1,
405 .simple_ch_prep_sm = true,
406 .read_only_wordlength = true,
407 },
408 [WSA881X_PORT_VISENSE] = {
409 .num = WSA881X_PORT_VISENSE + 1,
410 .type = SDW_DPN_SIMPLE,
411 .min_ch = 1,
412 .max_ch = 1,
413 .simple_ch_prep_sm = true,
414 .read_only_wordlength = true,
415 }
416 };
417
418 static const struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = {
419 [WSA881X_PORT_DAC] = {
420 .num = WSA881X_PORT_DAC + 1,
421 .ch_mask = 0x1,
422 },
423 [WSA881X_PORT_COMP] = {
424 .num = WSA881X_PORT_COMP + 1,
425 .ch_mask = 0xf,
426 },
427 [WSA881X_PORT_BOOST] = {
428 .num = WSA881X_PORT_BOOST + 1,
429 .ch_mask = 0x3,
430 },
431 [WSA881X_PORT_VISENSE] = {
432 .num = WSA881X_PORT_VISENSE + 1,
433 .ch_mask = 0x3,
434 },
435 };
436
wsa881x_readable_register(struct device * dev,unsigned int reg)437 static bool wsa881x_readable_register(struct device *dev, unsigned int reg)
438 {
439 switch (reg) {
440 case WSA881X_CHIP_ID0:
441 case WSA881X_CHIP_ID1:
442 case WSA881X_CHIP_ID2:
443 case WSA881X_CHIP_ID3:
444 case WSA881X_BUS_ID:
445 case WSA881X_CDC_RST_CTL:
446 case WSA881X_CDC_TOP_CLK_CTL:
447 case WSA881X_CDC_ANA_CLK_CTL:
448 case WSA881X_CDC_DIG_CLK_CTL:
449 case WSA881X_CLOCK_CONFIG:
450 case WSA881X_ANA_CTL:
451 case WSA881X_SWR_RESET_EN:
452 case WSA881X_RESET_CTL:
453 case WSA881X_TADC_VALUE_CTL:
454 case WSA881X_TEMP_DETECT_CTL:
455 case WSA881X_TEMP_MSB:
456 case WSA881X_TEMP_LSB:
457 case WSA881X_TEMP_CONFIG0:
458 case WSA881X_TEMP_CONFIG1:
459 case WSA881X_CDC_CLIP_CTL:
460 case WSA881X_SDM_PDM9_LSB:
461 case WSA881X_SDM_PDM9_MSB:
462 case WSA881X_CDC_RX_CTL:
463 case WSA881X_DEM_BYPASS_DATA0:
464 case WSA881X_DEM_BYPASS_DATA1:
465 case WSA881X_DEM_BYPASS_DATA2:
466 case WSA881X_DEM_BYPASS_DATA3:
467 case WSA881X_OTP_CTRL0:
468 case WSA881X_OTP_CTRL1:
469 case WSA881X_HDRIVE_CTL_GROUP1:
470 case WSA881X_INTR_MODE:
471 case WSA881X_INTR_MASK:
472 case WSA881X_INTR_STATUS:
473 case WSA881X_INTR_CLEAR:
474 case WSA881X_INTR_LEVEL:
475 case WSA881X_INTR_SET:
476 case WSA881X_INTR_TEST:
477 case WSA881X_PDM_TEST_MODE:
478 case WSA881X_ATE_TEST_MODE:
479 case WSA881X_PIN_CTL_MODE:
480 case WSA881X_PIN_CTL_OE:
481 case WSA881X_PIN_WDATA_IOPAD:
482 case WSA881X_PIN_STATUS:
483 case WSA881X_DIG_DEBUG_MODE:
484 case WSA881X_DIG_DEBUG_SEL:
485 case WSA881X_DIG_DEBUG_EN:
486 case WSA881X_SWR_HM_TEST1:
487 case WSA881X_SWR_HM_TEST2:
488 case WSA881X_TEMP_DETECT_DBG_CTL:
489 case WSA881X_TEMP_DEBUG_MSB:
490 case WSA881X_TEMP_DEBUG_LSB:
491 case WSA881X_SAMPLE_EDGE_SEL:
492 case WSA881X_IOPAD_CTL:
493 case WSA881X_SPARE_0:
494 case WSA881X_SPARE_1:
495 case WSA881X_SPARE_2:
496 case WSA881X_OTP_REG_0:
497 case WSA881X_OTP_REG_1:
498 case WSA881X_OTP_REG_2:
499 case WSA881X_OTP_REG_3:
500 case WSA881X_OTP_REG_4:
501 case WSA881X_OTP_REG_5:
502 case WSA881X_OTP_REG_6:
503 case WSA881X_OTP_REG_7:
504 case WSA881X_OTP_REG_8:
505 case WSA881X_OTP_REG_9:
506 case WSA881X_OTP_REG_10:
507 case WSA881X_OTP_REG_11:
508 case WSA881X_OTP_REG_12:
509 case WSA881X_OTP_REG_13:
510 case WSA881X_OTP_REG_14:
511 case WSA881X_OTP_REG_15:
512 case WSA881X_OTP_REG_16:
513 case WSA881X_OTP_REG_17:
514 case WSA881X_OTP_REG_18:
515 case WSA881X_OTP_REG_19:
516 case WSA881X_OTP_REG_20:
517 case WSA881X_OTP_REG_21:
518 case WSA881X_OTP_REG_22:
519 case WSA881X_OTP_REG_23:
520 case WSA881X_OTP_REG_24:
521 case WSA881X_OTP_REG_25:
522 case WSA881X_OTP_REG_26:
523 case WSA881X_OTP_REG_27:
524 case WSA881X_OTP_REG_28:
525 case WSA881X_OTP_REG_29:
526 case WSA881X_OTP_REG_30:
527 case WSA881X_OTP_REG_31:
528 case WSA881X_OTP_REG_63:
529 case WSA881X_BIAS_REF_CTRL:
530 case WSA881X_BIAS_TEST:
531 case WSA881X_BIAS_BIAS:
532 case WSA881X_TEMP_OP:
533 case WSA881X_TEMP_IREF_CTRL:
534 case WSA881X_TEMP_ISENS_CTRL:
535 case WSA881X_TEMP_CLK_CTRL:
536 case WSA881X_TEMP_TEST:
537 case WSA881X_TEMP_BIAS:
538 case WSA881X_TEMP_ADC_CTRL:
539 case WSA881X_TEMP_DOUT_MSB:
540 case WSA881X_TEMP_DOUT_LSB:
541 case WSA881X_ADC_EN_MODU_V:
542 case WSA881X_ADC_EN_MODU_I:
543 case WSA881X_ADC_EN_DET_TEST_V:
544 case WSA881X_ADC_EN_DET_TEST_I:
545 case WSA881X_ADC_SEL_IBIAS:
546 case WSA881X_ADC_EN_SEL_IBAIS:
547 case WSA881X_SPKR_DRV_EN:
548 case WSA881X_SPKR_DRV_GAIN:
549 case WSA881X_SPKR_DAC_CTL:
550 case WSA881X_SPKR_DRV_DBG:
551 case WSA881X_SPKR_PWRSTG_DBG:
552 case WSA881X_SPKR_OCP_CTL:
553 case WSA881X_SPKR_CLIP_CTL:
554 case WSA881X_SPKR_BBM_CTL:
555 case WSA881X_SPKR_MISC_CTL1:
556 case WSA881X_SPKR_MISC_CTL2:
557 case WSA881X_SPKR_BIAS_INT:
558 case WSA881X_SPKR_PA_INT:
559 case WSA881X_SPKR_BIAS_CAL:
560 case WSA881X_SPKR_BIAS_PSRR:
561 case WSA881X_SPKR_STATUS1:
562 case WSA881X_SPKR_STATUS2:
563 case WSA881X_BOOST_EN_CTL:
564 case WSA881X_BOOST_CURRENT_LIMIT:
565 case WSA881X_BOOST_PS_CTL:
566 case WSA881X_BOOST_PRESET_OUT1:
567 case WSA881X_BOOST_PRESET_OUT2:
568 case WSA881X_BOOST_FORCE_OUT:
569 case WSA881X_BOOST_LDO_PROG:
570 case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB:
571 case WSA881X_BOOST_RON_CTL:
572 case WSA881X_BOOST_LOOP_STABILITY:
573 case WSA881X_BOOST_ZX_CTL:
574 case WSA881X_BOOST_START_CTL:
575 case WSA881X_BOOST_MISC1_CTL:
576 case WSA881X_BOOST_MISC2_CTL:
577 case WSA881X_BOOST_MISC3_CTL:
578 case WSA881X_BOOST_ATEST_CTL:
579 case WSA881X_SPKR_PROT_FE_GAIN:
580 case WSA881X_SPKR_PROT_FE_CM_LDO_SET:
581 case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1:
582 case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2:
583 case WSA881X_SPKR_PROT_ATEST1:
584 case WSA881X_SPKR_PROT_ATEST2:
585 case WSA881X_SPKR_PROT_FE_VSENSE_VCM:
586 case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1:
587 case WSA881X_BONGO_RESRV_REG1:
588 case WSA881X_BONGO_RESRV_REG2:
589 case WSA881X_SPKR_PROT_SAR:
590 case WSA881X_SPKR_STATUS3:
591 return true;
592 default:
593 return false;
594 }
595 }
596
wsa881x_volatile_register(struct device * dev,unsigned int reg)597 static bool wsa881x_volatile_register(struct device *dev, unsigned int reg)
598 {
599 switch (reg) {
600 case WSA881X_CHIP_ID0:
601 case WSA881X_CHIP_ID1:
602 case WSA881X_CHIP_ID2:
603 case WSA881X_CHIP_ID3:
604 case WSA881X_BUS_ID:
605 case WSA881X_TEMP_MSB:
606 case WSA881X_TEMP_LSB:
607 case WSA881X_SDM_PDM9_LSB:
608 case WSA881X_SDM_PDM9_MSB:
609 case WSA881X_OTP_CTRL1:
610 case WSA881X_INTR_STATUS:
611 case WSA881X_ATE_TEST_MODE:
612 case WSA881X_PIN_STATUS:
613 case WSA881X_SWR_HM_TEST2:
614 case WSA881X_SPKR_STATUS1:
615 case WSA881X_SPKR_STATUS2:
616 case WSA881X_SPKR_STATUS3:
617 case WSA881X_OTP_REG_0:
618 case WSA881X_OTP_REG_1:
619 case WSA881X_OTP_REG_2:
620 case WSA881X_OTP_REG_3:
621 case WSA881X_OTP_REG_4:
622 case WSA881X_OTP_REG_5:
623 case WSA881X_OTP_REG_31:
624 case WSA881X_TEMP_DOUT_MSB:
625 case WSA881X_TEMP_DOUT_LSB:
626 case WSA881X_TEMP_OP:
627 case WSA881X_SPKR_PROT_SAR:
628 return true;
629 default:
630 return false;
631 }
632 }
633
634 static const struct regmap_config wsa881x_regmap_config = {
635 .reg_bits = 32,
636 .val_bits = 8,
637 .cache_type = REGCACHE_MAPLE,
638 .reg_defaults = wsa881x_defaults,
639 .max_register = WSA881X_SPKR_STATUS3,
640 .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults),
641 .volatile_reg = wsa881x_volatile_register,
642 .readable_reg = wsa881x_readable_register,
643 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
644 .val_format_endian = REGMAP_ENDIAN_NATIVE,
645 };
646
647 enum {
648 G_18DB = 0,
649 G_16P5DB,
650 G_15DB,
651 G_13P5DB,
652 G_12DB,
653 G_10P5DB,
654 G_9DB,
655 G_7P5DB,
656 G_6DB,
657 G_4P5DB,
658 G_3DB,
659 G_1P5DB,
660 G_0DB,
661 };
662
663 /*
664 * Private data Structure for wsa881x. All parameters related to
665 * WSA881X codec needs to be defined here.
666 */
667 struct wsa881x_priv {
668 struct regmap *regmap;
669 struct device *dev;
670 struct sdw_slave *slave;
671 struct sdw_stream_config sconfig;
672 struct sdw_stream_runtime *sruntime;
673 struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS];
674 struct gpio_desc *sd_n;
675 /*
676 * Logical state for SD_N GPIO: high for shutdown, low for enable.
677 * For backwards compatibility.
678 */
679 unsigned int sd_n_val;
680 int active_ports;
681 bool port_prepared[WSA881X_MAX_SWR_PORTS];
682 bool port_enable[WSA881X_MAX_SWR_PORTS];
683 };
684
wsa881x_init(struct wsa881x_priv * wsa881x)685 static void wsa881x_init(struct wsa881x_priv *wsa881x)
686 {
687 struct regmap *rm = wsa881x->regmap;
688 unsigned int val = 0;
689
690 regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0,
691 ARRAY_SIZE(wsa881x_rev_2_0));
692
693 /* Enable software reset output from soundwire slave */
694 regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07);
695
696 /* Bring out of analog reset */
697 regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02);
698
699 /* Bring out of digital reset */
700 regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01);
701 regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10);
702 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02);
703 regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80);
704 regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06);
705 regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00);
706 regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40);
707 regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E);
708 regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03);
709 regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14);
710 regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80);
711 regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00);
712 regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04);
713 regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00);
714
715 regmap_read(rm, WSA881X_OTP_REG_0, &val);
716 if (val)
717 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70);
718
719 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30);
720 regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08);
721 regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08);
722 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30);
723 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00);
724 regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A);
725 regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2);
726 regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05);
727 }
728
wsa881x_component_probe(struct snd_soc_component * comp)729 static int wsa881x_component_probe(struct snd_soc_component *comp)
730 {
731 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
732
733 snd_soc_component_init_regmap(comp, wsa881x->regmap);
734
735 return 0;
736 }
737
wsa881x_put_pa_gain(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)738 static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
739 struct snd_ctl_elem_value *ucontrol)
740 {
741 struct snd_soc_component *comp = snd_soc_kcontrol_component(kc);
742 struct soc_mixer_control *mc =
743 (struct soc_mixer_control *)kc->private_value;
744 int max = mc->max;
745 unsigned int mask = (1 << fls(max)) - 1;
746 int val, ret, min_gain, max_gain;
747
748 ret = pm_runtime_resume_and_get(comp->dev);
749 if (ret < 0 && ret != -EACCES)
750 return ret;
751
752 max_gain = (max - ucontrol->value.integer.value[0]) & mask;
753 /*
754 * Gain has to set incrementally in 4 steps
755 * as per HW sequence
756 */
757 if (max_gain > G_4P5DB)
758 min_gain = G_0DB;
759 else
760 min_gain = max_gain + 3;
761 /*
762 * 1ms delay is needed before change in gain
763 * as per HW requirement.
764 */
765 usleep_range(1000, 1010);
766
767 for (val = min_gain; max_gain <= val; val--) {
768 ret = snd_soc_component_update_bits(comp,
769 WSA881X_SPKR_DRV_GAIN,
770 WSA881X_SPKR_PAG_GAIN_MASK,
771 val << 4);
772 if (ret < 0)
773 dev_err(comp->dev, "Failed to change PA gain");
774
775 usleep_range(1000, 1010);
776 }
777
778 pm_runtime_put_autosuspend(comp->dev);
779
780 return 1;
781 }
782
wsa881x_get_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)783 static int wsa881x_get_port(struct snd_kcontrol *kcontrol,
784 struct snd_ctl_elem_value *ucontrol)
785 {
786 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
787 struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
788 struct soc_mixer_control *mixer =
789 (struct soc_mixer_control *)kcontrol->private_value;
790 int portidx = mixer->reg;
791
792 ucontrol->value.integer.value[0] = data->port_enable[portidx];
793
794
795 return 0;
796 }
797
wsa881x_boost_ctrl(struct snd_soc_component * comp,bool enable)798 static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable)
799 {
800 if (enable)
801 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
802 WSA881X_BOOST_EN_MASK,
803 WSA881X_BOOST_EN);
804 else
805 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
806 WSA881X_BOOST_EN_MASK, 0);
807 /*
808 * 1.5ms sleep is needed after boost enable/disable as per
809 * HW requirement
810 */
811 usleep_range(1500, 1510);
812 return 0;
813 }
814
wsa881x_set_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)815 static int wsa881x_set_port(struct snd_kcontrol *kcontrol,
816 struct snd_ctl_elem_value *ucontrol)
817 {
818 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
819 struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
820 struct soc_mixer_control *mixer =
821 (struct soc_mixer_control *)kcontrol->private_value;
822 int portidx = mixer->reg;
823
824 if (ucontrol->value.integer.value[0]) {
825 if (data->port_enable[portidx])
826 return 0;
827
828 data->port_enable[portidx] = true;
829 } else {
830 if (!data->port_enable[portidx])
831 return 0;
832
833 data->port_enable[portidx] = false;
834 }
835
836 if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */
837 wsa881x_boost_ctrl(comp, data->port_enable[portidx]);
838
839 return 1;
840 }
841
842 static const char * const smart_boost_lvl_text[] = {
843 "6.625 V", "6.750 V", "6.875 V", "7.000 V",
844 "7.125 V", "7.250 V", "7.375 V", "7.500 V",
845 "7.625 V", "7.750 V", "7.875 V", "8.000 V",
846 "8.125 V", "8.250 V", "8.375 V", "8.500 V"
847 };
848
849 static const struct soc_enum smart_boost_lvl_enum =
850 SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0,
851 ARRAY_SIZE(smart_boost_lvl_text),
852 smart_boost_lvl_text);
853
854 static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0);
855
856 static const struct snd_kcontrol_new wsa881x_snd_controls[] = {
857 SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum),
858 WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN,
859 4, 0xC, 1, pa_gain),
860 SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0,
861 wsa881x_get_port, wsa881x_set_port),
862 SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0,
863 wsa881x_get_port, wsa881x_set_port),
864 SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0,
865 wsa881x_get_port, wsa881x_set_port),
866 SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0,
867 wsa881x_get_port, wsa881x_set_port),
868 };
869
870 static const struct snd_soc_dapm_route wsa881x_audio_map[] = {
871 { "RDAC", NULL, "IN" },
872 { "RDAC", NULL, "DCLK" },
873 { "RDAC", NULL, "ACLK" },
874 { "RDAC", NULL, "Bandgap" },
875 { "SPKR PGA", NULL, "RDAC" },
876 { "SPKR", NULL, "SPKR PGA" },
877 };
878
wsa881x_visense_txfe_ctrl(struct snd_soc_component * comp,bool enable)879 static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp,
880 bool enable)
881 {
882 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
883
884 if (enable) {
885 regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0,
886 ARRAY_SIZE(wsa881x_vi_txfe_en_2_0));
887 } else {
888 snd_soc_component_update_bits(comp,
889 WSA881X_SPKR_PROT_FE_VSENSE_VCM,
890 0x08, 0x08);
891 /*
892 * 200us sleep is needed after visense txfe disable as per
893 * HW requirement.
894 */
895 usleep_range(200, 210);
896 snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN,
897 0x01, 0x00);
898 }
899 return 0;
900 }
901
wsa881x_visense_adc_ctrl(struct snd_soc_component * comp,bool enable)902 static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp,
903 bool enable)
904 {
905 snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7),
906 (enable << 7));
907 snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7),
908 (enable << 7));
909 return 0;
910 }
911
wsa881x_spkr_pa_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)912 static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w,
913 struct snd_kcontrol *kcontrol, int event)
914 {
915 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
916 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
917
918 switch (event) {
919 case SND_SOC_DAPM_PRE_PMU:
920 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
921 WSA881X_SPKR_OCP_MASK,
922 WSA881X_SPKR_OCP_EN);
923 regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0,
924 ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0));
925
926 snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN,
927 WSA881X_PA_GAIN_SEL_MASK,
928 WSA881X_PA_GAIN_SEL_REG);
929 break;
930 case SND_SOC_DAPM_POST_PMU:
931 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
932 wsa881x_visense_txfe_ctrl(comp, true);
933 snd_soc_component_update_bits(comp,
934 WSA881X_ADC_EN_SEL_IBAIS,
935 0x07, 0x01);
936 wsa881x_visense_adc_ctrl(comp, true);
937 }
938
939 break;
940 case SND_SOC_DAPM_POST_PMD:
941 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
942 wsa881x_visense_adc_ctrl(comp, false);
943 wsa881x_visense_txfe_ctrl(comp, false);
944 }
945
946 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
947 WSA881X_SPKR_OCP_MASK,
948 WSA881X_SPKR_OCP_EN |
949 WSA881X_SPKR_OCP_HOLD);
950 break;
951 }
952 return 0;
953 }
954
955 static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = {
956 SND_SOC_DAPM_INPUT("IN"),
957 SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0,
958 NULL,
959 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
960 SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
961 wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU |
962 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
963 SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL,
964 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
965 SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL,
966 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
967 SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0,
968 NULL,
969 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
970 SND_SOC_DAPM_OUTPUT("SPKR"),
971 };
972
wsa881x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)973 static int wsa881x_hw_params(struct snd_pcm_substream *substream,
974 struct snd_pcm_hw_params *params,
975 struct snd_soc_dai *dai)
976 {
977 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
978 int i;
979
980 wsa881x->active_ports = 0;
981 for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) {
982 if (!wsa881x->port_enable[i])
983 continue;
984
985 wsa881x->port_config[wsa881x->active_ports] =
986 wsa881x_pconfig[i];
987 wsa881x->active_ports++;
988 }
989
990 return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig,
991 wsa881x->port_config, wsa881x->active_ports,
992 wsa881x->sruntime);
993 }
994
wsa881x_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)995 static int wsa881x_hw_free(struct snd_pcm_substream *substream,
996 struct snd_soc_dai *dai)
997 {
998 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
999
1000 sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime);
1001
1002 return 0;
1003 }
1004
wsa881x_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)1005 static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai,
1006 void *stream, int direction)
1007 {
1008 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1009
1010 wsa881x->sruntime = stream;
1011
1012 return 0;
1013 }
1014
wsa881x_digital_mute(struct snd_soc_dai * dai,int mute,int stream)1015 static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1016 {
1017 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1018
1019 if (mute)
1020 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1021 0x00);
1022 else
1023 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1024 0x80);
1025
1026 return 0;
1027 }
1028
1029 static const struct snd_soc_dai_ops wsa881x_dai_ops = {
1030 .hw_params = wsa881x_hw_params,
1031 .hw_free = wsa881x_hw_free,
1032 .mute_stream = wsa881x_digital_mute,
1033 .set_stream = wsa881x_set_sdw_stream,
1034 };
1035
1036 static struct snd_soc_dai_driver wsa881x_dais[] = {
1037 {
1038 .name = "SPKR",
1039 .id = 0,
1040 .playback = {
1041 .stream_name = "SPKR Playback",
1042 .rates = SNDRV_PCM_RATE_48000,
1043 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1044 .rate_max = 48000,
1045 .rate_min = 48000,
1046 .channels_min = 1,
1047 .channels_max = 1,
1048 },
1049 .ops = &wsa881x_dai_ops,
1050 },
1051 };
1052
1053 static const struct snd_soc_component_driver wsa881x_component_drv = {
1054 .name = "WSA881x",
1055 .probe = wsa881x_component_probe,
1056 .controls = wsa881x_snd_controls,
1057 .num_controls = ARRAY_SIZE(wsa881x_snd_controls),
1058 .dapm_widgets = wsa881x_dapm_widgets,
1059 .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets),
1060 .dapm_routes = wsa881x_audio_map,
1061 .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map),
1062 .endianness = 1,
1063 };
1064
wsa881x_update_status(struct sdw_slave * slave,enum sdw_slave_status status)1065 static int wsa881x_update_status(struct sdw_slave *slave,
1066 enum sdw_slave_status status)
1067 {
1068 struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1069
1070 if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1071 wsa881x_init(wsa881x);
1072
1073 return 0;
1074 }
1075
wsa881x_port_prep(struct sdw_slave * slave,struct sdw_prepare_ch * prepare_ch,enum sdw_port_prep_ops state)1076 static int wsa881x_port_prep(struct sdw_slave *slave,
1077 struct sdw_prepare_ch *prepare_ch,
1078 enum sdw_port_prep_ops state)
1079 {
1080 struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1081
1082 if (state == SDW_OPS_PORT_POST_PREP)
1083 wsa881x->port_prepared[prepare_ch->num - 1] = true;
1084 else
1085 wsa881x->port_prepared[prepare_ch->num - 1] = false;
1086
1087 return 0;
1088 }
1089
wsa881x_bus_config(struct sdw_slave * slave,struct sdw_bus_params * params)1090 static int wsa881x_bus_config(struct sdw_slave *slave,
1091 struct sdw_bus_params *params)
1092 {
1093 sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
1094 0x01);
1095
1096 return 0;
1097 }
1098
1099 static const struct sdw_slave_ops wsa881x_slave_ops = {
1100 .update_status = wsa881x_update_status,
1101 .bus_config = wsa881x_bus_config,
1102 .port_prep = wsa881x_port_prep,
1103 };
1104
wsa881x_probe(struct sdw_slave * pdev,const struct sdw_device_id * id)1105 static int wsa881x_probe(struct sdw_slave *pdev,
1106 const struct sdw_device_id *id)
1107 {
1108 struct wsa881x_priv *wsa881x;
1109 struct device *dev = &pdev->dev;
1110
1111 wsa881x = devm_kzalloc(dev, sizeof(*wsa881x), GFP_KERNEL);
1112 if (!wsa881x)
1113 return -ENOMEM;
1114
1115 wsa881x->sd_n = devm_gpiod_get_optional(dev, "powerdown",
1116 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1117 if (IS_ERR(wsa881x->sd_n))
1118 return dev_err_probe(dev, PTR_ERR(wsa881x->sd_n),
1119 "Shutdown Control GPIO not found\n");
1120
1121 /*
1122 * Backwards compatibility work-around.
1123 *
1124 * The SD_N GPIO is active low, however upstream DTS used always active
1125 * high. Changing the flag in driver and DTS will break backwards
1126 * compatibility, so add a simple value inversion to work with both old
1127 * and new DTS.
1128 *
1129 * This won't work properly with DTS using the flags properly in cases:
1130 * 1. Old DTS with proper ACTIVE_LOW, however such case was broken
1131 * before as the driver required the active high.
1132 * 2. New DTS with proper ACTIVE_HIGH (intended), which is rare case
1133 * (not existing upstream) but possible. This is the price of
1134 * backwards compatibility, therefore this hack should be removed at
1135 * some point.
1136 */
1137 wsa881x->sd_n_val = gpiod_is_active_low(wsa881x->sd_n);
1138 if (!wsa881x->sd_n_val)
1139 dev_warn(dev, "Using ACTIVE_HIGH for shutdown GPIO. Your DTB might be outdated or you use unsupported configuration for the GPIO.");
1140
1141 dev_set_drvdata(dev, wsa881x);
1142 wsa881x->slave = pdev;
1143 wsa881x->dev = dev;
1144 wsa881x->sconfig.ch_count = 1;
1145 wsa881x->sconfig.bps = 1;
1146 wsa881x->sconfig.frame_rate = 48000;
1147 wsa881x->sconfig.direction = SDW_DATA_DIR_RX;
1148 wsa881x->sconfig.type = SDW_STREAM_PDM;
1149 pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS - 1, 0);
1150 pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1151 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1152 pdev->prop.clk_stop_mode1 = true;
1153 gpiod_direction_output(wsa881x->sd_n, !wsa881x->sd_n_val);
1154
1155 wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config);
1156 if (IS_ERR(wsa881x->regmap))
1157 return dev_err_probe(dev, PTR_ERR(wsa881x->regmap), "regmap_init failed\n");
1158
1159 pm_runtime_set_autosuspend_delay(dev, 3000);
1160 pm_runtime_use_autosuspend(dev);
1161 pm_runtime_mark_last_busy(dev);
1162 pm_runtime_set_active(dev);
1163 pm_runtime_enable(dev);
1164
1165 return devm_snd_soc_register_component(dev,
1166 &wsa881x_component_drv,
1167 wsa881x_dais,
1168 ARRAY_SIZE(wsa881x_dais));
1169 }
1170
wsa881x_runtime_suspend(struct device * dev)1171 static int wsa881x_runtime_suspend(struct device *dev)
1172 {
1173 struct regmap *regmap = dev_get_regmap(dev, NULL);
1174 struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
1175
1176 gpiod_direction_output(wsa881x->sd_n, wsa881x->sd_n_val);
1177
1178 regcache_cache_only(regmap, true);
1179 regcache_mark_dirty(regmap);
1180
1181 return 0;
1182 }
1183
wsa881x_runtime_resume(struct device * dev)1184 static int wsa881x_runtime_resume(struct device *dev)
1185 {
1186 struct sdw_slave *slave = dev_to_sdw_dev(dev);
1187 struct regmap *regmap = dev_get_regmap(dev, NULL);
1188 struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
1189 unsigned long time;
1190
1191 gpiod_direction_output(wsa881x->sd_n, !wsa881x->sd_n_val);
1192
1193 time = wait_for_completion_timeout(&slave->initialization_complete,
1194 msecs_to_jiffies(WSA881X_PROBE_TIMEOUT));
1195 if (!time) {
1196 dev_err(dev, "Initialization not complete, timed out\n");
1197 gpiod_direction_output(wsa881x->sd_n, wsa881x->sd_n_val);
1198 return -ETIMEDOUT;
1199 }
1200
1201 regcache_cache_only(regmap, false);
1202 regcache_sync(regmap);
1203
1204 return 0;
1205 }
1206
1207 static const struct dev_pm_ops wsa881x_pm_ops = {
1208 RUNTIME_PM_OPS(wsa881x_runtime_suspend, wsa881x_runtime_resume, NULL)
1209 };
1210
1211 static const struct sdw_device_id wsa881x_slave_id[] = {
1212 SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
1213 SDW_SLAVE_ENTRY(0x0217, 0x2110, 0),
1214 {},
1215 };
1216 MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);
1217
1218 static struct sdw_driver wsa881x_codec_driver = {
1219 .probe = wsa881x_probe,
1220 .ops = &wsa881x_slave_ops,
1221 .id_table = wsa881x_slave_id,
1222 .driver = {
1223 .name = "wsa881x-codec",
1224 .pm = pm_ptr(&wsa881x_pm_ops),
1225 }
1226 };
1227 module_sdw_driver(wsa881x_codec_driver);
1228
1229 MODULE_DESCRIPTION("WSA881x codec driver");
1230 MODULE_LICENSE("GPL v2");
1231