1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel Whiskey Cove PMIC GPIO Driver
4 *
5 * This driver is written based on gpio-crystalcove.c
6 *
7 * Copyright (C) 2016 Intel Corporation. All rights reserved.
8 */
9
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/mfd/intel_soc_pmic.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/seq_file.h>
18 #include <linux/string_choices.h>
19
20 /*
21 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
22 * Bank 0: Pin 0 - 6
23 * Bank 1: Pin 7 - 10
24 * Bank 2: Pin 11 - 12
25 * Each pin has one output control register and one input control register.
26 */
27 #define BANK0_NR_PINS 7
28 #define BANK1_NR_PINS 4
29 #define BANK2_NR_PINS 2
30 #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
31 #define WCOVE_VGPIO_NUM 94
32 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
33 #define GPIO_OUT_CTRL_BASE 0x4e44
34 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
35 #define GPIO_IN_CTRL_BASE 0x4e51
36
37 /*
38 * GPIO interrupts are organized in two groups:
39 * Group 0: Bank 0 pins (Pin 0 - 6)
40 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
41 * Each group has two registers (one bit per pin): status and mask.
42 */
43 #define GROUP0_NR_IRQS 7
44 #define GROUP1_NR_IRQS 6
45 #define IRQ_MASK_BASE 0x4e19
46 #define IRQ_STATUS_BASE 0x4e0b
47 #define GPIO_IRQ0_MASK GENMASK(6, 0)
48 #define GPIO_IRQ1_MASK GENMASK(5, 0)
49 #define UPDATE_IRQ_TYPE BIT(0)
50 #define UPDATE_IRQ_MASK BIT(1)
51
52 #define CTLI_INTCNT_DIS (0 << 1)
53 #define CTLI_INTCNT_NE (1 << 1)
54 #define CTLI_INTCNT_PE (2 << 1)
55 #define CTLI_INTCNT_BE (3 << 1)
56
57 #define CTLO_DIR_IN (0 << 5)
58 #define CTLO_DIR_OUT (1 << 5)
59
60 #define CTLO_DRV_MASK (1 << 4)
61 #define CTLO_DRV_OD (0 << 4)
62 #define CTLO_DRV_CMOS (1 << 4)
63
64 #define CTLO_DRV_REN (1 << 3)
65
66 #define CTLO_RVAL_2KDOWN (0 << 1)
67 #define CTLO_RVAL_2KUP (1 << 1)
68 #define CTLO_RVAL_50KDOWN (2 << 1)
69 #define CTLO_RVAL_50KUP (3 << 1)
70
71 #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
72 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
73
74 enum ctrl_register {
75 CTRL_IN,
76 CTRL_OUT,
77 IRQ_STATUS,
78 IRQ_MASK,
79 };
80
81 /*
82 * struct wcove_gpio - Whiskey Cove GPIO controller
83 * @buslock: for bus lock/sync and unlock.
84 * @chip: the abstract gpio_chip structure.
85 * @dev: the gpio device
86 * @regmap: the regmap from the parent device.
87 * @regmap_irq_chip: the regmap of the gpio irq chip.
88 * @update: pending IRQ setting update, to be written to the chip upon unlock.
89 * @intcnt: the Interrupt Detect value to be written.
90 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
91 */
92 struct wcove_gpio {
93 struct mutex buslock;
94 struct gpio_chip chip;
95 struct device *dev;
96 struct regmap *regmap;
97 struct regmap_irq_chip_data *regmap_irq_chip;
98 int update;
99 int intcnt;
100 bool set_irq_mask;
101 };
102
to_reg(int gpio,enum ctrl_register type)103 static inline int to_reg(int gpio, enum ctrl_register type)
104 {
105 unsigned int reg = type == CTRL_IN ? GPIO_IN_CTRL_BASE : GPIO_OUT_CTRL_BASE;
106
107 if (gpio >= WCOVE_GPIO_NUM)
108 return -ENOTSUPP;
109
110 return reg + gpio;
111 }
112
to_ireg(int gpio,enum ctrl_register type,unsigned int * mask)113 static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask)
114 {
115 unsigned int reg = type == IRQ_STATUS ? IRQ_STATUS_BASE : IRQ_MASK_BASE;
116
117 if (gpio < GROUP0_NR_IRQS) {
118 reg += 0;
119 *mask = BIT(gpio);
120 } else {
121 reg += 1;
122 *mask = BIT(gpio - GROUP0_NR_IRQS);
123 }
124
125 return reg;
126 }
127
wcove_update_irq_mask(struct wcove_gpio * wg,irq_hw_number_t gpio)128 static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio)
129 {
130 unsigned int mask, reg = to_ireg(gpio, IRQ_MASK, &mask);
131
132 if (wg->set_irq_mask)
133 regmap_set_bits(wg->regmap, reg, mask);
134 else
135 regmap_clear_bits(wg->regmap, reg, mask);
136 }
137
wcove_update_irq_ctrl(struct wcove_gpio * wg,irq_hw_number_t gpio)138 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio)
139 {
140 int reg = to_reg(gpio, CTRL_IN);
141
142 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
143 }
144
wcove_gpio_dir_in(struct gpio_chip * chip,unsigned int gpio)145 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
146 {
147 struct wcove_gpio *wg = gpiochip_get_data(chip);
148 int reg = to_reg(gpio, CTRL_OUT);
149
150 if (reg < 0)
151 return 0;
152
153 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
154 }
155
wcove_gpio_dir_out(struct gpio_chip * chip,unsigned int gpio,int value)156 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
157 int value)
158 {
159 struct wcove_gpio *wg = gpiochip_get_data(chip);
160 int reg = to_reg(gpio, CTRL_OUT);
161
162 if (reg < 0)
163 return 0;
164
165 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
166 }
167
wcove_gpio_get_direction(struct gpio_chip * chip,unsigned int gpio)168 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
169 {
170 struct wcove_gpio *wg = gpiochip_get_data(chip);
171 unsigned int val;
172 int ret, reg = to_reg(gpio, CTRL_OUT);
173
174 if (reg < 0)
175 return GPIO_LINE_DIRECTION_OUT;
176
177 ret = regmap_read(wg->regmap, reg, &val);
178 if (ret)
179 return ret;
180
181 if (val & CTLO_DIR_OUT)
182 return GPIO_LINE_DIRECTION_OUT;
183
184 return GPIO_LINE_DIRECTION_IN;
185 }
186
wcove_gpio_get(struct gpio_chip * chip,unsigned int gpio)187 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
188 {
189 struct wcove_gpio *wg = gpiochip_get_data(chip);
190 unsigned int val;
191 int ret, reg = to_reg(gpio, CTRL_IN);
192
193 if (reg < 0)
194 return 0;
195
196 ret = regmap_read(wg->regmap, reg, &val);
197 if (ret)
198 return ret;
199
200 return val & 0x1;
201 }
202
wcove_gpio_set(struct gpio_chip * chip,unsigned int gpio,int value)203 static int wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
204 {
205 struct wcove_gpio *wg = gpiochip_get_data(chip);
206 int reg = to_reg(gpio, CTRL_OUT);
207
208 if (reg < 0)
209 return 0;
210
211 return regmap_assign_bits(wg->regmap, reg, 1, value);
212 }
213
wcove_gpio_set_config(struct gpio_chip * chip,unsigned int gpio,unsigned long config)214 static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
215 unsigned long config)
216 {
217 struct wcove_gpio *wg = gpiochip_get_data(chip);
218 int reg = to_reg(gpio, CTRL_OUT);
219
220 if (reg < 0)
221 return 0;
222
223 switch (pinconf_to_config_param(config)) {
224 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
225 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
226 CTLO_DRV_OD);
227 case PIN_CONFIG_DRIVE_PUSH_PULL:
228 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
229 CTLO_DRV_CMOS);
230 default:
231 break;
232 }
233
234 return -ENOTSUPP;
235 }
236
wcove_irq_type(struct irq_data * data,unsigned int type)237 static int wcove_irq_type(struct irq_data *data, unsigned int type)
238 {
239 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
240 struct wcove_gpio *wg = gpiochip_get_data(chip);
241 irq_hw_number_t gpio = irqd_to_hwirq(data);
242
243 if (gpio >= WCOVE_GPIO_NUM)
244 return 0;
245
246 switch (type) {
247 case IRQ_TYPE_NONE:
248 wg->intcnt = CTLI_INTCNT_DIS;
249 break;
250 case IRQ_TYPE_EDGE_BOTH:
251 wg->intcnt = CTLI_INTCNT_BE;
252 break;
253 case IRQ_TYPE_EDGE_RISING:
254 wg->intcnt = CTLI_INTCNT_PE;
255 break;
256 case IRQ_TYPE_EDGE_FALLING:
257 wg->intcnt = CTLI_INTCNT_NE;
258 break;
259 default:
260 return -EINVAL;
261 }
262
263 wg->update |= UPDATE_IRQ_TYPE;
264
265 return 0;
266 }
267
wcove_bus_lock(struct irq_data * data)268 static void wcove_bus_lock(struct irq_data *data)
269 {
270 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
271 struct wcove_gpio *wg = gpiochip_get_data(chip);
272
273 mutex_lock(&wg->buslock);
274 }
275
wcove_bus_sync_unlock(struct irq_data * data)276 static void wcove_bus_sync_unlock(struct irq_data *data)
277 {
278 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
279 struct wcove_gpio *wg = gpiochip_get_data(chip);
280 irq_hw_number_t gpio = irqd_to_hwirq(data);
281
282 if (wg->update & UPDATE_IRQ_TYPE)
283 wcove_update_irq_ctrl(wg, gpio);
284 if (wg->update & UPDATE_IRQ_MASK)
285 wcove_update_irq_mask(wg, gpio);
286 wg->update = 0;
287
288 mutex_unlock(&wg->buslock);
289 }
290
wcove_irq_unmask(struct irq_data * data)291 static void wcove_irq_unmask(struct irq_data *data)
292 {
293 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
294 struct wcove_gpio *wg = gpiochip_get_data(chip);
295 irq_hw_number_t gpio = irqd_to_hwirq(data);
296
297 if (gpio >= WCOVE_GPIO_NUM)
298 return;
299
300 gpiochip_enable_irq(chip, gpio);
301
302 wg->set_irq_mask = false;
303 wg->update |= UPDATE_IRQ_MASK;
304 }
305
wcove_irq_mask(struct irq_data * data)306 static void wcove_irq_mask(struct irq_data *data)
307 {
308 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
309 struct wcove_gpio *wg = gpiochip_get_data(chip);
310 irq_hw_number_t gpio = irqd_to_hwirq(data);
311
312 if (gpio >= WCOVE_GPIO_NUM)
313 return;
314
315 wg->set_irq_mask = true;
316 wg->update |= UPDATE_IRQ_MASK;
317
318 gpiochip_disable_irq(chip, gpio);
319 }
320
321 static const struct irq_chip wcove_irqchip = {
322 .name = "Whiskey Cove",
323 .irq_mask = wcove_irq_mask,
324 .irq_unmask = wcove_irq_unmask,
325 .irq_set_type = wcove_irq_type,
326 .irq_bus_lock = wcove_bus_lock,
327 .irq_bus_sync_unlock = wcove_bus_sync_unlock,
328 .flags = IRQCHIP_IMMUTABLE,
329 GPIOCHIP_IRQ_RESOURCE_HELPERS,
330 };
331
wcove_gpio_irq_handler(int irq,void * data)332 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
333 {
334 struct wcove_gpio *wg = (struct wcove_gpio *)data;
335 unsigned int virq, gpio;
336 unsigned long pending;
337 u8 p[2];
338
339 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
340 dev_err(wg->dev, "Failed to read irq status register\n");
341 return IRQ_NONE;
342 }
343
344 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
345 if (!pending)
346 return IRQ_NONE;
347
348 /* Iterate until no interrupt is pending */
349 while (pending) {
350 /* One iteration is for all pending bits */
351 for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) {
352 unsigned int mask, reg = to_ireg(gpio, IRQ_STATUS, &mask);
353
354 virq = irq_find_mapping(wg->chip.irq.domain, gpio);
355 handle_nested_irq(virq);
356 regmap_set_bits(wg->regmap, reg, mask);
357 }
358
359 /* Next iteration */
360 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
361 dev_err(wg->dev, "Failed to read irq status\n");
362 break;
363 }
364
365 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
366 }
367
368 return IRQ_HANDLED;
369 }
370
wcove_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)371 static void wcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
372 {
373 unsigned int ctlo, ctli, irq_mask, irq_status;
374 struct wcove_gpio *wg = gpiochip_get_data(chip);
375 int gpio, mask, ret = 0;
376
377 for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
378 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
379 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
380 if (ret) {
381 dev_err(wg->dev, "Failed to read registers: CTRL out/in\n");
382 break;
383 }
384
385 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask);
386 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status);
387 if (ret) {
388 dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n");
389 break;
390 }
391
392 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
393 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
394 str_hi_lo(ctli & 0x1),
395 ctli & CTLI_INTCNT_NE ? "fall" : " ",
396 ctli & CTLI_INTCNT_PE ? "rise" : " ",
397 ctlo,
398 irq_mask & mask ? "mask " : "unmask",
399 irq_status & mask ? "pending" : " ");
400 }
401 }
402
wcove_gpio_probe(struct platform_device * pdev)403 static int wcove_gpio_probe(struct platform_device *pdev)
404 {
405 struct intel_soc_pmic *pmic;
406 struct wcove_gpio *wg;
407 int virq, ret, irq;
408 struct device *dev;
409 struct gpio_irq_chip *girq;
410
411 /*
412 * This gpio platform device is created by a mfd device (see
413 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
414 * shared by all sub-devices created by the mfd device, the regmap
415 * pointer for instance, is stored as driver data of the mfd device
416 * driver.
417 */
418 pmic = dev_get_drvdata(pdev->dev.parent);
419 if (!pmic)
420 return -ENODEV;
421
422 irq = platform_get_irq(pdev, 0);
423 if (irq < 0)
424 return irq;
425
426 dev = &pdev->dev;
427
428 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
429 if (!wg)
430 return -ENOMEM;
431
432 wg->regmap_irq_chip = pmic->irq_chip_data;
433
434 platform_set_drvdata(pdev, wg);
435
436 mutex_init(&wg->buslock);
437 wg->chip.label = KBUILD_MODNAME;
438 wg->chip.direction_input = wcove_gpio_dir_in;
439 wg->chip.direction_output = wcove_gpio_dir_out;
440 wg->chip.get_direction = wcove_gpio_get_direction;
441 wg->chip.get = wcove_gpio_get;
442 wg->chip.set_rv = wcove_gpio_set;
443 wg->chip.set_config = wcove_gpio_set_config;
444 wg->chip.base = -1;
445 wg->chip.ngpio = WCOVE_VGPIO_NUM;
446 wg->chip.can_sleep = true;
447 wg->chip.parent = pdev->dev.parent;
448 wg->chip.dbg_show = wcove_gpio_dbg_show;
449 wg->dev = dev;
450 wg->regmap = pmic->regmap;
451
452 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
453 if (virq < 0) {
454 dev_err(dev, "Failed to get virq by irq %d\n", irq);
455 return virq;
456 }
457
458 girq = &wg->chip.irq;
459 gpio_irq_chip_set_chip(girq, &wcove_irqchip);
460 /* This will let us handle the parent IRQ in the driver */
461 girq->parent_handler = NULL;
462 girq->num_parents = 0;
463 girq->parents = NULL;
464 girq->default_type = IRQ_TYPE_NONE;
465 girq->handler = handle_simple_irq;
466 girq->threaded = true;
467
468 ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
469 IRQF_ONESHOT, pdev->name, wg);
470 if (ret) {
471 dev_err(dev, "Failed to request irq %d\n", virq);
472 return ret;
473 }
474
475 ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
476 if (ret) {
477 dev_err(dev, "Failed to add gpiochip: %d\n", ret);
478 return ret;
479 }
480
481 /* Enable GPIO0 interrupts */
482 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK);
483 if (ret)
484 return ret;
485
486 /* Enable GPIO1 interrupts */
487 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK);
488 if (ret)
489 return ret;
490
491 return 0;
492 }
493
494 /*
495 * Whiskey Cove PMIC itself is a analog device(but with digital control
496 * interface) providing power management support for other devices in
497 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
498 */
499 static struct platform_driver wcove_gpio_driver = {
500 .driver = {
501 .name = "bxt_wcove_gpio",
502 },
503 .probe = wcove_gpio_probe,
504 };
505
506 module_platform_driver(wcove_gpio_driver);
507
508 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
509 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
510 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
511 MODULE_LICENSE("GPL v2");
512 MODULE_ALIAS("platform:bxt_wcove_gpio");
513