xref: /linux/sound/soc/codecs/wcd938x.h (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __WCD938X_H__
3 #define __WCD938X_H__
4 #include <linux/soundwire/sdw.h>
5 #include <linux/soundwire/sdw_type.h>
6 
7 #define WCD938X_BASE_ADDRESS			(0x3000)
8 #define WCD938X_ANA_PAGE_REGISTER               (0x3000)
9 #define WCD938X_ANA_BIAS                        (0x3001)
10 #define WCD938X_ANA_RX_SUPPLIES                 (0x3008)
11 #define WCD938X_RX_BIAS_EN_MASK			BIT(0)
12 #define WCD938X_REGULATOR_MODE_MASK		BIT(1)
13 #define WCD938X_REGULATOR_MODE_CLASS_AB		1
14 #define WCD938X_VNEG_EN_MASK			BIT(6)
15 #define WCD938X_VPOS_EN_MASK			BIT(7)
16 #define WCD938X_ANA_HPH                         (0x3009)
17 #define WCD938X_HPHR_REF_EN_MASK		BIT(4)
18 #define WCD938X_HPHL_REF_EN_MASK		BIT(5)
19 #define WCD938X_HPHR_EN_MASK			BIT(6)
20 #define WCD938X_HPHL_EN_MASK			BIT(7)
21 #define WCD938X_ANA_EAR                         (0x300A)
22 #define WCD938X_ANA_EAR_COMPANDER_CTL           (0x300B)
23 #define WCD938X_GAIN_OVRD_REG_MASK		BIT(7)
24 #define WCD938X_EAR_GAIN_MASK			GENMASK(6, 2)
25 #define WCD938X_ANA_TX_CH1                      (0x300E)
26 #define WCD938X_ANA_TX_CH2                      (0x300F)
27 #define WCD938X_HPF1_INIT_MASK			BIT(6)
28 #define WCD938X_HPF2_INIT_MASK			BIT(5)
29 #define WCD938X_ANA_TX_CH3                      (0x3010)
30 #define WCD938X_ANA_TX_CH4                      (0x3011)
31 #define WCD938X_HPF3_INIT_MASK			BIT(6)
32 #define WCD938X_HPF4_INIT_MASK			BIT(5)
33 #define WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC    (0x3012)
34 #define WCD938X_ANA_MICB3_DSP_EN_LOGIC          (0x3013)
35 #define WCD938X_ANA_MBHC_MECH                   (0x3014)
36 #define WCD938X_MBHC_L_DET_EN_MASK		BIT(7)
37 #define WCD938X_MBHC_L_DET_EN			BIT(7)
38 #define WCD938X_MBHC_GND_DET_EN_MASK		BIT(6)
39 #define WCD938X_MBHC_MECH_DETECT_TYPE_MASK	BIT(5)
40 #define WCD938X_MBHC_MECH_DETECT_TYPE_INS	1
41 #define WCD938X_MBHC_HPHL_PLUG_TYPE_MASK	BIT(4)
42 #define WCD938X_MBHC_HPHL_PLUG_TYPE_NO		1
43 #define WCD938X_MBHC_GND_PLUG_TYPE_MASK		BIT(3)
44 #define WCD938X_MBHC_GND_PLUG_TYPE_NO		1
45 #define WCD938X_MBHC_HSL_PULLUP_COMP_EN		BIT(2)
46 #define WCD938X_MBHC_HSG_PULLUP_COMP_EN		BIT(1)
47 #define WCD938X_MBHC_HPHL_100K_TO_GND_EN	BIT(0)
48 
49 #define WCD938X_ANA_MBHC_ELECT                  (0x3015)
50 #define WCD938X_ANA_MBHC_BD_ISRC_CTL_MASK	GENMASK(6, 4)
51 #define WCD938X_ANA_MBHC_BD_ISRC_100UA		GENMASK(5, 4)
52 #define WCD938X_ANA_MBHC_BD_ISRC_OFF		0
53 #define WCD938X_ANA_MBHC_BIAS_EN_MASK		BIT(0)
54 #define WCD938X_ANA_MBHC_BIAS_EN		BIT(0)
55 #define WCD938X_ANA_MBHC_ZDET                   (0x3016)
56 #define WCD938X_ANA_MBHC_RESULT_1               (0x3017)
57 #define WCD938X_ANA_MBHC_RESULT_2               (0x3018)
58 #define WCD938X_ANA_MBHC_RESULT_3               (0x3019)
59 #define WCD938X_MBHC_BTN_RESULT_MASK		GENMASK(2, 0)
60 #define WCD938X_ANA_MBHC_BTN0                   (0x301A)
61 #define WCD938X_MBHC_BTN_VTH_MASK		GENMASK(7, 2)
62 #define WCD938X_ANA_MBHC_BTN1                   (0x301B)
63 #define WCD938X_ANA_MBHC_BTN2                   (0x301C)
64 #define WCD938X_ANA_MBHC_BTN3                   (0x301D)
65 #define WCD938X_ANA_MBHC_BTN4                   (0x301E)
66 #define WCD938X_ANA_MBHC_BTN5                   (0x301F)
67 #define WCD938X_VTH_MASK			GENMASK(7, 2)
68 #define WCD938X_ANA_MBHC_BTN6                   (0x3020)
69 #define WCD938X_ANA_MBHC_BTN7                   (0x3021)
70 #define WCD938X_ANA_MICB1                       (0x3022)
71 #define WCD938X_MICB_VOUT_MASK			GENMASK(5, 0)
72 #define WCD938X_MICB_EN_MASK			GENMASK(7, 6)
73 #define WCD938X_MICB_DISABLE			0
74 #define WCD938X_MICB_ENABLE			1
75 #define WCD938X_MICB_PULL_UP			2
76 #define WCD938X_MICB_PULL_DOWN			3
77 #define WCD938X_ANA_MICB2                       (0x3023)
78 #define WCD938X_ANA_MICB2_RAMP                  (0x3024)
79 #define WCD938X_RAMP_EN_MASK			BIT(7)
80 #define WCD938X_RAMP_SHIFT_CTRL_MASK		GENMASK(4, 2)
81 #define WCD938X_ANA_MICB3                       (0x3025)
82 #define WCD938X_ANA_MICB4                       (0x3026)
83 #define WCD938X_BIAS_CTL                        (0x3028)
84 #define WCD938X_BIAS_VBG_FINE_ADJ               (0x3029)
85 #define WCD938X_LDOL_VDDCX_ADJUST               (0x3040)
86 #define WCD938X_LDOL_DISABLE_LDOL               (0x3041)
87 #define WCD938X_MBHC_CTL_CLK                    (0x3056)
88 #define WCD938X_MBHC_CTL_ANA                    (0x3057)
89 #define WCD938X_MBHC_CTL_SPARE_1                (0x3058)
90 #define WCD938X_MBHC_CTL_SPARE_2                (0x3059)
91 #define WCD938X_MBHC_CTL_BCS                    (0x305A)
92 #define WCD938X_MBHC_MOISTURE_DET_FSM_STATUS    (0x305B)
93 #define WCD938X_MBHC_TEST_CTL                   (0x305C)
94 #define WCD938X_LDOH_MODE                       (0x3067)
95 #define WCD938X_LDOH_EN_MASK			BIT(7)
96 #define WCD938X_LDOH_BIAS                       (0x3068)
97 #define WCD938X_LDOH_STB_LOADS                  (0x3069)
98 #define WCD938X_LDOH_SLOWRAMP                   (0x306A)
99 #define WCD938X_MICB1_TEST_CTL_1                (0x306B)
100 #define WCD938X_MICB1_TEST_CTL_2                (0x306C)
101 #define WCD938X_MICB1_TEST_CTL_3                (0x306D)
102 #define WCD938X_MICB2_TEST_CTL_1                (0x306E)
103 #define WCD938X_MICB2_TEST_CTL_2                (0x306F)
104 #define WCD938X_MICB2_TEST_CTL_3                (0x3070)
105 #define WCD938X_MICB3_TEST_CTL_1                (0x3071)
106 #define WCD938X_MICB3_TEST_CTL_2                (0x3072)
107 #define WCD938X_MICB3_TEST_CTL_3                (0x3073)
108 #define WCD938X_MICB4_TEST_CTL_1                (0x3074)
109 #define WCD938X_MICB4_TEST_CTL_2                (0x3075)
110 #define WCD938X_MICB4_TEST_CTL_3                (0x3076)
111 #define WCD938X_TX_COM_ADC_VCM                  (0x3077)
112 #define WCD938X_TX_COM_BIAS_ATEST               (0x3078)
113 #define WCD938X_TX_COM_SPARE1                   (0x3079)
114 #define WCD938X_TX_COM_SPARE2                   (0x307A)
115 #define WCD938X_TX_COM_TXFE_DIV_CTL             (0x307B)
116 #define WCD938X_TX_COM_TXFE_DIV_START           (0x307C)
117 #define WCD938X_TX_COM_SPARE3                   (0x307D)
118 #define WCD938X_TX_COM_SPARE4                   (0x307E)
119 #define WCD938X_TX_1_2_TEST_EN                  (0x307F)
120 #define WCD938X_TX_1_2_ADC_IB                   (0x3080)
121 #define WCD938X_TX_1_2_ATEST_REFCTL             (0x3081)
122 #define WCD938X_TX_1_2_TEST_CTL                 (0x3082)
123 #define WCD938X_TX_1_2_TEST_BLK_EN1             (0x3083)
124 #define WCD938X_TX_1_2_TXFE1_CLKDIV             (0x3084)
125 #define WCD938X_TX_1_2_SAR2_ERR                 (0x3085)
126 #define WCD938X_TX_1_2_SAR1_ERR                 (0x3086)
127 #define WCD938X_TX_3_4_TEST_EN                  (0x3087)
128 #define WCD938X_TX_3_4_ADC_IB                   (0x3088)
129 #define WCD938X_TX_3_4_ATEST_REFCTL             (0x3089)
130 #define WCD938X_TX_3_4_TEST_CTL                 (0x308A)
131 #define WCD938X_TX_3_4_TEST_BLK_EN3             (0x308B)
132 #define WCD938X_TX_3_4_TXFE3_CLKDIV             (0x308C)
133 #define WCD938X_TX_3_4_SAR4_ERR                 (0x308D)
134 #define WCD938X_TX_3_4_SAR3_ERR                 (0x308E)
135 #define WCD938X_TX_3_4_TEST_BLK_EN2             (0x308F)
136 #define WCD938X_TX_3_4_TXFE2_CLKDIV             (0x3090)
137 #define WCD938X_TX_3_4_SPARE1                   (0x3091)
138 #define WCD938X_TX_3_4_TEST_BLK_EN4             (0x3092)
139 #define WCD938X_TX_3_4_TXFE4_CLKDIV             (0x3093)
140 #define WCD938X_TX_3_4_SPARE2                   (0x3094)
141 #define WCD938X_CLASSH_MODE_1                   (0x3097)
142 #define WCD938X_CLASSH_MODE_2                   (0x3098)
143 #define WCD938X_CLASSH_MODE_3                   (0x3099)
144 #define WCD938X_CLASSH_CTRL_VCL_1               (0x309A)
145 #define WCD938X_CLASSH_CTRL_VCL_2               (0x309B)
146 #define WCD938X_CLASSH_CTRL_CCL_1               (0x309C)
147 #define WCD938X_CLASSH_CTRL_CCL_2               (0x309D)
148 #define WCD938X_CLASSH_CTRL_CCL_3               (0x309E)
149 #define WCD938X_CLASSH_CTRL_CCL_4               (0x309F)
150 #define WCD938X_CLASSH_CTRL_CCL_5               (0x30A0)
151 #define WCD938X_CLASSH_BUCK_TMUX_A_D            (0x30A1)
152 #define WCD938X_CLASSH_BUCK_SW_DRV_CNTL         (0x30A2)
153 #define WCD938X_CLASSH_SPARE                    (0x30A3)
154 #define WCD938X_FLYBACK_EN                      (0x30A4)
155 #define WCD938X_EN_CUR_DET_MASK			BIT(2)
156 #define WCD938X_FLYBACK_VNEG_CTRL_1             (0x30A5)
157 #define WCD938X_FLYBACK_VNEG_CTRL_2             (0x30A6)
158 #define WCD938X_FLYBACK_VNEG_CTRL_3             (0x30A7)
159 #define WCD938X_FLYBACK_VNEG_CTRL_4             (0x30A8)
160 #define WCD938X_FLYBACK_VNEG_CTRL_5             (0x30A9)
161 #define WCD938X_FLYBACK_VNEG_CTRL_6             (0x30AA)
162 #define WCD938X_FLYBACK_VNEG_CTRL_7             (0x30AB)
163 #define WCD938X_FLYBACK_VNEG_CTRL_8             (0x30AC)
164 #define WCD938X_FLYBACK_VNEG_CTRL_9             (0x30AD)
165 #define WCD938X_FLYBACK_VNEGDAC_CTRL_1          (0x30AE)
166 #define WCD938X_FLYBACK_VNEGDAC_CTRL_2          (0x30AF)
167 #define WCD938X_FLYBACK_VNEGDAC_CTRL_3          (0x30B0)
168 #define WCD938X_FLYBACK_CTRL_1                  (0x30B1)
169 #define WCD938X_FLYBACK_TEST_CTL                (0x30B2)
170 #define WCD938X_RX_AUX_SW_CTL                   (0x30B3)
171 #define WCD938X_RX_PA_AUX_IN_CONN               (0x30B4)
172 #define WCD938X_RX_TIMER_DIV                    (0x30B5)
173 #define WCD938X_RX_OCP_CTL                      (0x30B6)
174 #define WCD938X_RX_OCP_COUNT                    (0x30B7)
175 #define WCD938X_RX_BIAS_EAR_DAC                 (0x30B8)
176 #define WCD938X_RX_BIAS_EAR_AMP                 (0x30B9)
177 #define WCD938X_RX_BIAS_HPH_LDO                 (0x30BA)
178 #define WCD938X_RX_BIAS_HPH_PA                  (0x30BB)
179 #define WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2       (0x30BC)
180 #define WCD938X_RX_BIAS_HPH_RDAC_LDO            (0x30BD)
181 #define WCD938X_RX_BIAS_HPH_CNP1                (0x30BE)
182 #define WCD938X_RX_BIAS_HPH_LOWPOWER            (0x30BF)
183 #define WCD938X_RX_BIAS_AUX_DAC                 (0x30C0)
184 #define WCD938X_RX_BIAS_AUX_AMP                 (0x30C1)
185 #define WCD938X_RX_BIAS_VNEGDAC_BLEEDER         (0x30C2)
186 #define WCD938X_RX_BIAS_MISC                    (0x30C3)
187 #define WCD938X_RX_BIAS_BUCK_RST                (0x30C4)
188 #define WCD938X_RX_BIAS_BUCK_VREF_ERRAMP        (0x30C5)
189 #define WCD938X_RX_BIAS_FLYB_ERRAMP             (0x30C6)
190 #define WCD938X_RX_BIAS_FLYB_BUFF               (0x30C7)
191 #define WCD938X_RX_BIAS_FLYB_MID_RST            (0x30C8)
192 #define WCD938X_HPH_L_STATUS                    (0x30C9)
193 #define WCD938X_HPH_R_STATUS                    (0x30CA)
194 #define WCD938X_HPH_CNP_EN                      (0x30CB)
195 #define WCD938X_HPH_CNP_WG_CTL                  (0x30CC)
196 #define WCD938X_HPH_CNP_WG_TIME                 (0x30CD)
197 #define WCD938X_HPH_OCP_CTL                     (0x30CE)
198 #define WCD938X_HPH_AUTO_CHOP                   (0x30CF)
199 #define WCD938X_HPH_CHOP_CTL                    (0x30D0)
200 #define WCD938X_HPH_PA_CTL1                     (0x30D1)
201 #define WCD938X_HPH_PA_CTL2                     (0x30D2)
202 #define WCD938X_HPHPA_GND_R_MASK		BIT(6)
203 #define WCD938X_HPHPA_GND_L_MASK		BIT(4)
204 #define WCD938X_HPH_L_EN                        (0x30D3)
205 #define WCD938X_HPH_L_TEST                      (0x30D4)
206 #define WCD938X_HPH_L_ATEST                     (0x30D5)
207 #define WCD938X_HPH_R_EN                        (0x30D6)
208 #define WCD938X_GAIN_SRC_SEL_MASK		BIT(5)
209 #define WCD938X_GAIN_SRC_SEL_REGISTER		1
210 #define WCD938X_HPH_R_TEST                      (0x30D7)
211 #define WCD938X_HPH_R_ATEST                     (0x30D8)
212 #define WCD938X_HPHPA_GND_OVR_MASK		BIT(1)
213 #define WCD938X_HPH_RDAC_CLK_CTL1               (0x30D9)
214 #define WCD938X_CHOP_CLK_EN_MASK		BIT(7)
215 #define WCD938X_HPH_RDAC_CLK_CTL2               (0x30DA)
216 #define WCD938X_HPH_RDAC_LDO_CTL                (0x30DB)
217 #define WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL        (0x30DC)
218 #define WCD938X_HPH_REFBUFF_UHQA_CTL            (0x30DD)
219 #define WCD938X_HPH_REFBUFF_LP_CTL              (0x30DE)
220 #define WCD938X_PREREF_FLIT_BYPASS_MASK		BIT(0)
221 #define WCD938X_HPH_L_DAC_CTL                   (0x30DF)
222 #define WCD938X_HPH_R_DAC_CTL                   (0x30E0)
223 #define WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL  (0x30E1)
224 #define WCD938X_HPH_SURGE_HPHLR_SURGE_EN        (0x30E2)
225 #define WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1     (0x30E3)
226 #define WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS    (0x30E4)
227 #define WCD938X_EAR_EAR_EN_REG                  (0x30E9)
228 #define WCD938X_EAR_EAR_PA_CON                  (0x30EA)
229 #define WCD938X_EAR_EAR_SP_CON                  (0x30EB)
230 #define WCD938X_EAR_EAR_DAC_CON                 (0x30EC)
231 #define WCD938X_DAC_SAMPLE_EDGE_SEL_MASK	BIT(7)
232 #define WCD938X_EAR_EAR_CNP_FSM_CON             (0x30ED)
233 #define WCD938X_EAR_TEST_CTL                    (0x30EE)
234 #define WCD938X_EAR_STATUS_REG_1                (0x30EF)
235 #define WCD938X_EAR_STATUS_REG_2                (0x30F0)
236 #define WCD938X_ANA_NEW_PAGE_REGISTER           (0x3100)
237 #define WCD938X_HPH_NEW_ANA_HPH2                (0x3101)
238 #define WCD938X_HPH_NEW_ANA_HPH3                (0x3102)
239 #define WCD938X_SLEEP_CTL                       (0x3103)
240 #define WCD938X_SLEEP_WATCHDOG_CTL              (0x3104)
241 #define WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL    (0x311F)
242 #define WCD938X_MBHC_NEW_CTL_1                  (0x3120)
243 #define WCD938X_MBHC_CTL_RCO_EN_MASK		BIT(7)
244 #define WCD938X_MBHC_CTL_RCO_EN			BIT(7)
245 #define WCD938X_MBHC_BTN_DBNC_MASK		GENMASK(1, 0)
246 #define WCD938X_MBHC_BTN_DBNC_T_16_MS		0x2
247 #define WCD938X_MBHC_NEW_CTL_2                  (0x3121)
248 #define WCD938X_M_RTH_CTL_MASK			GENMASK(3, 2)
249 #define WCD938X_MBHC_HS_VREF_CTL_MASK		GENMASK(1, 0)
250 #define WCD938X_MBHC_HS_VREF_1P5_V		0x1
251 #define WCD938X_MBHC_NEW_PLUG_DETECT_CTL        (0x3122)
252 #define WCD938X_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS	0x6
253 
254 #define WCD938X_MBHC_NEW_ZDET_ANA_CTL           (0x3123)
255 #define WCD938X_ZDET_RANGE_CTL_MASK		GENMASK(3, 0)
256 #define WCD938X_ZDET_MAXV_CTL_MASK		GENMASK(6, 4)
257 #define WCD938X_MBHC_NEW_ZDET_RAMP_CTL          (0x3124)
258 #define WCD938X_MBHC_NEW_FSM_STATUS             (0x3125)
259 #define WCD938X_MBHC_NEW_ADC_RESULT             (0x3126)
260 #define WCD938X_TX_NEW_AMIC_MUX_CFG             (0x3127)
261 #define WCD938X_AUX_AUXPA                       (0x3128)
262 #define WCD938X_AUXPA_CLK_EN_MASK		BIT(4)
263 #define WCD938X_LDORXTX_MODE                    (0x3129)
264 #define WCD938X_LDORXTX_CONFIG                  (0x312A)
265 #define WCD938X_DIE_CRACK_DIE_CRK_DET_EN        (0x312C)
266 #define WCD938X_DIE_CRACK_DIE_CRK_DET_OUT       (0x312D)
267 #define WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL       (0x3132)
268 #define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L      (0x3133)
269 #define WCD938X_HPH_NEW_INT_RDAC_VREF_CTL       (0x3134)
270 #define WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL   (0x3135)
271 #define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R      (0x3136)
272 #define WCD938X_HPH_RES_DIV_MASK		GENMASK(4, 0)
273 #define WCD938X_HPH_NEW_INT_PA_MISC1            (0x3137)
274 #define WCD938X_HPH_NEW_INT_PA_MISC2            (0x3138)
275 #define WCD938X_HPH_NEW_INT_PA_RDAC_MISC        (0x3139)
276 #define WCD938X_HPH_NEW_INT_HPH_TIMER1          (0x313A)
277 #define WCD938X_AUTOCHOP_TIMER_EN		BIT(1)
278 #define WCD938X_HPH_NEW_INT_HPH_TIMER2          (0x313B)
279 #define WCD938X_HPH_NEW_INT_HPH_TIMER3          (0x313C)
280 #define WCD938X_HPH_NEW_INT_HPH_TIMER4          (0x313D)
281 #define WCD938X_HPH_NEW_INT_PA_RDAC_MISC2       (0x313E)
282 #define WCD938X_HPH_NEW_INT_PA_RDAC_MISC3       (0x313F)
283 #define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW  (0x3140)
284 #define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW  (0x3141)
285 #define WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (0x3145)
286 #define WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP    (0x3146)
287 #define WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP      (0x3147)
288 #define WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL  (0x31AF)
289 #define WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (0x31B0)
290 #define WCD938X_MOISTURE_EN_POLLING_MASK	BIT(2)
291 #define WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT   (0x31B1)
292 #define WCD938X_HSDET_PULLUP_C_MASK		GENMASK(4, 0)
293 #define WCD938X_MBHC_NEW_INT_SPARE_2            (0x31B2)
294 #define WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON     (0x31B7)
295 #define WCD938X_EAR_INT_NEW_CNP_VCM_CON1        (0x31B8)
296 #define WCD938X_EAR_INT_NEW_CNP_VCM_CON2        (0x31B9)
297 #define WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS    (0x31BA)
298 #define WCD938X_AUX_INT_EN_REG                  (0x31BD)
299 #define WCD938X_AUX_INT_PA_CTRL                 (0x31BE)
300 #define WCD938X_AUX_INT_SP_CTRL                 (0x31BF)
301 #define WCD938X_AUX_INT_DAC_CTRL                (0x31C0)
302 #define WCD938X_AUX_INT_CLK_CTRL                (0x31C1)
303 #define WCD938X_AUX_INT_TEST_CTRL               (0x31C2)
304 #define WCD938X_AUX_INT_STATUS_REG              (0x31C3)
305 #define WCD938X_AUX_INT_MISC                    (0x31C4)
306 #define WCD938X_LDORXTX_INT_BIAS                (0x31C5)
307 #define WCD938X_LDORXTX_INT_STB_LOADS_DTEST     (0x31C6)
308 #define WCD938X_LDORXTX_INT_TEST0               (0x31C7)
309 #define WCD938X_LDORXTX_INT_STARTUP_TIMER       (0x31C8)
310 #define WCD938X_LDORXTX_INT_TEST1               (0x31C9)
311 #define WCD938X_LDORXTX_INT_STATUS              (0x31CA)
312 #define WCD938X_SLEEP_INT_WATCHDOG_CTL_1        (0x31D0)
313 #define WCD938X_SLEEP_INT_WATCHDOG_CTL_2        (0x31D1)
314 #define WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1  (0x31D3)
315 #define WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2  (0x31D4)
316 #define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2  (0x31D5)
317 #define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1  (0x31D6)
318 #define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0  (0x31D7)
319 #define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M	(0x31D8)
320 #define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M	(0x31D9)
321 #define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1	(0x31DA)
322 #define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0       (0x31DB)
323 #define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP      (0x31DC)
324 #define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1 (0x31DD)
325 #define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0   (0x31DE)
326 #define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP  (0x31DF)
327 #define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0 (0x31E0)
328 #define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP	(0x31E1)
329 #define WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1	(0x31E2)
330 #define WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP	(0x31E3)
331 #define WCD938X_TX_COM_NEW_INT_TXADC_INT_L2     (0x31E4)
332 #define WCD938X_TX_COM_NEW_INT_TXADC_INT_L1     (0x31E5)
333 #define WCD938X_TX_COM_NEW_INT_TXADC_INT_L0     (0x31E6)
334 #define WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP    (0x31E7)
335 #define WCD938X_DIGITAL_PAGE_REGISTER           (0x3400)
336 #define WCD938X_DIGITAL_CHIP_ID0                (0x3401)
337 #define WCD938X_DIGITAL_CHIP_ID1                (0x3402)
338 #define WCD938X_DIGITAL_CHIP_ID2                (0x3403)
339 #define WCD938X_DIGITAL_CHIP_ID3                (0x3404)
340 #define WCD938X_DIGITAL_SWR_TX_CLK_RATE         (0x3405)
341 #define WCD938X_DIGITAL_CDC_RST_CTL             (0x3406)
342 #define WCD938X_DIGITAL_TOP_CLK_CFG             (0x3407)
343 #define WCD938X_DIGITAL_CDC_ANA_CLK_CTL         (0x3408)
344 #define WCD938X_ANA_RX_CLK_EN_MASK		BIT(0)
345 #define WCD938X_ANA_RX_DIV2_CLK_EN_MASK		BIT(1)
346 #define WCD938X_ANA_RX_DIV4_CLK_EN_MASK		BIT(2)
347 #define WCD938X_ANA_TX_CLK_EN_MASK		BIT(3)
348 #define WCD938X_ANA_TX_DIV2_CLK_EN_MASK		BIT(4)
349 #define WCD938X_ANA_TX_DIV4_CLK_EN_MASK		BIT(5)
350 #define WCD938X_DIGITAL_CDC_DIG_CLK_CTL         (0x3409)
351 #define WCD938X_TXD3_CLK_EN_MASK		BIT(7)
352 #define WCD938X_TXD2_CLK_EN_MASK		BIT(6)
353 #define WCD938X_TXD1_CLK_EN_MASK		BIT(5)
354 #define WCD938X_TXD0_CLK_EN_MASK		BIT(4)
355 #define WCD938X_TX_CLK_EN_MASK			GENMASK(7, 4)
356 #define WCD938X_RXD2_CLK_EN_MASK		BIT(2)
357 #define WCD938X_RXD1_CLK_EN_MASK		BIT(1)
358 #define WCD938X_RXD0_CLK_EN_MASK		BIT(0)
359 #define WCD938X_DIGITAL_SWR_RST_EN              (0x340A)
360 #define WCD938X_DIGITAL_CDC_PATH_MODE           (0x340B)
361 #define WCD938X_DIGITAL_CDC_RX_RST              (0x340C)
362 #define WCD938X_DIGITAL_CDC_RX0_CTL             (0x340D)
363 #define WCD938X_DEM_DITHER_ENABLE_MASK		BIT(6)
364 #define WCD938X_DIGITAL_CDC_RX1_CTL             (0x340E)
365 #define WCD938X_DIGITAL_CDC_RX2_CTL             (0x340F)
366 #define WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1     (0x3410)
367 #define WCD938X_TXD0_MODE_MASK			GENMASK(3, 0)
368 #define WCD938X_TXD1_MODE_MASK			GENMASK(7, 4)
369 #define WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3     (0x3411)
370 #define WCD938X_TXD2_MODE_MASK			GENMASK(3, 0)
371 #define WCD938X_TXD3_MODE_MASK			GENMASK(7, 4)
372 #define WCD938X_DIGITAL_CDC_COMP_CTL_0          (0x3414)
373 #define WCD938X_HPHR_COMP_EN_MASK		BIT(0)
374 #define WCD938X_HPHL_COMP_EN_MASK		BIT(1)
375 #define WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL      (0x3417)
376 #define WCD938X_TX_SC_CLK_EN_MASK		BIT(0)
377 #define WCD938X_DIGITAL_CDC_HPH_DSM_A1_0        (0x3418)
378 #define WCD938X_DIGITAL_CDC_HPH_DSM_A1_1        (0x3419)
379 #define WCD938X_DIGITAL_CDC_HPH_DSM_A2_0        (0x341A)
380 #define WCD938X_DIGITAL_CDC_HPH_DSM_A2_1        (0x341B)
381 #define WCD938X_DIGITAL_CDC_HPH_DSM_A3_0        (0x341C)
382 #define WCD938X_DIGITAL_CDC_HPH_DSM_A3_1        (0x341D)
383 #define WCD938X_DIGITAL_CDC_HPH_DSM_A4_0        (0x341E)
384 #define WCD938X_DIGITAL_CDC_HPH_DSM_A4_1        (0x341F)
385 #define WCD938X_DIGITAL_CDC_HPH_DSM_A5_0        (0x3420)
386 #define WCD938X_DIGITAL_CDC_HPH_DSM_A5_1        (0x3421)
387 #define WCD938X_DIGITAL_CDC_HPH_DSM_A6_0        (0x3422)
388 #define WCD938X_DIGITAL_CDC_HPH_DSM_A7_0        (0x3423)
389 #define WCD938X_DIGITAL_CDC_HPH_DSM_C_0         (0x3424)
390 #define WCD938X_DIGITAL_CDC_HPH_DSM_C_1         (0x3425)
391 #define WCD938X_DIGITAL_CDC_HPH_DSM_C_2         (0x3426)
392 #define WCD938X_DIGITAL_CDC_HPH_DSM_C_3         (0x3427)
393 #define WCD938X_DIGITAL_CDC_HPH_DSM_R1          (0x3428)
394 #define WCD938X_DIGITAL_CDC_HPH_DSM_R2          (0x3429)
395 #define WCD938X_DIGITAL_CDC_HPH_DSM_R3          (0x342A)
396 #define WCD938X_DIGITAL_CDC_HPH_DSM_R4          (0x342B)
397 #define WCD938X_DIGITAL_CDC_HPH_DSM_R5          (0x342C)
398 #define WCD938X_DIGITAL_CDC_HPH_DSM_R6          (0x342D)
399 #define WCD938X_DIGITAL_CDC_HPH_DSM_R7          (0x342E)
400 #define WCD938X_DIGITAL_CDC_AUX_DSM_A1_0        (0x342F)
401 #define WCD938X_DIGITAL_CDC_AUX_DSM_A1_1        (0x3430)
402 #define WCD938X_DIGITAL_CDC_AUX_DSM_A2_0        (0x3431)
403 #define WCD938X_DIGITAL_CDC_AUX_DSM_A2_1        (0x3432)
404 #define WCD938X_DIGITAL_CDC_AUX_DSM_A3_0        (0x3433)
405 #define WCD938X_DIGITAL_CDC_AUX_DSM_A3_1        (0x3434)
406 #define WCD938X_DIGITAL_CDC_AUX_DSM_A4_0        (0x3435)
407 #define WCD938X_DIGITAL_CDC_AUX_DSM_A4_1        (0x3436)
408 #define WCD938X_DIGITAL_CDC_AUX_DSM_A5_0        (0x3437)
409 #define WCD938X_DIGITAL_CDC_AUX_DSM_A5_1        (0x3438)
410 #define WCD938X_DIGITAL_CDC_AUX_DSM_A6_0        (0x3439)
411 #define WCD938X_DIGITAL_CDC_AUX_DSM_A7_0        (0x343A)
412 #define WCD938X_DIGITAL_CDC_AUX_DSM_C_0         (0x343B)
413 #define WCD938X_DIGITAL_CDC_AUX_DSM_C_1         (0x343C)
414 #define WCD938X_DIGITAL_CDC_AUX_DSM_C_2         (0x343D)
415 #define WCD938X_DIGITAL_CDC_AUX_DSM_C_3         (0x343E)
416 #define WCD938X_DIGITAL_CDC_AUX_DSM_R1          (0x343F)
417 #define WCD938X_DIGITAL_CDC_AUX_DSM_R2          (0x3440)
418 #define WCD938X_DIGITAL_CDC_AUX_DSM_R3          (0x3441)
419 #define WCD938X_DIGITAL_CDC_AUX_DSM_R4          (0x3442)
420 #define WCD938X_DIGITAL_CDC_AUX_DSM_R5          (0x3443)
421 #define WCD938X_DIGITAL_CDC_AUX_DSM_R6          (0x3444)
422 #define WCD938X_DIGITAL_CDC_AUX_DSM_R7          (0x3445)
423 #define WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0       (0x3446)
424 #define WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1       (0x3447)
425 #define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0      (0x3448)
426 #define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1      (0x3449)
427 #define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2      (0x344A)
428 #define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0      (0x344B)
429 #define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1      (0x344C)
430 #define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2      (0x344D)
431 #define WCD938X_DIGITAL_CDC_HPH_GAIN_CTL        (0x344E)
432 #define WCD938X_HPHL_RX_EN_MASK			BIT(2)
433 #define WCD938X_HPHR_RX_EN_MASK			BIT(3)
434 #define WCD938X_DIGITAL_CDC_AUX_GAIN_CTL        (0x344F)
435 #define WCD938X_AUX_EN_MASK			BIT(0)
436 #define WCD938X_DIGITAL_CDC_EAR_PATH_CTL        (0x3450)
437 #define WCD938X_DIGITAL_CDC_SWR_CLH             (0x3451)
438 #define WCD938X_DIGITAL_SWR_CLH_BYP             (0x3452)
439 #define WCD938X_DIGITAL_CDC_TX0_CTL             (0x3453)
440 #define WCD938X_DIGITAL_CDC_TX1_CTL             (0x3454)
441 #define WCD938X_DIGITAL_CDC_TX2_CTL             (0x3455)
442 #define WCD938X_DIGITAL_CDC_TX_RST              (0x3456)
443 #define WCD938X_DIGITAL_CDC_REQ_CTL             (0x3457)
444 #define WCD938X_FS_RATE_4P8_MASK		BIT(1)
445 #define WCD938X_NO_NOTCH_MASK			BIT(0)
446 #define WCD938X_DIGITAL_CDC_RST                 (0x3458)
447 #define WCD938X_DIGITAL_CDC_AMIC_CTL            (0x345A)
448 #define WCD938X_AMIC1_IN_SEL_DMIC		0
449 #define WCD938X_AMIC1_IN_SEL_AMIC		0
450 #define WCD938X_AMIC1_IN_SEL_MASK		BIT(0)
451 #define WCD938X_AMIC3_IN_SEL_MASK		BIT(1)
452 #define WCD938X_AMIC4_IN_SEL_MASK		BIT(2)
453 #define WCD938X_AMIC5_IN_SEL_MASK		BIT(3)
454 #define WCD938X_DIGITAL_CDC_DMIC_CTL            (0x345B)
455 #define WCD938X_DMIC_CLK_SCALING_EN_MASK	GENMASK(2, 1)
456 #define WCD938X_DIGITAL_CDC_DMIC1_CTL           (0x345C)
457 #define WCD938X_DMIC_CLK_EN_MASK		BIT(3)
458 #define WCD938X_DIGITAL_CDC_DMIC2_CTL           (0x345D)
459 #define WCD938X_DIGITAL_CDC_DMIC3_CTL           (0x345E)
460 #define WCD938X_DIGITAL_CDC_DMIC4_CTL           (0x345F)
461 #define WCD938X_DIGITAL_EFUSE_PRG_CTL           (0x3460)
462 #define WCD938X_DIGITAL_EFUSE_CTL               (0x3461)
463 #define WCD938X_DIGITAL_CDC_DMIC_RATE_1_2       (0x3462)
464 #define WCD938X_DIGITAL_CDC_DMIC_RATE_3_4       (0x3463)
465 #define WCD938X_DMIC1_RATE_MASK			GENMASK(3, 0)
466 #define WCD938X_DMIC2_RATE_MASK			GENMASK(7, 4)
467 #define WCD938X_DMIC3_RATE_MASK			GENMASK(3, 0)
468 #define WCD938X_DMIC4_RATE_MASK			GENMASK(7, 4)
469 #define WCD938X_DMIC4_RATE_2P4MHZ		3
470 
471 #define WCD938X_DIGITAL_PDM_WD_CTL0             (0x3465)
472 #define WCD938X_PDM_WD_EN_MASK			GENMASK(2, 0)
473 #define WCD938X_DIGITAL_PDM_WD_CTL1             (0x3466)
474 #define WCD938X_DIGITAL_PDM_WD_CTL2             (0x3467)
475 #define WCD938X_AUX_PDM_WD_EN_MASK			GENMASK(2, 0)
476 #define WCD938X_DIGITAL_INTR_MODE               (0x346A)
477 #define WCD938X_DIGITAL_INTR_MASK_0             (0x346B)
478 #define WCD938X_DIGITAL_INTR_MASK_1             (0x346C)
479 #define WCD938X_DIGITAL_INTR_MASK_2             (0x346D)
480 #define WCD938X_DIGITAL_INTR_STATUS_0           (0x346E)
481 #define WCD938X_DIGITAL_INTR_STATUS_1           (0x346F)
482 #define WCD938X_DIGITAL_INTR_STATUS_2           (0x3470)
483 #define WCD938X_DIGITAL_INTR_CLEAR_0            (0x3471)
484 #define WCD938X_DIGITAL_INTR_CLEAR_1            (0x3472)
485 #define WCD938X_DIGITAL_INTR_CLEAR_2            (0x3473)
486 #define WCD938X_DIGITAL_INTR_LEVEL_0            (0x3474)
487 #define WCD938X_DIGITAL_INTR_LEVEL_1            (0x3475)
488 #define WCD938X_DIGITAL_INTR_LEVEL_2            (0x3476)
489 #define WCD938X_DIGITAL_INTR_SET_0              (0x3477)
490 #define WCD938X_DIGITAL_INTR_SET_1              (0x3478)
491 #define WCD938X_DIGITAL_INTR_SET_2              (0x3479)
492 #define WCD938X_DIGITAL_INTR_TEST_0             (0x347A)
493 #define WCD938X_DIGITAL_INTR_TEST_1             (0x347B)
494 #define WCD938X_DIGITAL_INTR_TEST_2             (0x347C)
495 #define WCD938X_DIGITAL_TX_MODE_DBG_EN          (0x347F)
496 #define WCD938X_DIGITAL_TX_MODE_DBG_0_1         (0x3480)
497 #define WCD938X_DIGITAL_TX_MODE_DBG_2_3         (0x3481)
498 #define WCD938X_DIGITAL_LB_IN_SEL_CTL           (0x3482)
499 #define WCD938X_DIGITAL_LOOP_BACK_MODE          (0x3483)
500 #define WCD938X_DIGITAL_SWR_DAC_TEST            (0x3484)
501 #define WCD938X_DIGITAL_SWR_HM_TEST_RX_0        (0x3485)
502 #define WCD938X_DIGITAL_SWR_HM_TEST_TX_0        (0x3486)
503 #define WCD938X_DIGITAL_SWR_HM_TEST_RX_1        (0x3487)
504 #define WCD938X_DIGITAL_SWR_HM_TEST_TX_1        (0x3488)
505 #define WCD938X_DIGITAL_SWR_HM_TEST_TX_2        (0x3489)
506 #define WCD938X_DIGITAL_SWR_HM_TEST_0           (0x348A)
507 #define WCD938X_DIGITAL_SWR_HM_TEST_1           (0x348B)
508 #define WCD938X_DIGITAL_PAD_CTL_SWR_0           (0x348C)
509 #define WCD938X_DIGITAL_PAD_CTL_SWR_1           (0x348D)
510 #define WCD938X_DIGITAL_I2C_CTL                 (0x348E)
511 #define WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE   (0x348F)
512 #define WCD938X_DIGITAL_EFUSE_TEST_CTL_0        (0x3490)
513 #define WCD938X_DIGITAL_EFUSE_TEST_CTL_1        (0x3491)
514 #define WCD938X_DIGITAL_EFUSE_T_DATA_0          (0x3492)
515 #define WCD938X_DIGITAL_EFUSE_T_DATA_1          (0x3493)
516 #define WCD938X_DIGITAL_PAD_CTL_PDM_RX0         (0x3494)
517 #define WCD938X_DIGITAL_PAD_CTL_PDM_RX1         (0x3495)
518 #define WCD938X_DIGITAL_PAD_CTL_PDM_TX0         (0x3496)
519 #define WCD938X_DIGITAL_PAD_CTL_PDM_TX1         (0x3497)
520 #define WCD938X_DIGITAL_PAD_CTL_PDM_TX2         (0x3498)
521 #define WCD938X_DIGITAL_PAD_INP_DIS_0           (0x3499)
522 #define WCD938X_DIGITAL_PAD_INP_DIS_1           (0x349A)
523 #define WCD938X_DIGITAL_DRIVE_STRENGTH_0        (0x349B)
524 #define WCD938X_DIGITAL_DRIVE_STRENGTH_1        (0x349C)
525 #define WCD938X_DIGITAL_DRIVE_STRENGTH_2        (0x349D)
526 #define WCD938X_DIGITAL_RX_DATA_EDGE_CTL        (0x349E)
527 #define WCD938X_DIGITAL_TX_DATA_EDGE_CTL        (0x349F)
528 #define WCD938X_DIGITAL_GPIO_MODE               (0x34A0)
529 #define WCD938X_DIGITAL_PIN_CTL_OE              (0x34A1)
530 #define WCD938X_DIGITAL_PIN_CTL_DATA_0          (0x34A2)
531 #define WCD938X_DIGITAL_PIN_CTL_DATA_1          (0x34A3)
532 #define WCD938X_DIGITAL_PIN_STATUS_0            (0x34A4)
533 #define WCD938X_DIGITAL_PIN_STATUS_1            (0x34A5)
534 #define WCD938X_DIGITAL_DIG_DEBUG_CTL           (0x34A6)
535 #define WCD938X_DIGITAL_DIG_DEBUG_EN            (0x34A7)
536 #define WCD938X_DIGITAL_ANA_CSR_DBG_ADD         (0x34A8)
537 #define WCD938X_DIGITAL_ANA_CSR_DBG_CTL         (0x34A9)
538 #define WCD938X_DIGITAL_SSP_DBG                 (0x34AA)
539 #define WCD938X_DIGITAL_MODE_STATUS_0           (0x34AB)
540 #define WCD938X_DIGITAL_MODE_STATUS_1           (0x34AC)
541 #define WCD938X_DIGITAL_SPARE_0                 (0x34AD)
542 #define WCD938X_DIGITAL_SPARE_1                 (0x34AE)
543 #define WCD938X_DIGITAL_SPARE_2                 (0x34AF)
544 #define WCD938X_DIGITAL_EFUSE_REG_0             (0x34B0)
545 #define WCD938X_ID_MASK				GENMASK(4, 1)
546 #define WCD938X_DIGITAL_EFUSE_REG_1             (0x34B1)
547 #define WCD938X_DIGITAL_EFUSE_REG_2             (0x34B2)
548 #define WCD938X_DIGITAL_EFUSE_REG_3             (0x34B3)
549 #define WCD938X_DIGITAL_EFUSE_REG_4             (0x34B4)
550 #define WCD938X_DIGITAL_EFUSE_REG_5             (0x34B5)
551 #define WCD938X_DIGITAL_EFUSE_REG_6             (0x34B6)
552 #define WCD938X_DIGITAL_EFUSE_REG_7             (0x34B7)
553 #define WCD938X_DIGITAL_EFUSE_REG_8             (0x34B8)
554 #define WCD938X_DIGITAL_EFUSE_REG_9             (0x34B9)
555 #define WCD938X_DIGITAL_EFUSE_REG_10            (0x34BA)
556 #define WCD938X_DIGITAL_EFUSE_REG_11            (0x34BB)
557 #define WCD938X_DIGITAL_EFUSE_REG_12            (0x34BC)
558 #define WCD938X_DIGITAL_EFUSE_REG_13            (0x34BD)
559 #define WCD938X_DIGITAL_EFUSE_REG_14            (0x34BE)
560 #define WCD938X_DIGITAL_EFUSE_REG_15            (0x34BF)
561 #define WCD938X_DIGITAL_EFUSE_REG_16            (0x34C0)
562 #define WCD938X_DIGITAL_EFUSE_REG_17            (0x34C1)
563 #define WCD938X_DIGITAL_EFUSE_REG_18            (0x34C2)
564 #define WCD938X_DIGITAL_EFUSE_REG_19            (0x34C3)
565 #define WCD938X_DIGITAL_EFUSE_REG_20            (0x34C4)
566 #define WCD938X_DIGITAL_EFUSE_REG_21            (0x34C5)
567 #define WCD938X_DIGITAL_EFUSE_REG_22            (0x34C6)
568 #define WCD938X_DIGITAL_EFUSE_REG_23            (0x34C7)
569 #define WCD938X_DIGITAL_EFUSE_REG_24            (0x34C8)
570 #define WCD938X_DIGITAL_EFUSE_REG_25            (0x34C9)
571 #define WCD938X_DIGITAL_EFUSE_REG_26            (0x34CA)
572 #define WCD938X_DIGITAL_EFUSE_REG_27            (0x34CB)
573 #define WCD938X_DIGITAL_EFUSE_REG_28            (0x34CC)
574 #define WCD938X_DIGITAL_EFUSE_REG_29            (0x34CD)
575 #define WCD938X_DIGITAL_EFUSE_REG_30            (0x34CE)
576 #define WCD938X_DIGITAL_EFUSE_REG_31            (0x34CF)
577 #define WCD938X_DIGITAL_TX_REQ_FB_CTL_0         (0x34D0)
578 #define WCD938X_DIGITAL_TX_REQ_FB_CTL_1         (0x34D1)
579 #define WCD938X_DIGITAL_TX_REQ_FB_CTL_2         (0x34D2)
580 #define WCD938X_DIGITAL_TX_REQ_FB_CTL_3         (0x34D3)
581 #define WCD938X_DIGITAL_TX_REQ_FB_CTL_4         (0x34D4)
582 #define WCD938X_DIGITAL_DEM_BYPASS_DATA0        (0x34D5)
583 #define WCD938X_DIGITAL_DEM_BYPASS_DATA1        (0x34D6)
584 #define WCD938X_DIGITAL_DEM_BYPASS_DATA2        (0x34D7)
585 #define WCD938X_DIGITAL_DEM_BYPASS_DATA3        (0x34D8)
586 #define WCD938X_MAX_REGISTER			(WCD938X_DIGITAL_DEM_BYPASS_DATA3)
587 
588 #define WCD938X_MAX_SWR_CH_IDS	15
589 
590 struct wcd938x_sdw_ch_info {
591 	int port_num;
592 	unsigned int ch_mask;
593 };
594 
595 #define WCD_SDW_CH(id, pn, cmask)	\
596 	[id] = {			\
597 		.port_num = pn,		\
598 		.ch_mask = cmask,	\
599 	}
600 
601 enum wcd938x_tx_sdw_ports {
602 	WCD938X_ADC_1_2_PORT = 1,
603 	WCD938X_ADC_3_4_PORT,
604 	/* DMIC0_0, DMIC0_1, DMIC1_0, DMIC1_1 */
605 	WCD938X_DMIC_0_3_MBHC_PORT,
606 	WCD938X_DMIC_4_7_PORT,
607 	WCD938X_MAX_TX_SWR_PORTS = WCD938X_DMIC_4_7_PORT,
608 };
609 
610 enum wcd938x_tx_sdw_channels {
611 	WCD938X_ADC1,
612 	WCD938X_ADC2,
613 	WCD938X_ADC3,
614 	WCD938X_ADC4,
615 	WCD938X_DMIC0,
616 	WCD938X_DMIC1,
617 	WCD938X_MBHC,
618 	WCD938X_DMIC2,
619 	WCD938X_DMIC3,
620 	WCD938X_DMIC4,
621 	WCD938X_DMIC5,
622 	WCD938X_DMIC6,
623 	WCD938X_DMIC7,
624 };
625 
626 enum wcd938x_rx_sdw_ports {
627 	WCD938X_HPH_PORT = 1,
628 	WCD938X_CLSH_PORT,
629 	WCD938X_COMP_PORT,
630 	WCD938X_LO_PORT,
631 	WCD938X_DSD_PORT,
632 	WCD938X_MAX_SWR_PORTS = WCD938X_DSD_PORT,
633 };
634 
635 enum wcd938x_rx_sdw_channels {
636 	WCD938X_HPH_L,
637 	WCD938X_HPH_R,
638 	WCD938X_CLSH,
639 	WCD938X_COMP_L,
640 	WCD938X_COMP_R,
641 	WCD938X_LO,
642 	WCD938X_DSD_R,
643 	WCD938X_DSD_L,
644 };
645 
646 struct wcd938x_priv;
647 struct wcd938x_sdw_priv {
648 	struct sdw_slave *sdev;
649 	struct sdw_stream_config sconfig;
650 	struct sdw_stream_runtime *sruntime;
651 	struct sdw_port_config port_config[WCD938X_MAX_SWR_PORTS];
652 	const struct wcd938x_sdw_ch_info *ch_info;
653 	bool port_enable[WCD938X_MAX_SWR_CH_IDS];
654 	int active_ports;
655 	bool is_tx;
656 	struct wcd938x_priv *wcd938x;
657 	struct irq_domain *slave_irq;
658 	struct regmap *regmap;
659 };
660 
661 #if IS_ENABLED(CONFIG_SND_SOC_WCD938X_SDW)
662 int wcd938x_sdw_free(struct wcd938x_sdw_priv *wcd,
663 		     struct snd_pcm_substream *substream,
664 		     struct snd_soc_dai *dai);
665 int wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv *wcd,
666 			       struct snd_soc_dai *dai,
667 			       void *stream, int direction);
668 int wcd938x_sdw_hw_params(struct wcd938x_sdw_priv *wcd,
669 			  struct snd_pcm_substream *substream,
670 			  struct snd_pcm_hw_params *params,
671 			  struct snd_soc_dai *dai);
672 
673 struct device *wcd938x_sdw_device_get(struct device_node *np);
674 int wcd938x_swr_get_current_bank(struct sdw_slave *sdev);
675 
676 #else
677 
wcd938x_sdw_free(struct wcd938x_sdw_priv * wcd,struct snd_pcm_substream * substream,struct snd_soc_dai * dai)678 static inline int wcd938x_sdw_free(struct wcd938x_sdw_priv *wcd,
679 		     struct snd_pcm_substream *substream,
680 		     struct snd_soc_dai *dai)
681 {
682 	return -EOPNOTSUPP;
683 }
684 
wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv * wcd,struct snd_soc_dai * dai,void * stream,int direction)685 static inline int wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv *wcd,
686 			       struct snd_soc_dai *dai,
687 			       void *stream, int direction)
688 {
689 	return -EOPNOTSUPP;
690 }
691 
wcd938x_sdw_hw_params(struct wcd938x_sdw_priv * wcd,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)692 static inline int wcd938x_sdw_hw_params(struct wcd938x_sdw_priv *wcd,
693 			  struct snd_pcm_substream *substream,
694 			  struct snd_pcm_hw_params *params,
695 			  struct snd_soc_dai *dai)
696 {
697 	return -EOPNOTSUPP;
698 }
699 
wcd938x_sdw_device_get(struct device_node * np)700 static inline struct device *wcd938x_sdw_device_get(struct device_node *np)
701 {
702 	return NULL;
703 }
704 
wcd938x_swr_get_current_bank(struct sdw_slave * sdev)705 static inline int wcd938x_swr_get_current_bank(struct sdw_slave *sdev)
706 {
707 	return 0;
708 }
709 #endif /* CONFIG_SND_SOC_WCD938X_SDW */
710 #endif /* __WCD938X_H__ */
711