1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
3
4 #include <linux/cleanup.h>
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
7 #include <linux/interrupt.h>
8 #include <linux/kernel.h>
9 #include <linux/mfd/wcd934x/registers.h>
10 #include <linux/mfd/wcd934x/wcd934x.h>
11 #include <linux/module.h>
12 #include <linux/mutex.h>
13 #include <linux/of_clk.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/slimbus.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/soc-dapm.h>
22 #include <sound/tlv.h>
23 #include "wcd-clsh-v2.h"
24 #include "wcd-mbhc-v2.h"
25
26 #include <dt-bindings/sound/qcom,wcd934x.h>
27
28 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
29 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
30 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
31 /* Fractional Rates */
32 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
33 SNDRV_PCM_RATE_176400)
34 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
35 SNDRV_PCM_FMTBIT_S24_LE)
36
37 /* slave port water mark level
38 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
39 */
40 #define SLAVE_PORT_WATER_MARK_6BYTES 0
41 #define SLAVE_PORT_WATER_MARK_9BYTES 1
42 #define SLAVE_PORT_WATER_MARK_12BYTES 2
43 #define SLAVE_PORT_WATER_MARK_15BYTES 3
44 #define SLAVE_PORT_WATER_MARK_SHIFT 1
45 #define SLAVE_PORT_ENABLE 1
46 #define SLAVE_PORT_DISABLE 0
47 #define WCD934X_SLIM_WATER_MARK_VAL \
48 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
49 (SLAVE_PORT_ENABLE))
50
51 #define WCD934X_SLIM_NUM_PORT_REG 3
52 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
53 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0)
54 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1)
55 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2)
56
57 #define WCD934X_MCLK_CLK_12P288MHZ 12288000
58 #define WCD934X_MCLK_CLK_9P6MHZ 9600000
59
60 /* Only valid for 9.6 MHz mclk */
61 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
62 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
63
64 /* Only valid for 12.288 MHz mclk */
65 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
66
67 #define WCD934X_DMIC_CLK_DIV_2 0x0
68 #define WCD934X_DMIC_CLK_DIV_3 0x1
69 #define WCD934X_DMIC_CLK_DIV_4 0x2
70 #define WCD934X_DMIC_CLK_DIV_6 0x3
71 #define WCD934X_DMIC_CLK_DIV_8 0x4
72 #define WCD934X_DMIC_CLK_DIV_16 0x5
73 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
74
75 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
76 #define CF_MIN_3DB_4HZ 0x0
77 #define CF_MIN_3DB_75HZ 0x1
78 #define CF_MIN_3DB_150HZ 0x2
79
80 #define WCD934X_RX_START 16
81 #define WCD934X_NUM_INTERPOLATORS 9
82 #define WCD934X_RX_PATH_CTL_OFFSET 20
83 #define WCD934X_MAX_VALID_ADC_MUX 13
84 #define WCD934X_INVALID_ADC_MUX 9
85
86 #define WCD934X_SLIM_RX_CH(p) \
87 {.port = p + WCD934X_RX_START, .shift = p,}
88
89 #define WCD934X_SLIM_TX_CH(p) \
90 {.port = p, .shift = p,}
91
92 /* Feature masks to distinguish codec version */
93 #define DSD_DISABLED_MASK 0
94 #define SLNQ_DISABLED_MASK 1
95
96 #define DSD_DISABLED BIT(DSD_DISABLED_MASK)
97 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK)
98
99 /* As fine version info cannot be retrieved before wcd probe.
100 * Define three coarse versions for possible future use before wcd probe.
101 */
102 #define WCD_VERSION_WCD9340_1_0 0x400
103 #define WCD_VERSION_WCD9341_1_0 0x410
104 #define WCD_VERSION_WCD9340_1_1 0x401
105 #define WCD_VERSION_WCD9341_1_1 0x411
106 #define WCD934X_AMIC_PWR_LEVEL_LP 0
107 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1
108 #define WCD934X_AMIC_PWR_LEVEL_HP 2
109 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3
110 #define WCD934X_AMIC_PWR_LVL_MASK 0x60
111 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5
112
113 #define WCD934X_DEC_PWR_LVL_MASK 0x06
114 #define WCD934X_DEC_PWR_LVL_LP 0x02
115 #define WCD934X_DEC_PWR_LVL_HP 0x04
116 #define WCD934X_DEC_PWR_LVL_DF 0x00
117 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
118
119 #define WCD934X_DEF_MICBIAS_MV 1800
120 #define WCD934X_MAX_MICBIAS_MV 2850
121
122 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
123
124 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
125 { \
126 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
127 .info = wcd934x_iir_filter_info, \
128 .get = wcd934x_get_iir_band_audio_mixer, \
129 .put = wcd934x_put_iir_band_audio_mixer, \
130 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
131 .iir_idx = iidx, \
132 .band_idx = bidx, \
133 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
134 } \
135 }
136
137 /* Z value defined in milliohm */
138 #define WCD934X_ZDET_VAL_32 32000
139 #define WCD934X_ZDET_VAL_400 400000
140 #define WCD934X_ZDET_VAL_1200 1200000
141 #define WCD934X_ZDET_VAL_100K 100000000
142 /* Z floating defined in ohms */
143 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
144
145 #define WCD934X_ZDET_NUM_MEASUREMENTS 900
146 #define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
147 #define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF)
148 /* Z value compared in milliOhm */
149 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
150 #define WCD934X_MBHC_ZDET_CONST (86 * 16384)
151 #define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM
152 #define WCD934X_MBHC_MAX_BUTTONS (8)
153 #define WCD_MBHC_HS_V_MAX 1600
154
155 #define WCD934X_INTERPOLATOR_PATH(id) \
156 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
157 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
158 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
159 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
160 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
161 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
162 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
163 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
164 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
165 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
166 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
167 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
168 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
169 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
170 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
171 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
172 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
173 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
174 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
175 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
176 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
177 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
178 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
179 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
180 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
181 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
182 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
183 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
184 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
185 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
186 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
187 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
188 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
189 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
190 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
191 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
192 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
193 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
194 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
195 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
196 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
197 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
198 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
199 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
200 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
201 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
202 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
203 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
204 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
205
206 #define WCD934X_INTERPOLATOR_MIX2(id) \
207 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
208 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
209
210 #define WCD934X_SLIM_RX_AIF_PATH(id) \
211 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
212 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
213 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
214 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
215 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
216
217 #define WCD934X_ADC_MUX(id) \
218 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
219 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
220 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
221 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
222 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
223 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
224 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
225 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
226 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
227 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
228 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
229 {"AMIC MUX" #id, "ADC4", "ADC4"}
230
231 #define WCD934X_IIR_INP_MUX(id) \
232 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
233 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
234 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
235 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
236 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
237 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
238 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
239 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
240 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
241 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
242 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
243 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
244 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
245 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
246 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
247 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
248 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
249 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
250 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
251 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
252 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
253 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
254 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
255 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
256 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
257 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
258 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
259 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
260 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
261 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
262 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
263 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
264 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
265 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
266 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
267 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
268 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
269 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
270 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
271 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
272 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
273 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
274 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
275 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
276 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
277 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
278 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
279 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
280 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
281 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
282 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
283 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
284 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
285 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
286 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
287 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
288 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
289 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
290 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
291 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
292 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
293 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
294 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
295 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
296 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
297 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
298 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
299 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
300 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
301 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
302 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
303 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
304
305 #define WCD934X_SLIM_TX_AIF_PATH(id) \
306 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
307 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
308 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
309 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
310
311 #define WCD934X_MAX_MICBIAS MIC_BIAS_4
312 #define NUM_CODEC_DAIS 9
313
314 enum {
315 SIDO_SOURCE_INTERNAL,
316 SIDO_SOURCE_RCO_BG,
317 };
318
319 enum {
320 INTERP_EAR = 0,
321 INTERP_HPHL,
322 INTERP_HPHR,
323 INTERP_LO1,
324 INTERP_LO2,
325 INTERP_LO3_NA, /* LO3 not avalible in Tavil */
326 INTERP_LO4_NA,
327 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
328 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
329 INTERP_MAX,
330 };
331
332 enum {
333 WCD934X_RX0 = 0,
334 WCD934X_RX1,
335 WCD934X_RX2,
336 WCD934X_RX3,
337 WCD934X_RX4,
338 WCD934X_RX5,
339 WCD934X_RX6,
340 WCD934X_RX7,
341 WCD934X_RX8,
342 WCD934X_RX9,
343 WCD934X_RX10,
344 WCD934X_RX11,
345 WCD934X_RX12,
346 WCD934X_RX_MAX,
347 };
348
349 enum {
350 WCD934X_TX0 = 0,
351 WCD934X_TX1,
352 WCD934X_TX2,
353 WCD934X_TX3,
354 WCD934X_TX4,
355 WCD934X_TX5,
356 WCD934X_TX6,
357 WCD934X_TX7,
358 WCD934X_TX8,
359 WCD934X_TX9,
360 WCD934X_TX10,
361 WCD934X_TX11,
362 WCD934X_TX12,
363 WCD934X_TX13,
364 WCD934X_TX14,
365 WCD934X_TX15,
366 WCD934X_TX_MAX,
367 };
368
369 struct wcd934x_slim_ch {
370 u32 ch_num;
371 u16 port;
372 u16 shift;
373 struct list_head list;
374 };
375
376 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
377 WCD934X_SLIM_TX_CH(0),
378 WCD934X_SLIM_TX_CH(1),
379 WCD934X_SLIM_TX_CH(2),
380 WCD934X_SLIM_TX_CH(3),
381 WCD934X_SLIM_TX_CH(4),
382 WCD934X_SLIM_TX_CH(5),
383 WCD934X_SLIM_TX_CH(6),
384 WCD934X_SLIM_TX_CH(7),
385 WCD934X_SLIM_TX_CH(8),
386 WCD934X_SLIM_TX_CH(9),
387 WCD934X_SLIM_TX_CH(10),
388 WCD934X_SLIM_TX_CH(11),
389 WCD934X_SLIM_TX_CH(12),
390 WCD934X_SLIM_TX_CH(13),
391 WCD934X_SLIM_TX_CH(14),
392 WCD934X_SLIM_TX_CH(15),
393 };
394
395 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
396 WCD934X_SLIM_RX_CH(0), /* 16 */
397 WCD934X_SLIM_RX_CH(1), /* 17 */
398 WCD934X_SLIM_RX_CH(2),
399 WCD934X_SLIM_RX_CH(3),
400 WCD934X_SLIM_RX_CH(4),
401 WCD934X_SLIM_RX_CH(5),
402 WCD934X_SLIM_RX_CH(6),
403 WCD934X_SLIM_RX_CH(7),
404 WCD934X_SLIM_RX_CH(8),
405 WCD934X_SLIM_RX_CH(9),
406 WCD934X_SLIM_RX_CH(10),
407 WCD934X_SLIM_RX_CH(11),
408 WCD934X_SLIM_RX_CH(12),
409 };
410
411 /* Codec supports 2 IIR filters */
412 enum {
413 IIR0 = 0,
414 IIR1,
415 IIR_MAX,
416 };
417
418 /* Each IIR has 5 Filter Stages */
419 enum {
420 BAND1 = 0,
421 BAND2,
422 BAND3,
423 BAND4,
424 BAND5,
425 BAND_MAX,
426 };
427
428 enum {
429 COMPANDER_1, /* HPH_L */
430 COMPANDER_2, /* HPH_R */
431 COMPANDER_3, /* LO1_DIFF */
432 COMPANDER_4, /* LO2_DIFF */
433 COMPANDER_5, /* LO3_SE - not used in Tavil */
434 COMPANDER_6, /* LO4_SE - not used in Tavil */
435 COMPANDER_7, /* SWR SPK CH1 */
436 COMPANDER_8, /* SWR SPK CH2 */
437 COMPANDER_MAX,
438 };
439
440 enum {
441 INTn_1_INP_SEL_ZERO = 0,
442 INTn_1_INP_SEL_DEC0,
443 INTn_1_INP_SEL_DEC1,
444 INTn_1_INP_SEL_IIR0,
445 INTn_1_INP_SEL_IIR1,
446 INTn_1_INP_SEL_RX0,
447 INTn_1_INP_SEL_RX1,
448 INTn_1_INP_SEL_RX2,
449 INTn_1_INP_SEL_RX3,
450 INTn_1_INP_SEL_RX4,
451 INTn_1_INP_SEL_RX5,
452 INTn_1_INP_SEL_RX6,
453 INTn_1_INP_SEL_RX7,
454 };
455
456 enum {
457 INTn_2_INP_SEL_ZERO = 0,
458 INTn_2_INP_SEL_RX0,
459 INTn_2_INP_SEL_RX1,
460 INTn_2_INP_SEL_RX2,
461 INTn_2_INP_SEL_RX3,
462 INTn_2_INP_SEL_RX4,
463 INTn_2_INP_SEL_RX5,
464 INTn_2_INP_SEL_RX6,
465 INTn_2_INP_SEL_RX7,
466 INTn_2_INP_SEL_PROXIMITY,
467 };
468
469 struct interp_sample_rate {
470 int sample_rate;
471 int rate_val;
472 };
473
474 static const struct interp_sample_rate sr_val_tbl[] = {
475 {8000, 0x0},
476 {16000, 0x1},
477 {32000, 0x3},
478 {48000, 0x4},
479 {96000, 0x5},
480 {192000, 0x6},
481 {384000, 0x7},
482 {44100, 0x9},
483 {88200, 0xA},
484 {176400, 0xB},
485 {352800, 0xC},
486 };
487
488 struct wcd934x_mbhc_zdet_param {
489 u16 ldo_ctl;
490 u16 noff;
491 u16 nshift;
492 u16 btn5;
493 u16 btn6;
494 u16 btn7;
495 };
496
497 struct wcd_slim_codec_dai_data {
498 struct list_head slim_ch_list;
499 struct slim_stream_config sconfig;
500 struct slim_stream_runtime *sruntime;
501 };
502
503 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
504 {
505 .name = "WCD9335-IFC-DEV",
506 .range_min = 0x0,
507 .range_max = 0xffff,
508 .selector_reg = 0x800,
509 .selector_mask = 0xfff,
510 .selector_shift = 0,
511 .window_start = 0x800,
512 .window_len = 0x400,
513 },
514 };
515
516 static const struct regmap_config wcd934x_ifc_regmap_config = {
517 .reg_bits = 16,
518 .val_bits = 8,
519 .max_register = 0xffff,
520 .ranges = wcd934x_ifc_ranges,
521 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
522 };
523
524 struct wcd934x_codec {
525 struct device *dev;
526 struct clk_hw hw;
527 struct clk *extclk;
528 struct regmap *regmap;
529 struct regmap *if_regmap;
530 struct slim_device *sdev;
531 struct slim_device *sidev;
532 struct wcd_clsh_ctrl *clsh_ctrl;
533 struct snd_soc_component *component;
534 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
535 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
536 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
537 int rate;
538 u32 version;
539 u32 hph_mode;
540 u32 tx_port_value[WCD934X_TX_MAX];
541 u32 rx_port_value[WCD934X_RX_MAX];
542 int sido_input_src;
543 int dmic_0_1_clk_cnt;
544 int dmic_2_3_clk_cnt;
545 int dmic_4_5_clk_cnt;
546 int dmic_sample_rate;
547 int comp_enabled[COMPANDER_MAX];
548 int sysclk_users;
549 struct mutex sysclk_mutex;
550 /* mbhc module */
551 struct wcd_mbhc *mbhc;
552 struct wcd_mbhc_config mbhc_cfg;
553 struct wcd_mbhc_intr intr_ids;
554 bool mbhc_started;
555 struct mutex micb_lock;
556 u32 micb_ref[WCD934X_MAX_MICBIAS];
557 u32 pullup_ref[WCD934X_MAX_MICBIAS];
558 u32 micb2_mv;
559 };
560
561 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
562
563 struct wcd_iir_filter_ctl {
564 unsigned int iir_idx;
565 unsigned int band_idx;
566 struct soc_bytes_ext bytes_ext;
567 };
568
569 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
570 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
571 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
572 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
573
574 /* Cutoff frequency for high pass filter */
575 static const char * const cf_text[] = {
576 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
577 };
578
579 static const char * const rx_cf_text[] = {
580 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
581 "CF_NEG_3DB_0P48HZ"
582 };
583
584 static const char * const rx_hph_mode_mux_text[] = {
585 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
586 "Class-H Hi-Fi Low Power"
587 };
588
589 static const char *const slim_rx_mux_text[] = {
590 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
591 };
592
593 static const char * const rx_int0_7_mix_mux_text[] = {
594 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
595 "RX6", "RX7", "PROXIMITY"
596 };
597
598 static const char * const rx_int_mix_mux_text[] = {
599 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
600 "RX6", "RX7"
601 };
602
603 static const char * const rx_prim_mix_text[] = {
604 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
605 "RX3", "RX4", "RX5", "RX6", "RX7"
606 };
607
608 static const char * const rx_sidetone_mix_text[] = {
609 "ZERO", "SRC0", "SRC1", "SRC_SUM"
610 };
611
612 static const char * const iir_inp_mux_text[] = {
613 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
614 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
615 };
616
617 static const char * const rx_int_dem_inp_mux_text[] = {
618 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
619 };
620
621 static const char * const rx_int0_1_interp_mux_text[] = {
622 "ZERO", "RX INT0_1 MIX1",
623 };
624
625 static const char * const rx_int1_1_interp_mux_text[] = {
626 "ZERO", "RX INT1_1 MIX1",
627 };
628
629 static const char * const rx_int2_1_interp_mux_text[] = {
630 "ZERO", "RX INT2_1 MIX1",
631 };
632
633 static const char * const rx_int3_1_interp_mux_text[] = {
634 "ZERO", "RX INT3_1 MIX1",
635 };
636
637 static const char * const rx_int4_1_interp_mux_text[] = {
638 "ZERO", "RX INT4_1 MIX1",
639 };
640
641 static const char * const rx_int7_1_interp_mux_text[] = {
642 "ZERO", "RX INT7_1 MIX1",
643 };
644
645 static const char * const rx_int8_1_interp_mux_text[] = {
646 "ZERO", "RX INT8_1 MIX1",
647 };
648
649 static const char * const rx_int0_2_interp_mux_text[] = {
650 "ZERO", "RX INT0_2 MUX",
651 };
652
653 static const char * const rx_int1_2_interp_mux_text[] = {
654 "ZERO", "RX INT1_2 MUX",
655 };
656
657 static const char * const rx_int2_2_interp_mux_text[] = {
658 "ZERO", "RX INT2_2 MUX",
659 };
660
661 static const char * const rx_int3_2_interp_mux_text[] = {
662 "ZERO", "RX INT3_2 MUX",
663 };
664
665 static const char * const rx_int4_2_interp_mux_text[] = {
666 "ZERO", "RX INT4_2 MUX",
667 };
668
669 static const char * const rx_int7_2_interp_mux_text[] = {
670 "ZERO", "RX INT7_2 MUX",
671 };
672
673 static const char * const rx_int8_2_interp_mux_text[] = {
674 "ZERO", "RX INT8_2 MUX",
675 };
676
677 static const char * const dmic_mux_text[] = {
678 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
679 };
680
681 static const char * const amic_mux_text[] = {
682 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
683 };
684
685 static const char * const amic4_5_sel_text[] = {
686 "AMIC4", "AMIC5"
687 };
688
689 static const char * const adc_mux_text[] = {
690 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
691 };
692
693 static const char * const cdc_if_tx0_mux_text[] = {
694 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
695 };
696
697 static const char * const cdc_if_tx1_mux_text[] = {
698 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
699 };
700
701 static const char * const cdc_if_tx2_mux_text[] = {
702 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
703 };
704
705 static const char * const cdc_if_tx3_mux_text[] = {
706 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
707 };
708
709 static const char * const cdc_if_tx4_mux_text[] = {
710 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
711 };
712
713 static const char * const cdc_if_tx5_mux_text[] = {
714 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
715 };
716
717 static const char * const cdc_if_tx6_mux_text[] = {
718 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
719 };
720
721 static const char * const cdc_if_tx7_mux_text[] = {
722 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
723 };
724
725 static const char * const cdc_if_tx8_mux_text[] = {
726 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
727 };
728
729 static const char * const cdc_if_tx9_mux_text[] = {
730 "ZERO", "DEC7", "DEC7_192"
731 };
732
733 static const char * const cdc_if_tx10_mux_text[] = {
734 "ZERO", "DEC6", "DEC6_192"
735 };
736
737 static const char * const cdc_if_tx11_mux_text[] = {
738 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
739 };
740
741 static const char * const cdc_if_tx11_inp1_mux_text[] = {
742 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
743 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
744 };
745
746 static const char * const cdc_if_tx13_mux_text[] = {
747 "CDC_DEC_5", "MAD_BRDCST"
748 };
749
750 static const char * const cdc_if_tx13_inp1_mux_text[] = {
751 "ZERO", "DEC5", "DEC5_192"
752 };
753
754 static const struct soc_enum cf_dec0_enum =
755 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
756
757 static const struct soc_enum cf_dec1_enum =
758 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
759
760 static const struct soc_enum cf_dec2_enum =
761 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
762
763 static const struct soc_enum cf_dec3_enum =
764 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
765
766 static const struct soc_enum cf_dec4_enum =
767 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
768
769 static const struct soc_enum cf_dec5_enum =
770 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
771
772 static const struct soc_enum cf_dec6_enum =
773 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
774
775 static const struct soc_enum cf_dec7_enum =
776 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
777
778 static const struct soc_enum cf_dec8_enum =
779 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
780
781 static const struct soc_enum cf_int0_1_enum =
782 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
783
784 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
785 rx_cf_text);
786
787 static const struct soc_enum cf_int1_1_enum =
788 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
789
790 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
791 rx_cf_text);
792
793 static const struct soc_enum cf_int2_1_enum =
794 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
795
796 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
797 rx_cf_text);
798
799 static const struct soc_enum cf_int3_1_enum =
800 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
801
802 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
803 rx_cf_text);
804
805 static const struct soc_enum cf_int4_1_enum =
806 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
807
808 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
809 rx_cf_text);
810
811 static const struct soc_enum cf_int7_1_enum =
812 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
813
814 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
815 rx_cf_text);
816
817 static const struct soc_enum cf_int8_1_enum =
818 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
819
820 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
821 rx_cf_text);
822
823 static const struct soc_enum rx_hph_mode_mux_enum =
824 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
825 rx_hph_mode_mux_text);
826
827 static const struct soc_enum slim_rx_mux_enum =
828 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
829
830 static const struct soc_enum rx_int0_2_mux_chain_enum =
831 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
832 rx_int0_7_mix_mux_text);
833
834 static const struct soc_enum rx_int1_2_mux_chain_enum =
835 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
836 rx_int_mix_mux_text);
837
838 static const struct soc_enum rx_int2_2_mux_chain_enum =
839 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
840 rx_int_mix_mux_text);
841
842 static const struct soc_enum rx_int3_2_mux_chain_enum =
843 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
844 rx_int_mix_mux_text);
845
846 static const struct soc_enum rx_int4_2_mux_chain_enum =
847 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
848 rx_int_mix_mux_text);
849
850 static const struct soc_enum rx_int7_2_mux_chain_enum =
851 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
852 rx_int0_7_mix_mux_text);
853
854 static const struct soc_enum rx_int8_2_mux_chain_enum =
855 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
856 rx_int_mix_mux_text);
857
858 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
859 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
860 rx_prim_mix_text);
861
862 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
863 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
864 rx_prim_mix_text);
865
866 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
867 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
868 rx_prim_mix_text);
869
870 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
871 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
872 rx_prim_mix_text);
873
874 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
875 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
876 rx_prim_mix_text);
877
878 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
879 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
880 rx_prim_mix_text);
881
882 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
883 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
884 rx_prim_mix_text);
885
886 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
887 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
888 rx_prim_mix_text);
889
890 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
891 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
892 rx_prim_mix_text);
893
894 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
895 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
896 rx_prim_mix_text);
897
898 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
899 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
900 rx_prim_mix_text);
901
902 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
903 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
904 rx_prim_mix_text);
905
906 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
907 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
908 rx_prim_mix_text);
909
910 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
911 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
912 rx_prim_mix_text);
913
914 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
915 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
916 rx_prim_mix_text);
917
918 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
919 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
920 rx_prim_mix_text);
921
922 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
923 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
924 rx_prim_mix_text);
925
926 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
927 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
928 rx_prim_mix_text);
929
930 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
931 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
932 rx_prim_mix_text);
933
934 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
935 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
936 rx_prim_mix_text);
937
938 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
939 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
940 rx_prim_mix_text);
941
942 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
943 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
944 rx_sidetone_mix_text);
945
946 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
947 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
948 rx_sidetone_mix_text);
949
950 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
951 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
952 rx_sidetone_mix_text);
953
954 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
955 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
956 rx_sidetone_mix_text);
957
958 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
959 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
960 rx_sidetone_mix_text);
961
962 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
963 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
964 rx_sidetone_mix_text);
965
966 static const struct soc_enum iir0_inp0_mux_enum =
967 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
968 0, 18, iir_inp_mux_text);
969
970 static const struct soc_enum iir0_inp1_mux_enum =
971 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
972 0, 18, iir_inp_mux_text);
973
974 static const struct soc_enum iir0_inp2_mux_enum =
975 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
976 0, 18, iir_inp_mux_text);
977
978 static const struct soc_enum iir0_inp3_mux_enum =
979 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
980 0, 18, iir_inp_mux_text);
981
982 static const struct soc_enum iir1_inp0_mux_enum =
983 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
984 0, 18, iir_inp_mux_text);
985
986 static const struct soc_enum iir1_inp1_mux_enum =
987 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
988 0, 18, iir_inp_mux_text);
989
990 static const struct soc_enum iir1_inp2_mux_enum =
991 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
992 0, 18, iir_inp_mux_text);
993
994 static const struct soc_enum iir1_inp3_mux_enum =
995 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
996 0, 18, iir_inp_mux_text);
997
998 static const struct soc_enum rx_int0_dem_inp_mux_enum =
999 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
1000 ARRAY_SIZE(rx_int_dem_inp_mux_text),
1001 rx_int_dem_inp_mux_text);
1002
1003 static const struct soc_enum rx_int1_dem_inp_mux_enum =
1004 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
1005 ARRAY_SIZE(rx_int_dem_inp_mux_text),
1006 rx_int_dem_inp_mux_text);
1007
1008 static const struct soc_enum rx_int2_dem_inp_mux_enum =
1009 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
1010 ARRAY_SIZE(rx_int_dem_inp_mux_text),
1011 rx_int_dem_inp_mux_text);
1012
1013 static const struct soc_enum tx_adc_mux0_enum =
1014 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1015 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1016 static const struct soc_enum tx_adc_mux1_enum =
1017 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1018 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1019 static const struct soc_enum tx_adc_mux2_enum =
1020 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1021 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1022 static const struct soc_enum tx_adc_mux3_enum =
1023 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1024 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1025 static const struct soc_enum tx_adc_mux4_enum =
1026 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1027 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1028 static const struct soc_enum tx_adc_mux5_enum =
1029 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1030 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1031 static const struct soc_enum tx_adc_mux6_enum =
1032 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1033 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1034 static const struct soc_enum tx_adc_mux7_enum =
1035 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1036 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1037 static const struct soc_enum tx_adc_mux8_enum =
1038 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1039 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1040
1041 static const struct soc_enum rx_int0_1_interp_mux_enum =
1042 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1043 rx_int0_1_interp_mux_text);
1044
1045 static const struct soc_enum rx_int1_1_interp_mux_enum =
1046 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1047 rx_int1_1_interp_mux_text);
1048
1049 static const struct soc_enum rx_int2_1_interp_mux_enum =
1050 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1051 rx_int2_1_interp_mux_text);
1052
1053 static const struct soc_enum rx_int3_1_interp_mux_enum =
1054 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text);
1055
1056 static const struct soc_enum rx_int4_1_interp_mux_enum =
1057 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text);
1058
1059 static const struct soc_enum rx_int7_1_interp_mux_enum =
1060 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text);
1061
1062 static const struct soc_enum rx_int8_1_interp_mux_enum =
1063 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text);
1064
1065 static const struct soc_enum rx_int0_2_interp_mux_enum =
1066 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text);
1067
1068 static const struct soc_enum rx_int1_2_interp_mux_enum =
1069 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text);
1070
1071 static const struct soc_enum rx_int2_2_interp_mux_enum =
1072 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text);
1073
1074 static const struct soc_enum rx_int3_2_interp_mux_enum =
1075 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text);
1076
1077 static const struct soc_enum rx_int4_2_interp_mux_enum =
1078 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text);
1079
1080 static const struct soc_enum rx_int7_2_interp_mux_enum =
1081 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text);
1082
1083 static const struct soc_enum rx_int8_2_interp_mux_enum =
1084 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text);
1085
1086 static const struct soc_enum tx_dmic_mux0_enum =
1087 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1088 dmic_mux_text);
1089
1090 static const struct soc_enum tx_dmic_mux1_enum =
1091 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1092 dmic_mux_text);
1093
1094 static const struct soc_enum tx_dmic_mux2_enum =
1095 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1096 dmic_mux_text);
1097
1098 static const struct soc_enum tx_dmic_mux3_enum =
1099 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1100 dmic_mux_text);
1101
1102 static const struct soc_enum tx_dmic_mux4_enum =
1103 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1104 dmic_mux_text);
1105
1106 static const struct soc_enum tx_dmic_mux5_enum =
1107 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1108 dmic_mux_text);
1109
1110 static const struct soc_enum tx_dmic_mux6_enum =
1111 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1112 dmic_mux_text);
1113
1114 static const struct soc_enum tx_dmic_mux7_enum =
1115 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1116 dmic_mux_text);
1117
1118 static const struct soc_enum tx_dmic_mux8_enum =
1119 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1120 dmic_mux_text);
1121
1122 static const struct soc_enum tx_amic_mux0_enum =
1123 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1124 amic_mux_text);
1125 static const struct soc_enum tx_amic_mux1_enum =
1126 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1127 amic_mux_text);
1128 static const struct soc_enum tx_amic_mux2_enum =
1129 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1130 amic_mux_text);
1131 static const struct soc_enum tx_amic_mux3_enum =
1132 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1133 amic_mux_text);
1134 static const struct soc_enum tx_amic_mux4_enum =
1135 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1136 amic_mux_text);
1137 static const struct soc_enum tx_amic_mux5_enum =
1138 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1139 amic_mux_text);
1140 static const struct soc_enum tx_amic_mux6_enum =
1141 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1142 amic_mux_text);
1143 static const struct soc_enum tx_amic_mux7_enum =
1144 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1145 amic_mux_text);
1146 static const struct soc_enum tx_amic_mux8_enum =
1147 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1148 amic_mux_text);
1149
1150 static const struct soc_enum tx_amic4_5_enum =
1151 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1152
1153 static const struct soc_enum cdc_if_tx0_mux_enum =
1154 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1155 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1156 static const struct soc_enum cdc_if_tx1_mux_enum =
1157 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1158 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1159 static const struct soc_enum cdc_if_tx2_mux_enum =
1160 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1161 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1162 static const struct soc_enum cdc_if_tx3_mux_enum =
1163 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1164 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1165 static const struct soc_enum cdc_if_tx4_mux_enum =
1166 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1167 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1168 static const struct soc_enum cdc_if_tx5_mux_enum =
1169 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1170 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1171 static const struct soc_enum cdc_if_tx6_mux_enum =
1172 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1173 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1174 static const struct soc_enum cdc_if_tx7_mux_enum =
1175 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1176 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1177 static const struct soc_enum cdc_if_tx8_mux_enum =
1178 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1179 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1180 static const struct soc_enum cdc_if_tx9_mux_enum =
1181 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1182 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1183 static const struct soc_enum cdc_if_tx10_mux_enum =
1184 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1185 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1186 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1187 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1188 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1189 cdc_if_tx11_inp1_mux_text);
1190 static const struct soc_enum cdc_if_tx11_mux_enum =
1191 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1192 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1193 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1194 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1195 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1196 cdc_if_tx13_inp1_mux_text);
1197 static const struct soc_enum cdc_if_tx13_mux_enum =
1198 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1199 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1200
1201 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
1202 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80),
1203 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40),
1204 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20),
1205 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
1206 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08),
1207 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0),
1208 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04),
1209 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10),
1210 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08),
1211 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01),
1212 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06),
1213 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80),
1214 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
1215 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03),
1216 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03),
1217 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08),
1218 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1219 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20),
1220 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80),
1221 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40),
1222 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10),
1223 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07),
1224 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70),
1225 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF),
1226 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0),
1227 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF),
1228 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40),
1229 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80),
1230 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0),
1231 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1232 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02),
1233 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01),
1234 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70),
1235 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20),
1236 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40),
1237 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10),
1238 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01),
1239 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01),
1240 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04),
1241 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08),
1242 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08),
1243 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40),
1244 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80),
1245 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF),
1246 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F),
1247 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10),
1248 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04),
1249 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02),
1250 };
1251
wcd934x_set_sido_input_src(struct wcd934x_codec * wcd,int sido_src)1252 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1253 {
1254 if (sido_src == wcd->sido_input_src)
1255 return 0;
1256
1257 if (sido_src == SIDO_SOURCE_RCO_BG) {
1258 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1259 WCD934X_ANA_RCO_BG_EN_MASK,
1260 WCD934X_ANA_RCO_BG_ENABLE);
1261 usleep_range(100, 110);
1262 }
1263 wcd->sido_input_src = sido_src;
1264
1265 return 0;
1266 }
1267
wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec * wcd)1268 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1269 {
1270 mutex_lock(&wcd->sysclk_mutex);
1271
1272 if (++wcd->sysclk_users != 1) {
1273 mutex_unlock(&wcd->sysclk_mutex);
1274 return 0;
1275 }
1276 mutex_unlock(&wcd->sysclk_mutex);
1277
1278 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1279 WCD934X_ANA_BIAS_EN_MASK,
1280 WCD934X_ANA_BIAS_EN);
1281 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1282 WCD934X_ANA_PRECHRG_EN_MASK,
1283 WCD934X_ANA_PRECHRG_EN);
1284 /*
1285 * 1ms delay is required after pre-charge is enabled
1286 * as per HW requirement
1287 */
1288 usleep_range(1000, 1100);
1289 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1290 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1291 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1292 WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1293
1294 /*
1295 * In data clock contrl register is changed
1296 * to CLK_SYS_MCLK_PRG
1297 */
1298
1299 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1300 WCD934X_EXT_CLK_BUF_EN_MASK,
1301 WCD934X_EXT_CLK_BUF_EN);
1302 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1303 WCD934X_EXT_CLK_DIV_RATIO_MASK,
1304 WCD934X_EXT_CLK_DIV_BY_2);
1305 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1306 WCD934X_MCLK_SRC_MASK,
1307 WCD934X_MCLK_SRC_EXT_CLK);
1308 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1309 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1310 regmap_update_bits(wcd->regmap,
1311 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1312 WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1313 WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1314 regmap_update_bits(wcd->regmap,
1315 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1316 WCD934X_MCLK_EN_MASK,
1317 WCD934X_MCLK_EN);
1318 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1319 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1320 /*
1321 * 10us sleep is required after clock is enabled
1322 * as per HW requirement
1323 */
1324 usleep_range(10, 15);
1325
1326 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1327
1328 return 0;
1329 }
1330
wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec * wcd)1331 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1332 {
1333 mutex_lock(&wcd->sysclk_mutex);
1334 if (--wcd->sysclk_users != 0) {
1335 mutex_unlock(&wcd->sysclk_mutex);
1336 return 0;
1337 }
1338 mutex_unlock(&wcd->sysclk_mutex);
1339
1340 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1341 WCD934X_EXT_CLK_BUF_EN_MASK |
1342 WCD934X_MCLK_EN_MASK, 0x0);
1343 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1344 WCD934X_ANA_BIAS_EN_MASK, 0);
1345 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1346 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1347
1348 return 0;
1349 }
1350
__wcd934x_cdc_mclk_enable(struct wcd934x_codec * wcd,bool enable)1351 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1352 {
1353 int ret = 0;
1354
1355 if (enable) {
1356 ret = clk_prepare_enable(wcd->extclk);
1357
1358 if (ret) {
1359 dev_err(wcd->dev, "%s: ext clk enable failed\n",
1360 __func__);
1361 return ret;
1362 }
1363 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1364 } else {
1365 int val;
1366
1367 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1368 &val);
1369
1370 /* Don't disable clock if soundwire using it.*/
1371 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1372 return 0;
1373
1374 wcd934x_disable_ana_bias_and_syclk(wcd);
1375 clk_disable_unprepare(wcd->extclk);
1376 }
1377
1378 return ret;
1379 }
1380
wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)1381 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1382 struct snd_kcontrol *kc, int event)
1383 {
1384 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1385 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1386
1387 switch (event) {
1388 case SND_SOC_DAPM_PRE_PMU:
1389 return __wcd934x_cdc_mclk_enable(wcd, true);
1390 case SND_SOC_DAPM_POST_PMD:
1391 return __wcd934x_cdc_mclk_enable(wcd, false);
1392 }
1393
1394 return 0;
1395 }
1396
wcd934x_get_version(struct wcd934x_codec * wcd)1397 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1398 {
1399 int val1, val2, ver, ret;
1400 struct regmap *regmap;
1401 u16 id_minor;
1402 u32 version_mask = 0;
1403
1404 regmap = wcd->regmap;
1405 ver = 0;
1406
1407 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1408 (u8 *)&id_minor, sizeof(u16));
1409
1410 if (ret)
1411 return ret;
1412
1413 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1414 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1415
1416 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1417 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1418
1419 switch (version_mask) {
1420 case DSD_DISABLED | SLNQ_DISABLED:
1421 if (id_minor == 0)
1422 ver = WCD_VERSION_WCD9340_1_0;
1423 else if (id_minor == 0x01)
1424 ver = WCD_VERSION_WCD9340_1_1;
1425 break;
1426 case SLNQ_DISABLED:
1427 if (id_minor == 0)
1428 ver = WCD_VERSION_WCD9341_1_0;
1429 else if (id_minor == 0x01)
1430 ver = WCD_VERSION_WCD9341_1_1;
1431 break;
1432 }
1433
1434 wcd->version = ver;
1435 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1436
1437 return 0;
1438 }
1439
wcd934x_enable_efuse_sensing(struct wcd934x_codec * wcd)1440 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1441 {
1442 int rc, val;
1443
1444 __wcd934x_cdc_mclk_enable(wcd, true);
1445
1446 regmap_update_bits(wcd->regmap,
1447 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1448 WCD934X_EFUSE_SENSE_STATE_MASK,
1449 WCD934X_EFUSE_SENSE_STATE_DEF);
1450 regmap_update_bits(wcd->regmap,
1451 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1452 WCD934X_EFUSE_SENSE_EN_MASK,
1453 WCD934X_EFUSE_SENSE_ENABLE);
1454 /*
1455 * 5ms sleep required after enabling efuse control
1456 * before checking the status.
1457 */
1458 usleep_range(5000, 5500);
1459 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1460
1461 rc = regmap_read(wcd->regmap,
1462 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1463 if (rc || (!(val & 0x01)))
1464 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1465 __func__, val, rc);
1466
1467 __wcd934x_cdc_mclk_enable(wcd, false);
1468 }
1469
wcd934x_swrm_clock(struct wcd934x_codec * wcd,bool enable)1470 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1471 {
1472 if (enable) {
1473 __wcd934x_cdc_mclk_enable(wcd, true);
1474 regmap_update_bits(wcd->regmap,
1475 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1476 WCD934X_CDC_SWR_CLK_EN_MASK,
1477 WCD934X_CDC_SWR_CLK_ENABLE);
1478 } else {
1479 regmap_update_bits(wcd->regmap,
1480 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1481 WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1482 __wcd934x_cdc_mclk_enable(wcd, false);
1483 }
1484
1485 return 0;
1486 }
1487
wcd934x_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1488 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1489 u8 rate_val, u32 rate)
1490 {
1491 struct snd_soc_component *comp = dai->component;
1492 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1493 struct wcd934x_slim_ch *ch;
1494 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1495 int inp, j;
1496
1497 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1498 inp = ch->shift + INTn_1_INP_SEL_RX0;
1499 /*
1500 * Loop through all interpolator MUX inputs and find out
1501 * to which interpolator input, the slim rx port
1502 * is connected
1503 */
1504 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1505 /* Interpolators 5 and 6 are not aviliable in Tavil */
1506 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1507 continue;
1508
1509 cfg0 = snd_soc_component_read(comp,
1510 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1511 cfg1 = snd_soc_component_read(comp,
1512 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1513
1514 inp0_sel = cfg0 &
1515 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1516 inp1_sel = (cfg0 >> 4) &
1517 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1518 inp2_sel = (cfg1 >> 4) &
1519 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1520
1521 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1522 (inp2_sel == inp)) {
1523 /* rate is in Hz */
1524 /*
1525 * Ear and speaker primary path does not support
1526 * native sample rates
1527 */
1528 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1529 j == INTERP_SPKR2) && rate == 44100)
1530 dev_err(wcd->dev,
1531 "Cannot set 44.1KHz on INT%d\n",
1532 j);
1533 else
1534 snd_soc_component_update_bits(comp,
1535 WCD934X_CDC_RX_PATH_CTL(j),
1536 WCD934X_CDC_MIX_PCM_RATE_MASK,
1537 rate_val);
1538 }
1539 }
1540 }
1541
1542 return 0;
1543 }
1544
wcd934x_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1545 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1546 int rate_val, u32 rate)
1547 {
1548 struct snd_soc_component *component = dai->component;
1549 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1550 struct wcd934x_slim_ch *ch;
1551 int val, j;
1552
1553 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1554 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1555 /* Interpolators 5 and 6 are not aviliable in Tavil */
1556 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1557 continue;
1558 val = snd_soc_component_read(component,
1559 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1560 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1561
1562 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1563 /*
1564 * Ear mix path supports only 48, 96, 192,
1565 * 384KHz only
1566 */
1567 if ((j == INTERP_EAR) &&
1568 (rate_val < 0x4 ||
1569 rate_val > 0x7)) {
1570 dev_err(component->dev,
1571 "Invalid rate for AIF_PB DAI(%d)\n",
1572 dai->id);
1573 return -EINVAL;
1574 }
1575
1576 snd_soc_component_update_bits(component,
1577 WCD934X_CDC_RX_PATH_MIX_CTL(j),
1578 WCD934X_CDC_MIX_PCM_RATE_MASK,
1579 rate_val);
1580 }
1581 }
1582 }
1583
1584 return 0;
1585 }
1586
wcd934x_set_interpolator_rate(struct snd_soc_dai * dai,u32 sample_rate)1587 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1588 u32 sample_rate)
1589 {
1590 int rate_val = 0;
1591 int i, ret;
1592
1593 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1594 if (sample_rate == sr_val_tbl[i].sample_rate) {
1595 rate_val = sr_val_tbl[i].rate_val;
1596 break;
1597 }
1598 }
1599 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1600 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1601 return -EINVAL;
1602 }
1603
1604 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1605 sample_rate);
1606 if (ret)
1607 return ret;
1608 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1609 sample_rate);
1610
1611 return ret;
1612 }
1613
wcd934x_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1614 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1615 u8 rate_val, u32 rate)
1616 {
1617 struct snd_soc_component *comp = dai->component;
1618 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1619 u8 shift = 0, shift_val = 0, tx_mux_sel;
1620 struct wcd934x_slim_ch *ch;
1621 int tx_port, tx_port_reg;
1622 int decimator = -1;
1623
1624 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1625 tx_port = ch->port;
1626 /* Find the SB TX MUX input - which decimator is connected */
1627 switch (tx_port) {
1628 case 0 ... 3:
1629 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1630 shift = (tx_port << 1);
1631 shift_val = 0x03;
1632 break;
1633 case 4 ... 7:
1634 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1635 shift = ((tx_port - 4) << 1);
1636 shift_val = 0x03;
1637 break;
1638 case 8 ... 10:
1639 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1640 shift = ((tx_port - 8) << 1);
1641 shift_val = 0x03;
1642 break;
1643 case 11:
1644 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1645 shift = 0;
1646 shift_val = 0x0F;
1647 break;
1648 case 13:
1649 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1650 shift = 4;
1651 shift_val = 0x03;
1652 break;
1653 default:
1654 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1655 tx_port, dai->id);
1656 return -EINVAL;
1657 }
1658
1659 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1660 (shift_val << shift);
1661
1662 tx_mux_sel = tx_mux_sel >> shift;
1663 switch (tx_port) {
1664 case 0 ... 8:
1665 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1666 decimator = tx_port;
1667 break;
1668 case 9 ... 10:
1669 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1670 decimator = ((tx_port == 9) ? 7 : 6);
1671 break;
1672 case 11:
1673 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1674 decimator = tx_mux_sel - 1;
1675 break;
1676 case 13:
1677 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1678 decimator = 5;
1679 break;
1680 default:
1681 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1682 tx_port);
1683 return -EINVAL;
1684 }
1685
1686 snd_soc_component_update_bits(comp,
1687 WCD934X_CDC_TX_PATH_CTL(decimator),
1688 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1689 rate_val);
1690 }
1691
1692 return 0;
1693 }
1694
wcd934x_slim_set_hw_params(struct wcd934x_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1695 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1696 struct wcd_slim_codec_dai_data *dai_data,
1697 int direction)
1698 {
1699 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1700 struct slim_stream_config *cfg = &dai_data->sconfig;
1701 struct wcd934x_slim_ch *ch;
1702 u16 payload = 0;
1703 int ret, i;
1704
1705 cfg->ch_count = 0;
1706 cfg->direction = direction;
1707 cfg->port_mask = 0;
1708
1709 /* Configure slave interface device */
1710 list_for_each_entry(ch, slim_ch_list, list) {
1711 cfg->ch_count++;
1712 payload |= 1 << ch->shift;
1713 cfg->port_mask |= BIT(ch->port);
1714 }
1715
1716 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1717 if (!cfg->chs)
1718 return -ENOMEM;
1719
1720 i = 0;
1721 list_for_each_entry(ch, slim_ch_list, list) {
1722 cfg->chs[i++] = ch->ch_num;
1723 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1724 /* write to interface device */
1725 ret = regmap_write(wcd->if_regmap,
1726 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1727 payload);
1728
1729 if (ret < 0)
1730 goto err;
1731
1732 /* configure the slave port for water mark and enable*/
1733 ret = regmap_write(wcd->if_regmap,
1734 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1735 WCD934X_SLIM_WATER_MARK_VAL);
1736 if (ret < 0)
1737 goto err;
1738 } else {
1739 ret = regmap_write(wcd->if_regmap,
1740 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1741 payload & 0x00FF);
1742 if (ret < 0)
1743 goto err;
1744
1745 /* ports 8,9 */
1746 ret = regmap_write(wcd->if_regmap,
1747 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1748 (payload & 0xFF00) >> 8);
1749 if (ret < 0)
1750 goto err;
1751
1752 /* configure the slave port for water mark and enable*/
1753 ret = regmap_write(wcd->if_regmap,
1754 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1755 WCD934X_SLIM_WATER_MARK_VAL);
1756
1757 if (ret < 0)
1758 goto err;
1759 }
1760 }
1761
1762 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1763
1764 return 0;
1765
1766 err:
1767 dev_err(wcd->dev, "Error Setting slim hw params\n");
1768 kfree(cfg->chs);
1769 cfg->chs = NULL;
1770
1771 return ret;
1772 }
1773
wcd934x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1774 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1775 struct snd_pcm_hw_params *params,
1776 struct snd_soc_dai *dai)
1777 {
1778 struct wcd934x_codec *wcd;
1779 int ret, tx_fs_rate = 0;
1780
1781 wcd = snd_soc_component_get_drvdata(dai->component);
1782
1783 switch (substream->stream) {
1784 case SNDRV_PCM_STREAM_PLAYBACK:
1785 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1786 if (ret) {
1787 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1788 params_rate(params));
1789 return ret;
1790 }
1791 switch (params_width(params)) {
1792 case 16 ... 24:
1793 wcd->dai[dai->id].sconfig.bps = params_width(params);
1794 break;
1795 default:
1796 dev_err(wcd->dev, "Invalid format 0x%x\n",
1797 params_width(params));
1798 return -EINVAL;
1799 }
1800 break;
1801
1802 case SNDRV_PCM_STREAM_CAPTURE:
1803 switch (params_rate(params)) {
1804 case 8000:
1805 tx_fs_rate = 0;
1806 break;
1807 case 16000:
1808 tx_fs_rate = 1;
1809 break;
1810 case 32000:
1811 tx_fs_rate = 3;
1812 break;
1813 case 48000:
1814 tx_fs_rate = 4;
1815 break;
1816 case 96000:
1817 tx_fs_rate = 5;
1818 break;
1819 case 192000:
1820 tx_fs_rate = 6;
1821 break;
1822 case 384000:
1823 tx_fs_rate = 7;
1824 break;
1825 default:
1826 dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1827 params_rate(params));
1828 return -EINVAL;
1829
1830 }
1831
1832 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1833 params_rate(params));
1834 if (ret < 0) {
1835 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1836 return ret;
1837 }
1838 switch (params_width(params)) {
1839 case 16 ... 32:
1840 wcd->dai[dai->id].sconfig.bps = params_width(params);
1841 break;
1842 default:
1843 dev_err(wcd->dev, "Invalid format 0x%x\n",
1844 params_width(params));
1845 return -EINVAL;
1846 }
1847 break;
1848 default:
1849 dev_err(wcd->dev, "Invalid stream type %d\n",
1850 substream->stream);
1851 return -EINVAL;
1852 }
1853
1854 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1855
1856 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1857 }
1858
wcd934x_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1859 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1860 struct snd_soc_dai *dai)
1861 {
1862 struct wcd_slim_codec_dai_data *dai_data;
1863 struct wcd934x_codec *wcd;
1864
1865 wcd = snd_soc_component_get_drvdata(dai->component);
1866
1867 dai_data = &wcd->dai[dai->id];
1868
1869 kfree(dai_data->sconfig.chs);
1870
1871 return 0;
1872 }
1873
wcd934x_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1874 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1875 struct snd_soc_dai *dai)
1876 {
1877 struct wcd_slim_codec_dai_data *dai_data;
1878 struct wcd934x_codec *wcd;
1879 struct slim_stream_config *cfg;
1880
1881 wcd = snd_soc_component_get_drvdata(dai->component);
1882
1883 dai_data = &wcd->dai[dai->id];
1884
1885 switch (cmd) {
1886 case SNDRV_PCM_TRIGGER_START:
1887 case SNDRV_PCM_TRIGGER_RESUME:
1888 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1889 cfg = &dai_data->sconfig;
1890 slim_stream_prepare(dai_data->sruntime, cfg);
1891 slim_stream_enable(dai_data->sruntime);
1892 break;
1893 case SNDRV_PCM_TRIGGER_STOP:
1894 case SNDRV_PCM_TRIGGER_SUSPEND:
1895 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1896 slim_stream_disable(dai_data->sruntime);
1897 slim_stream_unprepare(dai_data->sruntime);
1898 break;
1899 default:
1900 break;
1901 }
1902
1903 return 0;
1904 }
1905
wcd934x_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,const unsigned int * tx_slot,unsigned int rx_num,const unsigned int * rx_slot)1906 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1907 unsigned int tx_num,
1908 const unsigned int *tx_slot,
1909 unsigned int rx_num,
1910 const unsigned int *rx_slot)
1911 {
1912 struct wcd934x_codec *wcd;
1913 int i;
1914
1915 wcd = snd_soc_component_get_drvdata(dai->component);
1916
1917 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1918 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1919 tx_num, rx_num);
1920 return -EINVAL;
1921 }
1922
1923 if (!tx_slot || !rx_slot) {
1924 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1925 tx_slot, rx_slot);
1926 return -EINVAL;
1927 }
1928
1929 for (i = 0; i < rx_num; i++) {
1930 wcd->rx_chs[i].ch_num = rx_slot[i];
1931 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1932 }
1933
1934 for (i = 0; i < tx_num; i++) {
1935 wcd->tx_chs[i].ch_num = tx_slot[i];
1936 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1937 }
1938
1939 return 0;
1940 }
1941
wcd934x_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)1942 static int wcd934x_get_channel_map(const struct snd_soc_dai *dai,
1943 unsigned int *tx_num, unsigned int *tx_slot,
1944 unsigned int *rx_num, unsigned int *rx_slot)
1945 {
1946 struct wcd934x_slim_ch *ch;
1947 struct wcd934x_codec *wcd;
1948 int i = 0;
1949
1950 wcd = snd_soc_component_get_drvdata(dai->component);
1951
1952 switch (dai->id) {
1953 case AIF1_PB:
1954 case AIF2_PB:
1955 case AIF3_PB:
1956 case AIF4_PB:
1957 if (!rx_slot || !rx_num) {
1958 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1959 rx_slot, rx_num);
1960 return -EINVAL;
1961 }
1962
1963 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1964 rx_slot[i++] = ch->ch_num;
1965
1966 *rx_num = i;
1967 break;
1968 case AIF1_CAP:
1969 case AIF2_CAP:
1970 case AIF3_CAP:
1971 if (!tx_slot || !tx_num) {
1972 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1973 tx_slot, tx_num);
1974 return -EINVAL;
1975 }
1976
1977 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1978 tx_slot[i++] = ch->ch_num;
1979
1980 *tx_num = i;
1981 break;
1982 default:
1983 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1984 break;
1985 }
1986
1987 return 0;
1988 }
1989
1990 static const struct snd_soc_dai_ops wcd934x_dai_ops = {
1991 .hw_params = wcd934x_hw_params,
1992 .hw_free = wcd934x_hw_free,
1993 .trigger = wcd934x_trigger,
1994 .set_channel_map = wcd934x_set_channel_map,
1995 .get_channel_map = wcd934x_get_channel_map,
1996 };
1997
1998 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
1999 [0] = {
2000 .name = "wcd934x_rx1",
2001 .id = AIF1_PB,
2002 .playback = {
2003 .stream_name = "AIF1 Playback",
2004 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2005 .formats = WCD934X_FORMATS_S16_S24_LE,
2006 .rate_max = 192000,
2007 .rate_min = 8000,
2008 .channels_min = 1,
2009 .channels_max = 2,
2010 },
2011 .ops = &wcd934x_dai_ops,
2012 },
2013 [1] = {
2014 .name = "wcd934x_tx1",
2015 .id = AIF1_CAP,
2016 .capture = {
2017 .stream_name = "AIF1 Capture",
2018 .rates = WCD934X_RATES_MASK,
2019 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2020 .rate_min = 8000,
2021 .rate_max = 192000,
2022 .channels_min = 1,
2023 .channels_max = 4,
2024 },
2025 .ops = &wcd934x_dai_ops,
2026 },
2027 [2] = {
2028 .name = "wcd934x_rx2",
2029 .id = AIF2_PB,
2030 .playback = {
2031 .stream_name = "AIF2 Playback",
2032 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2033 .formats = WCD934X_FORMATS_S16_S24_LE,
2034 .rate_min = 8000,
2035 .rate_max = 192000,
2036 .channels_min = 1,
2037 .channels_max = 2,
2038 },
2039 .ops = &wcd934x_dai_ops,
2040 },
2041 [3] = {
2042 .name = "wcd934x_tx2",
2043 .id = AIF2_CAP,
2044 .capture = {
2045 .stream_name = "AIF2 Capture",
2046 .rates = WCD934X_RATES_MASK,
2047 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2048 .rate_min = 8000,
2049 .rate_max = 192000,
2050 .channels_min = 1,
2051 .channels_max = 4,
2052 },
2053 .ops = &wcd934x_dai_ops,
2054 },
2055 [4] = {
2056 .name = "wcd934x_rx3",
2057 .id = AIF3_PB,
2058 .playback = {
2059 .stream_name = "AIF3 Playback",
2060 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2061 .formats = WCD934X_FORMATS_S16_S24_LE,
2062 .rate_min = 8000,
2063 .rate_max = 192000,
2064 .channels_min = 1,
2065 .channels_max = 2,
2066 },
2067 .ops = &wcd934x_dai_ops,
2068 },
2069 [5] = {
2070 .name = "wcd934x_tx3",
2071 .id = AIF3_CAP,
2072 .capture = {
2073 .stream_name = "AIF3 Capture",
2074 .rates = WCD934X_RATES_MASK,
2075 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2076 .rate_min = 8000,
2077 .rate_max = 192000,
2078 .channels_min = 1,
2079 .channels_max = 4,
2080 },
2081 .ops = &wcd934x_dai_ops,
2082 },
2083 [6] = {
2084 .name = "wcd934x_rx4",
2085 .id = AIF4_PB,
2086 .playback = {
2087 .stream_name = "AIF4 Playback",
2088 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2089 .formats = WCD934X_FORMATS_S16_S24_LE,
2090 .rate_min = 8000,
2091 .rate_max = 192000,
2092 .channels_min = 1,
2093 .channels_max = 2,
2094 },
2095 .ops = &wcd934x_dai_ops,
2096 },
2097 };
2098
swclk_gate_enable(struct clk_hw * hw)2099 static int swclk_gate_enable(struct clk_hw *hw)
2100 {
2101 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2102 }
2103
swclk_gate_disable(struct clk_hw * hw)2104 static void swclk_gate_disable(struct clk_hw *hw)
2105 {
2106 wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2107 }
2108
swclk_gate_is_enabled(struct clk_hw * hw)2109 static int swclk_gate_is_enabled(struct clk_hw *hw)
2110 {
2111 struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2112 int ret, val;
2113
2114 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2115 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2116
2117 return ret;
2118 }
2119
swclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2120 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2121 unsigned long parent_rate)
2122 {
2123 return parent_rate / 2;
2124 }
2125
2126 static const struct clk_ops swclk_gate_ops = {
2127 .prepare = swclk_gate_enable,
2128 .unprepare = swclk_gate_disable,
2129 .is_enabled = swclk_gate_is_enabled,
2130 .recalc_rate = swclk_recalc_rate,
2131
2132 };
2133
wcd934x_register_mclk_output(struct wcd934x_codec * wcd)2134 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2135 {
2136 struct clk *parent = wcd->extclk;
2137 struct device *dev = wcd->dev;
2138 struct device_node *np = dev->parent->of_node;
2139 const char *parent_clk_name = NULL;
2140 const char *clk_name = "mclk";
2141 struct clk_hw *hw;
2142 struct clk_init_data init;
2143 int ret;
2144
2145 if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2146 return NULL;
2147
2148 parent_clk_name = __clk_get_name(parent);
2149
2150 of_property_read_string(np, "clock-output-names", &clk_name);
2151
2152 init.name = clk_name;
2153 init.ops = &swclk_gate_ops;
2154 init.flags = 0;
2155 init.parent_names = &parent_clk_name;
2156 init.num_parents = 1;
2157 wcd->hw.init = &init;
2158
2159 hw = &wcd->hw;
2160 ret = devm_clk_hw_register(wcd->dev->parent, hw);
2161 if (ret)
2162 return ERR_PTR(ret);
2163
2164 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2165 if (ret)
2166 return ERR_PTR(ret);
2167
2168 return NULL;
2169 }
2170
wcd934x_get_micbias_val(struct device * dev,const char * micbias,u32 * micb_mv)2171 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias,
2172 u32 *micb_mv)
2173 {
2174 int mv;
2175
2176 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2177 dev_err(dev, "%s value not found, using default\n", micbias);
2178 mv = WCD934X_DEF_MICBIAS_MV;
2179 } else {
2180 /* convert it to milli volts */
2181 mv = mv/1000;
2182 }
2183
2184 if (mv < 1000 || mv > 2850) {
2185 dev_err(dev, "%s value not in valid range, using default\n",
2186 micbias);
2187 mv = WCD934X_DEF_MICBIAS_MV;
2188 }
2189
2190 if (micb_mv)
2191 *micb_mv = mv;
2192
2193 return (mv - 1000) / 50;
2194 }
2195
wcd934x_init_dmic(struct snd_soc_component * comp)2196 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2197 {
2198 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2199 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2200 u32 def_dmic_rate, dmic_clk_drv;
2201
2202 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2203 "qcom,micbias1-microvolt", NULL);
2204 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2205 "qcom,micbias2-microvolt",
2206 &wcd->micb2_mv);
2207 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2208 "qcom,micbias3-microvolt", NULL);
2209 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2210 "qcom,micbias4-microvolt", NULL);
2211
2212 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2213 WCD934X_MICB_VAL_MASK, vout_ctl_1);
2214 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2215 WCD934X_MICB_VAL_MASK, vout_ctl_2);
2216 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2217 WCD934X_MICB_VAL_MASK, vout_ctl_3);
2218 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2219 WCD934X_MICB_VAL_MASK, vout_ctl_4);
2220
2221 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2222 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2223 else
2224 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2225
2226 wcd->dmic_sample_rate = def_dmic_rate;
2227
2228 dmic_clk_drv = 0;
2229 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2230 0x0C, dmic_clk_drv << 2);
2231
2232 return 0;
2233 }
2234
wcd934x_hw_init(struct wcd934x_codec * wcd)2235 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2236 {
2237 struct regmap *rm = wcd->regmap;
2238
2239 /* set SPKR rate to FS_2P4_3P072 */
2240 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2241 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2242
2243 /* Take DMICs out of reset */
2244 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2245 }
2246
wcd934x_comp_init(struct snd_soc_component * component)2247 static int wcd934x_comp_init(struct snd_soc_component *component)
2248 {
2249 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2250
2251 wcd934x_hw_init(wcd);
2252 wcd934x_enable_efuse_sensing(wcd);
2253 wcd934x_get_version(wcd);
2254
2255 return 0;
2256 }
2257
wcd934x_slim_irq_handler(int irq,void * data)2258 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2259 {
2260 struct wcd934x_codec *wcd = data;
2261 unsigned long status = 0;
2262 unsigned int i, j, port_id;
2263 unsigned int val, int_val = 0;
2264 irqreturn_t ret = IRQ_NONE;
2265 bool tx;
2266 unsigned short reg = 0;
2267
2268 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2269 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2270 regmap_read(wcd->if_regmap, i, &val);
2271 status |= ((u32)val << (8 * j));
2272 }
2273
2274 for_each_set_bit(j, &status, 32) {
2275 tx = false;
2276 port_id = j;
2277
2278 if (j >= 16) {
2279 tx = true;
2280 port_id = j - 16;
2281 }
2282
2283 regmap_read(wcd->if_regmap,
2284 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2285 if (val) {
2286 if (!tx)
2287 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2288 (port_id / 8);
2289 else
2290 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2291 (port_id / 8);
2292 regmap_read(wcd->if_regmap, reg, &int_val);
2293 }
2294
2295 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2296 dev_err_ratelimited(wcd->dev,
2297 "overflow error on %s port %d, value %x\n",
2298 (tx ? "TX" : "RX"), port_id, val);
2299
2300 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2301 dev_err_ratelimited(wcd->dev,
2302 "underflow error on %s port %d, value %x\n",
2303 (tx ? "TX" : "RX"), port_id, val);
2304
2305 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2306 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2307 if (!tx)
2308 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2309 (port_id / 8);
2310 else
2311 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2312 (port_id / 8);
2313 regmap_read(
2314 wcd->if_regmap, reg, &int_val);
2315 if (int_val & (1 << (port_id % 8))) {
2316 int_val = int_val ^ (1 << (port_id % 8));
2317 regmap_write(wcd->if_regmap,
2318 reg, int_val);
2319 }
2320 }
2321
2322 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2323 dev_err_ratelimited(wcd->dev,
2324 "Port Closed %s port %d, value %x\n",
2325 (tx ? "TX" : "RX"), port_id, val);
2326
2327 regmap_write(wcd->if_regmap,
2328 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2329 BIT(j % 8));
2330 ret = IRQ_HANDLED;
2331 }
2332
2333 return ret;
2334 }
2335
wcd934x_mbhc_clk_setup(struct snd_soc_component * component,bool enable)2336 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component,
2337 bool enable)
2338 {
2339 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1,
2340 WCD934X_MBHC_CTL_RCO_EN_MASK, enable);
2341 }
2342
wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component * component,bool enable)2343 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2344 bool enable)
2345 {
2346 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT,
2347 WCD934X_ANA_MBHC_BIAS_EN, enable);
2348 }
2349
wcd934x_mbhc_program_btn_thr(struct snd_soc_component * component,int * btn_low,int * btn_high,int num_btn,bool is_micbias)2350 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component,
2351 int *btn_low, int *btn_high,
2352 int num_btn, bool is_micbias)
2353 {
2354 int i, vth;
2355
2356 if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2357 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2358 __func__, num_btn);
2359 return;
2360 }
2361
2362 for (i = 0; i < num_btn; i++) {
2363 vth = ((btn_high[i] * 2) / 25) & 0x3F;
2364 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i,
2365 WCD934X_MBHC_BTN_VTH_MASK, vth);
2366 }
2367 }
2368
wcd934x_mbhc_micb_en_status(struct snd_soc_component * component,int micb_num)2369 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2370 {
2371 u8 val;
2372
2373 if (micb_num == MIC_BIAS_2) {
2374 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2,
2375 WCD934X_ANA_MICB2_ENABLE_MASK);
2376 if (val == WCD934X_MICB_ENABLE)
2377 return true;
2378 }
2379 return false;
2380 }
2381
wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component * component,enum mbhc_hs_pullup_iref pull_up_cur)2382 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2383 enum mbhc_hs_pullup_iref pull_up_cur)
2384 {
2385 /* Default pull up current to 2uA */
2386 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
2387 pull_up_cur == I_DEFAULT)
2388 pull_up_cur = I_2P0_UA;
2389
2390
2391 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL,
2392 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur);
2393 }
2394
wcd934x_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2395 static int wcd934x_micbias_control(struct snd_soc_component *component,
2396 int micb_num, int req, bool is_dapm)
2397 {
2398 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2399 int micb_index = micb_num - 1;
2400 u16 micb_reg;
2401
2402 switch (micb_num) {
2403 case MIC_BIAS_1:
2404 micb_reg = WCD934X_ANA_MICB1;
2405 break;
2406 case MIC_BIAS_2:
2407 micb_reg = WCD934X_ANA_MICB2;
2408 break;
2409 case MIC_BIAS_3:
2410 micb_reg = WCD934X_ANA_MICB3;
2411 break;
2412 case MIC_BIAS_4:
2413 micb_reg = WCD934X_ANA_MICB4;
2414 break;
2415 default:
2416 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2417 __func__, micb_num);
2418 return -EINVAL;
2419 }
2420 mutex_lock(&wcd934x->micb_lock);
2421
2422 switch (req) {
2423 case MICB_PULLUP_ENABLE:
2424 wcd934x->pullup_ref[micb_index]++;
2425 if ((wcd934x->pullup_ref[micb_index] == 1) &&
2426 (wcd934x->micb_ref[micb_index] == 0))
2427 snd_soc_component_write_field(component, micb_reg,
2428 WCD934X_ANA_MICB_EN_MASK,
2429 WCD934X_MICB_PULL_UP);
2430 break;
2431 case MICB_PULLUP_DISABLE:
2432 if (wcd934x->pullup_ref[micb_index] > 0)
2433 wcd934x->pullup_ref[micb_index]--;
2434
2435 if ((wcd934x->pullup_ref[micb_index] == 0) &&
2436 (wcd934x->micb_ref[micb_index] == 0))
2437 snd_soc_component_write_field(component, micb_reg,
2438 WCD934X_ANA_MICB_EN_MASK, 0);
2439 break;
2440 case MICB_ENABLE:
2441 wcd934x->micb_ref[micb_index]++;
2442 if (wcd934x->micb_ref[micb_index] == 1) {
2443 snd_soc_component_write_field(component, micb_reg,
2444 WCD934X_ANA_MICB_EN_MASK,
2445 WCD934X_MICB_ENABLE);
2446 if (micb_num == MIC_BIAS_2)
2447 wcd_mbhc_event_notify(wcd934x->mbhc,
2448 WCD_EVENT_POST_MICBIAS_2_ON);
2449 }
2450
2451 if (micb_num == MIC_BIAS_2 && is_dapm)
2452 wcd_mbhc_event_notify(wcd934x->mbhc,
2453 WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2454 break;
2455 case MICB_DISABLE:
2456 if (wcd934x->micb_ref[micb_index] > 0)
2457 wcd934x->micb_ref[micb_index]--;
2458
2459 if ((wcd934x->micb_ref[micb_index] == 0) &&
2460 (wcd934x->pullup_ref[micb_index] > 0))
2461 snd_soc_component_write_field(component, micb_reg,
2462 WCD934X_ANA_MICB_EN_MASK,
2463 WCD934X_MICB_PULL_UP);
2464 else if ((wcd934x->micb_ref[micb_index] == 0) &&
2465 (wcd934x->pullup_ref[micb_index] == 0)) {
2466 if (micb_num == MIC_BIAS_2)
2467 wcd_mbhc_event_notify(wcd934x->mbhc,
2468 WCD_EVENT_PRE_MICBIAS_2_OFF);
2469
2470 snd_soc_component_write_field(component, micb_reg,
2471 WCD934X_ANA_MICB_EN_MASK, 0);
2472 if (micb_num == MIC_BIAS_2)
2473 wcd_mbhc_event_notify(wcd934x->mbhc,
2474 WCD_EVENT_POST_MICBIAS_2_OFF);
2475 }
2476 if (is_dapm && micb_num == MIC_BIAS_2)
2477 wcd_mbhc_event_notify(wcd934x->mbhc,
2478 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2479 break;
2480 }
2481
2482 mutex_unlock(&wcd934x->micb_lock);
2483
2484 return 0;
2485 }
2486
wcd934x_mbhc_request_micbias(struct snd_soc_component * component,int micb_num,int req)2487 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component,
2488 int micb_num, int req)
2489 {
2490 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2491 int ret;
2492
2493 if (req == MICB_ENABLE)
2494 __wcd934x_cdc_mclk_enable(wcd, true);
2495
2496 ret = wcd934x_micbias_control(component, micb_num, req, false);
2497
2498 if (req == MICB_DISABLE)
2499 __wcd934x_cdc_mclk_enable(wcd, false);
2500
2501 return ret;
2502 }
2503
wcd934x_mbhc_micb_ramp_control(struct snd_soc_component * component,bool enable)2504 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component,
2505 bool enable)
2506 {
2507 if (enable) {
2508 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2509 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3);
2510 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2511 WCD934X_RAMP_EN_MASK, 1);
2512 } else {
2513 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2514 WCD934X_RAMP_EN_MASK, 0);
2515 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2516 WCD934X_RAMP_SHIFT_CTRL_MASK, 0);
2517 }
2518 }
2519
wcd934x_get_micb_vout_ctl_val(u32 micb_mv)2520 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv)
2521 {
2522 /* min micbias voltage is 1V and maximum is 2.85V */
2523 if (micb_mv < 1000 || micb_mv > 2850)
2524 return -EINVAL;
2525
2526 return (micb_mv - 1000) / 50;
2527 }
2528
wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component * component,int req_volt,int micb_num)2529 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
2530 int req_volt, int micb_num)
2531 {
2532 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2533 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
2534
2535 switch (micb_num) {
2536 case MIC_BIAS_1:
2537 micb_reg = WCD934X_ANA_MICB1;
2538 break;
2539 case MIC_BIAS_2:
2540 micb_reg = WCD934X_ANA_MICB2;
2541 break;
2542 case MIC_BIAS_3:
2543 micb_reg = WCD934X_ANA_MICB3;
2544 break;
2545 case MIC_BIAS_4:
2546 micb_reg = WCD934X_ANA_MICB4;
2547 break;
2548 default:
2549 return -EINVAL;
2550 }
2551 mutex_lock(&wcd934x->micb_lock);
2552 /*
2553 * If requested micbias voltage is same as current micbias
2554 * voltage, then just return. Otherwise, adjust voltage as
2555 * per requested value. If micbias is already enabled, then
2556 * to avoid slow micbias ramp-up or down enable pull-up
2557 * momentarily, change the micbias value and then re-enable
2558 * micbias.
2559 */
2560 micb_en = snd_soc_component_read_field(component, micb_reg,
2561 WCD934X_ANA_MICB_EN_MASK);
2562 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
2563 WCD934X_MICB_VAL_MASK);
2564
2565 req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt);
2566 if (req_vout_ctl < 0) {
2567 ret = -EINVAL;
2568 goto exit;
2569 }
2570
2571 if (cur_vout_ctl == req_vout_ctl) {
2572 ret = 0;
2573 goto exit;
2574 }
2575
2576 if (micb_en == WCD934X_MICB_ENABLE)
2577 snd_soc_component_write_field(component, micb_reg,
2578 WCD934X_ANA_MICB_EN_MASK,
2579 WCD934X_MICB_PULL_UP);
2580
2581 snd_soc_component_write_field(component, micb_reg,
2582 WCD934X_MICB_VAL_MASK,
2583 req_vout_ctl);
2584
2585 if (micb_en == WCD934X_MICB_ENABLE) {
2586 snd_soc_component_write_field(component, micb_reg,
2587 WCD934X_ANA_MICB_EN_MASK,
2588 WCD934X_MICB_ENABLE);
2589 /*
2590 * Add 2ms delay as per HW requirement after enabling
2591 * micbias
2592 */
2593 usleep_range(2000, 2100);
2594 }
2595 exit:
2596 mutex_unlock(&wcd934x->micb_lock);
2597 return ret;
2598 }
2599
wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component * component,int micb_num,bool req_en)2600 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2601 int micb_num, bool req_en)
2602 {
2603 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2604 int rc, micb_mv;
2605
2606 if (micb_num != MIC_BIAS_2)
2607 return -EINVAL;
2608 /*
2609 * If device tree micbias level is already above the minimum
2610 * voltage needed to detect threshold microphone, then do
2611 * not change the micbias, just return.
2612 */
2613 if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2614 return 0;
2615
2616 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv;
2617
2618 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2619
2620 return rc;
2621 }
2622
wcd934x_mbhc_get_result_params(struct wcd934x_codec * wcd934x,s16 * d1_a,u16 noff,int32_t * zdet)2623 static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x,
2624 s16 *d1_a, u16 noff,
2625 int32_t *zdet)
2626 {
2627 int i;
2628 int val, val1;
2629 s16 c1;
2630 s32 x1, d1;
2631 int32_t denom;
2632 static const int minCode_param[] = {
2633 3277, 1639, 820, 410, 205, 103, 52, 26
2634 };
2635
2636 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20);
2637 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) {
2638 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val);
2639 if (val & 0x80)
2640 break;
2641 }
2642 val = val << 0x8;
2643 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1);
2644 val |= val1;
2645 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00);
2646 x1 = WCD934X_MBHC_GET_X1(val);
2647 c1 = WCD934X_MBHC_GET_C1(val);
2648 /* If ramp is not complete, give additional 5ms */
2649 if ((c1 < 2) && x1)
2650 usleep_range(5000, 5050);
2651
2652 if (!c1 || !x1) {
2653 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2654 __func__, c1, x1);
2655 goto ramp_down;
2656 }
2657 d1 = d1_a[c1];
2658 denom = (x1 * d1) - (1 << (14 - noff));
2659 if (denom > 0)
2660 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom;
2661 else if (x1 < minCode_param[noff])
2662 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE;
2663
2664 dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n",
2665 __func__, d1, c1, x1, *zdet);
2666 ramp_down:
2667 i = 0;
2668
2669 while (x1) {
2670 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val);
2671 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1);
2672 val = val << 0x08;
2673 val |= val1;
2674 x1 = WCD934X_MBHC_GET_X1(val);
2675 i++;
2676 if (i == WCD934X_ZDET_NUM_MEASUREMENTS)
2677 break;
2678 }
2679 }
2680
wcd934x_mbhc_zdet_ramp(struct snd_soc_component * component,struct wcd934x_mbhc_zdet_param * zdet_param,int32_t * zl,int32_t * zr,s16 * d1_a)2681 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component,
2682 struct wcd934x_mbhc_zdet_param *zdet_param,
2683 int32_t *zl, int32_t *zr, s16 *d1_a)
2684 {
2685 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2686 int32_t zdet = 0;
2687
2688 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2689 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
2690 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5,
2691 WCD934X_VTH_MASK, zdet_param->btn5);
2692 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6,
2693 WCD934X_VTH_MASK, zdet_param->btn6);
2694 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7,
2695 WCD934X_VTH_MASK, zdet_param->btn7);
2696 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2697 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
2698 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL,
2699 0x0F, zdet_param->nshift);
2700
2701 if (!zl)
2702 goto z_right;
2703 /* Start impedance measurement for HPH_L */
2704 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80);
2705 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2706 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00);
2707
2708 *zl = zdet;
2709
2710 z_right:
2711 if (!zr)
2712 return;
2713 /* Start impedance measurement for HPH_R */
2714 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40);
2715 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2716 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00);
2717
2718 *zr = zdet;
2719 }
2720
wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component * component,int32_t * z_val,int flag_l_r)2721 static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2722 int32_t *z_val, int flag_l_r)
2723 {
2724 s16 q1;
2725 int q1_cal;
2726
2727 if (*z_val < (WCD934X_ZDET_VAL_400/1000))
2728 q1 = snd_soc_component_read(component,
2729 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
2730 else
2731 q1 = snd_soc_component_read(component,
2732 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
2733 if (q1 & 0x80)
2734 q1_cal = (10000 - ((q1 & 0x7F) * 25));
2735 else
2736 q1_cal = (10000 + (q1 * 25));
2737 if (q1_cal > 0)
2738 *z_val = ((*z_val) * 10000) / q1_cal;
2739 }
2740
wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component * component,uint32_t * zl,uint32_t * zr)2741 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2742 uint32_t *zl, uint32_t *zr)
2743 {
2744 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2745 s16 reg0, reg1, reg2, reg3, reg4;
2746 int32_t z1L, z1R, z1Ls;
2747 int zMono, z_diff1, z_diff2;
2748 bool is_fsm_disable = false;
2749 struct wcd934x_mbhc_zdet_param zdet_param[] = {
2750 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
2751 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
2752 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
2753 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
2754 };
2755 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL;
2756 s16 d1_a[][4] = {
2757 {0, 30, 90, 30},
2758 {0, 30, 30, 5},
2759 {0, 30, 30, 5},
2760 {0, 30, 30, 5},
2761 };
2762 s16 *d1 = NULL;
2763
2764 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5);
2765 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6);
2766 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7);
2767 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK);
2768 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL);
2769
2770 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) {
2771 is_fsm_disable = true;
2772 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00);
2773 }
2774
2775 /* For NO-jack, disable L_DET_EN before Z-det measurements */
2776 if (wcd934x->mbhc_cfg.hphl_swh)
2777 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00);
2778
2779 /* Turn off 100k pull down on HPHL */
2780 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00);
2781
2782 /* First get impedance on Left */
2783 d1 = d1_a[1];
2784 zdet_param_ptr = &zdet_param[1];
2785 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2786
2787 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
2788 goto left_ch_impedance;
2789
2790 /* Second ramp for left ch */
2791 if (z1L < WCD934X_ZDET_VAL_32) {
2792 zdet_param_ptr = &zdet_param[0];
2793 d1 = d1_a[0];
2794 } else if ((z1L > WCD934X_ZDET_VAL_400) &&
2795 (z1L <= WCD934X_ZDET_VAL_1200)) {
2796 zdet_param_ptr = &zdet_param[2];
2797 d1 = d1_a[2];
2798 } else if (z1L > WCD934X_ZDET_VAL_1200) {
2799 zdet_param_ptr = &zdet_param[3];
2800 d1 = d1_a[3];
2801 }
2802 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2803
2804 left_ch_impedance:
2805 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2806 (z1L > WCD934X_ZDET_VAL_100K)) {
2807 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE;
2808 zdet_param_ptr = &zdet_param[1];
2809 d1 = d1_a[1];
2810 } else {
2811 *zl = z1L/1000;
2812 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0);
2813 }
2814 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2815 __func__, *zl);
2816
2817 /* Start of right impedance ramp and calculation */
2818 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2819 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
2820 if (((z1R > WCD934X_ZDET_VAL_1200) &&
2821 (zdet_param_ptr->noff == 0x6)) ||
2822 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE))
2823 goto right_ch_impedance;
2824 /* Second ramp for right ch */
2825 if (z1R < WCD934X_ZDET_VAL_32) {
2826 zdet_param_ptr = &zdet_param[0];
2827 d1 = d1_a[0];
2828 } else if ((z1R > WCD934X_ZDET_VAL_400) &&
2829 (z1R <= WCD934X_ZDET_VAL_1200)) {
2830 zdet_param_ptr = &zdet_param[2];
2831 d1 = d1_a[2];
2832 } else if (z1R > WCD934X_ZDET_VAL_1200) {
2833 zdet_param_ptr = &zdet_param[3];
2834 d1 = d1_a[3];
2835 }
2836 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2837 }
2838 right_ch_impedance:
2839 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2840 (z1R > WCD934X_ZDET_VAL_100K)) {
2841 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE;
2842 } else {
2843 *zr = z1R/1000;
2844 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1);
2845 }
2846 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2847 __func__, *zr);
2848
2849 /* Mono/stereo detection */
2850 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) &&
2851 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) {
2852 dev_dbg(component->dev,
2853 "%s: plug type is invalid or extension cable\n",
2854 __func__);
2855 goto zdet_complete;
2856 }
2857 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2858 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2859 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
2860 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
2861 dev_dbg(component->dev,
2862 "%s: Mono plug type with one ch floating or shorted to GND\n",
2863 __func__);
2864 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2865 goto zdet_complete;
2866 }
2867 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2868 WCD934X_HPHPA_GND_OVR_MASK, 1);
2869 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2870 WCD934X_HPHPA_GND_R_MASK, 1);
2871 if (*zl < (WCD934X_ZDET_VAL_32/1000))
2872 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
2873 else
2874 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
2875 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2876 WCD934X_HPHPA_GND_R_MASK, 0);
2877 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2878 WCD934X_HPHPA_GND_OVR_MASK, 0);
2879 z1Ls /= 1000;
2880 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
2881 /* Parallel of left Z and 9 ohm pull down resistor */
2882 zMono = ((*zl) * 9) / ((*zl) + 9);
2883 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
2884 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
2885 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
2886 dev_err(component->dev, "%s: stereo plug type detected\n",
2887 __func__);
2888 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO);
2889 } else {
2890 dev_err(component->dev, "%s: MONO plug type detected\n",
2891 __func__);
2892 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2893 }
2894
2895 zdet_complete:
2896 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0);
2897 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1);
2898 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2);
2899 /* Turn on 100k pull down on HPHL */
2900 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01);
2901
2902 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2903 if (wcd934x->mbhc_cfg.hphl_swh)
2904 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80);
2905
2906 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2907 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3);
2908 if (is_fsm_disable)
2909 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80);
2910 }
2911
wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component * component,bool enable)2912 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2913 bool enable)
2914 {
2915 if (enable) {
2916 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2917 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1);
2918 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2919 WCD934X_MBHC_GND_DET_EN_MASK, 1);
2920 } else {
2921 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2922 WCD934X_MBHC_GND_DET_EN_MASK, 0);
2923 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2924 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0);
2925 }
2926 }
2927
wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component * component,bool enable)2928 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2929 bool enable)
2930 {
2931 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2932 WCD934X_HPHPA_GND_R_MASK, enable);
2933 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2934 WCD934X_HPHPA_GND_L_MASK, enable);
2935 }
2936
2937 static const struct wcd_mbhc_cb mbhc_cb = {
2938 .clk_setup = wcd934x_mbhc_clk_setup,
2939 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control,
2940 .set_btn_thr = wcd934x_mbhc_program_btn_thr,
2941 .micbias_enable_status = wcd934x_mbhc_micb_en_status,
2942 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control,
2943 .mbhc_micbias_control = wcd934x_mbhc_request_micbias,
2944 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control,
2945 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic,
2946 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance,
2947 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl,
2948 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl,
2949 };
2950
wcd934x_get_hph_type(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2951 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol,
2952 struct snd_ctl_elem_value *ucontrol)
2953 {
2954 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2955 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2956
2957 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc);
2958
2959 return 0;
2960 }
2961
wcd934x_hph_impedance_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2962 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2963 struct snd_ctl_elem_value *ucontrol)
2964 {
2965 uint32_t zl, zr;
2966 bool hphr;
2967 struct soc_mixer_control *mc;
2968 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2969 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2970
2971 mc = (struct soc_mixer_control *)(kcontrol->private_value);
2972 hphr = mc->shift;
2973 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr);
2974 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2975 ucontrol->value.integer.value[0] = hphr ? zr : zl;
2976
2977 return 0;
2978 }
2979 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
2980 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
2981 wcd934x_get_hph_type, NULL),
2982 };
2983
2984 static const struct snd_kcontrol_new impedance_detect_controls[] = {
2985 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
2986 wcd934x_hph_impedance_get, NULL),
2987 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
2988 wcd934x_hph_impedance_get, NULL),
2989 };
2990
wcd934x_mbhc_init(struct snd_soc_component * component)2991 static int wcd934x_mbhc_init(struct snd_soc_component *component)
2992 {
2993 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent);
2994 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2995 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids;
2996
2997 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data,
2998 WCD934X_IRQ_MBHC_SW_DET);
2999 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data,
3000 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET);
3001 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data,
3002 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET);
3003 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data,
3004 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3005 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data,
3006 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET);
3007 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data,
3008 WCD934X_IRQ_HPH_PA_OCPL_FAULT);
3009 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data,
3010 WCD934X_IRQ_HPH_PA_OCPR_FAULT);
3011
3012 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3013 if (IS_ERR(wcd->mbhc)) {
3014 wcd->mbhc = NULL;
3015 return -EINVAL;
3016 }
3017
3018 snd_soc_add_component_controls(component, impedance_detect_controls,
3019 ARRAY_SIZE(impedance_detect_controls));
3020 snd_soc_add_component_controls(component, hph_type_detect_controls,
3021 ARRAY_SIZE(hph_type_detect_controls));
3022
3023 return 0;
3024 }
3025
wcd934x_mbhc_deinit(struct snd_soc_component * component)3026 static void wcd934x_mbhc_deinit(struct snd_soc_component *component)
3027 {
3028 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3029
3030 if (!wcd->mbhc)
3031 return;
3032
3033 wcd_mbhc_deinit(wcd->mbhc);
3034 }
3035
wcd934x_comp_probe(struct snd_soc_component * component)3036 static int wcd934x_comp_probe(struct snd_soc_component *component)
3037 {
3038 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3039 int i;
3040
3041 snd_soc_component_init_regmap(component, wcd->regmap);
3042 wcd->component = component;
3043
3044 /* Class-H Init*/
3045 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
3046 if (IS_ERR(wcd->clsh_ctrl))
3047 return PTR_ERR(wcd->clsh_ctrl);
3048
3049 /* Default HPH Mode to Class-H Low HiFi */
3050 wcd->hph_mode = CLS_H_LOHIFI;
3051
3052 wcd934x_comp_init(component);
3053
3054 for (i = 0; i < NUM_CODEC_DAIS; i++)
3055 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
3056
3057 wcd934x_init_dmic(component);
3058
3059 if (wcd934x_mbhc_init(component))
3060 dev_err(component->dev, "Failed to Initialize MBHC\n");
3061
3062 return 0;
3063 }
3064
wcd934x_comp_remove(struct snd_soc_component * comp)3065 static void wcd934x_comp_remove(struct snd_soc_component *comp)
3066 {
3067 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3068
3069 wcd934x_mbhc_deinit(comp);
3070 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
3071 }
3072
wcd934x_comp_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)3073 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
3074 int clk_id, int source,
3075 unsigned int freq, int dir)
3076 {
3077 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3078 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
3079
3080 wcd->rate = freq;
3081
3082 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
3083 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
3084
3085 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
3086 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
3087 val);
3088
3089 return clk_set_rate(wcd->extclk, freq);
3090 }
3091
get_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,int coeff_idx)3092 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
3093 int iir_idx, int band_idx, int coeff_idx)
3094 {
3095 u32 value = 0;
3096 int reg, b2_reg;
3097
3098 /* Address does not automatically update if reading */
3099 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3100 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3101
3102 snd_soc_component_write(component, reg,
3103 ((band_idx * BAND_MAX + coeff_idx) *
3104 sizeof(uint32_t)) & 0x7F);
3105
3106 value |= snd_soc_component_read(component, b2_reg);
3107 snd_soc_component_write(component, reg,
3108 ((band_idx * BAND_MAX + coeff_idx)
3109 * sizeof(uint32_t) + 1) & 0x7F);
3110
3111 value |= (snd_soc_component_read(component, b2_reg) << 8);
3112 snd_soc_component_write(component, reg,
3113 ((band_idx * BAND_MAX + coeff_idx)
3114 * sizeof(uint32_t) + 2) & 0x7F);
3115
3116 value |= (snd_soc_component_read(component, b2_reg) << 16);
3117 snd_soc_component_write(component, reg,
3118 ((band_idx * BAND_MAX + coeff_idx)
3119 * sizeof(uint32_t) + 3) & 0x7F);
3120
3121 /* Mask bits top 2 bits since they are reserved */
3122 value |= (snd_soc_component_read(component, b2_reg) << 24);
3123 return value;
3124 }
3125
set_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,uint32_t value)3126 static void set_iir_band_coeff(struct snd_soc_component *component,
3127 int iir_idx, int band_idx, uint32_t value)
3128 {
3129 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3130
3131 snd_soc_component_write(component, reg, (value & 0xFF));
3132 snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
3133 snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
3134 /* Mask top 2 bits, 7-8 are reserved */
3135 snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
3136 }
3137
wcd934x_put_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3138 static int wcd934x_put_iir_band_audio_mixer(
3139 struct snd_kcontrol *kcontrol,
3140 struct snd_ctl_elem_value *ucontrol)
3141 {
3142 struct snd_soc_component *component =
3143 snd_soc_kcontrol_component(kcontrol);
3144 struct wcd_iir_filter_ctl *ctl =
3145 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3146 struct soc_bytes_ext *params = &ctl->bytes_ext;
3147 int iir_idx = ctl->iir_idx;
3148 int band_idx = ctl->band_idx;
3149 u32 coeff[BAND_MAX];
3150 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3151
3152 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
3153
3154 /* Mask top bit it is reserved */
3155 /* Updates addr automatically for each B2 write */
3156 snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
3157 sizeof(uint32_t)) & 0x7F);
3158
3159 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
3160 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
3161 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
3162 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
3163 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
3164
3165 return 0;
3166 }
3167
wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3168 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
3169 struct snd_ctl_elem_value *ucontrol)
3170 {
3171 struct snd_soc_component *component =
3172 snd_soc_kcontrol_component(kcontrol);
3173 struct wcd_iir_filter_ctl *ctl =
3174 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3175 struct soc_bytes_ext *params = &ctl->bytes_ext;
3176 int iir_idx = ctl->iir_idx;
3177 int band_idx = ctl->band_idx;
3178 u32 coeff[BAND_MAX];
3179
3180 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
3181 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
3182 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
3183 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
3184 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
3185
3186 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
3187
3188 return 0;
3189 }
3190
wcd934x_iir_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * ucontrol)3191 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
3192 struct snd_ctl_elem_info *ucontrol)
3193 {
3194 struct wcd_iir_filter_ctl *ctl =
3195 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3196 struct soc_bytes_ext *params = &ctl->bytes_ext;
3197
3198 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
3199 ucontrol->count = params->max;
3200
3201 return 0;
3202 }
3203
wcd934x_compander_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3204 static int wcd934x_compander_get(struct snd_kcontrol *kc,
3205 struct snd_ctl_elem_value *ucontrol)
3206 {
3207 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3208 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3209 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3210
3211 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
3212
3213 return 0;
3214 }
3215
wcd934x_compander_set(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3216 static int wcd934x_compander_set(struct snd_kcontrol *kc,
3217 struct snd_ctl_elem_value *ucontrol)
3218 {
3219 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3220 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3221 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3222 int value = ucontrol->value.integer.value[0];
3223 int sel;
3224
3225 if (wcd->comp_enabled[comp] == value)
3226 return 0;
3227
3228 wcd->comp_enabled[comp] = value;
3229 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
3230 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
3231
3232 /* Any specific register configuration for compander */
3233 switch (comp) {
3234 case COMPANDER_1:
3235 /* Set Gain Source Select based on compander enable/disable */
3236 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
3237 WCD934X_HPH_GAIN_SRC_SEL_MASK,
3238 sel);
3239 break;
3240 case COMPANDER_2:
3241 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
3242 WCD934X_HPH_GAIN_SRC_SEL_MASK,
3243 sel);
3244 break;
3245 case COMPANDER_3:
3246 case COMPANDER_4:
3247 case COMPANDER_7:
3248 case COMPANDER_8:
3249 break;
3250 default:
3251 return 0;
3252 }
3253
3254 return 1;
3255 }
3256
wcd934x_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3257 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
3258 struct snd_ctl_elem_value *ucontrol)
3259 {
3260 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3261 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3262
3263 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
3264
3265 return 0;
3266 }
3267
wcd934x_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3268 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
3269 struct snd_ctl_elem_value *ucontrol)
3270 {
3271 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3272 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3273 u32 mode_val;
3274
3275 mode_val = ucontrol->value.enumerated.item[0];
3276
3277 if (mode_val == wcd->hph_mode)
3278 return 0;
3279
3280 if (mode_val == 0) {
3281 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
3282 mode_val = CLS_H_LOHIFI;
3283 }
3284 wcd->hph_mode = mode_val;
3285
3286 return 1;
3287 }
3288
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3289 static int slim_rx_mux_get(struct snd_kcontrol *kc,
3290 struct snd_ctl_elem_value *ucontrol)
3291 {
3292 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3293 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3294 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3295
3296 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
3297
3298 return 0;
3299 }
3300
slim_rx_mux_to_dai_id(int mux)3301 static int slim_rx_mux_to_dai_id(int mux)
3302 {
3303 int aif_id;
3304
3305 switch (mux) {
3306 case 1:
3307 aif_id = AIF1_PB;
3308 break;
3309 case 2:
3310 aif_id = AIF2_PB;
3311 break;
3312 case 3:
3313 aif_id = AIF3_PB;
3314 break;
3315 case 4:
3316 aif_id = AIF4_PB;
3317 break;
3318 default:
3319 aif_id = -1;
3320 break;
3321 }
3322
3323 return aif_id;
3324 }
3325
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3326 static int slim_rx_mux_put(struct snd_kcontrol *kc,
3327 struct snd_ctl_elem_value *ucontrol)
3328 {
3329 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3330 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
3331 struct soc_enum *e = (struct soc_enum *)kc->private_value;
3332 struct snd_soc_dapm_update *update = NULL;
3333 struct wcd934x_slim_ch *ch, *c;
3334 u32 port_id = w->shift;
3335 bool found = false;
3336 int mux_idx;
3337 int prev_mux_idx = wcd->rx_port_value[port_id];
3338 int aif_id;
3339
3340 mux_idx = ucontrol->value.enumerated.item[0];
3341
3342 if (mux_idx == prev_mux_idx)
3343 return 0;
3344
3345 switch(mux_idx) {
3346 case 0:
3347 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
3348 if (aif_id < 0)
3349 return 0;
3350
3351 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
3352 if (ch->port == port_id + WCD934X_RX_START) {
3353 found = true;
3354 list_del_init(&ch->list);
3355 break;
3356 }
3357 }
3358 if (!found)
3359 return 0;
3360
3361 break;
3362 case 1 ... 4:
3363 aif_id = slim_rx_mux_to_dai_id(mux_idx);
3364 if (aif_id < 0)
3365 return 0;
3366
3367 if (list_empty(&wcd->rx_chs[port_id].list)) {
3368 list_add_tail(&wcd->rx_chs[port_id].list,
3369 &wcd->dai[aif_id].slim_ch_list);
3370 } else {
3371 dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
3372 return 0;
3373 }
3374 break;
3375
3376 default:
3377 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
3378 goto err;
3379 }
3380
3381 wcd->rx_port_value[port_id] = mux_idx;
3382 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
3383 e, update);
3384
3385 return 1;
3386 err:
3387 return -EINVAL;
3388 }
3389
wcd934x_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3390 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
3391 struct snd_ctl_elem_value *ucontrol)
3392 {
3393 struct soc_enum *e = (struct soc_enum *)kc->private_value;
3394 struct snd_soc_component *component;
3395 int reg, val;
3396
3397 component = snd_soc_dapm_kcontrol_component(kc);
3398 val = ucontrol->value.enumerated.item[0];
3399 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
3400 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
3401 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
3402 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3403 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
3404 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3405 else
3406 return -EINVAL;
3407
3408 /* Set Look Ahead Delay */
3409 if (val)
3410 snd_soc_component_update_bits(component, reg,
3411 WCD934X_RX_DLY_ZN_EN_MASK,
3412 WCD934X_RX_DLY_ZN_ENABLE);
3413 else
3414 snd_soc_component_update_bits(component, reg,
3415 WCD934X_RX_DLY_ZN_EN_MASK,
3416 WCD934X_RX_DLY_ZN_DISABLE);
3417
3418 return snd_soc_dapm_put_enum_double(kc, ucontrol);
3419 }
3420
wcd934x_dec_enum_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3421 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
3422 struct snd_ctl_elem_value *ucontrol)
3423 {
3424 struct snd_soc_component *comp;
3425 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3426 unsigned int val;
3427 u16 mic_sel_reg = 0;
3428 u8 mic_sel;
3429
3430 comp = snd_soc_dapm_kcontrol_component(kcontrol);
3431
3432 val = ucontrol->value.enumerated.item[0];
3433 if (val > e->items - 1)
3434 return -EINVAL;
3435
3436 switch (e->reg) {
3437 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
3438 if (e->shift_l == 0)
3439 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
3440 else if (e->shift_l == 2)
3441 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
3442 else if (e->shift_l == 4)
3443 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
3444 break;
3445 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
3446 if (e->shift_l == 0)
3447 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
3448 else if (e->shift_l == 2)
3449 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
3450 break;
3451 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
3452 if (e->shift_l == 0)
3453 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
3454 else if (e->shift_l == 2)
3455 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
3456 break;
3457 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
3458 if (e->shift_l == 0)
3459 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
3460 else if (e->shift_l == 2)
3461 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
3462 break;
3463 default:
3464 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
3465 __func__, e->reg);
3466 return -EINVAL;
3467 }
3468
3469 /* ADC: 0, DMIC: 1 */
3470 mic_sel = val ? 0x0 : 0x1;
3471 if (mic_sel_reg)
3472 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
3473 mic_sel << 7);
3474
3475 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
3476 }
3477
3478 static const struct snd_kcontrol_new rx_int0_2_mux =
3479 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
3480
3481 static const struct snd_kcontrol_new rx_int1_2_mux =
3482 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
3483
3484 static const struct snd_kcontrol_new rx_int2_2_mux =
3485 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
3486
3487 static const struct snd_kcontrol_new rx_int3_2_mux =
3488 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
3489
3490 static const struct snd_kcontrol_new rx_int4_2_mux =
3491 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
3492
3493 static const struct snd_kcontrol_new rx_int7_2_mux =
3494 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
3495
3496 static const struct snd_kcontrol_new rx_int8_2_mux =
3497 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
3498
3499 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
3500 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
3501
3502 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
3503 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
3504
3505 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
3506 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
3507
3508 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
3509 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
3510
3511 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
3512 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
3513
3514 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
3515 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
3516
3517 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
3518 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
3519
3520 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
3521 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
3522
3523 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
3524 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
3525
3526 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
3527 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
3528
3529 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
3530 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
3531
3532 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
3533 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
3534
3535 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
3536 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
3537
3538 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
3539 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
3540
3541 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
3542 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
3543
3544 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
3545 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
3546
3547 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
3548 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
3549
3550 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
3551 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
3552
3553 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
3554 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
3555
3556 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
3557 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
3558
3559 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
3560 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
3561
3562 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
3563 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
3564
3565 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
3566 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
3567
3568 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
3569 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
3570
3571 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
3572 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
3573
3574 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
3575 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
3576
3577 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
3578 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
3579
3580 static const struct snd_kcontrol_new iir0_inp0_mux =
3581 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
3582 static const struct snd_kcontrol_new iir0_inp1_mux =
3583 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
3584 static const struct snd_kcontrol_new iir0_inp2_mux =
3585 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
3586 static const struct snd_kcontrol_new iir0_inp3_mux =
3587 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
3588
3589 static const struct snd_kcontrol_new iir1_inp0_mux =
3590 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
3591 static const struct snd_kcontrol_new iir1_inp1_mux =
3592 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
3593 static const struct snd_kcontrol_new iir1_inp2_mux =
3594 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
3595 static const struct snd_kcontrol_new iir1_inp3_mux =
3596 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
3597
3598 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
3599 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
3600 slim_rx_mux_get, slim_rx_mux_put),
3601 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
3602 slim_rx_mux_get, slim_rx_mux_put),
3603 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
3604 slim_rx_mux_get, slim_rx_mux_put),
3605 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
3606 slim_rx_mux_get, slim_rx_mux_put),
3607 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
3608 slim_rx_mux_get, slim_rx_mux_put),
3609 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
3610 slim_rx_mux_get, slim_rx_mux_put),
3611 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
3612 slim_rx_mux_get, slim_rx_mux_put),
3613 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
3614 slim_rx_mux_get, slim_rx_mux_put),
3615 };
3616
3617 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
3618 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
3619 };
3620
3621 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
3622 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
3623 };
3624
3625 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
3626 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
3627 };
3628
3629 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
3630 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
3631 };
3632
3633 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
3634 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
3635 snd_soc_dapm_get_enum_double,
3636 wcd934x_int_dem_inp_mux_put);
3637
3638 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
3639 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
3640 snd_soc_dapm_get_enum_double,
3641 wcd934x_int_dem_inp_mux_put);
3642
3643 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
3644 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
3645 snd_soc_dapm_get_enum_double,
3646 wcd934x_int_dem_inp_mux_put);
3647
3648 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
3649 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
3650
3651 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
3652 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
3653
3654 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
3655 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
3656
3657 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
3658 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
3659
3660 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
3661 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
3662
3663 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
3664 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
3665
3666 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
3667 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
3668
3669 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
3670 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
3671
3672 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
3673 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
3674
3675 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
3676 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
3677
3678 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
3679 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
3680
3681 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
3682 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
3683
3684 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
3685 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
3686
3687 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
3688 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
3689
3690 static const struct snd_kcontrol_new tx_dmic_mux0 =
3691 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
3692
3693 static const struct snd_kcontrol_new tx_dmic_mux1 =
3694 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
3695
3696 static const struct snd_kcontrol_new tx_dmic_mux2 =
3697 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
3698
3699 static const struct snd_kcontrol_new tx_dmic_mux3 =
3700 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
3701
3702 static const struct snd_kcontrol_new tx_dmic_mux4 =
3703 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
3704
3705 static const struct snd_kcontrol_new tx_dmic_mux5 =
3706 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
3707
3708 static const struct snd_kcontrol_new tx_dmic_mux6 =
3709 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
3710
3711 static const struct snd_kcontrol_new tx_dmic_mux7 =
3712 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
3713
3714 static const struct snd_kcontrol_new tx_dmic_mux8 =
3715 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
3716
3717 static const struct snd_kcontrol_new tx_amic_mux0 =
3718 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
3719
3720 static const struct snd_kcontrol_new tx_amic_mux1 =
3721 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
3722
3723 static const struct snd_kcontrol_new tx_amic_mux2 =
3724 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
3725
3726 static const struct snd_kcontrol_new tx_amic_mux3 =
3727 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
3728
3729 static const struct snd_kcontrol_new tx_amic_mux4 =
3730 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
3731
3732 static const struct snd_kcontrol_new tx_amic_mux5 =
3733 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
3734
3735 static const struct snd_kcontrol_new tx_amic_mux6 =
3736 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
3737
3738 static const struct snd_kcontrol_new tx_amic_mux7 =
3739 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
3740
3741 static const struct snd_kcontrol_new tx_amic_mux8 =
3742 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
3743
3744 static const struct snd_kcontrol_new tx_amic4_5 =
3745 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
3746
3747 static const struct snd_kcontrol_new tx_adc_mux0_mux =
3748 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
3749 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3750 static const struct snd_kcontrol_new tx_adc_mux1_mux =
3751 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
3752 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3753 static const struct snd_kcontrol_new tx_adc_mux2_mux =
3754 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
3755 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3756 static const struct snd_kcontrol_new tx_adc_mux3_mux =
3757 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
3758 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3759 static const struct snd_kcontrol_new tx_adc_mux4_mux =
3760 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
3761 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3762 static const struct snd_kcontrol_new tx_adc_mux5_mux =
3763 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
3764 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3765 static const struct snd_kcontrol_new tx_adc_mux6_mux =
3766 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
3767 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3768 static const struct snd_kcontrol_new tx_adc_mux7_mux =
3769 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
3770 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3771 static const struct snd_kcontrol_new tx_adc_mux8_mux =
3772 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
3773 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3774
3775 static const struct snd_kcontrol_new cdc_if_tx0_mux =
3776 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
3777 static const struct snd_kcontrol_new cdc_if_tx1_mux =
3778 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
3779 static const struct snd_kcontrol_new cdc_if_tx2_mux =
3780 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
3781 static const struct snd_kcontrol_new cdc_if_tx3_mux =
3782 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
3783 static const struct snd_kcontrol_new cdc_if_tx4_mux =
3784 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
3785 static const struct snd_kcontrol_new cdc_if_tx5_mux =
3786 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
3787 static const struct snd_kcontrol_new cdc_if_tx6_mux =
3788 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
3789 static const struct snd_kcontrol_new cdc_if_tx7_mux =
3790 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
3791 static const struct snd_kcontrol_new cdc_if_tx8_mux =
3792 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
3793 static const struct snd_kcontrol_new cdc_if_tx9_mux =
3794 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3795 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3796 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3797 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3798 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3799 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3800 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3801 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3802 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3803 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3804 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3805
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3806 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3807 struct snd_ctl_elem_value *ucontrol)
3808 {
3809 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3810 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3811 struct soc_mixer_control *mixer =
3812 (struct soc_mixer_control *)kc->private_value;
3813 int port_id = mixer->shift;
3814
3815 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3816
3817 return 0;
3818 }
3819
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3820 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3821 struct snd_ctl_elem_value *ucontrol)
3822 {
3823 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3824 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3825 struct snd_soc_dapm_update *update = NULL;
3826 struct soc_mixer_control *mixer =
3827 (struct soc_mixer_control *)kc->private_value;
3828 int enable = ucontrol->value.integer.value[0];
3829 struct wcd934x_slim_ch *ch, *c;
3830 int dai_id = widget->shift;
3831 int port_id = mixer->shift;
3832
3833 /* only add to the list if value not set */
3834 if (enable == wcd->tx_port_value[port_id])
3835 return 0;
3836
3837 if (enable) {
3838 if (list_empty(&wcd->tx_chs[port_id].list)) {
3839 list_add_tail(&wcd->tx_chs[port_id].list,
3840 &wcd->dai[dai_id].slim_ch_list);
3841 } else {
3842 dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
3843 return 0;
3844 }
3845 } else {
3846 bool found = false;
3847
3848 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
3849 if (ch->port == port_id) {
3850 found = true;
3851 list_del_init(&wcd->tx_chs[port_id].list);
3852 break;
3853 }
3854 }
3855 if (!found)
3856 return 0;
3857 }
3858
3859 wcd->tx_port_value[port_id] = enable;
3860 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3861
3862 return 1;
3863 }
3864
3865 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3866 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3867 slim_tx_mixer_get, slim_tx_mixer_put),
3868 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3869 slim_tx_mixer_get, slim_tx_mixer_put),
3870 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3871 slim_tx_mixer_get, slim_tx_mixer_put),
3872 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3873 slim_tx_mixer_get, slim_tx_mixer_put),
3874 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3875 slim_tx_mixer_get, slim_tx_mixer_put),
3876 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3877 slim_tx_mixer_get, slim_tx_mixer_put),
3878 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3879 slim_tx_mixer_get, slim_tx_mixer_put),
3880 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3881 slim_tx_mixer_get, slim_tx_mixer_put),
3882 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3883 slim_tx_mixer_get, slim_tx_mixer_put),
3884 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3885 slim_tx_mixer_get, slim_tx_mixer_put),
3886 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3887 slim_tx_mixer_get, slim_tx_mixer_put),
3888 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3889 slim_tx_mixer_get, slim_tx_mixer_put),
3890 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3891 slim_tx_mixer_get, slim_tx_mixer_put),
3892 };
3893
3894 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3895 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3896 slim_tx_mixer_get, slim_tx_mixer_put),
3897 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3898 slim_tx_mixer_get, slim_tx_mixer_put),
3899 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3900 slim_tx_mixer_get, slim_tx_mixer_put),
3901 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3902 slim_tx_mixer_get, slim_tx_mixer_put),
3903 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3904 slim_tx_mixer_get, slim_tx_mixer_put),
3905 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3906 slim_tx_mixer_get, slim_tx_mixer_put),
3907 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3908 slim_tx_mixer_get, slim_tx_mixer_put),
3909 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3910 slim_tx_mixer_get, slim_tx_mixer_put),
3911 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3912 slim_tx_mixer_get, slim_tx_mixer_put),
3913 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3914 slim_tx_mixer_get, slim_tx_mixer_put),
3915 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3916 slim_tx_mixer_get, slim_tx_mixer_put),
3917 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3918 slim_tx_mixer_get, slim_tx_mixer_put),
3919 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3920 slim_tx_mixer_get, slim_tx_mixer_put),
3921 };
3922
3923 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3924 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3925 slim_tx_mixer_get, slim_tx_mixer_put),
3926 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3927 slim_tx_mixer_get, slim_tx_mixer_put),
3928 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3929 slim_tx_mixer_get, slim_tx_mixer_put),
3930 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3931 slim_tx_mixer_get, slim_tx_mixer_put),
3932 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3933 slim_tx_mixer_get, slim_tx_mixer_put),
3934 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3935 slim_tx_mixer_get, slim_tx_mixer_put),
3936 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3937 slim_tx_mixer_get, slim_tx_mixer_put),
3938 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3939 slim_tx_mixer_get, slim_tx_mixer_put),
3940 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3941 slim_tx_mixer_get, slim_tx_mixer_put),
3942 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3943 slim_tx_mixer_get, slim_tx_mixer_put),
3944 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3945 slim_tx_mixer_get, slim_tx_mixer_put),
3946 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3947 slim_tx_mixer_get, slim_tx_mixer_put),
3948 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3949 slim_tx_mixer_get, slim_tx_mixer_put),
3950 };
3951
3952 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3953 /* Gain Controls */
3954 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3955 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3956 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3957 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3958 3, 16, 1, line_gain),
3959 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3960 3, 16, 1, line_gain),
3961
3962 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3963 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3964 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3965 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3966
3967 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3968 -84, 40, digital_gain), /* -84dB min - 40dB max */
3969 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3970 -84, 40, digital_gain),
3971 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3972 -84, 40, digital_gain),
3973 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3974 -84, 40, digital_gain),
3975 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3976 -84, 40, digital_gain),
3977 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3978 -84, 40, digital_gain),
3979 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3980 -84, 40, digital_gain),
3981 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3982 WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3983 -84, 40, digital_gain),
3984 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3985 WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
3986 -84, 40, digital_gain),
3987 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
3988 WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
3989 -84, 40, digital_gain),
3990 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
3991 WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
3992 -84, 40, digital_gain),
3993 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
3994 WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
3995 -84, 40, digital_gain),
3996 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
3997 WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
3998 -84, 40, digital_gain),
3999 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
4000 WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
4001 -84, 40, digital_gain),
4002
4003 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
4004 -84, 40, digital_gain),
4005 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
4006 -84, 40, digital_gain),
4007 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
4008 -84, 40, digital_gain),
4009 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
4010 -84, 40, digital_gain),
4011 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
4012 -84, 40, digital_gain),
4013 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
4014 -84, 40, digital_gain),
4015 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
4016 -84, 40, digital_gain),
4017 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
4018 -84, 40, digital_gain),
4019 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
4020 -84, 40, digital_gain),
4021
4022 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
4023 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
4024 digital_gain),
4025 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
4026 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
4027 digital_gain),
4028 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
4029 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
4030 digital_gain),
4031 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
4032 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
4033 digital_gain),
4034 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
4035 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
4036 digital_gain),
4037 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
4038 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
4039 digital_gain),
4040 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
4041 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
4042 digital_gain),
4043 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
4044 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
4045 digital_gain),
4046
4047 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
4048 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
4049 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
4050 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
4051 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
4052 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
4053 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
4054 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
4055 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
4056
4057 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
4058 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
4059 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
4060 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
4061 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
4062 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
4063 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
4064 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
4065 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
4066 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
4067 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
4068 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
4069 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
4070 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
4071
4072 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
4073 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
4074
4075 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4076 0, 1, 0),
4077 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4078 1, 1, 0),
4079 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4080 2, 1, 0),
4081 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4082 3, 1, 0),
4083 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4084 4, 1, 0),
4085 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4086 0, 1, 0),
4087 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4088 1, 1, 0),
4089 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4090 2, 1, 0),
4091 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4092 3, 1, 0),
4093 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4094 4, 1, 0),
4095 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
4096 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
4097 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
4098 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
4099 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
4100
4101 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
4102 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
4103 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
4104 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
4105 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
4106
4107 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
4108 wcd934x_compander_get, wcd934x_compander_set),
4109 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
4110 wcd934x_compander_get, wcd934x_compander_set),
4111 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
4112 wcd934x_compander_get, wcd934x_compander_set),
4113 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
4114 wcd934x_compander_get, wcd934x_compander_set),
4115 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
4116 wcd934x_compander_get, wcd934x_compander_set),
4117 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
4118 wcd934x_compander_get, wcd934x_compander_set),
4119 };
4120
wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)4121 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
4122 struct snd_soc_component *component)
4123 {
4124 int port_num = 0;
4125 unsigned short reg = 0;
4126 unsigned int val = 0;
4127 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
4128 struct wcd934x_slim_ch *ch;
4129
4130 list_for_each_entry(ch, &dai->slim_ch_list, list) {
4131 if (ch->port >= WCD934X_RX_START) {
4132 port_num = ch->port - WCD934X_RX_START;
4133 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
4134 } else {
4135 port_num = ch->port;
4136 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
4137 }
4138
4139 regmap_read(wcd->if_regmap, reg, &val);
4140 if (!(val & BIT(port_num % 8)))
4141 regmap_write(wcd->if_regmap, reg,
4142 val | BIT(port_num % 8));
4143 }
4144 }
4145
wcd934x_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4146 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
4147 struct snd_kcontrol *kc, int event)
4148 {
4149 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4150 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4151 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
4152
4153 switch (event) {
4154 case SND_SOC_DAPM_POST_PMU:
4155 wcd934x_codec_enable_int_port(dai, comp);
4156 break;
4157 }
4158
4159 return 0;
4160 }
4161
wcd934x_codec_hd2_control(struct snd_soc_component * component,u16 interp_idx,int event)4162 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
4163 u16 interp_idx, int event)
4164 {
4165 u16 hd2_scale_reg;
4166 u16 hd2_enable_reg = 0;
4167
4168 switch (interp_idx) {
4169 case INTERP_HPHL:
4170 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
4171 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
4172 break;
4173 case INTERP_HPHR:
4174 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
4175 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
4176 break;
4177 default:
4178 return;
4179 }
4180
4181 if (SND_SOC_DAPM_EVENT_ON(event)) {
4182 snd_soc_component_update_bits(component, hd2_scale_reg,
4183 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4184 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
4185 snd_soc_component_update_bits(component, hd2_enable_reg,
4186 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4187 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
4188 }
4189
4190 if (SND_SOC_DAPM_EVENT_OFF(event)) {
4191 snd_soc_component_update_bits(component, hd2_enable_reg,
4192 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4193 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
4194 snd_soc_component_update_bits(component, hd2_scale_reg,
4195 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4196 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
4197 }
4198 }
4199
wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component * comp,u16 interp_idx,int event)4200 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
4201 u16 interp_idx, int event)
4202 {
4203 u8 hph_dly_mask;
4204 u16 hph_lut_bypass_reg = 0;
4205
4206 switch (interp_idx) {
4207 case INTERP_HPHL:
4208 hph_dly_mask = 1;
4209 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
4210 break;
4211 case INTERP_HPHR:
4212 hph_dly_mask = 2;
4213 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
4214 break;
4215 default:
4216 return;
4217 }
4218
4219 if (SND_SOC_DAPM_EVENT_ON(event)) {
4220 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4221 hph_dly_mask, 0x0);
4222 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4223 WCD934X_HPH_LUT_BYPASS_MASK,
4224 WCD934X_HPH_LUT_BYPASS_ENABLE);
4225 }
4226
4227 if (SND_SOC_DAPM_EVENT_OFF(event)) {
4228 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4229 hph_dly_mask, hph_dly_mask);
4230 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4231 WCD934X_HPH_LUT_BYPASS_MASK,
4232 WCD934X_HPH_LUT_BYPASS_DISABLE);
4233 }
4234 }
4235
wcd934x_config_compander(struct snd_soc_component * comp,int interp_n,int event)4236 static int wcd934x_config_compander(struct snd_soc_component *comp,
4237 int interp_n, int event)
4238 {
4239 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4240 int compander;
4241 u16 comp_ctl0_reg, rx_path_cfg0_reg;
4242
4243 /* EAR does not have compander */
4244 if (!interp_n)
4245 return 0;
4246
4247 compander = interp_n - 1;
4248 if (!wcd->comp_enabled[compander])
4249 return 0;
4250
4251 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
4252 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
4253
4254 switch (event) {
4255 case SND_SOC_DAPM_PRE_PMU:
4256 /* Enable Compander Clock */
4257 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4258 WCD934X_COMP_CLK_EN_MASK,
4259 WCD934X_COMP_CLK_ENABLE);
4260 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4261 WCD934X_COMP_SOFT_RST_MASK,
4262 WCD934X_COMP_SOFT_RST_ENABLE);
4263 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4264 WCD934X_COMP_SOFT_RST_MASK,
4265 WCD934X_COMP_SOFT_RST_DISABLE);
4266 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4267 WCD934X_HPH_CMP_EN_MASK,
4268 WCD934X_HPH_CMP_ENABLE);
4269 break;
4270 case SND_SOC_DAPM_POST_PMD:
4271 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4272 WCD934X_HPH_CMP_EN_MASK,
4273 WCD934X_HPH_CMP_DISABLE);
4274 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4275 WCD934X_COMP_HALT_MASK,
4276 WCD934X_COMP_HALT);
4277 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4278 WCD934X_COMP_SOFT_RST_MASK,
4279 WCD934X_COMP_SOFT_RST_ENABLE);
4280 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4281 WCD934X_COMP_SOFT_RST_MASK,
4282 WCD934X_COMP_SOFT_RST_DISABLE);
4283 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4284 WCD934X_COMP_CLK_EN_MASK, 0x0);
4285 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4286 WCD934X_COMP_SOFT_RST_MASK, 0x0);
4287 break;
4288 }
4289
4290 return 0;
4291 }
4292
wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4293 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
4294 struct snd_kcontrol *kc, int event)
4295 {
4296 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4297 int interp_idx = w->shift;
4298 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
4299
4300 switch (event) {
4301 case SND_SOC_DAPM_PRE_PMU:
4302 /* Clk enable */
4303 snd_soc_component_update_bits(comp, main_reg,
4304 WCD934X_RX_CLK_EN_MASK,
4305 WCD934X_RX_CLK_ENABLE);
4306 wcd934x_codec_hd2_control(comp, interp_idx, event);
4307 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4308 wcd934x_config_compander(comp, interp_idx, event);
4309 break;
4310 case SND_SOC_DAPM_POST_PMD:
4311 wcd934x_config_compander(comp, interp_idx, event);
4312 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4313 wcd934x_codec_hd2_control(comp, interp_idx, event);
4314 /* Clk Disable */
4315 snd_soc_component_update_bits(comp, main_reg,
4316 WCD934X_RX_CLK_EN_MASK, 0);
4317 /* Reset enable and disable */
4318 snd_soc_component_update_bits(comp, main_reg,
4319 WCD934X_RX_RESET_MASK,
4320 WCD934X_RX_RESET_ENABLE);
4321 snd_soc_component_update_bits(comp, main_reg,
4322 WCD934X_RX_RESET_MASK,
4323 WCD934X_RX_RESET_DISABLE);
4324 /* Reset rate to 48K*/
4325 snd_soc_component_update_bits(comp, main_reg,
4326 WCD934X_RX_PCM_RATE_MASK,
4327 WCD934X_RX_PCM_RATE_F_48K);
4328 break;
4329 }
4330
4331 return 0;
4332 }
4333
wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4334 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
4335 struct snd_kcontrol *kc, int event)
4336 {
4337 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4338 int offset_val = 0;
4339 u16 gain_reg, mix_reg;
4340 int val = 0;
4341
4342 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
4343 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4344 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
4345 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4346
4347 switch (event) {
4348 case SND_SOC_DAPM_PRE_PMU:
4349 /* Clk enable */
4350 snd_soc_component_update_bits(comp, mix_reg,
4351 WCD934X_CDC_RX_MIX_CLK_EN_MASK,
4352 WCD934X_CDC_RX_MIX_CLK_ENABLE);
4353 break;
4354
4355 case SND_SOC_DAPM_POST_PMU:
4356 val = snd_soc_component_read(comp, gain_reg);
4357 val += offset_val;
4358 snd_soc_component_write(comp, gain_reg, val);
4359 break;
4360 }
4361
4362 return 0;
4363 }
4364
wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4365 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
4366 struct snd_kcontrol *kcontrol, int event)
4367 {
4368 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4369 int reg = w->reg;
4370
4371 switch (event) {
4372 case SND_SOC_DAPM_POST_PMU:
4373 /* B1 GAIN */
4374 snd_soc_component_write(comp, reg,
4375 snd_soc_component_read(comp, reg));
4376 /* B2 GAIN */
4377 reg++;
4378 snd_soc_component_write(comp, reg,
4379 snd_soc_component_read(comp, reg));
4380 /* B3 GAIN */
4381 reg++;
4382 snd_soc_component_write(comp, reg,
4383 snd_soc_component_read(comp, reg));
4384 /* B4 GAIN */
4385 reg++;
4386 snd_soc_component_write(comp, reg,
4387 snd_soc_component_read(comp, reg));
4388 /* B5 GAIN */
4389 reg++;
4390 snd_soc_component_write(comp, reg,
4391 snd_soc_component_read(comp, reg));
4392 break;
4393 default:
4394 break;
4395 }
4396 return 0;
4397 }
4398
wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4399 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
4400 struct snd_kcontrol *kcontrol,
4401 int event)
4402 {
4403 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4404 u16 gain_reg;
4405
4406 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
4407 WCD934X_RX_PATH_CTL_OFFSET);
4408
4409 switch (event) {
4410 case SND_SOC_DAPM_POST_PMU:
4411 snd_soc_component_write(comp, gain_reg,
4412 snd_soc_component_read(comp, gain_reg));
4413 break;
4414 }
4415
4416 return 0;
4417 }
4418
wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4419 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
4420 struct snd_kcontrol *kc, int event)
4421 {
4422 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4423 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4424
4425 switch (event) {
4426 case SND_SOC_DAPM_PRE_PMU:
4427 /* Disable AutoChop timer during power up */
4428 snd_soc_component_update_bits(comp,
4429 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4430 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4431 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4432 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4433
4434 break;
4435 case SND_SOC_DAPM_POST_PMD:
4436 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4437 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4438 break;
4439 }
4440
4441 return 0;
4442 }
4443
wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4444 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
4445 struct snd_kcontrol *kcontrol,
4446 int event)
4447 {
4448 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4449 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4450 int hph_mode = wcd->hph_mode;
4451 u8 dem_inp;
4452
4453 switch (event) {
4454 case SND_SOC_DAPM_PRE_PMU:
4455 /* Read DEM INP Select */
4456 dem_inp = snd_soc_component_read(comp,
4457 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
4458
4459 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4460 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4461 return -EINVAL;
4462 }
4463 if (hph_mode != CLS_H_LP)
4464 /* Ripple freq control enable */
4465 snd_soc_component_update_bits(comp,
4466 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4467 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4468 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4469 /* Disable AutoChop timer during power up */
4470 snd_soc_component_update_bits(comp,
4471 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4472 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4473 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4474 WCD_CLSH_STATE_HPHL, hph_mode);
4475
4476 break;
4477 case SND_SOC_DAPM_POST_PMD:
4478 /* 1000us required as per HW requirement */
4479 usleep_range(1000, 1100);
4480 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4481 WCD_CLSH_STATE_HPHL, hph_mode);
4482 if (hph_mode != CLS_H_LP)
4483 /* Ripple freq control disable */
4484 snd_soc_component_update_bits(comp,
4485 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4486 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4487
4488 break;
4489 default:
4490 break;
4491 }
4492
4493 return 0;
4494 }
4495
wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4496 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
4497 struct snd_kcontrol *kcontrol,
4498 int event)
4499 {
4500 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4501 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4502 int hph_mode = wcd->hph_mode;
4503 u8 dem_inp;
4504
4505 switch (event) {
4506 case SND_SOC_DAPM_PRE_PMU:
4507 dem_inp = snd_soc_component_read(comp,
4508 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
4509 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4510 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4511 return -EINVAL;
4512 }
4513 if (hph_mode != CLS_H_LP)
4514 /* Ripple freq control enable */
4515 snd_soc_component_update_bits(comp,
4516 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4517 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4518 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4519 /* Disable AutoChop timer during power up */
4520 snd_soc_component_update_bits(comp,
4521 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4522 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4523 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4524 WCD_CLSH_STATE_HPHR,
4525 hph_mode);
4526 break;
4527 case SND_SOC_DAPM_POST_PMD:
4528 /* 1000us required as per HW requirement */
4529 usleep_range(1000, 1100);
4530
4531 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4532 WCD_CLSH_STATE_HPHR, hph_mode);
4533 if (hph_mode != CLS_H_LP)
4534 /* Ripple freq control disable */
4535 snd_soc_component_update_bits(comp,
4536 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4537 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4538 break;
4539 default:
4540 break;
4541 }
4542
4543 return 0;
4544 }
4545
wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4546 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
4547 struct snd_kcontrol *kc, int event)
4548 {
4549 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4550 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4551
4552 switch (event) {
4553 case SND_SOC_DAPM_PRE_PMU:
4554 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4555 WCD_CLSH_STATE_LO, CLS_AB);
4556 break;
4557 case SND_SOC_DAPM_POST_PMD:
4558 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4559 WCD_CLSH_STATE_LO, CLS_AB);
4560 break;
4561 }
4562
4563 return 0;
4564 }
4565
wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4566 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
4567 struct snd_kcontrol *kcontrol,
4568 int event)
4569 {
4570 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4571 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4572
4573 switch (event) {
4574 case SND_SOC_DAPM_POST_PMU:
4575 /*
4576 * 7ms sleep is required after PA is enabled as per
4577 * HW requirement. If compander is disabled, then
4578 * 20ms delay is needed.
4579 */
4580 usleep_range(20000, 20100);
4581
4582 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4583 WCD934X_HPH_OCP_DET_MASK,
4584 WCD934X_HPH_OCP_DET_ENABLE);
4585 /* Remove Mute on primary path */
4586 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4587 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4588 0);
4589 /* Enable GM3 boost */
4590 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4591 WCD934X_HPH_GM3_BOOST_EN_MASK,
4592 WCD934X_HPH_GM3_BOOST_ENABLE);
4593 /* Enable AutoChop timer at the end of power up */
4594 snd_soc_component_update_bits(comp,
4595 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4596 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4597 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4598 /* Remove mix path mute */
4599 snd_soc_component_update_bits(comp,
4600 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4601 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
4602 break;
4603 case SND_SOC_DAPM_PRE_PMD:
4604 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4605 /* Enable DSD Mute before PA disable */
4606 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4607 WCD934X_HPH_OCP_DET_MASK,
4608 WCD934X_HPH_OCP_DET_DISABLE);
4609 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4610 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4611 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4612 snd_soc_component_update_bits(comp,
4613 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4614 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4615 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4616 break;
4617 case SND_SOC_DAPM_POST_PMD:
4618 /*
4619 * 5ms sleep is required after PA disable. If compander is
4620 * disabled, then 20ms delay is needed after PA disable.
4621 */
4622 usleep_range(20000, 20100);
4623 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4624 break;
4625 }
4626
4627 return 0;
4628 }
4629
wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4630 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
4631 struct snd_kcontrol *kcontrol,
4632 int event)
4633 {
4634 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4635 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4636
4637 switch (event) {
4638 case SND_SOC_DAPM_POST_PMU:
4639 /*
4640 * 7ms sleep is required after PA is enabled as per
4641 * HW requirement. If compander is disabled, then
4642 * 20ms delay is needed.
4643 */
4644 usleep_range(20000, 20100);
4645 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4646 WCD934X_HPH_OCP_DET_MASK,
4647 WCD934X_HPH_OCP_DET_ENABLE);
4648 /* Remove mute */
4649 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4650 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4651 0);
4652 /* Enable GM3 boost */
4653 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4654 WCD934X_HPH_GM3_BOOST_EN_MASK,
4655 WCD934X_HPH_GM3_BOOST_ENABLE);
4656 /* Enable AutoChop timer at the end of power up */
4657 snd_soc_component_update_bits(comp,
4658 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4659 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4660 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4661 /* Remove mix path mute if it is enabled */
4662 if ((snd_soc_component_read(comp,
4663 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
4664 snd_soc_component_update_bits(comp,
4665 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4666 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4667 WCD934X_CDC_RX_PGA_MUTE_DISABLE);
4668 break;
4669 case SND_SOC_DAPM_PRE_PMD:
4670 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
4671 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4672 WCD934X_HPH_OCP_DET_MASK,
4673 WCD934X_HPH_OCP_DET_DISABLE);
4674 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4675 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4676 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4677 snd_soc_component_update_bits(comp,
4678 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4679 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4680 WCD934X_CDC_RX_PGA_MUTE_ENABLE);
4681 break;
4682 case SND_SOC_DAPM_POST_PMD:
4683 /*
4684 * 5ms sleep is required after PA disable. If compander is
4685 * disabled, then 20ms delay is needed after PA disable.
4686 */
4687 usleep_range(20000, 20100);
4688 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
4689 break;
4690 }
4691
4692 return 0;
4693 }
4694
wcd934x_get_dmic_sample_rate(struct snd_soc_component * comp,unsigned int dmic,struct wcd934x_codec * wcd)4695 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
4696 unsigned int dmic,
4697 struct wcd934x_codec *wcd)
4698 {
4699 u8 tx_stream_fs;
4700 u8 adc_mux_index = 0, adc_mux_sel = 0;
4701 bool dec_found = false;
4702 u16 adc_mux_ctl_reg, tx_fs_reg;
4703 u32 dmic_fs;
4704
4705 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
4706 if (adc_mux_index < 4) {
4707 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4708 (adc_mux_index * 2);
4709 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
4710 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4711 adc_mux_index - 4;
4712 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
4713 ++adc_mux_index;
4714 continue;
4715 }
4716 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
4717 & 0xF8) >> 3) - 1;
4718
4719 if (adc_mux_sel == dmic) {
4720 dec_found = true;
4721 break;
4722 }
4723
4724 ++adc_mux_index;
4725 }
4726
4727 if (dec_found && adc_mux_index <= 8) {
4728 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
4729 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
4730 if (tx_stream_fs <= 4)
4731 dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ);
4732 else
4733 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
4734 } else {
4735 dmic_fs = wcd->dmic_sample_rate;
4736 }
4737
4738 return dmic_fs;
4739 }
4740
wcd934x_get_dmic_clk_val(struct snd_soc_component * comp,u32 mclk_rate,u32 dmic_clk_rate)4741 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
4742 u32 mclk_rate, u32 dmic_clk_rate)
4743 {
4744 u32 div_factor;
4745 u8 dmic_ctl_val;
4746
4747 /* Default value to return in case of error */
4748 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
4749 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4750 else
4751 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4752
4753 if (dmic_clk_rate == 0) {
4754 dev_err(comp->dev,
4755 "%s: dmic_sample_rate cannot be 0\n",
4756 __func__);
4757 goto done;
4758 }
4759
4760 div_factor = mclk_rate / dmic_clk_rate;
4761 switch (div_factor) {
4762 case 2:
4763 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4764 break;
4765 case 3:
4766 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4767 break;
4768 case 4:
4769 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
4770 break;
4771 case 6:
4772 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
4773 break;
4774 case 8:
4775 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
4776 break;
4777 case 16:
4778 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
4779 break;
4780 default:
4781 dev_err(comp->dev,
4782 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
4783 __func__, div_factor, mclk_rate, dmic_clk_rate);
4784 break;
4785 }
4786
4787 done:
4788 return dmic_ctl_val;
4789 }
4790
wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4791 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
4792 struct snd_kcontrol *kcontrol, int event)
4793 {
4794 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4795 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4796 u8 dmic_clk_en = 0x01;
4797 u16 dmic_clk_reg;
4798 s32 *dmic_clk_cnt;
4799 u8 dmic_rate_val, dmic_rate_shift = 1;
4800 unsigned int dmic;
4801 u32 dmic_sample_rate;
4802 int ret;
4803 char *wname;
4804
4805 wname = strpbrk(w->name, "012345");
4806 if (!wname) {
4807 dev_err(comp->dev, "%s: widget not found\n", __func__);
4808 return -EINVAL;
4809 }
4810
4811 ret = kstrtouint(wname, 10, &dmic);
4812 if (ret < 0) {
4813 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4814 __func__);
4815 return -EINVAL;
4816 }
4817
4818 switch (dmic) {
4819 case 0:
4820 case 1:
4821 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4822 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4823 break;
4824 case 2:
4825 case 3:
4826 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4827 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4828 break;
4829 case 4:
4830 case 5:
4831 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4832 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4833 break;
4834 default:
4835 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4836 __func__);
4837 return -EINVAL;
4838 }
4839
4840 switch (event) {
4841 case SND_SOC_DAPM_PRE_PMU:
4842 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4843 wcd);
4844 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4845 dmic_sample_rate);
4846 (*dmic_clk_cnt)++;
4847 if (*dmic_clk_cnt == 1) {
4848 dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4849 snd_soc_component_update_bits(comp, dmic_clk_reg,
4850 WCD934X_DMIC_RATE_MASK,
4851 dmic_rate_val);
4852 snd_soc_component_update_bits(comp, dmic_clk_reg,
4853 dmic_clk_en, dmic_clk_en);
4854 }
4855
4856 break;
4857 case SND_SOC_DAPM_POST_PMD:
4858 (*dmic_clk_cnt)--;
4859 if (*dmic_clk_cnt == 0)
4860 snd_soc_component_update_bits(comp, dmic_clk_reg,
4861 dmic_clk_en, 0);
4862 break;
4863 }
4864
4865 return 0;
4866 }
4867
wcd934x_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)4868 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4869 int adc_mux_n)
4870 {
4871 u16 mask, shift, adc_mux_in_reg;
4872 u16 amic_mux_sel_reg;
4873 bool is_amic;
4874
4875 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4876 adc_mux_n == WCD934X_INVALID_ADC_MUX)
4877 return 0;
4878
4879 if (adc_mux_n < 3) {
4880 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4881 adc_mux_n;
4882 mask = 0x03;
4883 shift = 0;
4884 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4885 2 * adc_mux_n;
4886 } else if (adc_mux_n < 4) {
4887 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4888 mask = 0x03;
4889 shift = 0;
4890 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4891 2 * adc_mux_n;
4892 } else if (adc_mux_n < 7) {
4893 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4894 (adc_mux_n - 4);
4895 mask = 0x0C;
4896 shift = 2;
4897 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4898 adc_mux_n - 4;
4899 } else if (adc_mux_n < 8) {
4900 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4901 mask = 0x0C;
4902 shift = 2;
4903 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4904 adc_mux_n - 4;
4905 } else if (adc_mux_n < 12) {
4906 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4907 ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4908 (adc_mux_n - 9));
4909 mask = 0x30;
4910 shift = 4;
4911 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4912 adc_mux_n - 4;
4913 } else if (adc_mux_n < 13) {
4914 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4915 mask = 0x30;
4916 shift = 4;
4917 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4918 adc_mux_n - 4;
4919 } else {
4920 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4921 mask = 0xC0;
4922 shift = 6;
4923 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4924 adc_mux_n - 4;
4925 }
4926
4927 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4928 & mask) >> shift) == 1);
4929 if (!is_amic)
4930 return 0;
4931
4932 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4933 }
4934
wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)4935 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4936 int amic)
4937 {
4938 u16 pwr_level_reg = 0;
4939
4940 switch (amic) {
4941 case 1:
4942 case 2:
4943 pwr_level_reg = WCD934X_ANA_AMIC1;
4944 break;
4945
4946 case 3:
4947 case 4:
4948 pwr_level_reg = WCD934X_ANA_AMIC3;
4949 break;
4950 default:
4951 break;
4952 }
4953
4954 return pwr_level_reg;
4955 }
4956
wcd934x_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4957 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4958 struct snd_kcontrol *kcontrol, int event)
4959 {
4960 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4961 unsigned int decimator;
4962 char *dec_adc_mux_name = NULL;
4963 char *widget_name;
4964 int ret = 0, amic_n;
4965 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4966 u16 tx_gain_ctl_reg;
4967 char *dec;
4968 u8 hpf_coff_freq;
4969
4970 char *wname __free(kfree) = kstrndup(w->name, 15, GFP_KERNEL);
4971 if (!wname)
4972 return -ENOMEM;
4973
4974 widget_name = wname;
4975 dec_adc_mux_name = strsep(&widget_name, " ");
4976 if (!dec_adc_mux_name) {
4977 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4978 __func__, w->name);
4979 return -EINVAL;
4980 }
4981 dec_adc_mux_name = widget_name;
4982
4983 dec = strpbrk(dec_adc_mux_name, "012345678");
4984 if (!dec) {
4985 dev_err(comp->dev, "%s: decimator index not found\n",
4986 __func__);
4987 return -EINVAL;
4988 }
4989
4990 ret = kstrtouint(dec, 10, &decimator);
4991 if (ret < 0) {
4992 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4993 __func__, wname);
4994 return -EINVAL;
4995 }
4996
4997 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
4998 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
4999 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
5000 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
5001
5002 switch (event) {
5003 case SND_SOC_DAPM_PRE_PMU:
5004 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
5005 if (amic_n)
5006 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
5007 amic_n);
5008
5009 if (!pwr_level_reg)
5010 break;
5011
5012 switch ((snd_soc_component_read(comp, pwr_level_reg) &
5013 WCD934X_AMIC_PWR_LVL_MASK) >>
5014 WCD934X_AMIC_PWR_LVL_SHIFT) {
5015 case WCD934X_AMIC_PWR_LEVEL_LP:
5016 snd_soc_component_update_bits(comp, dec_cfg_reg,
5017 WCD934X_DEC_PWR_LVL_MASK,
5018 WCD934X_DEC_PWR_LVL_LP);
5019 break;
5020 case WCD934X_AMIC_PWR_LEVEL_HP:
5021 snd_soc_component_update_bits(comp, dec_cfg_reg,
5022 WCD934X_DEC_PWR_LVL_MASK,
5023 WCD934X_DEC_PWR_LVL_HP);
5024 break;
5025 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
5026 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
5027 default:
5028 snd_soc_component_update_bits(comp, dec_cfg_reg,
5029 WCD934X_DEC_PWR_LVL_MASK,
5030 WCD934X_DEC_PWR_LVL_DF);
5031 break;
5032 }
5033 break;
5034 case SND_SOC_DAPM_POST_PMU:
5035 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5036 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5037 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5038 snd_soc_component_update_bits(comp, dec_cfg_reg,
5039 TX_HPF_CUT_OFF_FREQ_MASK,
5040 CF_MIN_3DB_150HZ << 5);
5041 snd_soc_component_update_bits(comp, hpf_gate_reg,
5042 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5043 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5044 /*
5045 * Minimum 1 clk cycle delay is required as per
5046 * HW spec.
5047 */
5048 usleep_range(1000, 1010);
5049 snd_soc_component_update_bits(comp, hpf_gate_reg,
5050 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5051 0);
5052 }
5053 /* apply gain after decimator is enabled */
5054 snd_soc_component_write(comp, tx_gain_ctl_reg,
5055 snd_soc_component_read(comp,
5056 tx_gain_ctl_reg));
5057 break;
5058 case SND_SOC_DAPM_PRE_PMD:
5059 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5060 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5061
5062 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5063 snd_soc_component_update_bits(comp, dec_cfg_reg,
5064 TX_HPF_CUT_OFF_FREQ_MASK,
5065 hpf_coff_freq << 5);
5066 snd_soc_component_update_bits(comp, hpf_gate_reg,
5067 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5068 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5069 /*
5070 * Minimum 1 clk cycle delay is required as per
5071 * HW spec.
5072 */
5073 usleep_range(1000, 1010);
5074 snd_soc_component_update_bits(comp, hpf_gate_reg,
5075 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5076 0);
5077 }
5078 break;
5079 case SND_SOC_DAPM_POST_PMD:
5080 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
5081 0x10, 0x00);
5082 snd_soc_component_update_bits(comp, dec_cfg_reg,
5083 WCD934X_DEC_PWR_LVL_MASK,
5084 WCD934X_DEC_PWR_LVL_DF);
5085 break;
5086 }
5087
5088 return ret;
5089 }
5090
wcd934x_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)5091 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
5092 u16 amic_reg, bool set)
5093 {
5094 u8 mask = 0x20;
5095 u8 val;
5096
5097 if (amic_reg == WCD934X_ANA_AMIC1 ||
5098 amic_reg == WCD934X_ANA_AMIC3)
5099 mask = 0x40;
5100
5101 val = set ? mask : 0x00;
5102
5103 switch (amic_reg) {
5104 case WCD934X_ANA_AMIC1:
5105 case WCD934X_ANA_AMIC2:
5106 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
5107 mask, val);
5108 break;
5109 case WCD934X_ANA_AMIC3:
5110 case WCD934X_ANA_AMIC4:
5111 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
5112 mask, val);
5113 break;
5114 default:
5115 break;
5116 }
5117 }
5118
wcd934x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)5119 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
5120 struct snd_kcontrol *kcontrol, int event)
5121 {
5122 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
5123
5124 switch (event) {
5125 case SND_SOC_DAPM_PRE_PMU:
5126 wcd934x_codec_set_tx_hold(comp, w->reg, true);
5127 break;
5128 default:
5129 break;
5130 }
5131
5132 return 0;
5133 }
5134
wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)5135 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
5136 struct snd_kcontrol *kcontrol,
5137 int event)
5138 {
5139 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
5140 int micb_num = w->shift;
5141
5142 switch (event) {
5143 case SND_SOC_DAPM_PRE_PMU:
5144 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true);
5145 break;
5146 case SND_SOC_DAPM_POST_PMU:
5147 /* 1 msec delay as per HW requirement */
5148 usleep_range(1000, 1100);
5149 break;
5150 case SND_SOC_DAPM_POST_PMD:
5151 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true);
5152 break;
5153 }
5154
5155 return 0;
5156 }
5157
5158 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
5159 /* Analog Outputs */
5160 SND_SOC_DAPM_OUTPUT("EAR"),
5161 SND_SOC_DAPM_OUTPUT("HPHL"),
5162 SND_SOC_DAPM_OUTPUT("HPHR"),
5163 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
5164 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
5165 SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
5166 SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
5167 SND_SOC_DAPM_OUTPUT("ANC EAR"),
5168 SND_SOC_DAPM_OUTPUT("ANC HPHL"),
5169 SND_SOC_DAPM_OUTPUT("ANC HPHR"),
5170 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
5171 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
5172 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
5173 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
5174 AIF1_PB, 0, wcd934x_codec_enable_slim,
5175 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5176 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
5177 AIF2_PB, 0, wcd934x_codec_enable_slim,
5178 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5179 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
5180 AIF3_PB, 0, wcd934x_codec_enable_slim,
5181 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5182 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
5183 AIF4_PB, 0, wcd934x_codec_enable_slim,
5184 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5185
5186 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
5187 &slim_rx_mux[WCD934X_RX0]),
5188 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
5189 &slim_rx_mux[WCD934X_RX1]),
5190 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
5191 &slim_rx_mux[WCD934X_RX2]),
5192 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
5193 &slim_rx_mux[WCD934X_RX3]),
5194 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
5195 &slim_rx_mux[WCD934X_RX4]),
5196 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
5197 &slim_rx_mux[WCD934X_RX5]),
5198 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
5199 &slim_rx_mux[WCD934X_RX6]),
5200 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
5201 &slim_rx_mux[WCD934X_RX7]),
5202
5203 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5204 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5205 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5206 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5207 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5208 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5209 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5210 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5211
5212 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
5213 &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
5214 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5215 SND_SOC_DAPM_POST_PMD),
5216 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
5217 &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
5218 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5219 SND_SOC_DAPM_POST_PMD),
5220 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
5221 &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
5222 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5223 SND_SOC_DAPM_POST_PMD),
5224 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
5225 &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
5226 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5227 SND_SOC_DAPM_POST_PMD),
5228 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
5229 &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
5230 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5231 SND_SOC_DAPM_POST_PMD),
5232 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
5233 &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
5234 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5235 SND_SOC_DAPM_POST_PMD),
5236 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
5237 &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
5238 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5239 SND_SOC_DAPM_POST_PMD),
5240
5241 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5242 &rx_int0_1_mix_inp0_mux),
5243 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5244 &rx_int0_1_mix_inp1_mux),
5245 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5246 &rx_int0_1_mix_inp2_mux),
5247 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5248 &rx_int1_1_mix_inp0_mux),
5249 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5250 &rx_int1_1_mix_inp1_mux),
5251 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5252 &rx_int1_1_mix_inp2_mux),
5253 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5254 &rx_int2_1_mix_inp0_mux),
5255 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5256 &rx_int2_1_mix_inp1_mux),
5257 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5258 &rx_int2_1_mix_inp2_mux),
5259 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5260 &rx_int3_1_mix_inp0_mux),
5261 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5262 &rx_int3_1_mix_inp1_mux),
5263 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5264 &rx_int3_1_mix_inp2_mux),
5265 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5266 &rx_int4_1_mix_inp0_mux),
5267 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5268 &rx_int4_1_mix_inp1_mux),
5269 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5270 &rx_int4_1_mix_inp2_mux),
5271 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5272 &rx_int7_1_mix_inp0_mux),
5273 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5274 &rx_int7_1_mix_inp1_mux),
5275 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5276 &rx_int7_1_mix_inp2_mux),
5277 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5278 &rx_int8_1_mix_inp0_mux),
5279 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5280 &rx_int8_1_mix_inp1_mux),
5281 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5282 &rx_int8_1_mix_inp2_mux),
5283 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5284 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5285 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5286 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
5287 rx_int1_asrc_switch,
5288 ARRAY_SIZE(rx_int1_asrc_switch)),
5289 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5290 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
5291 rx_int2_asrc_switch,
5292 ARRAY_SIZE(rx_int2_asrc_switch)),
5293 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5294 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
5295 rx_int3_asrc_switch,
5296 ARRAY_SIZE(rx_int3_asrc_switch)),
5297 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5298 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
5299 rx_int4_asrc_switch,
5300 ARRAY_SIZE(rx_int4_asrc_switch)),
5301 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5302 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5303 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5304 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5305 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5306 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5307 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5308 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5309 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5310 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5311 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5312 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5313 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5314
5315 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5316 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
5317 NULL, 0, NULL, 0),
5318 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
5319 NULL, 0, NULL, 0),
5320 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
5321 0, &rx_int0_mix2_inp_mux, NULL,
5322 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5323 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
5324 0, &rx_int1_mix2_inp_mux, NULL,
5325 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5326 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
5327 0, &rx_int2_mix2_inp_mux, NULL,
5328 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5329 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
5330 0, &rx_int3_mix2_inp_mux, NULL,
5331 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5332 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
5333 0, &rx_int4_mix2_inp_mux, NULL,
5334 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5335 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
5336 0, &rx_int7_mix2_inp_mux, NULL,
5337 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5338
5339 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
5340 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
5341 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
5342 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
5343 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
5344 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
5345 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
5346 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
5347
5348 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
5349 0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5350 SND_SOC_DAPM_POST_PMU),
5351 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
5352 1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5353 SND_SOC_DAPM_POST_PMU),
5354 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
5355 4, 0, NULL, 0),
5356 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
5357 4, 0, NULL, 0),
5358 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
5359 &rx_int0_dem_inp_mux),
5360 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
5361 &rx_int1_dem_inp_mux),
5362 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
5363 &rx_int2_dem_inp_mux),
5364
5365 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
5366 &rx_int0_1_interp_mux,
5367 wcd934x_codec_enable_main_path,
5368 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5369 SND_SOC_DAPM_POST_PMD),
5370 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
5371 &rx_int1_1_interp_mux,
5372 wcd934x_codec_enable_main_path,
5373 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5374 SND_SOC_DAPM_POST_PMD),
5375 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
5376 &rx_int2_1_interp_mux,
5377 wcd934x_codec_enable_main_path,
5378 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5379 SND_SOC_DAPM_POST_PMD),
5380 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
5381 &rx_int3_1_interp_mux,
5382 wcd934x_codec_enable_main_path,
5383 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5384 SND_SOC_DAPM_POST_PMD),
5385 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
5386 &rx_int4_1_interp_mux,
5387 wcd934x_codec_enable_main_path,
5388 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5389 SND_SOC_DAPM_POST_PMD),
5390 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
5391 &rx_int7_1_interp_mux,
5392 wcd934x_codec_enable_main_path,
5393 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5394 SND_SOC_DAPM_POST_PMD),
5395 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
5396 &rx_int8_1_interp_mux,
5397 wcd934x_codec_enable_main_path,
5398 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5399 SND_SOC_DAPM_POST_PMD),
5400
5401 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
5402 &rx_int0_2_interp_mux),
5403 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
5404 &rx_int1_2_interp_mux),
5405 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
5406 &rx_int2_2_interp_mux),
5407 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
5408 &rx_int3_2_interp_mux),
5409 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
5410 &rx_int4_2_interp_mux),
5411 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
5412 &rx_int7_2_interp_mux),
5413 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
5414 &rx_int8_2_interp_mux),
5415 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
5416 0, 0, wcd934x_codec_ear_dac_event,
5417 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5418 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5419 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
5420 5, 0, wcd934x_codec_hphl_dac_event,
5421 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5422 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5423 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
5424 4, 0, wcd934x_codec_hphr_dac_event,
5425 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5426 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5427 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
5428 0, 0, wcd934x_codec_lineout_dac_event,
5429 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5430 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
5431 0, 0, wcd934x_codec_lineout_dac_event,
5432 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5433 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
5434 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
5435 wcd934x_codec_enable_hphl_pa,
5436 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5437 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5438 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
5439 wcd934x_codec_enable_hphr_pa,
5440 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5441 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5442 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
5443 NULL, 0),
5444 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
5445 NULL, 0),
5446 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
5447 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5448 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
5449 0, 0, NULL, 0),
5450 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
5451 0, 0, NULL, 0),
5452 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
5453 0, 0, NULL, 0),
5454 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
5455 0, 0, NULL, 0),
5456 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
5457 wcd934x_codec_enable_interp_clk,
5458 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5459 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
5460 wcd934x_codec_enable_interp_clk,
5461 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5462 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
5463 wcd934x_codec_enable_interp_clk,
5464 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5465 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
5466 wcd934x_codec_enable_interp_clk,
5467 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5468 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
5469 wcd934x_codec_enable_interp_clk,
5470 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5471 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
5472 wcd934x_codec_enable_interp_clk,
5473 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5474 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
5475 wcd934x_codec_enable_interp_clk,
5476 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5477 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
5478 0, 0, NULL, 0),
5479 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
5480 0, 0, NULL, 0),
5481 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
5482 0, 0, NULL, 0),
5483 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
5484 0, 0, NULL, 0),
5485 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
5486 0, 0, NULL, 0),
5487 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
5488 0, 0, NULL, 0),
5489 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
5490 0, 0, NULL, 0),
5491 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
5492 wcd934x_codec_enable_mclk,
5493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5494
5495 /* TX */
5496 SND_SOC_DAPM_INPUT("AMIC1"),
5497 SND_SOC_DAPM_INPUT("AMIC2"),
5498 SND_SOC_DAPM_INPUT("AMIC3"),
5499 SND_SOC_DAPM_INPUT("AMIC4"),
5500 SND_SOC_DAPM_INPUT("AMIC5"),
5501 SND_SOC_DAPM_INPUT("DMIC0 Pin"),
5502 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
5503 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
5504 SND_SOC_DAPM_INPUT("DMIC3 Pin"),
5505 SND_SOC_DAPM_INPUT("DMIC4 Pin"),
5506 SND_SOC_DAPM_INPUT("DMIC5 Pin"),
5507
5508 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
5509 AIF1_CAP, 0, wcd934x_codec_enable_slim,
5510 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5511 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
5512 AIF2_CAP, 0, wcd934x_codec_enable_slim,
5513 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5514 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
5515 AIF3_CAP, 0, wcd934x_codec_enable_slim,
5516 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5517
5518 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5519 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5520 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5521 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5522 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5523 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5524 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5525 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5526 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
5527 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
5528 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
5529 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
5530 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
5531
5532 /* Digital Mic Inputs */
5533 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
5534 wcd934x_codec_enable_dmic,
5535 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5536 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
5537 wcd934x_codec_enable_dmic,
5538 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5539 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
5540 wcd934x_codec_enable_dmic,
5541 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5542 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
5543 wcd934x_codec_enable_dmic,
5544 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5545 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
5546 wcd934x_codec_enable_dmic,
5547 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5548 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
5549 wcd934x_codec_enable_dmic,
5550 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5551 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
5552 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
5553 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
5554 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
5555 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
5556 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
5557 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
5558 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
5559 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
5560 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
5561 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
5562 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
5563 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
5564 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
5565 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
5566 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
5567 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
5568 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
5569 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
5570 &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
5571 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5572 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5573 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
5574 &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
5575 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5576 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5577 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
5578 &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
5579 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5580 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5581 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
5582 &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
5583 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5584 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5585 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
5586 &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
5587 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5588 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5589 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
5590 &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
5591 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5592 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5593 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
5594 &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
5595 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5596 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5597 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
5598 &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
5599 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5600 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5601 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
5602 &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
5603 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5604 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5605 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
5606 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5607 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
5608 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5609 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
5610 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5611 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
5612 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5613 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
5614 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5615 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5616 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
5617 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5618 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5619 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
5620 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5621 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5622 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
5623 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5624 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5625
5626 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
5627 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
5628 &cdc_if_tx0_mux),
5629 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
5630 &cdc_if_tx1_mux),
5631 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
5632 &cdc_if_tx2_mux),
5633 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
5634 &cdc_if_tx3_mux),
5635 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
5636 &cdc_if_tx4_mux),
5637 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
5638 &cdc_if_tx5_mux),
5639 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
5640 &cdc_if_tx6_mux),
5641 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
5642 &cdc_if_tx7_mux),
5643 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
5644 &cdc_if_tx8_mux),
5645 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
5646 &cdc_if_tx9_mux),
5647 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
5648 &cdc_if_tx10_mux),
5649 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5650 &cdc_if_tx11_mux),
5651 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5652 &cdc_if_tx11_inp1_mux),
5653 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5654 &cdc_if_tx13_mux),
5655 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5656 &cdc_if_tx13_inp1_mux),
5657 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
5658 aif1_slim_cap_mixer,
5659 ARRAY_SIZE(aif1_slim_cap_mixer)),
5660 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
5661 aif2_slim_cap_mixer,
5662 ARRAY_SIZE(aif2_slim_cap_mixer)),
5663 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
5664 aif3_slim_cap_mixer,
5665 ARRAY_SIZE(aif3_slim_cap_mixer)),
5666 };
5667
5668 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
5669 /* RX0-RX7 */
5670 WCD934X_SLIM_RX_AIF_PATH(0),
5671 WCD934X_SLIM_RX_AIF_PATH(1),
5672 WCD934X_SLIM_RX_AIF_PATH(2),
5673 WCD934X_SLIM_RX_AIF_PATH(3),
5674 WCD934X_SLIM_RX_AIF_PATH(4),
5675 WCD934X_SLIM_RX_AIF_PATH(5),
5676 WCD934X_SLIM_RX_AIF_PATH(6),
5677 WCD934X_SLIM_RX_AIF_PATH(7),
5678
5679 /* RX0 Ear out */
5680 WCD934X_INTERPOLATOR_PATH(0),
5681 WCD934X_INTERPOLATOR_MIX2(0),
5682 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
5683 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
5684 {"RX INT0 DAC", NULL, "RX_BIAS"},
5685 {"EAR PA", NULL, "RX INT0 DAC"},
5686 {"EAR", NULL, "EAR PA"},
5687
5688 /* RX1 Headphone left */
5689 WCD934X_INTERPOLATOR_PATH(1),
5690 WCD934X_INTERPOLATOR_MIX2(1),
5691 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
5692 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
5693 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
5694 {"RX INT1 DAC", NULL, "RX_BIAS"},
5695 {"HPHL PA", NULL, "RX INT1 DAC"},
5696 {"HPHL", NULL, "HPHL PA"},
5697
5698 /* RX2 Headphone right */
5699 WCD934X_INTERPOLATOR_PATH(2),
5700 WCD934X_INTERPOLATOR_MIX2(2),
5701 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
5702 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
5703 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
5704 {"RX INT2 DAC", NULL, "RX_BIAS"},
5705 {"HPHR PA", NULL, "RX INT2 DAC"},
5706 {"HPHR", NULL, "HPHR PA"},
5707
5708 /* RX3 HIFi LineOut1 */
5709 WCD934X_INTERPOLATOR_PATH(3),
5710 WCD934X_INTERPOLATOR_MIX2(3),
5711 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
5712 {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
5713 {"RX INT3 DAC", NULL, "RX_BIAS"},
5714 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
5715 {"LINEOUT1", NULL, "LINEOUT1 PA"},
5716
5717 /* RX4 HIFi LineOut2 */
5718 WCD934X_INTERPOLATOR_PATH(4),
5719 WCD934X_INTERPOLATOR_MIX2(4),
5720 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
5721 {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
5722 {"RX INT4 DAC", NULL, "RX_BIAS"},
5723 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
5724 {"LINEOUT2", NULL, "LINEOUT2 PA"},
5725
5726 /* RX7 Speaker Left Out PA */
5727 WCD934X_INTERPOLATOR_PATH(7),
5728 WCD934X_INTERPOLATOR_MIX2(7),
5729 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
5730 {"RX INT7 CHAIN", NULL, "RX_BIAS"},
5731 {"RX INT7 CHAIN", NULL, "SBOOST0"},
5732 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
5733 {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
5734
5735 /* RX8 Speaker Right Out PA */
5736 WCD934X_INTERPOLATOR_PATH(8),
5737 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
5738 {"RX INT8 CHAIN", NULL, "RX_BIAS"},
5739 {"RX INT8 CHAIN", NULL, "SBOOST1"},
5740 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
5741 {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
5742
5743 /* Tx */
5744 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
5745 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
5746 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
5747
5748 WCD934X_SLIM_TX_AIF_PATH(0),
5749 WCD934X_SLIM_TX_AIF_PATH(1),
5750 WCD934X_SLIM_TX_AIF_PATH(2),
5751 WCD934X_SLIM_TX_AIF_PATH(3),
5752 WCD934X_SLIM_TX_AIF_PATH(4),
5753 WCD934X_SLIM_TX_AIF_PATH(5),
5754 WCD934X_SLIM_TX_AIF_PATH(6),
5755 WCD934X_SLIM_TX_AIF_PATH(7),
5756 WCD934X_SLIM_TX_AIF_PATH(8),
5757
5758 WCD934X_ADC_MUX(0),
5759 WCD934X_ADC_MUX(1),
5760 WCD934X_ADC_MUX(2),
5761 WCD934X_ADC_MUX(3),
5762 WCD934X_ADC_MUX(4),
5763 WCD934X_ADC_MUX(5),
5764 WCD934X_ADC_MUX(6),
5765 WCD934X_ADC_MUX(7),
5766 WCD934X_ADC_MUX(8),
5767
5768 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
5769 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
5770 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
5771 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
5772 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
5773 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
5774 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
5775 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
5776 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
5777
5778 {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
5779 {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
5780
5781 { "DMIC0", NULL, "DMIC0 Pin" },
5782 { "DMIC1", NULL, "DMIC1 Pin" },
5783 { "DMIC2", NULL, "DMIC2 Pin" },
5784 { "DMIC3", NULL, "DMIC3 Pin" },
5785 { "DMIC4", NULL, "DMIC4 Pin" },
5786 { "DMIC5", NULL, "DMIC5 Pin" },
5787
5788 {"ADC1", NULL, "AMIC1"},
5789 {"ADC2", NULL, "AMIC2"},
5790 {"ADC3", NULL, "AMIC3"},
5791 {"ADC4", NULL, "AMIC4_5 SEL"},
5792
5793 WCD934X_IIR_INP_MUX(0),
5794 WCD934X_IIR_INP_MUX(1),
5795
5796 {"SRC0", NULL, "IIR0"},
5797 {"SRC1", NULL, "IIR1"},
5798 };
5799
wcd934x_codec_set_jack(struct snd_soc_component * comp,struct snd_soc_jack * jack,void * data)5800 static int wcd934x_codec_set_jack(struct snd_soc_component *comp,
5801 struct snd_soc_jack *jack, void *data)
5802 {
5803 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
5804 int ret = 0;
5805
5806 if (!wcd->mbhc)
5807 return -ENOTSUPP;
5808
5809 if (jack && !wcd->mbhc_started) {
5810 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack);
5811 wcd->mbhc_started = true;
5812 } else if (wcd->mbhc_started) {
5813 wcd_mbhc_stop(wcd->mbhc);
5814 wcd->mbhc_started = false;
5815 }
5816
5817 return ret;
5818 }
5819
5820 static const struct snd_soc_component_driver wcd934x_component_drv = {
5821 .probe = wcd934x_comp_probe,
5822 .remove = wcd934x_comp_remove,
5823 .set_sysclk = wcd934x_comp_set_sysclk,
5824 .controls = wcd934x_snd_controls,
5825 .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
5826 .dapm_widgets = wcd934x_dapm_widgets,
5827 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
5828 .dapm_routes = wcd934x_audio_map,
5829 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
5830 .set_jack = wcd934x_codec_set_jack,
5831 .endianness = 1,
5832 };
5833
wcd934x_codec_parse_data(struct wcd934x_codec * wcd)5834 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
5835 {
5836 struct device *dev = &wcd->sdev->dev;
5837 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg;
5838 struct device_node *ifc_dev_np;
5839
5840 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5841 if (!ifc_dev_np)
5842 return dev_err_probe(dev, -EINVAL, "No Interface device found\n");
5843
5844 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
5845 of_node_put(ifc_dev_np);
5846 if (!wcd->sidev)
5847 return dev_err_probe(dev, -EINVAL, "Unable to get SLIM Interface device\n");
5848
5849 slim_get_logical_addr(wcd->sidev);
5850 wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5851 &wcd934x_ifc_regmap_config);
5852 if (IS_ERR(wcd->if_regmap))
5853 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
5854 "Failed to allocate ifc register map\n");
5855
5856 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5857 &wcd->dmic_sample_rate);
5858
5859 cfg->mbhc_micbias = MIC_BIAS_2;
5860 cfg->anc_micbias = MIC_BIAS_2;
5861 cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
5862 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS;
5863 cfg->micb_mv = wcd->micb2_mv;
5864 cfg->linein_th = 5000;
5865 cfg->hs_thr = 1700;
5866 cfg->hph_thr = 50;
5867
5868 wcd_dt_parse_mbhc_data(dev, cfg);
5869
5870
5871 return 0;
5872 }
5873
wcd934x_codec_probe(struct platform_device * pdev)5874 static int wcd934x_codec_probe(struct platform_device *pdev)
5875 {
5876 struct device *dev = &pdev->dev;
5877 struct wcd934x_ddata *data = dev_get_drvdata(dev->parent);
5878 struct wcd934x_codec *wcd;
5879 int ret, irq;
5880
5881 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5882 if (!wcd)
5883 return -ENOMEM;
5884
5885 wcd->dev = dev;
5886 wcd->regmap = data->regmap;
5887 wcd->extclk = data->extclk;
5888 wcd->sdev = to_slim_device(data->dev);
5889 mutex_init(&wcd->sysclk_mutex);
5890 mutex_init(&wcd->micb_lock);
5891
5892 ret = wcd934x_codec_parse_data(wcd);
5893 if (ret)
5894 return ret;
5895
5896 /* set default rate 9P6MHz */
5897 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5898 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5899 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5900 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5901 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5902
5903 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5904 if (irq < 0)
5905 return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n");
5906
5907 ret = devm_request_threaded_irq(dev, irq, NULL,
5908 wcd934x_slim_irq_handler,
5909 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5910 "slim", wcd);
5911 if (ret)
5912 return dev_err_probe(dev, ret, "Failed to request slimbus irq\n");
5913
5914 wcd934x_register_mclk_output(wcd);
5915 platform_set_drvdata(pdev, wcd);
5916
5917 return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5918 wcd934x_slim_dais,
5919 ARRAY_SIZE(wcd934x_slim_dais));
5920 }
5921
5922 static const struct platform_device_id wcd934x_driver_id[] = {
5923 {
5924 .name = "wcd934x-codec",
5925 },
5926 {},
5927 };
5928 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5929
5930 static struct platform_driver wcd934x_codec_driver = {
5931 .probe = &wcd934x_codec_probe,
5932 .id_table = wcd934x_driver_id,
5933 .driver = {
5934 .name = "wcd934x-codec",
5935 }
5936 };
5937
5938 module_platform_driver(wcd934x_codec_driver);
5939 MODULE_DESCRIPTION("WCD934x codec driver");
5940 MODULE_LICENSE("GPL v2");
5941