1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * GPIO interface for Winbond Super I/O chips
4 * Currently, only W83627UHG (Nuvoton NCT6627UD) is supported.
5 *
6 * Author: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/gpio/driver.h>
12 #include <linux/ioport.h>
13 #include <linux/isa.h>
14 #include <linux/module.h>
15
16 #define WB_GPIO_DRIVER_NAME KBUILD_MODNAME
17
18 #define WB_SIO_BASE 0x2e
19 #define WB_SIO_BASE_HIGH 0x4e
20
21 #define WB_SIO_EXT_ENTER_KEY 0x87
22 #define WB_SIO_EXT_EXIT_KEY 0xaa
23
24 /* global chip registers */
25
26 #define WB_SIO_REG_LOGICAL 0x07
27
28 #define WB_SIO_REG_CHIP_MSB 0x20
29 #define WB_SIO_REG_CHIP_LSB 0x21
30
31 #define WB_SIO_CHIP_ID_W83627UHG 0xa230
32 #define WB_SIO_CHIP_ID_W83627UHG_MASK GENMASK(15, 4)
33
34 #define WB_SIO_REG_DPD 0x22
35 #define WB_SIO_REG_DPD_UARTA 4
36 #define WB_SIO_REG_DPD_UARTB 5
37
38 #define WB_SIO_REG_IDPD 0x23
39 #define WB_SIO_REG_IDPD_UARTC 4
40 #define WB_SIO_REG_IDPD_UARTD 5
41 #define WB_SIO_REG_IDPD_UARTE 6
42 #define WB_SIO_REG_IDPD_UARTF 7
43
44 #define WB_SIO_REG_GLOBAL_OPT 0x24
45 #define WB_SIO_REG_GO_ENFDC 1
46
47 #define WB_SIO_REG_OVTGPIO3456 0x29
48 #define WB_SIO_REG_OG3456_G3PP 3
49 #define WB_SIO_REG_OG3456_G4PP 4
50 #define WB_SIO_REG_OG3456_G5PP 5
51 #define WB_SIO_REG_OG3456_G6PP 7
52
53 #define WB_SIO_REG_I2C_PS 0x2a
54 #define WB_SIO_REG_I2CPS_I2CFS 1
55
56 #define WB_SIO_REG_GPIO1_MF 0x2c
57 #define WB_SIO_REG_G1MF_G1PP 6
58 #define WB_SIO_REG_G1MF_G2PP 7
59 #define WB_SIO_REG_G1MF_FS_MASK GENMASK(1, 0)
60 #define WB_SIO_REG_G1MF_FS_IR_OFF 0
61 #define WB_SIO_REG_G1MF_FS_IR 1
62 #define WB_SIO_REG_G1MF_FS_GPIO1 2
63 #define WB_SIO_REG_G1MF_FS_UARTB 3
64
65 /* not an actual device number, just a value meaning 'no device' */
66 #define WB_SIO_DEV_NONE 0xff
67
68 /* registers with offsets >= 0x30 are specific for a particular device */
69
70 /* UART B logical device */
71 #define WB_SIO_DEV_UARTB 0x03
72 #define WB_SIO_UARTB_REG_ENABLE 0x30
73 #define WB_SIO_UARTB_ENABLE_ON 0
74
75 /* UART C logical device */
76 #define WB_SIO_DEV_UARTC 0x06
77 #define WB_SIO_UARTC_REG_ENABLE 0x30
78 #define WB_SIO_UARTC_ENABLE_ON 0
79
80 /* GPIO3, GPIO4 logical device */
81 #define WB_SIO_DEV_GPIO34 0x07
82 #define WB_SIO_GPIO34_REG_ENABLE 0x30
83 #define WB_SIO_GPIO34_ENABLE_3 0
84 #define WB_SIO_GPIO34_ENABLE_4 1
85 #define WB_SIO_GPIO34_REG_IO3 0xe0
86 #define WB_SIO_GPIO34_REG_DATA3 0xe1
87 #define WB_SIO_GPIO34_REG_INV3 0xe2
88 #define WB_SIO_GPIO34_REG_IO4 0xe4
89 #define WB_SIO_GPIO34_REG_DATA4 0xe5
90 #define WB_SIO_GPIO34_REG_INV4 0xe6
91
92 /* WDTO, PLED, GPIO5, GPIO6 logical device */
93 #define WB_SIO_DEV_WDGPIO56 0x08
94 #define WB_SIO_WDGPIO56_REG_ENABLE 0x30
95 #define WB_SIO_WDGPIO56_ENABLE_5 1
96 #define WB_SIO_WDGPIO56_ENABLE_6 2
97 #define WB_SIO_WDGPIO56_REG_IO5 0xe0
98 #define WB_SIO_WDGPIO56_REG_DATA5 0xe1
99 #define WB_SIO_WDGPIO56_REG_INV5 0xe2
100 #define WB_SIO_WDGPIO56_REG_IO6 0xe4
101 #define WB_SIO_WDGPIO56_REG_DATA6 0xe5
102 #define WB_SIO_WDGPIO56_REG_INV6 0xe6
103
104 /* GPIO1, GPIO2, SUSLED logical device */
105 #define WB_SIO_DEV_GPIO12 0x09
106 #define WB_SIO_GPIO12_REG_ENABLE 0x30
107 #define WB_SIO_GPIO12_ENABLE_1 0
108 #define WB_SIO_GPIO12_ENABLE_2 1
109 #define WB_SIO_GPIO12_REG_IO1 0xe0
110 #define WB_SIO_GPIO12_REG_DATA1 0xe1
111 #define WB_SIO_GPIO12_REG_INV1 0xe2
112 #define WB_SIO_GPIO12_REG_IO2 0xe4
113 #define WB_SIO_GPIO12_REG_DATA2 0xe5
114 #define WB_SIO_GPIO12_REG_INV2 0xe6
115
116 /* UART D logical device */
117 #define WB_SIO_DEV_UARTD 0x0d
118 #define WB_SIO_UARTD_REG_ENABLE 0x30
119 #define WB_SIO_UARTD_ENABLE_ON 0
120
121 /* UART E logical device */
122 #define WB_SIO_DEV_UARTE 0x0e
123 #define WB_SIO_UARTE_REG_ENABLE 0x30
124 #define WB_SIO_UARTE_ENABLE_ON 0
125
126 /*
127 * for a description what a particular field of this struct means please see
128 * a description of the relevant module parameter at the bottom of this file
129 */
130 struct winbond_gpio_params {
131 unsigned long base;
132 unsigned long gpios;
133 unsigned long ppgpios;
134 unsigned long odgpios;
135 bool pledgpio;
136 bool beepgpio;
137 bool i2cgpio;
138 };
139
140 static struct winbond_gpio_params params;
141
winbond_sio_enter(unsigned long base)142 static int winbond_sio_enter(unsigned long base)
143 {
144 if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME))
145 return -EBUSY;
146
147 /*
148 * datasheet says two successive writes of the "key" value are needed
149 * in order for chip to enter the "Extended Function Mode"
150 */
151 outb(WB_SIO_EXT_ENTER_KEY, base);
152 outb(WB_SIO_EXT_ENTER_KEY, base);
153
154 return 0;
155 }
156
winbond_sio_select_logical(unsigned long base,u8 dev)157 static void winbond_sio_select_logical(unsigned long base, u8 dev)
158 {
159 outb(WB_SIO_REG_LOGICAL, base);
160 outb(dev, base + 1);
161 }
162
winbond_sio_leave(unsigned long base)163 static void winbond_sio_leave(unsigned long base)
164 {
165 outb(WB_SIO_EXT_EXIT_KEY, base);
166
167 release_region(base, 2);
168 }
169
winbond_sio_reg_write(unsigned long base,u8 reg,u8 data)170 static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data)
171 {
172 outb(reg, base);
173 outb(data, base + 1);
174 }
175
winbond_sio_reg_read(unsigned long base,u8 reg)176 static u8 winbond_sio_reg_read(unsigned long base, u8 reg)
177 {
178 outb(reg, base);
179 return inb(base + 1);
180 }
181
winbond_sio_reg_bset(unsigned long base,u8 reg,u8 bit)182 static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit)
183 {
184 u8 val;
185
186 val = winbond_sio_reg_read(base, reg);
187 val |= BIT(bit);
188 winbond_sio_reg_write(base, reg, val);
189 }
190
winbond_sio_reg_bclear(unsigned long base,u8 reg,u8 bit)191 static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit)
192 {
193 u8 val;
194
195 val = winbond_sio_reg_read(base, reg);
196 val &= ~BIT(bit);
197 winbond_sio_reg_write(base, reg, val);
198 }
199
winbond_sio_reg_btest(unsigned long base,u8 reg,u8 bit)200 static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit)
201 {
202 return winbond_sio_reg_read(base, reg) & BIT(bit);
203 }
204
205 /**
206 * struct winbond_gpio_port_conflict - possibly conflicting device information
207 * @name: device name (NULL means no conflicting device defined)
208 * @dev: Super I/O logical device number where the testreg register
209 * is located (or WB_SIO_DEV_NONE - don't select any
210 * logical device)
211 * @testreg: register number where the testbit bit is located
212 * @testbit: index of a bit to check whether an actual conflict exists
213 * @warnonly: if set then a conflict isn't fatal (just warn about it),
214 * otherwise disable the particular GPIO port if a conflict
215 * is detected
216 */
217 struct winbond_gpio_port_conflict {
218 const char *name;
219 u8 dev;
220 u8 testreg;
221 u8 testbit;
222 bool warnonly;
223 };
224
225 /**
226 * struct winbond_gpio_info - information about a particular GPIO port (device)
227 * @dev: Super I/O logical device number of the registers
228 * specified below
229 * @enablereg: port enable bit register number
230 * @enablebit: index of a port enable bit
231 * @outputreg: output driver mode bit register number
232 * @outputppbit: index of a push-pull output driver mode bit
233 * @ioreg: data direction register number
234 * @invreg: pin data inversion register number
235 * @datareg: pin data register number
236 * @conflict: description of a device that possibly conflicts with
237 * this port
238 */
239 struct winbond_gpio_info {
240 u8 dev;
241 u8 enablereg;
242 u8 enablebit;
243 u8 outputreg;
244 u8 outputppbit;
245 u8 ioreg;
246 u8 invreg;
247 u8 datareg;
248 struct winbond_gpio_port_conflict conflict;
249 };
250
251 static const struct winbond_gpio_info winbond_gpio_infos[6] = {
252 { /* 0 */
253 .dev = WB_SIO_DEV_GPIO12,
254 .enablereg = WB_SIO_GPIO12_REG_ENABLE,
255 .enablebit = WB_SIO_GPIO12_ENABLE_1,
256 .outputreg = WB_SIO_REG_GPIO1_MF,
257 .outputppbit = WB_SIO_REG_G1MF_G1PP,
258 .ioreg = WB_SIO_GPIO12_REG_IO1,
259 .invreg = WB_SIO_GPIO12_REG_INV1,
260 .datareg = WB_SIO_GPIO12_REG_DATA1,
261 .conflict = {
262 .name = "UARTB",
263 .dev = WB_SIO_DEV_UARTB,
264 .testreg = WB_SIO_UARTB_REG_ENABLE,
265 .testbit = WB_SIO_UARTB_ENABLE_ON,
266 .warnonly = true
267 }
268 },
269 { /* 1 */
270 .dev = WB_SIO_DEV_GPIO12,
271 .enablereg = WB_SIO_GPIO12_REG_ENABLE,
272 .enablebit = WB_SIO_GPIO12_ENABLE_2,
273 .outputreg = WB_SIO_REG_GPIO1_MF,
274 .outputppbit = WB_SIO_REG_G1MF_G2PP,
275 .ioreg = WB_SIO_GPIO12_REG_IO2,
276 .invreg = WB_SIO_GPIO12_REG_INV2,
277 .datareg = WB_SIO_GPIO12_REG_DATA2
278 /* special conflict handling so doesn't use conflict data */
279 },
280 { /* 2 */
281 .dev = WB_SIO_DEV_GPIO34,
282 .enablereg = WB_SIO_GPIO34_REG_ENABLE,
283 .enablebit = WB_SIO_GPIO34_ENABLE_3,
284 .outputreg = WB_SIO_REG_OVTGPIO3456,
285 .outputppbit = WB_SIO_REG_OG3456_G3PP,
286 .ioreg = WB_SIO_GPIO34_REG_IO3,
287 .invreg = WB_SIO_GPIO34_REG_INV3,
288 .datareg = WB_SIO_GPIO34_REG_DATA3,
289 .conflict = {
290 .name = "UARTC",
291 .dev = WB_SIO_DEV_UARTC,
292 .testreg = WB_SIO_UARTC_REG_ENABLE,
293 .testbit = WB_SIO_UARTC_ENABLE_ON,
294 .warnonly = true
295 }
296 },
297 { /* 3 */
298 .dev = WB_SIO_DEV_GPIO34,
299 .enablereg = WB_SIO_GPIO34_REG_ENABLE,
300 .enablebit = WB_SIO_GPIO34_ENABLE_4,
301 .outputreg = WB_SIO_REG_OVTGPIO3456,
302 .outputppbit = WB_SIO_REG_OG3456_G4PP,
303 .ioreg = WB_SIO_GPIO34_REG_IO4,
304 .invreg = WB_SIO_GPIO34_REG_INV4,
305 .datareg = WB_SIO_GPIO34_REG_DATA4,
306 .conflict = {
307 .name = "UARTD",
308 .dev = WB_SIO_DEV_UARTD,
309 .testreg = WB_SIO_UARTD_REG_ENABLE,
310 .testbit = WB_SIO_UARTD_ENABLE_ON,
311 .warnonly = true
312 }
313 },
314 { /* 4 */
315 .dev = WB_SIO_DEV_WDGPIO56,
316 .enablereg = WB_SIO_WDGPIO56_REG_ENABLE,
317 .enablebit = WB_SIO_WDGPIO56_ENABLE_5,
318 .outputreg = WB_SIO_REG_OVTGPIO3456,
319 .outputppbit = WB_SIO_REG_OG3456_G5PP,
320 .ioreg = WB_SIO_WDGPIO56_REG_IO5,
321 .invreg = WB_SIO_WDGPIO56_REG_INV5,
322 .datareg = WB_SIO_WDGPIO56_REG_DATA5,
323 .conflict = {
324 .name = "UARTE",
325 .dev = WB_SIO_DEV_UARTE,
326 .testreg = WB_SIO_UARTE_REG_ENABLE,
327 .testbit = WB_SIO_UARTE_ENABLE_ON,
328 .warnonly = true
329 }
330 },
331 { /* 5 */
332 .dev = WB_SIO_DEV_WDGPIO56,
333 .enablereg = WB_SIO_WDGPIO56_REG_ENABLE,
334 .enablebit = WB_SIO_WDGPIO56_ENABLE_6,
335 .outputreg = WB_SIO_REG_OVTGPIO3456,
336 .outputppbit = WB_SIO_REG_OG3456_G6PP,
337 .ioreg = WB_SIO_WDGPIO56_REG_IO6,
338 .invreg = WB_SIO_WDGPIO56_REG_INV6,
339 .datareg = WB_SIO_WDGPIO56_REG_DATA6,
340 .conflict = {
341 .name = "FDC",
342 .dev = WB_SIO_DEV_NONE,
343 .testreg = WB_SIO_REG_GLOBAL_OPT,
344 .testbit = WB_SIO_REG_GO_ENFDC,
345 .warnonly = false
346 }
347 }
348 };
349
350 /* returns whether changing a pin is allowed */
winbond_gpio_get_info(unsigned int * gpio_num,const struct winbond_gpio_info ** info)351 static bool winbond_gpio_get_info(unsigned int *gpio_num,
352 const struct winbond_gpio_info **info)
353 {
354 bool allow_changing = true;
355 unsigned long i;
356
357 for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG) {
358 if (*gpio_num < 8)
359 break;
360
361 *gpio_num -= 8;
362 }
363
364 *info = &winbond_gpio_infos[i];
365
366 /*
367 * GPIO2 (the second port) shares some pins with a basic PC
368 * functionality, which is very likely controlled by the firmware.
369 * Don't allow changing these pins by default.
370 */
371 if (i == 1) {
372 if (*gpio_num == 0 && !params.pledgpio)
373 allow_changing = false;
374 else if (*gpio_num == 1 && !params.beepgpio)
375 allow_changing = false;
376 else if ((*gpio_num == 5 || *gpio_num == 6) && !params.i2cgpio)
377 allow_changing = false;
378 }
379
380 return allow_changing;
381 }
382
winbond_gpio_get(struct gpio_chip * gc,unsigned int offset)383 static int winbond_gpio_get(struct gpio_chip *gc, unsigned int offset)
384 {
385 unsigned long *base = gpiochip_get_data(gc);
386 const struct winbond_gpio_info *info;
387 bool val;
388 int ret;
389
390 winbond_gpio_get_info(&offset, &info);
391
392 ret = winbond_sio_enter(*base);
393 if (ret)
394 return ret;
395
396 winbond_sio_select_logical(*base, info->dev);
397
398 val = winbond_sio_reg_btest(*base, info->datareg, offset);
399 if (winbond_sio_reg_btest(*base, info->invreg, offset))
400 val = !val;
401
402 winbond_sio_leave(*base);
403
404 return val;
405 }
406
winbond_gpio_direction_in(struct gpio_chip * gc,unsigned int offset)407 static int winbond_gpio_direction_in(struct gpio_chip *gc, unsigned int offset)
408 {
409 unsigned long *base = gpiochip_get_data(gc);
410 const struct winbond_gpio_info *info;
411 int ret;
412
413 if (!winbond_gpio_get_info(&offset, &info))
414 return -EACCES;
415
416 ret = winbond_sio_enter(*base);
417 if (ret)
418 return ret;
419
420 winbond_sio_select_logical(*base, info->dev);
421
422 winbond_sio_reg_bset(*base, info->ioreg, offset);
423
424 winbond_sio_leave(*base);
425
426 return 0;
427 }
428
winbond_gpio_direction_out(struct gpio_chip * gc,unsigned int offset,int val)429 static int winbond_gpio_direction_out(struct gpio_chip *gc,
430 unsigned int offset,
431 int val)
432 {
433 unsigned long *base = gpiochip_get_data(gc);
434 const struct winbond_gpio_info *info;
435 int ret;
436
437 if (!winbond_gpio_get_info(&offset, &info))
438 return -EACCES;
439
440 ret = winbond_sio_enter(*base);
441 if (ret)
442 return ret;
443
444 winbond_sio_select_logical(*base, info->dev);
445
446 winbond_sio_reg_bclear(*base, info->ioreg, offset);
447
448 if (winbond_sio_reg_btest(*base, info->invreg, offset))
449 val = !val;
450
451 if (val)
452 winbond_sio_reg_bset(*base, info->datareg, offset);
453 else
454 winbond_sio_reg_bclear(*base, info->datareg, offset);
455
456 winbond_sio_leave(*base);
457
458 return 0;
459 }
460
winbond_gpio_set(struct gpio_chip * gc,unsigned int offset,int val)461 static int winbond_gpio_set(struct gpio_chip *gc, unsigned int offset,
462 int val)
463 {
464 unsigned long *base = gpiochip_get_data(gc);
465 const struct winbond_gpio_info *info;
466 int ret;
467
468 if (!winbond_gpio_get_info(&offset, &info))
469 return -EACCES;
470
471 ret = winbond_sio_enter(*base);
472 if (ret)
473 return ret;
474
475 winbond_sio_select_logical(*base, info->dev);
476
477 if (winbond_sio_reg_btest(*base, info->invreg, offset))
478 val = !val;
479
480 if (val)
481 winbond_sio_reg_bset(*base, info->datareg, offset);
482 else
483 winbond_sio_reg_bclear(*base, info->datareg, offset);
484
485 winbond_sio_leave(*base);
486
487 return 0;
488 }
489
490 static struct gpio_chip winbond_gpio_chip = {
491 .base = -1,
492 .label = WB_GPIO_DRIVER_NAME,
493 .owner = THIS_MODULE,
494 .can_sleep = true,
495 .get = winbond_gpio_get,
496 .direction_input = winbond_gpio_direction_in,
497 .set_rv = winbond_gpio_set,
498 .direction_output = winbond_gpio_direction_out,
499 };
500
winbond_gpio_configure_port0_pins(unsigned long base)501 static void winbond_gpio_configure_port0_pins(unsigned long base)
502 {
503 unsigned int val;
504
505 val = winbond_sio_reg_read(base, WB_SIO_REG_GPIO1_MF);
506 if ((val & WB_SIO_REG_G1MF_FS_MASK) == WB_SIO_REG_G1MF_FS_GPIO1)
507 return;
508
509 pr_warn("GPIO1 pins were connected to something else (%.2x), fixing\n",
510 val);
511
512 val &= ~WB_SIO_REG_G1MF_FS_MASK;
513 val |= WB_SIO_REG_G1MF_FS_GPIO1;
514
515 winbond_sio_reg_write(base, WB_SIO_REG_GPIO1_MF, val);
516 }
517
winbond_gpio_configure_port1_check_i2c(unsigned long base)518 static void winbond_gpio_configure_port1_check_i2c(unsigned long base)
519 {
520 params.i2cgpio = !winbond_sio_reg_btest(base, WB_SIO_REG_I2C_PS,
521 WB_SIO_REG_I2CPS_I2CFS);
522 if (!params.i2cgpio)
523 pr_warn("disabling GPIO2.5 and GPIO2.6 as I2C is enabled\n");
524 }
525
winbond_gpio_configure_port(unsigned long base,unsigned int idx)526 static bool winbond_gpio_configure_port(unsigned long base, unsigned int idx)
527 {
528 const struct winbond_gpio_info *info = &winbond_gpio_infos[idx];
529 const struct winbond_gpio_port_conflict *conflict = &info->conflict;
530
531 /* is there a possible conflicting device defined? */
532 if (conflict->name != NULL) {
533 if (conflict->dev != WB_SIO_DEV_NONE)
534 winbond_sio_select_logical(base, conflict->dev);
535
536 if (winbond_sio_reg_btest(base, conflict->testreg,
537 conflict->testbit)) {
538 if (conflict->warnonly)
539 pr_warn("enabled GPIO%u share pins with active %s\n",
540 idx + 1, conflict->name);
541 else {
542 pr_warn("disabling GPIO%u as %s is enabled\n",
543 idx + 1, conflict->name);
544 return false;
545 }
546 }
547 }
548
549 /* GPIO1 and GPIO2 need some (additional) special handling */
550 if (idx == 0)
551 winbond_gpio_configure_port0_pins(base);
552 else if (idx == 1)
553 winbond_gpio_configure_port1_check_i2c(base);
554
555 winbond_sio_select_logical(base, info->dev);
556
557 winbond_sio_reg_bset(base, info->enablereg, info->enablebit);
558
559 if (params.ppgpios & BIT(idx))
560 winbond_sio_reg_bset(base, info->outputreg,
561 info->outputppbit);
562 else if (params.odgpios & BIT(idx))
563 winbond_sio_reg_bclear(base, info->outputreg,
564 info->outputppbit);
565 else
566 pr_notice("GPIO%u pins are %s\n", idx + 1,
567 winbond_sio_reg_btest(base, info->outputreg,
568 info->outputppbit) ?
569 "push-pull" :
570 "open drain");
571
572 return true;
573 }
574
winbond_gpio_configure(unsigned long base)575 static int winbond_gpio_configure(unsigned long base)
576 {
577 unsigned long i;
578
579 for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG)
580 if (!winbond_gpio_configure_port(base, i))
581 __clear_bit(i, ¶ms.gpios);
582
583 if (!params.gpios) {
584 pr_err("please use 'gpios' module parameter to select some active GPIO ports to enable\n");
585 return -EINVAL;
586 }
587
588 return 0;
589 }
590
winbond_gpio_check_chip(unsigned long base)591 static int winbond_gpio_check_chip(unsigned long base)
592 {
593 int ret;
594 unsigned int chip;
595
596 ret = winbond_sio_enter(base);
597 if (ret)
598 return ret;
599
600 chip = winbond_sio_reg_read(base, WB_SIO_REG_CHIP_MSB) << 8;
601 chip |= winbond_sio_reg_read(base, WB_SIO_REG_CHIP_LSB);
602
603 pr_notice("chip ID at %lx is %.4x\n", base, chip);
604
605 if ((chip & WB_SIO_CHIP_ID_W83627UHG_MASK) !=
606 WB_SIO_CHIP_ID_W83627UHG) {
607 pr_err("not an our chip\n");
608 ret = -ENODEV;
609 }
610
611 winbond_sio_leave(base);
612
613 return ret;
614 }
615
winbond_gpio_imatch(struct device * dev,unsigned int id)616 static int winbond_gpio_imatch(struct device *dev, unsigned int id)
617 {
618 unsigned long gpios_rem;
619 int ret;
620
621 gpios_rem = params.gpios & ~GENMASK(ARRAY_SIZE(winbond_gpio_infos) - 1,
622 0);
623 if (gpios_rem) {
624 pr_warn("unknown ports (%lx) enabled in GPIO ports bitmask\n",
625 gpios_rem);
626 params.gpios &= ~gpios_rem;
627 }
628
629 if (params.ppgpios & params.odgpios) {
630 pr_err("some GPIO ports are set both to push-pull and open drain mode at the same time\n");
631 return 0;
632 }
633
634 if (params.base != 0)
635 return winbond_gpio_check_chip(params.base) == 0;
636
637 /*
638 * if the 'base' module parameter is unset probe two chip default
639 * I/O port bases
640 */
641 params.base = WB_SIO_BASE;
642 ret = winbond_gpio_check_chip(params.base);
643 if (ret == 0)
644 return 1;
645 if (ret != -ENODEV && ret != -EBUSY)
646 return 0;
647
648 params.base = WB_SIO_BASE_HIGH;
649 return winbond_gpio_check_chip(params.base) == 0;
650 }
651
winbond_gpio_iprobe(struct device * dev,unsigned int id)652 static int winbond_gpio_iprobe(struct device *dev, unsigned int id)
653 {
654 int ret;
655
656 if (params.base == 0)
657 return -EINVAL;
658
659 ret = winbond_sio_enter(params.base);
660 if (ret)
661 return ret;
662
663 ret = winbond_gpio_configure(params.base);
664
665 winbond_sio_leave(params.base);
666
667 if (ret)
668 return ret;
669
670 /*
671 * Add 8 gpios for every GPIO port that was enabled in gpios
672 * module parameter (that wasn't disabled earlier in
673 * winbond_gpio_configure() & co. due to, for example, a pin conflict).
674 */
675 winbond_gpio_chip.ngpio = hweight_long(params.gpios) * 8;
676
677 /*
678 * GPIO6 port has only 5 pins, so if it is enabled we have to adjust
679 * the total count appropriately
680 */
681 if (params.gpios & BIT(5))
682 winbond_gpio_chip.ngpio -= (8 - 5);
683
684 winbond_gpio_chip.parent = dev;
685
686 return devm_gpiochip_add_data(dev, &winbond_gpio_chip, ¶ms.base);
687 }
688
689 static struct isa_driver winbond_gpio_idriver = {
690 .driver = {
691 .name = WB_GPIO_DRIVER_NAME,
692 },
693 .match = winbond_gpio_imatch,
694 .probe = winbond_gpio_iprobe,
695 };
696
697 module_isa_driver(winbond_gpio_idriver, 1);
698
699 module_param_named(base, params.base, ulong, 0444);
700 MODULE_PARM_DESC(base,
701 "I/O port base (when unset - probe chip default ones)");
702
703 /* This parameter sets which GPIO devices (ports) we enable */
704 module_param_named(gpios, params.gpios, ulong, 0444);
705 MODULE_PARM_DESC(gpios,
706 "bitmask of GPIO ports to enable (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
707
708 /*
709 * These two parameters below set how we configure GPIO ports output drivers.
710 * It can't be a one bitmask since we need three values per port: push-pull,
711 * open-drain and keep as-is (this is the default).
712 */
713 module_param_named(ppgpios, params.ppgpios, ulong, 0444);
714 MODULE_PARM_DESC(ppgpios,
715 "bitmask of GPIO ports to set to push-pull mode (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
716
717 module_param_named(odgpios, params.odgpios, ulong, 0444);
718 MODULE_PARM_DESC(odgpios,
719 "bitmask of GPIO ports to set to open drain mode (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
720
721 /*
722 * GPIO2.0 and GPIO2.1 control a basic PC functionality that we
723 * don't allow tinkering with by default (it is very likely that the
724 * firmware owns these pins).
725 * These two parameters below allow overriding these prohibitions.
726 */
727 module_param_named(pledgpio, params.pledgpio, bool, 0644);
728 MODULE_PARM_DESC(pledgpio,
729 "enable changing value of GPIO2.0 bit (Power LED), default no.");
730
731 module_param_named(beepgpio, params.beepgpio, bool, 0644);
732 MODULE_PARM_DESC(beepgpio,
733 "enable changing value of GPIO2.1 bit (BEEP), default no.");
734
735 MODULE_AUTHOR("Maciej S. Szmigiero <mail@maciej.szmigiero.name>");
736 MODULE_DESCRIPTION("GPIO interface for Winbond Super I/O chips");
737 MODULE_LICENSE("GPL");
738