| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRegMatrix.cpp | 104 void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) { in assign()
121 void LiveRegMatrix::unassign(const LiveInterval &VirtReg) { in unassign()
146 bool LiveRegMatrix::checkRegMaskInterference(const LiveInterval &VirtReg, in checkRegMaskInterference()
164 bool LiveRegMatrix::checkRegUnitInterference(const LiveInterval &VirtReg, in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(const LiveInterval &VirtReg, in checkInterference()
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| H A D | RegAllocFast.cpp | 202 Register VirtReg; ///< Virtual register number. member
351 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg()
464 int RegAllocFastImpl::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor()
492 bool RegAllocFastImpl::mayLiveOut(Register VirtReg) { in mayLiveOut()
545 bool RegAllocFastImpl::mayLiveIn(Register VirtReg) { in mayLiveIn()
565 Register VirtReg, MCPhysReg AssignedReg, bool Kill, in spill()
626 Register VirtReg, MCPhysReg PhysReg) { in reload()
730 switch (unsigned VirtReg = RegUnitStates[Unit]) { in displacePhysReg() local
759 switch (unsigned VirtReg = RegUnitStates[FirstUnit]) { in freePhysReg() local
784 switch (unsigned VirtReg = RegUnitStates[Unit]) { in calcSpillCost() local
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| H A D | RegAllocGreedy.cpp | 234 bool RAGreedy::LRE_CanEraseVirtReg(Register VirtReg) { in LRE_CanEraseVirtReg()
249 void RAGreedy::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg()
397 MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg, in tryAssign()
455 bool RegAllocEvictionAdvisor::canReassign(const LiveInterval &VirtReg, in canReassign()
481 void RAGreedy::evictInterference(const LiveInterval &VirtReg, in evictInterference()
531 RegAllocEvictionAdvisor::getOrderLimit(const LiveInterval &VirtReg, in getOrderLimit()
577 MCRegister RAGreedy::tryEvict(const LiveInterval &VirtReg, in tryEvict()
1060 MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg, in tryRegionSplit()
1171 unsigned RAGreedy::calculateRegionSplitCost(const LiveInterval &VirtReg, in calculateRegionSplitCost()
1189 unsigned RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand, in doRegionSplit()
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| H A D | RegAllocBasic.cpp | 161 void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg()
206 bool RABasic::spillInterferences(const LiveInterval &VirtReg, in spillInterferences()
255 MCRegister RABasic::selectOrSplit(const LiveInterval &VirtReg, in selectOrSplit()
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| H A D | RegAllocEvictionAdvisor.cpp | 169 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference()
187 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in canEvictInterferenceBasedOnCost()
277 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
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| H A D | LiveIntervalUnion.cpp | 29 unify(const LiveInterval & VirtReg,const LiveRange & Range) unify() argument
57 extract(const LiveInterval & VirtReg,const LiveRange & Range) extract() argument
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| H A D | AllocationOrder.cpp | 29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create()
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| H A D | RegisterCoalescer.h | 64 CoalescerPair(Register VirtReg, MCRegister PhysReg, in CoalescerPair()
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| H A D | RegAllocBase.cpp | 89 while (const LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
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| H A D | VirtRegMap.cpp | 342 Register VirtReg = Register::index2VirtReg(Idx); in addMBBLiveIns() local
552 Register VirtReg = MO.getReg(); in rewrite() local
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| H A D | MLRegallocEvictAdvisor.cpp | |
| H A D | MLRegAllocEvictAdvisor.cpp | 336 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference()
600 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in loadInterferenceFeatures()
667 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
1088 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition()
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| H A D | RegAllocGreedy.h | 86 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
95 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
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| H A D | PHIElimination.cpp | 218 Register VirtReg = Register::index2VirtReg(Index); in run() local
315 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined()
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| H A D | LiveDebugVariables.cpp | 788 void LDVImpl::mapVirtReg(Register VirtReg, UserValue *EC) { in mapVirtReg()
794 UserValue *LDVImpl::lookupVirtReg(Register VirtReg) { in lookupVirtReg()
1531 Register VirtReg = Loc.getReg(); in rewriteLocations() local
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| H A D | MachineBasicBlock.cpp | 659 Register VirtReg = I->getOperand(0).getReg(); in addLiveIn() local
666 Register VirtReg = MRI.createVirtualRegister(RC); in addLiveIn() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastPreTileConfig.cpp | 118 int X86FastPreTileConfig::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor()
139 bool X86FastPreTileConfig::mayLiveOut(Register VirtReg, MachineInstr *CfgMI) { in mayLiveOut()
202 Register VirtReg, bool Kill) { in spill()
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| H A D | X86TileConfig.cpp | 126 Register VirtReg = Register::index2VirtReg(I); in INITIALIZE_PASS_DEPENDENCY() local
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| H A D | X86RegisterInfo.cpp | 1035 static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, in getTileShape()
1073 bool X86RegisterInfo::getRegAllocationHints(Register VirtReg, in getRegAllocationHints()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 125 const Register VirtReg = MO.getReg(); in rewriteRegs() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | VirtRegMap.h | 169 Register getOriginal(Register VirtReg) const { in getOriginal()
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| H A D | ScheduleDAGInstrs.h | 53 unsigned VirtReg; member
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| H A D | RegisterPressure.h | 536 bool hasUntiedDef(Register VirtReg) const { in hasUntiedDef()
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| H A D | TargetRegisterInfo.h | 1139 const LiveInterval &VirtReg) const { in shouldUseLastChanceRecoloringForVirtReg()
1154 const LiveInterval &VirtReg) const { in shouldUseDeferredSpillingForVirtReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
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