1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _MACHINE_HYPERVISOR_H_ 31 #define _MACHINE_HYPERVISOR_H_ 32 33 #include <machine/_armreg.h> 34 35 /* 36 * These registers are only useful when in hypervisor context, 37 * e.g. specific to EL2, or controlling the hypervisor. 38 */ 39 40 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 41 /* Valid if HCR_EL2.E2H == 0 */ 42 #define CNTHCTL_EL1PCTEN_SHIFT 0 43 #define CNTHCTL_EL1PCTEN_MASK (0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 44 #define CNTHCTL_EL1PCTEN_TRAP (0x0ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 45 #define CNTHCTL_EL1PCTEN_NOTRAP (0x1ul << CNTHCTL_EL1PCTEN_SHIFT) 46 #define CNTHCTL_EL1PCEN_SHIFT 1 47 #define CNTHCTL_EL1PCEN_MASK (0x1ul << CNTHCTL_EL1PCEN_SHIFT) 48 #define CNTHCTL_EL1PCEN_TRAP (0x0ul << CNTHCTL_EL1PCEN_SHIFT) 49 #define CNTHCTL_EL1PCEN_NOTRAP (0x1ul << CNTHCTL_EL1PCEN_SHIFT) 50 /* Valid if HCR_EL2.E2H == 1 */ 51 #define CNTHCTL_E2H_EL0PCTEN_SHIFT 0 52 #define CNTHCTL_E2H_EL0PCTEN_MASK (0x1ul << CNTHCTL_E2H_EL0PCTEN_SHIFT) 53 #define CNTHCTL_E2H_EL0PCTEN_TRAP (0x0ul << CNTHCTL_E2H_EL0PCTEN_SHIFT) 54 #define CNTHCTL_E2H_EL0PCTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL0PCTEN_SHIFT) 55 #define CNTHCTL_E2H_EL0VCTEN_SHIFT 1 56 #define CNTHCTL_E2H_EL0VCTEN_MASK (0x1ul << CNTHCTL_E2H_EL0VCTEN_SHIFT) 57 #define CNTHCTL_E2H_EL0VCTEN_TRAP (0x0ul << CNTHCTL_E2H_EL0VCTEN_SHIFT) 58 #define CNTHCTL_E2H_EL0VCTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL0VCTEN_SHIFT) 59 #define CNTHCTL_E2H_EL0VTEN_SHIFT 8 60 #define CNTHCTL_E2H_EL0VTEN_MASK (0x1ul << CNTHCTL_E2H_EL0VTEN_SHIFT) 61 #define CNTHCTL_E2H_EL0VTEN_TRAP (0x0ul << CNTHCTL_E2H_EL0VTEN_SHIFT) 62 #define CNTHCTL_E2H_EL0VTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL0VTEN_SHIFT) 63 #define CNTHCTL_E2H_EL0PTEN_SHIFT 9 64 #define CNTHCTL_E2H_EL0PTEN_MASK (0x1ul << CNTHCTL_E2H_EL0PTEN_SHIFT) 65 #define CNTHCTL_E2H_EL0PTEN_TRAP (0x0ul << CNTHCTL_E2H_EL0PTEN_SHIFT) 66 #define CNTHCTL_E2H_EL0PTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL0PTEN_SHIFT) 67 #define CNTHCTL_E2H_EL1PCTEN_SHIFT 10 68 #define CNTHCTL_E2H_EL1PCTEN_MASK (0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 69 #define CNTHCTL_E2H_EL1PCTEN_TRAP (0x0ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 70 #define CNTHCTL_E2H_EL1PCTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT) 71 #define CNTHCTL_E2H_EL1PTEN_SHIFT 11 72 #define CNTHCTL_E2H_EL1PTEN_MASK (0x1ul << CNTHCTL_E2H_EL1PTEN_SHIFT) 73 #define CNTHCTL_E2H_EL1PTEN_TRAP (0x0ul << CNTHCTL_E2H_EL1PTEN_SHIFT) 74 #define CNTHCTL_E2H_EL1PTEN_NOTRAP (0x1ul << CNTHCTL_E2H_EL1PTEN_SHIFT) 75 /* Unconditionally valid */ 76 #define CNTHCTL_EVNTEN_SHIFT 2 77 #define CNTHCTL_EVNTEN_MASK (0x1ul << CNTHCTL_EVNTEN_SHIFT) 78 #define CNTHCTL_EVNTEN_DIS (0x0ul << CNTHCTL_EVNTEN_SHIFT) 79 #define CNTHCTL_EVNTEN_EN (0x1ul << CNTHCTL_EVNTEN_SHIFT) 80 #define CNTHCTL_EVNTDIR_SHIFT 3 81 #define CNTHCTL_EVNTDIR_MASK (0x1ul << CNTHCTL_EVNTDIR_SHIFT) 82 #define CNTHCTL_EVNTDIR_HIGH (0x0ul << CNTHCTL_EVNTDIR_SHIFT) 83 #define CNTHCTL_EVNTDIR_LOW (0x1ul << CNTHCTL_EVNTDIR_SHIFT) 84 #define CNTHCTL_EVNTI_SHIFT 4 85 #define CNTHCTL_EVNTI_MASK (0xful << CNTHCTL_EVNTI_SHIFT) 86 #define CNTHCTL_ECV_SHIFT 12 87 #define CNTHCTL_ECV_MASK (0x1ul << CNTHCTL_ECV_SHIFT) 88 #define CNTHCTL_ECV_DIS (0x0ul << CNTHCTL_ECV_SHIFT) 89 #define CNTHCTL_ECV_EN (0x1ul << CNTHCTL_ECV_SHIFT) 90 #define CNTHCTL_EL1TVT_SHIFT 13 91 #define CNTHCTL_EL1TVT_MASK (0x1ul << CNTHCTL_EL1TVT_SHIFT) 92 #define CNTHCTL_EL1TVT_NOTRAP (0x0ul << CNTHCTL_EL1TVT_SHIFT) 93 #define CNTHCTL_EL1TVT_TRAP (0x1ul << CNTHCTL_EL1TVT_SHIFT) 94 #define CNTHCTL_EL1TVCT_SHIFT 14 95 #define CNTHCTL_EL1TVCT_MASK (0x1ul << CNTHCTL_EL1TVCT_SHIFT) 96 #define CNTHCTL_EL1TVCT_NOTRAP (0x0ul << CNTHCTL_EL1TVCT_SHIFT) 97 #define CNTHCTL_EL1TVCT_TRAP (0x1ul << CNTHCTL_EL1TVCT_SHIFT) 98 #define CNTHCTL_EL1NVPCT_SHIFT 15 99 #define CNTHCTL_EL1NVPCT_MASK (0x1ul << CNTHCTL_EL1NVPCT_SHIFT) 100 #define CNTHCTL_EL1NVPCT_NOTRAP (0x0ul << CNTHCTL_EL1NVPCT_SHIFT) 101 #define CNTHCTL_EL1NVPCT_TRAP (0x1ul << CNTHCTL_EL1NVPCT_SHIFT) 102 #define CNTHCTL_EL1NVVCT_SHIFT 16 103 #define CNTHCTL_EL1NVVCT_MASK (0x1ul << CNTHCTL_EL1NVVCT_SHIFT) 104 #define CNTHCTL_EL1NVVCT_NOTRAP (0x0ul << CNTHCTL_EL1NVVCT_SHIFT) 105 #define CNTHCTL_EL1NVVCT_TRAP (0x1ul << CNTHCTL_EL1NVVCT_SHIFT) 106 #define CNTHCTL_EVNTIS_SHIFT 17 107 #define CNTHCTL_EVNTIS_MASK (0x1ul << CNTHCTL_EVNTIS_SHIFT) 108 #define CNTHCTL_CNTVMASK_SHIFT 18 109 #define CNTHCTL_CNTVMASK_MASK (0x1ul << CNTHCTL_CNTVMASK_SHIFT) 110 #define CNTHCTL_CNTPMASK_SHIFT 19 111 #define CNTHCTL_CNTPMASK_MASK (0x1ul << CNTHCTL_CNTPMASK_SHIFT) 112 113 /* CNTPOFF_EL2 - Counter-timer Physical Offset Register */ 114 #define CNTPOFF_EL2_REG MRS_REG_ALT_NAME(CNTPOFF_EL2) 115 #define CNTPOFF_EL2_op0 3 116 #define CNTPOFF_EL2_op1 4 117 #define CNTPOFF_EL2_CRn 14 118 #define CNTPOFF_EL2_CRm 0 119 #define CNTPOFF_EL2_op2 6 120 121 /* CPTR_EL2 - Architecture feature trap register */ 122 /* Valid if HCR_EL2.E2H == 0 */ 123 #define CPTR_TRAP_ALL 0xc01037ff /* Enable all traps */ 124 #define CPTR_RES0 0x7fefc800 125 #define CPTR_RES1 0x000032ff 126 #define CPTR_TZ 0x00000100 127 #define CPTR_TFP 0x00000400 128 #define CPTR_TTA 0x00100000 129 /* Valid if HCR_EL2.E2H == 1 */ 130 #define CPTR_E2H_TRAP_ALL 0xd0000000 131 #define CPTR_E2H_ZPEN 0x00030000 132 #define CPTR_E2H_FPEN 0x00300000 133 #define CPTR_E2H_TTA 0x10000000 134 /* Unconditionally valid */ 135 #define CPTR_TCPAC 0x80000000 136 137 /* HCR_EL2 - Hypervisor Config Register */ 138 #define HCR_VM (UL(0x1) << 0) 139 #define HCR_SWIO (UL(0x1) << 1) 140 #define HCR_PTW (UL(0x1) << 2) 141 #define HCR_FMO (UL(0x1) << 3) 142 #define HCR_IMO (UL(0x1) << 4) 143 #define HCR_AMO (UL(0x1) << 5) 144 #define HCR_VF (UL(0x1) << 6) 145 #define HCR_VI (UL(0x1) << 7) 146 #define HCR_VSE (UL(0x1) << 8) 147 #define HCR_FB (UL(0x1) << 9) 148 #define HCR_BSU_MASK (UL(0x3) << 10) 149 #define HCR_BSU_IS (UL(0x1) << 10) 150 #define HCR_BSU_OS (UL(0x2) << 10) 151 #define HCR_BSU_FS (UL(0x3) << 10) 152 #define HCR_DC (UL(0x1) << 12) 153 #define HCR_TWI (UL(0x1) << 13) 154 #define HCR_TWE (UL(0x1) << 14) 155 #define HCR_TID0 (UL(0x1) << 15) 156 #define HCR_TID1 (UL(0x1) << 16) 157 #define HCR_TID2 (UL(0x1) << 17) 158 #define HCR_TID3 (UL(0x1) << 18) 159 #define HCR_TSC (UL(0x1) << 19) 160 #define HCR_TIDCP (UL(0x1) << 20) 161 #define HCR_TACR (UL(0x1) << 21) 162 #define HCR_TSW (UL(0x1) << 22) 163 #define HCR_TPCP (UL(0x1) << 23) 164 #define HCR_TPU (UL(0x1) << 24) 165 #define HCR_TTLB (UL(0x1) << 25) 166 #define HCR_TVM (UL(0x1) << 26) 167 #define HCR_TGE (UL(0x1) << 27) 168 #define HCR_TDZ (UL(0x1) << 28) 169 #define HCR_HCD (UL(0x1) << 29) 170 #define HCR_TRVM (UL(0x1) << 30) 171 #define HCR_RW (UL(0x1) << 31) 172 #define HCR_CD (UL(0x1) << 32) 173 #define HCR_ID (UL(0x1) << 33) 174 #define HCR_E2H (UL(0x1) << 34) 175 #define HCR_TLOR (UL(0x1) << 35) 176 #define HCR_TERR (UL(0x1) << 36) 177 #define HCR_TEA (UL(0x1) << 37) 178 #define HCR_MIOCNCE (UL(0x1) << 38) 179 /* Bit 39 is reserved */ 180 #define HCR_APK (UL(0x1) << 40) 181 #define HCR_API (UL(0x1) << 41) 182 #define HCR_NV (UL(0x1) << 42) 183 #define HCR_NV1 (UL(0x1) << 43) 184 #define HCR_AT (UL(0x1) << 44) 185 #define HCR_NV2 (UL(0x1) << 45) 186 #define HCR_FWB (UL(0x1) << 46) 187 #define HCR_FIEN (UL(0x1) << 47) 188 /* Bit 48 is reserved */ 189 #define HCR_TID4 (UL(0x1) << 49) 190 #define HCR_TICAB (UL(0x1) << 50) 191 #define HCR_AMVOFFEN (UL(0x1) << 51) 192 #define HCR_TOCU (UL(0x1) << 52) 193 #define HCR_EnSCXT (UL(0x1) << 53) 194 #define HCR_TTLBIS (UL(0x1) << 54) 195 #define HCR_TTLBOS (UL(0x1) << 55) 196 #define HCR_ATA (UL(0x1) << 56) 197 #define HCR_DCT (UL(0x1) << 57) 198 #define HCR_TID5 (UL(0x1) << 58) 199 #define HCR_TWEDEn (UL(0x1) << 59) 200 #define HCR_TWEDEL_MASK (UL(0xf) << 60) 201 202 /* HCRX_EL2 - Extended Hypervisor Configuration Register */ 203 #define HCRX_EL2_REG MRS_REG_ALT_NAME(HCRX_EL2) 204 #define HCRX_EL2_op0 3 205 #define HCRX_EL2_op1 4 206 #define HCRX_EL2_CRn 1 207 #define HCRX_EL2_CRm 2 208 #define HCRX_EL2_op2 2 209 210 #define HCRX_EnAS0 (UL(0x1) << 0) 211 #define HCRX_EnALS (UL(0x1) << 1) 212 #define HCRX_EnASR (UL(0x1) << 2) 213 #define HCRX_FnXS (UL(0x1) << 3) 214 #define HCRX_FGTnXS (UL(0x1) << 4) 215 #define HCRX_SMPME (UL(0x1) << 5) 216 #define HCRX_TALLINT (UL(0x1) << 6) 217 #define HCRX_VINMI (UL(0x1) << 7) 218 #define HCRX_VFNMI (UL(0x1) << 8) 219 #define HCRX_CMOW (UL(0x1) << 9) 220 #define HCRX_MCE2 (UL(0x1) << 10) 221 #define HCRX_MSCEn (UL(0x1) << 11) 222 /* Bits 12 & 13 are reserved */ 223 #define HCRX_TCR2En (UL(0x1) << 14) 224 #define HCRX_SCTLR2En (UL(0x1) << 15) 225 #define HCRX_PTTWI (UL(0x1) << 16) 226 #define HCRX_D128En (UL(0x1) << 17) 227 #define HCRX_EnSNERR (UL(0x1) << 18) 228 #define HCRX_TMEA (UL(0x1) << 19) 229 #define HCRX_EnSDERR (UL(0x1) << 20) 230 #define HCRX_EnIDCP128 (UL(0x1) << 21) 231 #define HCRX_GCSEn (UL(0x1) << 22) 232 #define HCRX_EnFPM (UL(0x1) << 23) 233 #define HCRX_PACMEn (UL(0x1) << 24) 234 /* Bit 25 is reserved */ 235 #define HCRX_SRMASKEn (UL(0x1) << 26) 236 237 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ 238 #define HPFAR_EL2_FIPA_SHIFT 4 239 #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 240 #define HPFAR_EL2_FIPA_GET(x) \ 241 (((x) & HPFAR_EL2_FIPA_MASK) >> HPFAR_EL2_FIPA_SHIFT) 242 /* HPFAR_EL2_FIPA holds the 4k page address */ 243 #define HPFAR_EL2_FIPA_ADDR(x) \ 244 (HPFAR_EL2_FIPA_GET(x) << 12) 245 /* The bits from FAR_EL2 we need to add to HPFAR_EL2_FIPA_ADDR */ 246 #define FAR_EL2_HPFAR_PAGE_MASK (0xffful) 247 248 /* ICC_SRE_EL2 */ 249 #define ICC_SRE_EL2_SRE (1UL << 0) 250 #define ICC_SRE_EL2_EN (1UL << 3) 251 252 /* MDCR_EL2 - Hyp Debug Control Register */ 253 #define MDCR_EL2_HPMN_MASK 0x1f 254 #define MDCR_EL2_HPMN_SHIFT 0 255 #define MDCR_EL2_TPMCR_SHIFT 5 256 #define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT) 257 #define MDCR_EL2_TPM_SHIFT 6 258 #define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT) 259 #define MDCR_EL2_HPME_SHIFT 7 260 #define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT) 261 #define MDCR_EL2_TDE_SHIFT 8 262 #define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT) 263 #define MDCR_EL2_TDA_SHIFT 9 264 #define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT) 265 #define MDCR_EL2_TDOSA_SHIFT 10 266 #define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) 267 #define MDCR_EL2_TDRA_SHIFT 11 268 #define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) 269 #define MDCR_EL2_E2PB_SHIFT 12 270 #define MDCR_EL2_E2PB_MASK (0x3UL << MDCR_EL2_E2PB_SHIFT) 271 #define MDCR_EL2_TPMS_SHIFT 14 272 #define MDCR_EL2_TPMS (0x1UL << MDCR_EL2_TPMS_SHIFT) 273 #define MDCR_EL2_EnSPM_SHIFT 15 274 #define MDCR_EL2_EnSPM (0x1UL << MDCR_EL2_EnSPM_SHIFT) 275 #define MDCR_EL2_HPMD_SHIFT 17 276 #define MDCR_EL2_HPMD (0x1UL << MDCR_EL2_HPMD_SHIFT) 277 #define MDCR_EL2_TTRF_SHIFT 19 278 #define MDCR_EL2_TTRF (0x1UL << MDCR_EL2_TTRF_SHIFT) 279 #define MDCR_EL2_HCCD_SHIFT 23 280 #define MDCR_EL2_HCCD (0x1UL << MDCR_EL2_HCCD_SHIFT) 281 #define MDCR_EL2_E2TB_SHIFT 24 282 #define MDCR_EL2_E2TB_MASK (0x3UL << MDCR_EL2_E2TB_SHIFT) 283 #define MDCR_EL2_HLP_SHIFT 26 284 #define MDCR_EL2_HLP (0x1UL << MDCR_EL2_HLP_SHIFT) 285 #define MDCR_EL2_TDCC_SHIFT 27 286 #define MDCR_EL2_TDCC (0x1UL << MDCR_EL2_TDCC_SHIFT) 287 #define MDCR_EL2_MTPME_SHIFT 28 288 #define MDCR_EL2_MTPME (0x1UL << MDCR_EL2_MTPME_SHIFT) 289 #define MDCR_EL2_HPMFZO_SHIFT 29 290 #define MDCR_EL2_HPMFZO (0x1UL << MDCR_EL2_HPMFZO_SHIFT) 291 #define MDCR_EL2_PMSSE_SHIFT 30 292 #define MDCR_EL2_PMSSE_MASK (0x3UL << MDCR_EL2_PMSSE_SHIFT) 293 #define MDCR_EL2_HPMFZS_SHIFT 36 294 #define MDCR_EL2_HPMFZS (0x1UL << MDCR_EL2_HPMFZS_SHIFT) 295 #define MDCR_EL2_PMEE_SHIFT 40 296 #define MDCR_EL2_PMEE_MASK (0x3UL << MDCR_EL2_PMEE_SHIFT) 297 #define MDCR_EL2_EBWE_SHIFT 43 298 #define MDCR_EL2_EBWE (0x1UL << MDCR_EL2_EBWE_SHIFT) 299 300 /* SCTLR_EL2 - System Control Register */ 301 #define SCTLR_EL2_RES1 0x30c50830 302 #define SCTLR_EL2_M_SHIFT 0 303 #define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT) 304 #define SCTLR_EL2_A_SHIFT 1 305 #define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT) 306 #define SCTLR_EL2_C_SHIFT 2 307 #define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT) 308 #define SCTLR_EL2_SA_SHIFT 3 309 #define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT) 310 #define SCTLR_EL2_EOS_SHIFT 11 311 #define SCTLR_EL2_EOS (0x1UL << SCTLR_EL2_EOS_SHIFT) 312 #define SCTLR_EL2_I_SHIFT 12 313 #define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT) 314 #define SCTLR_EL2_WXN_SHIFT 19 315 #define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT) 316 #define SCTLR_EL2_EIS_SHIFT 22 317 #define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT) 318 #define SCTLR_EL2_EE_SHIFT 25 319 #define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) 320 321 /* TCR_EL2 - Translation Control Register */ 322 #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) 323 #define TCR_EL2_T0SZ_SHIFT 0 324 #define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT) 325 #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) 326 /* Bits 7:6 are reserved */ 327 #define TCR_EL2_IRGN0_SHIFT 8 328 #define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT) 329 #define TCR_EL2_IRGN0_WBWA (1UL << TCR_EL2_IRGN0_SHIFT) 330 #define TCR_EL2_ORGN0_SHIFT 10 331 #define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT) 332 #define TCR_EL2_ORGN0_WBWA (1UL << TCR_EL2_ORGN0_SHIFT) 333 #define TCR_EL2_SH0_SHIFT 12 334 #define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT) 335 #define TCR_EL2_SH0_IS (3UL << TCR_EL2_SH0_SHIFT) 336 #define TCR_EL2_TG0_SHIFT 14 337 #define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT) 338 #define TCR_EL2_TG0_4K (0x0UL << TCR_EL2_TG0_SHIFT) 339 #define TCR_EL2_TG0_64K (0x1UL << TCR_EL2_TG0_SHIFT) 340 #define TCR_EL2_TG0_16K (0x2UL << TCR_EL2_TG0_SHIFT) 341 #define TCR_EL2_PS_SHIFT 16 342 #define TCR_EL2_PS_MASK (0xfUL << TCR_EL2_PS_SHIFT) 343 #define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT) 344 #define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT) 345 #define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT) 346 #define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT) 347 #define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT) 348 #define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT) 349 #define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT) 350 #define TCR_EL2_HPD_SHIFT 24 351 #define TCR_EL2_HPD (1UL << TCR_EL2_HPD_SHIFT) 352 #define TCR_EL2_HWU59_SHIFT 25 353 #define TCR_EL2_HWU59 (1UL << TCR_EL2_HWU59_SHIFT) 354 #define TCR_EL2_HWU60_SHIFT 26 355 #define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT) 356 #define TCR_EL2_HWU61_SHIFT 27 357 #define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT) 358 #define TCR_EL2_HWU62_SHIFT 28 359 #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT) 360 #define TCR_EL2_HWU \ 361 (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62) 362 363 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ 364 #define VMPIDR_EL2_U 0x0000000040000000 365 #define VMPIDR_EL2_MT 0x0000000001000000 366 #define VMPIDR_EL2_RES1 0x0000000080000000 367 368 /* VTCR_EL2 - Virtualization Translation Control Register */ 369 #define VTCR_EL2_RES1 (0x1UL << 31) 370 #define VTCR_EL2_T0SZ_SHIFT 0 371 #define VTCR_EL2_T0SZ_MASK (0x3fUL << VTCR_EL2_T0SZ_SHIFT) 372 #define VTCR_EL2_T0SZ(x) ((x) << VTCR_EL2_T0SZ_SHIFT) 373 #define VTCR_EL2_SL0_SHIFT 6 374 #define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT) 375 #define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT) 376 #define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT) 377 #define VTCR_EL2_SL0_16K_LVL2 (0x1UL << VTCR_EL2_SL0_SHIFT) 378 #define VTCR_EL2_SL0_16K_LVL1 (0x2UL << VTCR_EL2_SL0_SHIFT) 379 #define VTCR_EL2_SL0_16K_LVL0 (0x3UL << VTCR_EL2_SL0_SHIFT) 380 #define VTCR_EL2_IRGN0_SHIFT 8 381 #define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT) 382 #define VTCR_EL2_ORGN0_SHIFT 10 383 #define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT) 384 #define VTCR_EL2_SH0_SHIFT 12 385 #define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT) 386 #define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT) 387 #define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT) 388 #define VTCR_EL2_TG0_SHIFT 14 389 #define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT) 390 #define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT) 391 #define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT) 392 #define VTCR_EL2_PS_SHIFT 16 393 #define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT) 394 #define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT) 395 #define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT) 396 #define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT) 397 #define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT) 398 #define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT) 399 #define VTCR_EL2_PS_52BIT (0x6UL << VTCR_EL2_PS_SHIFT) 400 #define VTCR_EL2_DS_SHIFT 32 401 #define VTCR_EL2_DS (0x1UL << VTCR_EL2_DS_SHIFT) 402 403 /* VTTBR_EL2 - Virtualization Translation Table Base Register */ 404 #define VTTBR_VMID_MASK 0xffff000000000000 405 #define VTTBR_VMID_SHIFT 48 406 /* Assumed to be 0 by locore.S */ 407 #define VTTBR_HOST 0x0000000000000000 408 409 #endif /* !_MACHINE_HYPERVISOR_H_ */ 410