1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Thunderbolt driver - NHI registers 4 * 5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 6 * Copyright (C) 2018, Intel Corporation 7 */ 8 9 #ifndef NHI_REGS_H_ 10 #define NHI_REGS_H_ 11 12 #include <linux/types.h> 13 14 enum ring_flags { 15 RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */ 16 RING_FLAG_E2E_FLOW_CONTROL = 1 << 28, 17 RING_FLAG_PCI_NO_SNOOP = 1 << 29, 18 RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */ 19 RING_FLAG_ENABLE = 1 << 31, 20 }; 21 22 /** 23 * struct ring_desc - TX/RX ring entry 24 * @phys: DMA mapped address of the frame 25 * @length: Size of the ring 26 * @eof: End of frame protocol defined field 27 * @sof: Start of frame protocol defined field 28 * @flags: Ring descriptor flags 29 * @time: Fill with zero 30 * 31 * For TX set length/eof/sof. 32 * For RX length/eof/sof are set by the NHI. 33 */ 34 struct ring_desc { 35 u64 phys; 36 u32 length:12; 37 u32 eof:4; 38 u32 sof:4; 39 enum ring_desc_flags flags:12; 40 u32 time; /* write zero */ 41 } __packed; 42 43 /* NHI registers in bar 0 */ 44 45 /* 46 * 16 bytes per entry, one entry for every hop (REG_CAPS) 47 * 00: physical pointer to an array of struct ring_desc 48 * 08: ring tail (set by NHI) 49 * 10: ring head (index of first non posted descriptor) 50 * 12: descriptor count 51 */ 52 #define REG_TX_RING_BASE 0x00000 53 54 /* 55 * 16 bytes per entry, one entry for every hop (REG_CAPS) 56 * 00: physical pointer to an array of struct ring_desc 57 * 08: ring head (index of first not posted descriptor) 58 * 10: ring tail (set by NHI) 59 * 12: descriptor count 60 * 14: max frame sizes (anything larger than 0x100 has no effect) 61 */ 62 #define REG_RX_RING_BASE 0x08000 63 64 /* 65 * 32 bytes per entry, one entry for every hop (REG_CAPS) 66 * 00: enum_ring_flags 67 * 04: isoch time stamp ?? (write 0) 68 * ..: unknown 69 */ 70 #define REG_TX_OPTIONS_BASE 0x19800 71 72 /* 73 * 32 bytes per entry, one entry for every hop (REG_CAPS) 74 * 00: enum ring_flags 75 * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to 76 * the corresponding TX hop id. 77 * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings) 78 * ..: unknown 79 */ 80 #define REG_RX_OPTIONS_BASE 0x29800 81 #define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12) 82 #define REG_RX_OPTIONS_E2E_HOP_SHIFT 12 83 84 /* 85 * three bitfields: tx, rx, rx overflow 86 * Every bitfield contains one bit for every hop (REG_CAPS). 87 * New interrupts are fired only after ALL registers have been 88 * read (even those containing only disabled rings). 89 */ 90 #define REG_RING_NOTIFY_BASE 0x37800 91 #define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32) 92 #define REG_RING_INT_CLEAR 0x37808 93 94 /* 95 * two bitfields: rx, tx 96 * Both bitfields contains one bit for every hop (REG_CAPS). To 97 * enable/disable interrupts set/clear the corresponding bits. 98 */ 99 #define REG_RING_INTERRUPT_BASE 0x38200 100 #define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32) 101 102 #define REG_RING_INTERRUPT_MASK_CLEAR_BASE 0x38208 103 104 #define REG_INT_THROTTLING_RATE 0x38c00 105 #define REG_INT_THROTTLING_RATE_INTERVAL_MASK GENMASK(15, 0) 106 107 /* Interrupt Vector Allocation */ 108 #define REG_INT_VEC_ALLOC_BASE 0x38c40 109 #define REG_INT_VEC_ALLOC_BITS 4 110 #define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0) 111 #define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS) 112 113 /* The last 11 bits contain the number of hops supported by the NHI port. */ 114 #define REG_CAPS 0x39640 115 #define REG_CAPS_VERSION_MASK GENMASK(23, 16) 116 #define REG_CAPS_VERSION_2 0x40 117 118 #define REG_DMA_MISC 0x39864 119 #define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2) 120 #define REG_DMA_MISC_DISABLE_AUTO_CLEAR BIT(17) 121 122 #define REG_RESET 0x39898 123 #define REG_RESET_HRR BIT(0) 124 125 #define REG_INMAIL_DATA 0x39900 126 127 #define REG_INMAIL_CMD 0x39904 128 #define REG_INMAIL_CMD_MASK GENMASK(7, 0) 129 #define REG_INMAIL_ERROR BIT(30) 130 #define REG_INMAIL_OP_REQUEST BIT(31) 131 132 #define REG_OUTMAIL_CMD 0x3990c 133 #define REG_OUTMAIL_CMD_OPMODE_SHIFT 8 134 #define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8) 135 136 #define REG_FW_STS 0x39944 137 #define REG_FW_STS_NVM_AUTH_DONE BIT(31) 138 #define REG_FW_STS_CIO_RESET_REQ BIT(30) 139 #define REG_FW_STS_ICM_EN_CPU BIT(2) 140 #define REG_FW_STS_ICM_EN_INVERT BIT(1) 141 #define REG_FW_STS_ICM_EN BIT(0) 142 143 /* ICL NHI VSEC registers */ 144 145 /* FW ready */ 146 #define VS_CAP_9 0xc8 147 #define VS_CAP_9_FW_READY BIT(31) 148 /* UUID */ 149 #define VS_CAP_10 0xcc 150 #define VS_CAP_11 0xd0 151 /* LTR */ 152 #define VS_CAP_15 0xe0 153 #define VS_CAP_16 0xe4 154 /* TBT2PCIe */ 155 #define VS_CAP_18 0xec 156 #define VS_CAP_18_DONE BIT(0) 157 /* PCIe2TBT */ 158 #define VS_CAP_19 0xf0 159 #define VS_CAP_19_VALID BIT(0) 160 #define VS_CAP_19_CMD_SHIFT 1 161 #define VS_CAP_19_CMD_MASK GENMASK(7, 1) 162 /* Force power */ 163 #define VS_CAP_22 0xfc 164 #define VS_CAP_22_FORCE_POWER BIT(1) 165 #define VS_CAP_22_DMA_DELAY_MASK GENMASK(31, 24) 166 #define VS_CAP_22_DMA_DELAY_SHIFT 24 167 168 /** 169 * enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands 170 * @ICL_LC_GO2SX: Ask LC to enter Sx without wake 171 * @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake 172 * @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset 173 */ 174 enum icl_lc_mailbox_cmd { 175 ICL_LC_GO2SX = 0x02, 176 ICL_LC_GO2SX_NO_WAKE = 0x03, 177 ICL_LC_PREPARE_FOR_RESET = 0x21, 178 }; 179 180 #endif 181