1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * James Courtier-Dutton <James@superbug.co.uk>
5 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
6 * Creative Labs, Inc.
7 *
8 * Routines for effect processor FX8010
9 */
10
11 #include <linux/pci.h>
12 #include <linux/capability.h>
13 #include <linux/delay.h>
14 #include <linux/slab.h>
15 #include <linux/string.h>
16 #include <linux/vmalloc.h>
17 #include <linux/init.h>
18 #include <linux/mutex.h>
19 #include <linux/moduleparam.h>
20 #include <linux/nospec.h>
21
22 #include <sound/core.h>
23 #include <sound/tlv.h>
24 #include <sound/emu10k1.h>
25
26 #if 0 /* for testing purposes - digital out -> capture */
27 #define EMU10K1_CAPTURE_DIGITAL_OUT
28 #endif
29 #if 0 /* for testing purposes - set S/PDIF to AC3 output */
30 #define EMU10K1_SET_AC3_IEC958
31 #endif
32 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
33 #define EMU10K1_CENTER_LFE_FROM_FRONT
34 #endif
35
36 static bool high_res_gpr_volume;
37 module_param(high_res_gpr_volume, bool, 0444);
38 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
39
40 /*
41 * Tables
42 */
43
44 // Playback channel labels; corresponds with the public FXBUS_* defines.
45 // Unlike the tables below, this is not determined by the hardware.
46 const char * const snd_emu10k1_fxbus[32] = {
47 /* 0x00 */ "PCM Left",
48 /* 0x01 */ "PCM Right",
49 /* 0x02 */ "PCM Rear Left",
50 /* 0x03 */ "PCM Rear Right",
51 /* 0x04 */ "MIDI Left",
52 /* 0x05 */ "MIDI Right",
53 /* 0x06 */ "PCM Center",
54 /* 0x07 */ "PCM LFE",
55 /* 0x08 */ "PCM Front Left",
56 /* 0x09 */ "PCM Front Right",
57 /* 0x0a */ NULL,
58 /* 0x0b */ NULL,
59 /* 0x0c */ "MIDI Reverb",
60 /* 0x0d */ "MIDI Chorus",
61 /* 0x0e */ "PCM Side Left",
62 /* 0x0f */ "PCM Side Right",
63 /* 0x10 */ NULL,
64 /* 0x11 */ NULL,
65 /* 0x12 */ NULL,
66 /* 0x13 */ NULL,
67 /* 0x14 */ "Passthrough Left",
68 /* 0x15 */ "Passthrough Right",
69 /* 0x16 */ NULL,
70 /* 0x17 */ NULL,
71 /* 0x18 */ NULL,
72 /* 0x19 */ NULL,
73 /* 0x1a */ NULL,
74 /* 0x1b */ NULL,
75 /* 0x1c */ NULL,
76 /* 0x1d */ NULL,
77 /* 0x1e */ NULL,
78 /* 0x1f */ NULL
79 };
80
81 // Physical inputs; corresponds with the public EXTIN_* defines.
82 const char * const snd_emu10k1_sblive_ins[16] = {
83 /* 0x00 */ "AC97 Left",
84 /* 0x01 */ "AC97 Right",
85 /* 0x02 */ "TTL IEC958 Left",
86 /* 0x03 */ "TTL IEC958 Right",
87 /* 0x04 */ "Zoom Video Left",
88 /* 0x05 */ "Zoom Video Right",
89 /* 0x06 */ "Optical IEC958 Left",
90 /* 0x07 */ "Optical IEC958 Right",
91 /* 0x08 */ "Line/Mic 1 Left",
92 /* 0x09 */ "Line/Mic 1 Right",
93 /* 0x0a */ "Coaxial IEC958 Left",
94 /* 0x0b */ "Coaxial IEC958 Right",
95 /* 0x0c */ "Line/Mic 2 Left",
96 /* 0x0d */ "Line/Mic 2 Right",
97 /* 0x0e */ NULL,
98 /* 0x0f */ NULL
99 };
100
101 // Physical inputs; corresponds with the public A_EXTIN_* defines.
102 const char * const snd_emu10k1_audigy_ins[16] = {
103 /* 0x00 */ "AC97 Left",
104 /* 0x01 */ "AC97 Right",
105 /* 0x02 */ "Audigy CD Left",
106 /* 0x03 */ "Audigy CD Right",
107 /* 0x04 */ "Optical IEC958 Left",
108 /* 0x05 */ "Optical IEC958 Right",
109 /* 0x06 */ NULL,
110 /* 0x07 */ NULL,
111 /* 0x08 */ "Line/Mic 2 Left",
112 /* 0x09 */ "Line/Mic 2 Right",
113 /* 0x0a */ "SPDIF Left",
114 /* 0x0b */ "SPDIF Right",
115 /* 0x0c */ "Aux2 Left",
116 /* 0x0d */ "Aux2 Right",
117 /* 0x0e */ NULL,
118 /* 0x0f */ NULL
119 };
120
121 // Physical outputs; corresponds with the public EXTOUT_* defines.
122 const char * const snd_emu10k1_sblive_outs[32] = {
123 /* 0x00 */ "AC97 Left",
124 /* 0x01 */ "AC97 Right",
125 /* 0x02 */ "Optical IEC958 Left",
126 /* 0x03 */ "Optical IEC958 Right",
127 /* 0x04 */ "Center",
128 /* 0x05 */ "LFE",
129 /* 0x06 */ "Headphone Left",
130 /* 0x07 */ "Headphone Right",
131 /* 0x08 */ "Surround Left",
132 /* 0x09 */ "Surround Right",
133 /* 0x0a */ "PCM Capture Left",
134 /* 0x0b */ "PCM Capture Right",
135 /* 0x0c */ "MIC Capture",
136 /* 0x0d */ "AC97 Surround Left",
137 /* 0x0e */ "AC97 Surround Right",
138 /* 0x0f */ NULL,
139 // This is actually the FXBUS2 range; SB Live! 5.1 only.
140 /* 0x10 */ NULL,
141 /* 0x11 */ "Analog Center",
142 /* 0x12 */ "Analog LFE",
143 /* 0x13 */ NULL,
144 /* 0x14 */ NULL,
145 /* 0x15 */ NULL,
146 /* 0x16 */ NULL,
147 /* 0x17 */ NULL,
148 /* 0x18 */ NULL,
149 /* 0x19 */ NULL,
150 /* 0x1a */ NULL,
151 /* 0x1b */ NULL,
152 /* 0x1c */ NULL,
153 /* 0x1d */ NULL,
154 /* 0x1e */ NULL,
155 /* 0x1f */ NULL,
156 };
157
158 // Physical outputs; corresponds with the public A_EXTOUT_* defines.
159 const char * const snd_emu10k1_audigy_outs[32] = {
160 /* 0x00 */ "Digital Front Left",
161 /* 0x01 */ "Digital Front Right",
162 /* 0x02 */ "Digital Center",
163 /* 0x03 */ "Digital LEF",
164 /* 0x04 */ "Headphone Left",
165 /* 0x05 */ "Headphone Right",
166 /* 0x06 */ "Digital Rear Left",
167 /* 0x07 */ "Digital Rear Right",
168 /* 0x08 */ "Front Left",
169 /* 0x09 */ "Front Right",
170 /* 0x0a */ "Center",
171 /* 0x0b */ "LFE",
172 /* 0x0c */ NULL,
173 /* 0x0d */ NULL,
174 /* 0x0e */ "Rear Left",
175 /* 0x0f */ "Rear Right",
176 /* 0x10 */ "AC97 Front Left",
177 /* 0x11 */ "AC97 Front Right",
178 /* 0x12 */ "ADC Capture Left",
179 /* 0x13 */ "ADC Capture Right",
180 /* 0x14 */ NULL,
181 /* 0x15 */ NULL,
182 /* 0x16 */ NULL,
183 /* 0x17 */ NULL,
184 /* 0x18 */ NULL,
185 /* 0x19 */ NULL,
186 /* 0x1a */ NULL,
187 /* 0x1b */ NULL,
188 /* 0x1c */ NULL,
189 /* 0x1d */ NULL,
190 /* 0x1e */ NULL,
191 /* 0x1f */ NULL,
192 };
193
194 // On the SB Live! 5.1, FXBUS2[1] and FXBUS2[2] are occupied by EXTOUT_ACENTER
195 // and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
196 //
197 // Since only 14 of the 16 EXTINs are used, this is not a big problem.
198 // We route AC97 to FX capture 14 and 15, SPDIF_CD to FX capture 0 and 3,
199 // and the rest of the EXTINs to the corresponding FX capture channel.
200 // Multitrack recorders will still see the center/LFE output signal
201 // on the second and third "input" channel.
202 const s8 snd_emu10k1_sblive51_fxbus2_map[16] = {
203 2, -1, -1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 1
204 };
205
206 static const u32 bass_table[41][5] = {
207 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
208 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
209 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
210 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
211 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
212 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
213 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
214 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
215 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
216 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
217 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
218 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
219 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
220 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
221 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
222 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
223 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
224 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
225 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
226 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
227 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
228 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
229 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
230 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
231 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
232 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
233 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
234 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
235 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
236 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
237 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
238 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
239 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
240 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
241 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
242 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
243 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
244 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
245 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
246 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
247 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
248 };
249
250 static const u32 treble_table[41][5] = {
251 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
252 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
253 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
254 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
255 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
256 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
257 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
258 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
259 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
260 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
261 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
262 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
263 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
264 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
265 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
266 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
267 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
268 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
269 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
270 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
271 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
272 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
273 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
274 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
275 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
276 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
277 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
278 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
279 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
280 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
281 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
282 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
283 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
284 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
285 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
286 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
287 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
288 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
289 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
290 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
291 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
292 };
293
294 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
295 static const u32 db_table[101] = {
296 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
297 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
298 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
299 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
300 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
301 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
302 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
303 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
304 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
305 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
306 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
307 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
308 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
309 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
310 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
311 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
312 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
313 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
314 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
315 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
316 0x7fffffff,
317 };
318
319 /* EMU10k1/EMU10k2 DSP control db gain */
320 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
321 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
322
323 /* EMU10K1 bass/treble db gain */
324 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
325
326 static const u32 onoff_table[2] = {
327 0x00000000, 0x00000001
328 };
329
330 /*
331 * controls
332 */
333
snd_emu10k1_gpr_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)334 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
335 {
336 struct snd_emu10k1_fx8010_ctl *ctl =
337 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
338
339 if (ctl->min == 0 && ctl->max == 1)
340 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
341 else
342 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
343 uinfo->count = ctl->vcount;
344 uinfo->value.integer.min = ctl->min;
345 uinfo->value.integer.max = ctl->max;
346 return 0;
347 }
348
snd_emu10k1_gpr_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)349 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
350 {
351 struct snd_emu10k1_fx8010_ctl *ctl =
352 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
353 unsigned int i;
354
355 for (i = 0; i < ctl->vcount; i++)
356 ucontrol->value.integer.value[i] = ctl->value[i];
357 return 0;
358 }
359
snd_emu10k1_gpr_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)360 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
361 {
362 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
363 struct snd_emu10k1_fx8010_ctl *ctl =
364 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
365 int nval, val;
366 unsigned int i, j;
367 int change = 0;
368
369 for (i = 0; i < ctl->vcount; i++) {
370 nval = ucontrol->value.integer.value[i];
371 if (nval < ctl->min)
372 nval = ctl->min;
373 if (nval > ctl->max)
374 nval = ctl->max;
375 if (nval != ctl->value[i])
376 change = 1;
377 val = ctl->value[i] = nval;
378 switch (ctl->translation) {
379 case EMU10K1_GPR_TRANSLATION_NONE:
380 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
381 break;
382 case EMU10K1_GPR_TRANSLATION_NEGATE:
383 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, ~val);
384 break;
385 case EMU10K1_GPR_TRANSLATION_TABLE100:
386 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
387 break;
388 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100:
389 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0,
390 val == 100 ? 0x80000000 : -(int)db_table[val]);
391 break;
392 case EMU10K1_GPR_TRANSLATION_BASS:
393 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
394 change = -EIO;
395 goto __error;
396 }
397 for (j = 0; j < 5; j++)
398 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
399 break;
400 case EMU10K1_GPR_TRANSLATION_TREBLE:
401 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
402 change = -EIO;
403 goto __error;
404 }
405 for (j = 0; j < 5; j++)
406 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
407 break;
408 case EMU10K1_GPR_TRANSLATION_ONOFF:
409 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
410 break;
411 }
412 }
413 __error:
414 return change;
415 }
416
417 /*
418 * Interrupt handler
419 */
420
snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 * emu)421 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
422 {
423 struct snd_emu10k1_fx8010_irq *irq, *nirq;
424
425 irq = emu->fx8010.irq_handlers;
426 while (irq) {
427 nirq = irq->next; /* irq ptr can be removed from list */
428 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
429 if (irq->handler)
430 irq->handler(emu, irq->private_data);
431 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
432 }
433 irq = nirq;
434 }
435 }
436
snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 * emu,snd_fx8010_irq_handler_t * handler,unsigned char gpr_running,void * private_data,struct snd_emu10k1_fx8010_irq * irq)437 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
438 snd_fx8010_irq_handler_t *handler,
439 unsigned char gpr_running,
440 void *private_data,
441 struct snd_emu10k1_fx8010_irq *irq)
442 {
443 irq->handler = handler;
444 irq->gpr_running = gpr_running;
445 irq->private_data = private_data;
446 irq->next = NULL;
447 guard(spinlock_irqsave)(&emu->fx8010.irq_lock);
448 if (emu->fx8010.irq_handlers == NULL) {
449 emu->fx8010.irq_handlers = irq;
450 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
451 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
452 } else {
453 irq->next = emu->fx8010.irq_handlers;
454 emu->fx8010.irq_handlers = irq;
455 }
456 return 0;
457 }
458
snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_irq * irq)459 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
460 struct snd_emu10k1_fx8010_irq *irq)
461 {
462 struct snd_emu10k1_fx8010_irq *tmp;
463
464 guard(spinlock_irqsave)(&emu->fx8010.irq_lock);
465 tmp = emu->fx8010.irq_handlers;
466 if (tmp == irq) {
467 emu->fx8010.irq_handlers = tmp->next;
468 if (emu->fx8010.irq_handlers == NULL) {
469 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
470 emu->dsp_interrupt = NULL;
471 }
472 } else {
473 while (tmp && tmp->next != irq)
474 tmp = tmp->next;
475 if (tmp)
476 tmp->next = tmp->next->next;
477 }
478 return 0;
479 }
480
481 /*************************************************************************
482 * EMU10K1 effect manager
483 *************************************************************************/
484
snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code * icode,unsigned int * ptr,u32 op,u32 r,u32 a,u32 x,u32 y)485 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
486 unsigned int *ptr,
487 u32 op, u32 r, u32 a, u32 x, u32 y)
488 {
489 u_int32_t *code;
490 if (snd_BUG_ON(*ptr >= 512))
491 return;
492 code = icode->code + (*ptr) * 2;
493 set_bit(*ptr, icode->code_valid);
494 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
495 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
496 (*ptr)++;
497 }
498
499 #define OP(icode, ptr, op, r, a, x, y) \
500 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
501
snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code * icode,unsigned int * ptr,u32 op,u32 r,u32 a,u32 x,u32 y)502 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
503 unsigned int *ptr,
504 u32 op, u32 r, u32 a, u32 x, u32 y)
505 {
506 u_int32_t *code;
507 if (snd_BUG_ON(*ptr >= 1024))
508 return;
509 code = icode->code + (*ptr) * 2;
510 set_bit(*ptr, icode->code_valid);
511 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
512 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
513 (*ptr)++;
514 }
515
516 #define A_OP(icode, ptr, op, r, a, x, y) \
517 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
518
snd_emu10k1_efx_write(struct snd_emu10k1 * emu,unsigned int pc,unsigned int data)519 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
520 {
521 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
522 snd_emu10k1_ptr_write(emu, pc, 0, data);
523 }
524
snd_emu10k1_efx_read(struct snd_emu10k1 * emu,unsigned int pc)525 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
526 {
527 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
528 return snd_emu10k1_ptr_read(emu, pc, 0);
529 }
530
snd_emu10k1_gpr_poke(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode,bool in_kernel)531 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
532 struct snd_emu10k1_fx8010_code *icode,
533 bool in_kernel)
534 {
535 int gpr;
536 u32 val;
537
538 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
539 if (!test_bit(gpr, icode->gpr_valid))
540 continue;
541 if (in_kernel)
542 val = icode->gpr_map[gpr];
543 else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr]))
544 return -EFAULT;
545 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
546 }
547 return 0;
548 }
549
snd_emu10k1_gpr_peek(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode)550 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
551 struct snd_emu10k1_fx8010_code *icode)
552 {
553 int gpr;
554 u32 val;
555
556 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
557 set_bit(gpr, icode->gpr_valid);
558 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
559 if (put_user(val, (__user u32 *)&icode->gpr_map[gpr]))
560 return -EFAULT;
561 }
562 return 0;
563 }
564
snd_emu10k1_tram_poke(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode,bool in_kernel)565 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
566 struct snd_emu10k1_fx8010_code *icode,
567 bool in_kernel)
568 {
569 int tram;
570 u32 addr, val;
571
572 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
573 if (!test_bit(tram, icode->tram_valid))
574 continue;
575 if (in_kernel) {
576 val = icode->tram_data_map[tram];
577 addr = icode->tram_addr_map[tram];
578 } else {
579 if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) ||
580 get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram]))
581 return -EFAULT;
582 }
583 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
584 if (!emu->audigy) {
585 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
586 } else {
587 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
588 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
589 }
590 }
591 return 0;
592 }
593
snd_emu10k1_tram_peek(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode)594 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
595 struct snd_emu10k1_fx8010_code *icode)
596 {
597 int tram;
598 u32 val, addr;
599
600 memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
601 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
602 set_bit(tram, icode->tram_valid);
603 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
604 if (!emu->audigy) {
605 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
606 } else {
607 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
608 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
609 }
610 if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) ||
611 put_user(addr, (__user u32 *)&icode->tram_addr_map[tram]))
612 return -EFAULT;
613 }
614 return 0;
615 }
616
snd_emu10k1_code_poke(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode,bool in_kernel)617 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
618 struct snd_emu10k1_fx8010_code *icode,
619 bool in_kernel)
620 {
621 u32 pc, lo, hi;
622
623 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
624 if (!test_bit(pc / 2, icode->code_valid))
625 continue;
626 if (in_kernel) {
627 lo = icode->code[pc + 0];
628 hi = icode->code[pc + 1];
629 } else {
630 if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) ||
631 get_user(hi, (__user u32 *)&icode->code[pc + 1]))
632 return -EFAULT;
633 }
634 snd_emu10k1_efx_write(emu, pc + 0, lo);
635 snd_emu10k1_efx_write(emu, pc + 1, hi);
636 }
637 return 0;
638 }
639
snd_emu10k1_code_peek(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode)640 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
641 struct snd_emu10k1_fx8010_code *icode)
642 {
643 u32 pc;
644
645 memset(icode->code_valid, 0, sizeof(icode->code_valid));
646 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
647 set_bit(pc / 2, icode->code_valid);
648 if (put_user(snd_emu10k1_efx_read(emu, pc + 0),
649 (__user u32 *)&icode->code[pc + 0]))
650 return -EFAULT;
651 if (put_user(snd_emu10k1_efx_read(emu, pc + 1),
652 (__user u32 *)&icode->code[pc + 1]))
653 return -EFAULT;
654 }
655 return 0;
656 }
657
658 static struct snd_emu10k1_fx8010_ctl *
snd_emu10k1_look_for_ctl(struct snd_emu10k1 * emu,struct emu10k1_ctl_elem_id * _id)659 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu,
660 struct emu10k1_ctl_elem_id *_id)
661 {
662 struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id;
663 struct snd_emu10k1_fx8010_ctl *ctl;
664 struct snd_kcontrol *kcontrol;
665
666 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
667 kcontrol = ctl->kcontrol;
668 if (kcontrol->id.iface == id->iface &&
669 kcontrol->id.index == id->index &&
670 !strcmp(kcontrol->id.name, id->name))
671 return ctl;
672 }
673 return NULL;
674 }
675
676 #define MAX_TLV_SIZE 256
677
copy_tlv(const unsigned int __user * _tlv,bool in_kernel)678 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel)
679 {
680 unsigned int data[2];
681 unsigned int *tlv;
682
683 if (!_tlv)
684 return NULL;
685 if (in_kernel)
686 memcpy(data, (__force void *)_tlv, sizeof(data));
687 else if (copy_from_user(data, _tlv, sizeof(data)))
688 return NULL;
689 if (data[1] >= MAX_TLV_SIZE)
690 return NULL;
691 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
692 if (!tlv)
693 return NULL;
694 memcpy(tlv, data, sizeof(data));
695 if (in_kernel) {
696 memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]);
697 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
698 kfree(tlv);
699 return NULL;
700 }
701 return tlv;
702 }
703
copy_gctl(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_control_gpr * dst,struct snd_emu10k1_fx8010_control_gpr * src,int idx,bool in_kernel)704 static int copy_gctl(struct snd_emu10k1 *emu,
705 struct snd_emu10k1_fx8010_control_gpr *dst,
706 struct snd_emu10k1_fx8010_control_gpr *src,
707 int idx, bool in_kernel)
708 {
709 struct snd_emu10k1_fx8010_control_gpr __user *_src;
710 struct snd_emu10k1_fx8010_control_old_gpr *octl;
711 struct snd_emu10k1_fx8010_control_old_gpr __user *_octl;
712
713 _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src;
714 if (emu->support_tlv) {
715 if (in_kernel)
716 *dst = src[idx];
717 else if (copy_from_user(dst, &_src[idx], sizeof(*src)))
718 return -EFAULT;
719 return 0;
720 }
721
722 octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src;
723 _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl;
724 if (in_kernel)
725 memcpy(dst, &octl[idx], sizeof(*octl));
726 else if (copy_from_user(dst, &_octl[idx], sizeof(*octl)))
727 return -EFAULT;
728 dst->tlv = NULL;
729 return 0;
730 }
731
copy_gctl_to_user(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_control_gpr * dst,struct snd_emu10k1_fx8010_control_gpr * src,int idx)732 static int copy_gctl_to_user(struct snd_emu10k1 *emu,
733 struct snd_emu10k1_fx8010_control_gpr *dst,
734 struct snd_emu10k1_fx8010_control_gpr *src,
735 int idx)
736 {
737 struct snd_emu10k1_fx8010_control_gpr __user *_dst;
738 struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
739
740 _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst;
741 if (emu->support_tlv)
742 return copy_to_user(&_dst[idx], src, sizeof(*src));
743
744 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst;
745 return copy_to_user(&octl[idx], src, sizeof(*octl));
746 }
747
copy_ctl_elem_id(const struct emu10k1_ctl_elem_id * list,int i,struct emu10k1_ctl_elem_id * ret,bool in_kernel)748 static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i,
749 struct emu10k1_ctl_elem_id *ret, bool in_kernel)
750 {
751 struct emu10k1_ctl_elem_id __user *_id =
752 (struct emu10k1_ctl_elem_id __user *)&list[i];
753
754 if (in_kernel)
755 *ret = list[i];
756 else if (copy_from_user(ret, _id, sizeof(*ret)))
757 return -EFAULT;
758 return 0;
759 }
760
snd_emu10k1_verify_controls(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode,bool in_kernel)761 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
762 struct snd_emu10k1_fx8010_code *icode,
763 bool in_kernel)
764 {
765 unsigned int i;
766 struct emu10k1_ctl_elem_id id;
767 struct snd_emu10k1_fx8010_control_gpr *gctl;
768 struct snd_ctl_elem_id *gctl_id;
769 int err;
770
771 for (i = 0; i < icode->gpr_del_control_count; i++) {
772 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
773 in_kernel);
774 if (err < 0)
775 return err;
776 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
777 return -ENOENT;
778 }
779 gctl = kmalloc_obj(*gctl);
780 if (! gctl)
781 return -ENOMEM;
782 err = 0;
783 for (i = 0; i < icode->gpr_add_control_count; i++) {
784 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
785 in_kernel)) {
786 err = -EFAULT;
787 goto __error;
788 }
789 if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
790 continue;
791 gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
792 if (snd_ctl_find_id(emu->card, gctl_id)) {
793 err = -EEXIST;
794 goto __error;
795 }
796 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
797 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
798 err = -EINVAL;
799 goto __error;
800 }
801 switch (gctl->translation) {
802 case EMU10K1_GPR_TRANSLATION_NONE:
803 case EMU10K1_GPR_TRANSLATION_NEGATE:
804 break;
805 case EMU10K1_GPR_TRANSLATION_TABLE100:
806 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100:
807 if (gctl->min != 0 || gctl->max != 100) {
808 err = -EINVAL;
809 goto __error;
810 }
811 break;
812 case EMU10K1_GPR_TRANSLATION_BASS:
813 case EMU10K1_GPR_TRANSLATION_TREBLE:
814 if (gctl->min != 0 || gctl->max != 40) {
815 err = -EINVAL;
816 goto __error;
817 }
818 break;
819 case EMU10K1_GPR_TRANSLATION_ONOFF:
820 if (gctl->min != 0 || gctl->max != 1) {
821 err = -EINVAL;
822 goto __error;
823 }
824 break;
825 default:
826 err = -EINVAL;
827 goto __error;
828 }
829 }
830 for (i = 0; i < icode->gpr_list_control_count; i++) {
831 /* FIXME: we need to check the WRITE access */
832 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i,
833 in_kernel)) {
834 err = -EFAULT;
835 goto __error;
836 }
837 }
838 __error:
839 kfree(gctl);
840 return err;
841 }
842
snd_emu10k1_ctl_private_free(struct snd_kcontrol * kctl)843 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
844 {
845 struct snd_emu10k1_fx8010_ctl *ctl;
846
847 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
848 kctl->private_value = 0;
849 list_del(&ctl->list);
850 kfree(ctl);
851 kfree(kctl->tlv.p);
852 }
853
snd_emu10k1_add_controls(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode,bool in_kernel)854 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
855 struct snd_emu10k1_fx8010_code *icode,
856 bool in_kernel)
857 {
858 unsigned int i, j;
859 struct snd_emu10k1_fx8010_control_gpr *gctl;
860 struct snd_ctl_elem_id *gctl_id;
861 struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
862 struct snd_kcontrol_new knew;
863 struct snd_kcontrol *kctl;
864 struct snd_ctl_elem_value *val;
865 int err = 0;
866
867 val = kmalloc_obj(*val);
868 gctl = kmalloc_obj(*gctl);
869 nctl = kmalloc_obj(*nctl);
870 if (!val || !gctl || !nctl) {
871 err = -ENOMEM;
872 goto __error;
873 }
874
875 for (i = 0; i < icode->gpr_add_control_count; i++) {
876 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
877 in_kernel)) {
878 err = -EFAULT;
879 goto __error;
880 }
881 gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
882 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
883 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
884 err = -EINVAL;
885 goto __error;
886 }
887 if (!*gctl_id->name) {
888 err = -EINVAL;
889 goto __error;
890 }
891 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
892 memset(&knew, 0, sizeof(knew));
893 knew.iface = gctl_id->iface;
894 knew.name = gctl_id->name;
895 knew.index = gctl_id->index;
896 knew.device = gctl_id->device;
897 knew.subdevice = gctl_id->subdevice;
898 knew.info = snd_emu10k1_gpr_ctl_info;
899 knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel);
900 if (knew.tlv.p)
901 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
902 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
903 knew.get = snd_emu10k1_gpr_ctl_get;
904 knew.put = snd_emu10k1_gpr_ctl_put;
905 memset(nctl, 0, sizeof(*nctl));
906 nctl->vcount = gctl->vcount;
907 nctl->count = gctl->count;
908 for (j = 0; j < 32; j++) {
909 nctl->gpr[j] = gctl->gpr[j];
910 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
911 val->value.integer.value[j] = gctl->value[j];
912 }
913 nctl->min = gctl->min;
914 nctl->max = gctl->max;
915 nctl->translation = gctl->translation;
916 if (ctl == NULL) {
917 ctl = kmalloc_obj(*ctl);
918 if (ctl == NULL) {
919 err = -ENOMEM;
920 kfree(knew.tlv.p);
921 goto __error;
922 }
923 knew.private_value = (unsigned long)ctl;
924 *ctl = *nctl;
925 kctl = snd_ctl_new1(&knew, emu);
926 err = snd_ctl_add(emu->card, kctl);
927 if (err < 0) {
928 kfree(ctl);
929 kfree(knew.tlv.p);
930 goto __error;
931 }
932 kctl->private_free = snd_emu10k1_ctl_private_free;
933 ctl->kcontrol = kctl;
934 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
935 } else {
936 /* overwrite */
937 nctl->list = ctl->list;
938 nctl->kcontrol = ctl->kcontrol;
939 *ctl = *nctl;
940 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
941 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
942 }
943 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
944 }
945 __error:
946 kfree(nctl);
947 kfree(gctl);
948 kfree(val);
949 return err;
950 }
951
snd_emu10k1_del_controls(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode,bool in_kernel)952 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
953 struct snd_emu10k1_fx8010_code *icode,
954 bool in_kernel)
955 {
956 unsigned int i;
957 struct emu10k1_ctl_elem_id id;
958 struct snd_emu10k1_fx8010_ctl *ctl;
959 struct snd_card *card = emu->card;
960 int err;
961
962 for (i = 0; i < icode->gpr_del_control_count; i++) {
963 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
964 in_kernel);
965 if (err < 0)
966 return err;
967 ctl = snd_emu10k1_look_for_ctl(emu, &id);
968 if (ctl)
969 snd_ctl_remove(card, ctl->kcontrol);
970 }
971 return 0;
972 }
973
snd_emu10k1_list_controls(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode)974 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
975 struct snd_emu10k1_fx8010_code *icode)
976 {
977 unsigned int i = 0, j;
978 unsigned int total = 0;
979 struct snd_emu10k1_fx8010_control_gpr *gctl;
980 struct snd_emu10k1_fx8010_ctl *ctl;
981 struct snd_ctl_elem_id *id;
982
983 gctl = kmalloc_obj(*gctl);
984 if (! gctl)
985 return -ENOMEM;
986
987 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
988 total++;
989 if (icode->gpr_list_controls &&
990 i < icode->gpr_list_control_count) {
991 memset(gctl, 0, sizeof(*gctl));
992 id = &ctl->kcontrol->id;
993 gctl->id.iface = (__force int)id->iface;
994 strscpy(gctl->id.name, id->name, sizeof(gctl->id.name));
995 gctl->id.index = id->index;
996 gctl->id.device = id->device;
997 gctl->id.subdevice = id->subdevice;
998 gctl->vcount = ctl->vcount;
999 gctl->count = ctl->count;
1000 for (j = 0; j < 32; j++) {
1001 gctl->gpr[j] = ctl->gpr[j];
1002 gctl->value[j] = ctl->value[j];
1003 }
1004 gctl->min = ctl->min;
1005 gctl->max = ctl->max;
1006 gctl->translation = ctl->translation;
1007 if (copy_gctl_to_user(emu, icode->gpr_list_controls,
1008 gctl, i)) {
1009 kfree(gctl);
1010 return -EFAULT;
1011 }
1012 i++;
1013 }
1014 }
1015 icode->gpr_list_control_total = total;
1016 kfree(gctl);
1017 return 0;
1018 }
1019
snd_emu10k1_icode_poke(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode,bool in_kernel)1020 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
1021 struct snd_emu10k1_fx8010_code *icode,
1022 bool in_kernel)
1023 {
1024 int err;
1025
1026 guard(mutex)(&emu->fx8010.lock);
1027 err = snd_emu10k1_verify_controls(emu, icode, in_kernel);
1028 if (err < 0)
1029 return err;
1030 strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
1031 /* stop FX processor - this may be dangerous, but it's better to miss
1032 some samples than generate wrong ones - [jk] */
1033 if (emu->audigy)
1034 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
1035 else
1036 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
1037 /* ok, do the main job */
1038 err = snd_emu10k1_del_controls(emu, icode, in_kernel);
1039 if (err < 0)
1040 return err;
1041 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel);
1042 if (err < 0)
1043 return err;
1044 err = snd_emu10k1_tram_poke(emu, icode, in_kernel);
1045 if (err < 0)
1046 return err;
1047 err = snd_emu10k1_code_poke(emu, icode, in_kernel);
1048 if (err < 0)
1049 return err;
1050 err = snd_emu10k1_add_controls(emu, icode, in_kernel);
1051 if (err < 0)
1052 return err;
1053 /* start FX processor when the DSP code is updated */
1054 if (emu->audigy)
1055 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
1056 else
1057 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
1058 return 0;
1059 }
1060
snd_emu10k1_icode_peek(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_code * icode)1061 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
1062 struct snd_emu10k1_fx8010_code *icode)
1063 {
1064 int err;
1065
1066 guard(mutex)(&emu->fx8010.lock);
1067 strscpy(icode->name, emu->fx8010.name, sizeof(icode->name));
1068 /* ok, do the main job */
1069 err = snd_emu10k1_gpr_peek(emu, icode);
1070 if (err >= 0)
1071 err = snd_emu10k1_tram_peek(emu, icode);
1072 if (err >= 0)
1073 err = snd_emu10k1_code_peek(emu, icode);
1074 if (err >= 0)
1075 err = snd_emu10k1_list_controls(emu, icode);
1076 return err;
1077 }
1078
snd_emu10k1_ipcm_poke(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_pcm_rec * ipcm)1079 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
1080 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1081 {
1082 unsigned int i;
1083 struct snd_emu10k1_fx8010_pcm *pcm;
1084
1085 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1086 return -EINVAL;
1087 ipcm->substream = array_index_nospec(ipcm->substream,
1088 EMU10K1_FX8010_PCM_COUNT);
1089 if (ipcm->channels > 32)
1090 return -EINVAL;
1091 pcm = &emu->fx8010.pcm[ipcm->substream];
1092 guard(mutex)(&emu->fx8010.lock);
1093 guard(spinlock_irq)(&emu->reg_lock);
1094 if (pcm->opened)
1095 return -EBUSY;
1096 if (ipcm->channels == 0) { /* remove */
1097 pcm->valid = 0;
1098 } else {
1099 /* FIXME: we need to add universal code to the PCM transfer routine */
1100 if (ipcm->channels != 2)
1101 return -EINVAL;
1102 pcm->valid = 1;
1103 pcm->opened = 0;
1104 pcm->channels = ipcm->channels;
1105 pcm->tram_start = ipcm->tram_start;
1106 pcm->buffer_size = ipcm->buffer_size;
1107 pcm->gpr_size = ipcm->gpr_size;
1108 pcm->gpr_count = ipcm->gpr_count;
1109 pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
1110 pcm->gpr_ptr = ipcm->gpr_ptr;
1111 pcm->gpr_trigger = ipcm->gpr_trigger;
1112 pcm->gpr_running = ipcm->gpr_running;
1113 for (i = 0; i < pcm->channels; i++)
1114 pcm->etram[i] = ipcm->etram[i];
1115 }
1116 return 0;
1117 }
1118
snd_emu10k1_ipcm_peek(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_pcm_rec * ipcm)1119 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
1120 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1121 {
1122 unsigned int i;
1123 struct snd_emu10k1_fx8010_pcm *pcm;
1124
1125 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1126 return -EINVAL;
1127 ipcm->substream = array_index_nospec(ipcm->substream,
1128 EMU10K1_FX8010_PCM_COUNT);
1129 pcm = &emu->fx8010.pcm[ipcm->substream];
1130 guard(mutex)(&emu->fx8010.lock);
1131 guard(spinlock_irq)(&emu->reg_lock);
1132 ipcm->channels = pcm->channels;
1133 ipcm->tram_start = pcm->tram_start;
1134 ipcm->buffer_size = pcm->buffer_size;
1135 ipcm->gpr_size = pcm->gpr_size;
1136 ipcm->gpr_ptr = pcm->gpr_ptr;
1137 ipcm->gpr_count = pcm->gpr_count;
1138 ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
1139 ipcm->gpr_trigger = pcm->gpr_trigger;
1140 ipcm->gpr_running = pcm->gpr_running;
1141 for (i = 0; i < pcm->channels; i++)
1142 ipcm->etram[i] = pcm->etram[i];
1143 ipcm->res1 = ipcm->res2 = 0;
1144 ipcm->pad = 0;
1145 return 0;
1146 }
1147
1148 #define SND_EMU10K1_GPR_CONTROLS 44
1149 #define SND_EMU10K1_INPUTS 12
1150 #define SND_EMU10K1_PLAYBACK_CHANNELS 8
1151 #define SND_EMU10K1_CAPTURE_CHANNELS 4
1152
1153 #define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1)
1154
1155 static void
snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr * ctl,const char * name,int gpr,int defval,int defval_hr)1156 snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr *ctl,
1157 const char *name, int gpr, int defval, int defval_hr)
1158 {
1159 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1160 strscpy(ctl->id.name, name);
1161 ctl->vcount = ctl->count = 1;
1162 if (high_res_gpr_volume) {
1163 ctl->min = -1;
1164 ctl->max = 0x7fffffff;
1165 ctl->tlv = snd_emu10k1_db_linear;
1166 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE;
1167 defval = defval_hr;
1168 } else {
1169 ctl->min = 0;
1170 ctl->max = 100;
1171 ctl->tlv = snd_emu10k1_db_scale1;
1172 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100;
1173 }
1174 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1175 }
1176 #define snd_emu10k1_init_mono_control(ctl, name, gpr, defval) \
1177 snd_emu10k1_init_mono_control2(ctl, name, gpr, defval, HR_VAL(defval))
1178
1179 static void
snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr * ctl,const char * name,int gpr,int defval,int defval_hr)1180 snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr *ctl,
1181 const char *name, int gpr, int defval, int defval_hr)
1182 {
1183 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1184 strscpy(ctl->id.name, name);
1185 ctl->vcount = ctl->count = 2;
1186 if (high_res_gpr_volume) {
1187 ctl->min = -1;
1188 ctl->max = 0x7fffffff;
1189 ctl->tlv = snd_emu10k1_db_linear;
1190 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE;
1191 defval = defval_hr;
1192 } else {
1193 ctl->min = 0;
1194 ctl->max = 100;
1195 ctl->tlv = snd_emu10k1_db_scale1;
1196 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100;
1197 }
1198 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1199 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1200 }
1201 #define snd_emu10k1_init_stereo_control(ctl, name, gpr, defval) \
1202 snd_emu10k1_init_stereo_control2(ctl, name, gpr, defval, HR_VAL(defval))
1203
1204 static void
snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr * ctl,const char * name,int gpr,int defval)1205 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1206 const char *name, int gpr, int defval)
1207 {
1208 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1209 strscpy(ctl->id.name, name);
1210 ctl->vcount = ctl->count = 1;
1211 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1212 ctl->min = 0;
1213 ctl->max = 1;
1214 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1215 }
1216
1217 static void
snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr * ctl,const char * name,int gpr,int defval)1218 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1219 const char *name, int gpr, int defval)
1220 {
1221 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1222 strscpy(ctl->id.name, name);
1223 ctl->vcount = ctl->count = 2;
1224 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1225 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1226 ctl->min = 0;
1227 ctl->max = 1;
1228 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1229 }
1230
1231 /*
1232 * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA
1233 * to 2 x 16-bit registers in Audigy - their values are read via DMA.
1234 * Conversion is performed by Audigy DSP instructions of FX8010.
1235 */
snd_emu10k1_audigy_dsp_convert_32_to_2x16(struct snd_emu10k1_fx8010_code * icode,u32 * ptr,int tmp,int bit_shifter16,int reg_in,int reg_out)1236 static void snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1237 struct snd_emu10k1_fx8010_code *icode,
1238 u32 *ptr, int tmp, int bit_shifter16,
1239 int reg_in, int reg_out)
1240 {
1241 // This leaves the low word in place, which is fine,
1242 // as the low bits are completely ignored subsequently.
1243 // reg_out[1] = reg_in
1244 A_OP(icode, ptr, iACC3, reg_out + 1, reg_in, A_C_00000000, A_C_00000000);
1245 // It is fine to read reg_in multiple times.
1246 // tmp = reg_in << 15
1247 A_OP(icode, ptr, iMACINT1, A_GPR(tmp), A_C_00000000, reg_in, A_GPR(bit_shifter16));
1248 // Left-shift once more. This is a separate step, as the
1249 // signed multiplication would clobber the MSB.
1250 // reg_out[0] = tmp + ((tmp << 31) >> 31)
1251 A_OP(icode, ptr, iMAC3, reg_out, A_GPR(tmp), A_GPR(tmp), A_C_80000000);
1252 }
1253
1254 #define ENUM_GPR(name, size) name, name ## _dummy = name + (size) - 1
1255
1256 /*
1257 * initial DSP configuration for Audigy
1258 */
1259
_snd_emu10k1_audigy_init_efx(struct snd_emu10k1 * emu)1260 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
1261 {
1262 int err, z, nctl;
1263 enum {
1264 ENUM_GPR(playback, SND_EMU10K1_PLAYBACK_CHANNELS),
1265 ENUM_GPR(stereo_mix, 2),
1266 ENUM_GPR(capture, 2),
1267 ENUM_GPR(bit_shifter16, 1),
1268 // The fixed allocation of these breaks the pattern, but why not.
1269 // Splitting these into left/right is questionable, as it will break
1270 // down for center/lfe. But it works for stereo/quadro, so whatever.
1271 ENUM_GPR(bass_gpr, 2 * 5), // two sides, five coefficients
1272 ENUM_GPR(treble_gpr, 2 * 5),
1273 ENUM_GPR(bass_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), // four delay stages
1274 ENUM_GPR(treble_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4),
1275 ENUM_GPR(tmp, 3),
1276 num_static_gprs
1277 };
1278 int gpr = num_static_gprs;
1279 u32 ptr, ptr_skip;
1280 struct snd_emu10k1_fx8010_code *icode = NULL;
1281 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1282 u32 *gpr_map;
1283
1284 err = -ENOMEM;
1285 icode = kzalloc_obj(*icode);
1286 if (!icode)
1287 return err;
1288
1289 icode->gpr_map = kzalloc_objs(u_int32_t, 512 + 256 + 256 + 2 * 1024);
1290 if (!icode->gpr_map)
1291 goto __err_gpr;
1292 controls = kzalloc_objs(*controls, SND_EMU10K1_GPR_CONTROLS);
1293 if (!controls)
1294 goto __err_ctrls;
1295
1296 gpr_map = icode->gpr_map;
1297
1298 icode->tram_data_map = icode->gpr_map + 512;
1299 icode->tram_addr_map = icode->tram_data_map + 256;
1300 icode->code = icode->tram_addr_map + 256;
1301
1302 /* clear free GPRs */
1303 memset(icode->gpr_valid, 0xff, 512 / 8);
1304
1305 /* clear TRAM data & address lines */
1306 memset(icode->tram_valid, 0xff, 256 / 8);
1307
1308 strscpy(icode->name, "Audigy DSP code for ALSA");
1309 ptr = 0;
1310 nctl = 0;
1311 gpr_map[bit_shifter16] = 0x00008000;
1312
1313 #if 1
1314 /* PCM front Playback Volume (independent from stereo mix)
1315 * playback = -gpr * FXBUS_PCM_LEFT_FRONT >> 31
1316 * where gpr contains negated attenuation from corresponding mixer control
1317 * (snd_emu10k1_init_stereo_control)
1318 */
1319 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
1320 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
1321 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
1322 gpr += 2;
1323
1324 /* PCM Surround Playback (independent from stereo mix) */
1325 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
1326 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
1327 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
1328 gpr += 2;
1329
1330 /* PCM Side Playback (independent from stereo mix) */
1331 if (emu->card_capabilities->spk71) {
1332 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
1333 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
1334 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
1335 gpr += 2;
1336 }
1337
1338 /* PCM Center Playback (independent from stereo mix) */
1339 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
1340 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
1341 gpr++;
1342
1343 /* PCM LFE Playback (independent from stereo mix) */
1344 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
1345 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
1346 gpr++;
1347
1348 /*
1349 * Stereo Mix
1350 */
1351 /* Wave (PCM) Playback Volume (will be renamed later) */
1352 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1353 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1354 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
1355 gpr += 2;
1356
1357 /* Synth Playback */
1358 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1359 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1360 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
1361 gpr += 2;
1362
1363 /* Wave (PCM) Capture */
1364 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1365 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1366 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
1367 gpr += 2;
1368
1369 /* Synth Capture */
1370 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1371 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1372 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
1373 gpr += 2;
1374
1375 // We need to double the volume, as we configure the voices for half volume,
1376 // which is necessary for bit-identical reproduction.
1377 { static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); }
1378 for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++)
1379 A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000);
1380
1381 /*
1382 * inputs
1383 */
1384 #define A_ADD_VOLUME_IN(var,vol,input) \
1385 A_OP(icode, &ptr, iMAC1, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
1386
1387 if (emu->card_capabilities->emu_model) {
1388 /* EMU1010 DSP 0 and DSP 1 Capture */
1389 // The 24 MSB hold the actual value. We implicitly discard the 16 LSB.
1390 if (emu->card_capabilities->ca0108_chip) {
1391 // For unclear reasons, the EMU32IN cannot be the Y operand!
1392 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A3_EMU32IN(0x0), A_GPR(gpr));
1393 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels
1394 // need to be delayed as well; we use an auxiliary register for that.
1395 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1));
1396 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A3_EMU32IN(0x1), A_C_00000000, A_C_00000000);
1397 } else {
1398 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_P16VIN(0x0), A_GPR(gpr));
1399 // A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
1400 // need to be delayed as well; we use an auxiliary register for that.
1401 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1));
1402 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
1403 }
1404 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
1405 gpr_map[gpr + 2] = 0x00000000;
1406 gpr += 3;
1407 } else {
1408 if (emu->card_capabilities->ac97_chip) {
1409 /* AC'97 Playback Volume - used only for mic (renamed later) */
1410 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
1411 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
1412 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
1413 gpr += 2;
1414 /* AC'97 Capture Volume - used only for mic */
1415 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
1416 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
1417 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
1418 gpr += 2;
1419
1420 /* mic capture buffer */
1421 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R));
1422 }
1423
1424 /* Audigy CD Playback Volume */
1425 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
1426 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1427 snd_emu10k1_init_stereo_control(&controls[nctl++],
1428 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
1429 gpr, 0);
1430 gpr += 2;
1431 /* Audigy CD Capture Volume */
1432 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
1433 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1434 snd_emu10k1_init_stereo_control(&controls[nctl++],
1435 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
1436 gpr, 0);
1437 gpr += 2;
1438
1439 /* Optical SPDIF Playback Volume */
1440 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
1441 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1442 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
1443 gpr += 2;
1444 /* Optical SPDIF Capture Volume */
1445 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
1446 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1447 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
1448 gpr += 2;
1449
1450 /* Line2 Playback Volume */
1451 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
1452 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
1453 snd_emu10k1_init_stereo_control(&controls[nctl++],
1454 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
1455 gpr, 0);
1456 gpr += 2;
1457 /* Line2 Capture Volume */
1458 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
1459 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
1460 snd_emu10k1_init_stereo_control(&controls[nctl++],
1461 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
1462 gpr, 0);
1463 gpr += 2;
1464
1465 /* Philips ADC Playback Volume */
1466 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
1467 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
1468 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
1469 gpr += 2;
1470 /* Philips ADC Capture Volume */
1471 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
1472 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
1473 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
1474 gpr += 2;
1475
1476 /* Aux2 Playback Volume */
1477 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
1478 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
1479 snd_emu10k1_init_stereo_control(&controls[nctl++],
1480 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
1481 gpr, 0);
1482 gpr += 2;
1483 /* Aux2 Capture Volume */
1484 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
1485 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
1486 snd_emu10k1_init_stereo_control(&controls[nctl++],
1487 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
1488 gpr, 0);
1489 gpr += 2;
1490 }
1491
1492 /* Stereo Mix Front Playback Volume */
1493 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
1494 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1495 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
1496 gpr += 2;
1497
1498 /* Stereo Mix Surround Playback */
1499 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
1500 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1501 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
1502 gpr += 2;
1503
1504 /* Stereo Mix Center Playback */
1505 /* Center = sub = Left/2 + Right/2 */
1506 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1));
1507 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
1508 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
1509 gpr++;
1510
1511 /* Stereo Mix LFE Playback */
1512 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
1513 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
1514 gpr++;
1515
1516 if (emu->card_capabilities->spk71) {
1517 /* Stereo Mix Side Playback */
1518 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
1519 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1520 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
1521 gpr += 2;
1522 }
1523
1524 /*
1525 * outputs
1526 */
1527 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
1528 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
1529 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
1530
1531 #define _A_SWITCH(icode, ptr, dst, src, sw) \
1532 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
1533 #define A_SWITCH(icode, ptr, dst, src, sw) \
1534 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
1535 #define _A_SWITCH_NEG(icode, ptr, dst, src) \
1536 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
1537 #define A_SWITCH_NEG(icode, ptr, dst, src) \
1538 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
1539
1540
1541 /*
1542 * Process tone control
1543 */
1544 ctl = &controls[nctl + 0];
1545 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1546 strscpy(ctl->id.name, "Tone Control - Bass");
1547 ctl->vcount = 2;
1548 ctl->count = 10;
1549 ctl->min = 0;
1550 ctl->max = 40;
1551 ctl->value[0] = ctl->value[1] = 20;
1552 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
1553 ctl = &controls[nctl + 1];
1554 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1555 strscpy(ctl->id.name, "Tone Control - Treble");
1556 ctl->vcount = 2;
1557 ctl->count = 10;
1558 ctl->min = 0;
1559 ctl->max = 40;
1560 ctl->value[0] = ctl->value[1] = 20;
1561 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
1562 for (z = 0; z < 5; z++) {
1563 int j;
1564 for (j = 0; j < 2; j++) {
1565 controls[nctl + 0].gpr[z * 2 + j] = bass_gpr + z * 2 + j;
1566 controls[nctl + 1].gpr[z * 2 + j] = treble_gpr + z * 2 + j;
1567 }
1568 }
1569 nctl += 2;
1570
1571 A_OP(icode, &ptr, iACC3, A_C_00000000, A_GPR(gpr), A_C_00000000, A_C_00000000);
1572 snd_emu10k1_init_mono_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
1573 gpr++;
1574 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_CC_REG_ZERO, A_GPR(gpr));
1575 ptr_skip = ptr;
1576 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
1577 int j, k, l, d;
1578 for (j = 0; j < 2; j++) { /* left/right */
1579 k = bass_tmp + (z * 8) + (j * 4);
1580 l = treble_tmp + (z * 8) + (j * 4);
1581 d = playback + z * 2 + j;
1582
1583 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(bass_gpr + 0 + j));
1584 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j));
1585 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j));
1586 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j));
1587 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j));
1588 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
1589
1590 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j));
1591 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(treble_gpr + 4 + j));
1592 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j));
1593 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(treble_gpr + 8 + j));
1594 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(treble_gpr + 6 + j));
1595 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
1596
1597 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
1598
1599 if (z == 2) /* center */
1600 break;
1601 }
1602 }
1603 gpr_map[gpr++] = ptr - ptr_skip;
1604
1605 /* Master volume (will be renamed later) */
1606 for (z = 0; z < 8; z++)
1607 A_OP(icode, &ptr, iMAC1, A_GPR(playback+z), A_C_00000000, A_GPR(gpr), A_GPR(playback+z));
1608 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
1609 gpr++;
1610
1611 if (emu->card_capabilities->emu_model) {
1612 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
1613 dev_info(emu->card->dev, "EMU outputs on\n");
1614 for (z = 0; z < 8; z++) {
1615 if (emu->card_capabilities->ca0108_chip) {
1616 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + z), A_C_00000000, A_C_00000000);
1617 } else {
1618 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + z), A_C_00000000, A_C_00000000);
1619 }
1620 }
1621 } else {
1622 /* analog speakers */
1623 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback);
1624 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2);
1625 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4);
1626 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5);
1627 if (emu->card_capabilities->spk71)
1628 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6);
1629
1630 /* headphone */
1631 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback);
1632
1633 /* IEC958 Optical Raw Playback Switch */
1634 gpr_map[gpr++] = 0;
1635 gpr_map[gpr++] = 0x1008;
1636 gpr_map[gpr++] = 0xffff0000;
1637 for (z = 0; z < 2; z++) {
1638 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
1639 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
1640 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
1641 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
1642 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
1643 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
1644 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
1645 if ((z==1) && (emu->card_capabilities->spdif_bug)) {
1646 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
1647 dev_info(emu->card->dev,
1648 "Installing spdif_bug patch: %s\n",
1649 emu->card_capabilities->name);
1650 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
1651 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1652 } else {
1653 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1654 }
1655 }
1656 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
1657 gpr += 2;
1658
1659 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2);
1660 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4);
1661 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5);
1662 }
1663
1664 /* ADC buffer */
1665 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
1666 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback);
1667 #else
1668 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
1669 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
1670 #endif
1671
1672 if (emu->card_capabilities->emu_model) {
1673 /* Capture 16 channels of S32_LE sound. */
1674 if (emu->card_capabilities->ca0108_chip) {
1675 dev_info(emu->card->dev, "EMU2 inputs on\n");
1676 /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */
1677
1678 snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1679 icode, &ptr, tmp, bit_shifter16, A3_EMU32IN(0), A_FXBUS2(0));
1680 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels
1681 // need to be delayed as well; we use an auxiliary register for that.
1682 for (z = 1; z < 0x10; z++) {
1683 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
1684 bit_shifter16,
1685 A_GPR(gpr),
1686 A_FXBUS2(z*2) );
1687 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A3_EMU32IN(z), A_C_00000000, A_C_00000000);
1688 gpr_map[gpr++] = 0x00000000;
1689 }
1690 } else {
1691 dev_info(emu->card->dev, "EMU inputs on\n");
1692 /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */
1693
1694 /*
1695 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
1696 gpr, tmp);
1697 */
1698 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
1699 /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
1700 * will need to also be delayed; we use an auxiliary register for that. */
1701 for (z = 1; z < 0x10; z++) {
1702 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) );
1703 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000);
1704 gpr_map[gpr++] = 0x00000000;
1705 }
1706 }
1707
1708 #if 0
1709 for (z = 4; z < 8; z++) {
1710 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1711 }
1712 for (z = 0xc; z < 0x10; z++) {
1713 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1714 }
1715 #endif
1716 } else {
1717 /* EFX capture - capture the 16 EXTINs */
1718 /* Capture 16 channels of S16_LE sound */
1719 for (z = 0; z < 16; z++) {
1720 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
1721 }
1722 }
1723
1724 #endif /* JCD test */
1725 /*
1726 * ok, set up done..
1727 */
1728
1729 if (gpr > 512) {
1730 snd_BUG();
1731 err = -EIO;
1732 goto __err;
1733 }
1734
1735 /* clear remaining instruction memory */
1736 while (ptr < 0x400)
1737 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
1738
1739 icode->gpr_add_control_count = nctl;
1740 icode->gpr_add_controls = controls;
1741 emu->support_tlv = 1; /* support TLV */
1742 err = snd_emu10k1_icode_poke(emu, icode, true);
1743 emu->support_tlv = 0; /* clear again */
1744
1745 __err:
1746 kfree(controls);
1747 __err_ctrls:
1748 kfree(icode->gpr_map);
1749 __err_gpr:
1750 kfree(icode);
1751 return err;
1752 }
1753
1754
1755 /*
1756 * initial DSP configuration for Emu10k1
1757 */
1758
1759 /* Volumes are in the [-2^31, 0] range, zero being mute. */
_volume(struct snd_emu10k1_fx8010_code * icode,u32 * ptr,u32 dst,u32 src,u32 vol)1760 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1761 {
1762 OP(icode, ptr, iMAC1, dst, C_00000000, src, vol);
1763 }
_volume_add(struct snd_emu10k1_fx8010_code * icode,u32 * ptr,u32 dst,u32 src,u32 vol)1764 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1765 {
1766 OP(icode, ptr, iMAC1, dst, dst, src, vol);
1767 }
1768
1769 #define VOLUME(icode, ptr, dst, src, vol) \
1770 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1771 #define VOLUME_IN(icode, ptr, dst, src, vol) \
1772 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1773 #define VOLUME_ADD(icode, ptr, dst, src, vol) \
1774 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1775 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
1776 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1777 #define VOLUME_OUT(icode, ptr, dst, src, vol) \
1778 _volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
1779 #define _SWITCH(icode, ptr, dst, src, sw) \
1780 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
1781 #define SWITCH(icode, ptr, dst, src, sw) \
1782 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
1783 #define SWITCH_IN(icode, ptr, dst, src, sw) \
1784 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
1785 #define _SWITCH_NEG(icode, ptr, dst, src) \
1786 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
1787 #define SWITCH_NEG(icode, ptr, dst, src) \
1788 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
1789
1790
_snd_emu10k1_init_efx(struct snd_emu10k1 * emu)1791 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
1792 {
1793 int err, i, z, gpr, tmp, playback, capture;
1794 u32 ptr, ptr_skip;
1795 struct snd_emu10k1_fx8010_code *icode;
1796 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
1797 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1798 u32 *gpr_map;
1799
1800 err = -ENOMEM;
1801 icode = kzalloc_obj(*icode);
1802 if (!icode)
1803 return err;
1804
1805 icode->gpr_map = kzalloc_objs(u_int32_t, 256 + 160 + 160 + 2 * 512);
1806 if (!icode->gpr_map)
1807 goto __err_gpr;
1808
1809 controls = kzalloc_objs(struct snd_emu10k1_fx8010_control_gpr,
1810 SND_EMU10K1_GPR_CONTROLS);
1811 if (!controls)
1812 goto __err_ctrls;
1813
1814 ipcm = kzalloc_obj(*ipcm);
1815 if (!ipcm)
1816 goto __err_ipcm;
1817
1818 gpr_map = icode->gpr_map;
1819
1820 icode->tram_data_map = icode->gpr_map + 256;
1821 icode->tram_addr_map = icode->tram_data_map + 160;
1822 icode->code = icode->tram_addr_map + 160;
1823
1824 /* clear free GPRs */
1825 memset(icode->gpr_valid, 0xff, 256 / 8);
1826
1827 /* clear TRAM data & address lines */
1828 memset(icode->tram_valid, 0xff, 160 / 8);
1829
1830 strscpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
1831 ptr = 0; i = 0;
1832 /* we have 12 inputs */
1833 playback = SND_EMU10K1_INPUTS;
1834 /* we have 6 playback channels and tone control doubles */
1835 capture = playback + SND_EMU10K1_PLAYBACK_CHANNELS;
1836 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
1837 tmp = 0x88; /* we need 4 temporary GPR */
1838 /* from 0x8c to 0xff is the area for tone control */
1839
1840 /*
1841 * Process FX Buses
1842 */
1843 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008);
1844 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008);
1845 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000008);
1846 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000008);
1847 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000008);
1848 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000008);
1849 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000008);
1850 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000008);
1851 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
1852 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
1853 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000008);
1854 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000008);
1855
1856 /* Raw S/PDIF PCM */
1857 ipcm->substream = 0;
1858 ipcm->channels = 2;
1859 ipcm->tram_start = 0;
1860 ipcm->buffer_size = (64 * 1024) / 2;
1861 ipcm->gpr_size = gpr++;
1862 ipcm->gpr_ptr = gpr++;
1863 ipcm->gpr_count = gpr++;
1864 ipcm->gpr_tmpcount = gpr++;
1865 ipcm->gpr_trigger = gpr++;
1866 ipcm->gpr_running = gpr++;
1867 ipcm->etram[0] = 0;
1868 ipcm->etram[1] = 1;
1869
1870 gpr_map[gpr + 0] = 0xfffff000;
1871 gpr_map[gpr + 1] = 0xffff0000;
1872 gpr_map[gpr + 2] = 0x70000000;
1873 gpr_map[gpr + 3] = 0x00000007;
1874 gpr_map[gpr + 4] = 0x001f << 11;
1875 gpr_map[gpr + 5] = 0x001c << 11;
1876 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
1877 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
1878 gpr_map[gpr + 8] = 0x2000000 + (2<<11);
1879 gpr_map[gpr + 9] = 0x4000000 + (2<<11);
1880 gpr_map[gpr + 10] = 1<<11;
1881 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
1882 gpr_map[gpr + 12] = 0;
1883
1884 /* if the trigger flag is not set, skip */
1885 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
1886 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
1887 /* if the running flag is set, we're running */
1888 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
1889 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
1890 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
1891 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
1892 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
1893 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
1894 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
1895
1896 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
1897 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
1898 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
1899 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
1900
1901 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
1902 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1903 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1904 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1905 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
1906
1907 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
1908 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1909 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1910 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1911 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
1912
1913 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
1914 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
1915 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
1916 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
1917 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
1918
1919 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
1920 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1921 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
1922 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
1923 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
1924
1925 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
1926 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
1927
1928 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
1929 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
1930
1931 /* 24: */
1932 gpr += 13;
1933
1934 /* Wave Playback Volume */
1935 for (z = 0; z < 2; z++)
1936 VOLUME(icode, &ptr, playback + z, z, gpr + z);
1937 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
1938 gpr += 2;
1939
1940 /* Wave Surround Playback Volume */
1941 for (z = 0; z < 2; z++)
1942 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
1943 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
1944 gpr += 2;
1945
1946 /* Wave Center/LFE Playback Volume */
1947 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
1948 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000004);
1949 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
1950 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
1951 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
1952 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
1953
1954 /* Wave Capture Volume + Switch */
1955 for (z = 0; z < 2; z++) {
1956 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
1957 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
1958 }
1959 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
1960 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
1961 gpr += 4;
1962
1963 /* Synth Playback Volume */
1964 for (z = 0; z < 2; z++)
1965 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
1966 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
1967 gpr += 2;
1968
1969 /* Synth Capture Volume + Switch */
1970 for (z = 0; z < 2; z++) {
1971 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
1972 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
1973 }
1974 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
1975 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
1976 gpr += 4;
1977
1978 /* Surround Digital Playback Volume (renamed later without Digital) */
1979 for (z = 0; z < 2; z++)
1980 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
1981 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
1982 gpr += 2;
1983
1984 /* Surround Capture Volume + Switch */
1985 for (z = 0; z < 2; z++) {
1986 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
1987 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
1988 }
1989 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
1990 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
1991 gpr += 4;
1992
1993 /* Center Playback Volume (renamed later without Digital) */
1994 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
1995 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
1996
1997 /* LFE Playback Volume + Switch (renamed later without Digital) */
1998 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
1999 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
2000
2001 /* Front Playback Volume */
2002 for (z = 0; z < 2; z++)
2003 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
2004 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
2005 gpr += 2;
2006
2007 /* Front Capture Volume + Switch */
2008 for (z = 0; z < 2; z++) {
2009 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
2010 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2011 }
2012 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
2013 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
2014 gpr += 3;
2015
2016 /*
2017 * Process inputs
2018 */
2019
2020 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
2021 /* AC'97 Playback Volume */
2022 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
2023 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
2024 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
2025 /* AC'97 Capture Volume */
2026 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
2027 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
2028 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
2029 }
2030
2031 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
2032 /* IEC958 TTL Playback Volume */
2033 for (z = 0; z < 2; z++)
2034 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
2035 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
2036 gpr += 2;
2037
2038 /* IEC958 TTL Capture Volume + Switch */
2039 for (z = 0; z < 2; z++) {
2040 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
2041 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2042 }
2043 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
2044 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
2045 gpr += 4;
2046 }
2047
2048 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
2049 /* Zoom Video Playback Volume */
2050 for (z = 0; z < 2; z++)
2051 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
2052 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
2053 gpr += 2;
2054
2055 /* Zoom Video Capture Volume + Switch */
2056 for (z = 0; z < 2; z++) {
2057 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
2058 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2059 }
2060 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
2061 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
2062 gpr += 4;
2063 }
2064
2065 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
2066 /* IEC958 Optical Playback Volume */
2067 for (z = 0; z < 2; z++)
2068 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
2069 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
2070 gpr += 2;
2071
2072 /* IEC958 Optical Capture Volume */
2073 for (z = 0; z < 2; z++) {
2074 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
2075 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2076 }
2077 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
2078 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
2079 gpr += 4;
2080 }
2081
2082 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
2083 /* Line LiveDrive Playback Volume */
2084 for (z = 0; z < 2; z++)
2085 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
2086 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
2087 gpr += 2;
2088
2089 /* Line LiveDrive Capture Volume + Switch */
2090 for (z = 0; z < 2; z++) {
2091 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
2092 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2093 }
2094 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
2095 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
2096 gpr += 4;
2097 }
2098
2099 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
2100 /* IEC958 Coax Playback Volume */
2101 for (z = 0; z < 2; z++)
2102 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
2103 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
2104 gpr += 2;
2105
2106 /* IEC958 Coax Capture Volume + Switch */
2107 for (z = 0; z < 2; z++) {
2108 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
2109 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2110 }
2111 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
2112 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
2113 gpr += 4;
2114 }
2115
2116 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
2117 /* Line LiveDrive Playback Volume */
2118 for (z = 0; z < 2; z++)
2119 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
2120 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
2121 controls[i-1].id.index = 1;
2122 gpr += 2;
2123
2124 /* Line LiveDrive Capture Volume */
2125 for (z = 0; z < 2; z++) {
2126 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
2127 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2128 }
2129 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
2130 controls[i-1].id.index = 1;
2131 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
2132 controls[i-1].id.index = 1;
2133 gpr += 4;
2134 }
2135
2136 /*
2137 * Process tone control
2138 */
2139 ctl = &controls[i + 0];
2140 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
2141 strscpy(ctl->id.name, "Tone Control - Bass");
2142 ctl->vcount = 2;
2143 ctl->count = 10;
2144 ctl->min = 0;
2145 ctl->max = 40;
2146 ctl->value[0] = ctl->value[1] = 20;
2147 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2148 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
2149 ctl = &controls[i + 1];
2150 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
2151 strscpy(ctl->id.name, "Tone Control - Treble");
2152 ctl->vcount = 2;
2153 ctl->count = 10;
2154 ctl->min = 0;
2155 ctl->max = 40;
2156 ctl->value[0] = ctl->value[1] = 20;
2157 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2158 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
2159
2160 #define BASS_GPR 0x8c
2161 #define TREBLE_GPR 0x96
2162
2163 for (z = 0; z < 5; z++) {
2164 int j;
2165 for (j = 0; j < 2; j++) {
2166 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
2167 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
2168 }
2169 }
2170 i += 2;
2171
2172 OP(icode, &ptr, iACC3, C_00000000, GPR(gpr), C_00000000, C_00000000);
2173 snd_emu10k1_init_mono_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
2174 gpr++;
2175 OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr));
2176 ptr_skip = ptr;
2177 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
2178 int j, k, l, d;
2179 for (j = 0; j < 2; j++) { /* left/right */
2180 k = 0xa0 + (z * 8) + (j * 4);
2181 l = 0xd0 + (z * 8) + (j * 4);
2182 d = playback + z * 2 + j;
2183
2184 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
2185 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
2186 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
2187 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
2188 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
2189 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
2190
2191 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
2192 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
2193 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
2194 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
2195 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
2196 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
2197
2198 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
2199
2200 if (z == 2) /* center */
2201 break;
2202 }
2203 }
2204 gpr_map[gpr++] = ptr - ptr_skip;
2205
2206 #undef BASS_GPR
2207 #undef TREBLE_GPR
2208
2209 /*
2210 * Process outputs
2211 */
2212 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
2213 /* AC'97 Playback Volume */
2214
2215 for (z = 0; z < 2; z++)
2216 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + z), C_00000000, C_00000000);
2217 }
2218
2219 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
2220 /* IEC958 Optical Raw Playback Switch */
2221
2222 for (z = 0; z < 2; z++) {
2223 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
2224 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
2225 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2226 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2227 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
2228 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2229 #endif
2230 }
2231
2232 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
2233 gpr += 2;
2234 }
2235
2236 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
2237 /* Headphone Playback Volume */
2238
2239 for (z = 0; z < 2; z++) {
2240 SWITCH(icode, &ptr, tmp + 0, playback + 4 + z, gpr + 2 + z);
2241 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
2242 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2243 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2244 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
2245 }
2246
2247 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
2248 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
2249 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
2250 controls[i-1].id.index = 1;
2251 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
2252 controls[i-1].id.index = 1;
2253
2254 gpr += 4;
2255 }
2256
2257 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
2258 for (z = 0; z < 2; z++)
2259 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000);
2260
2261 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
2262 for (z = 0; z < 2; z++)
2263 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000);
2264
2265 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
2266 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2267 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 4), C_00000000, C_00000000);
2268 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 4), C_00000000, C_00000000);
2269 #else
2270 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 0), C_00000000, C_00000000);
2271 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 0), C_00000000, C_00000000);
2272 #endif
2273 }
2274
2275 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
2276 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2277 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 5), C_00000000, C_00000000);
2278 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 5), C_00000000, C_00000000);
2279 #else
2280 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 1), C_00000000, C_00000000);
2281 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 1), C_00000000, C_00000000);
2282 #endif
2283 }
2284
2285 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
2286 for (z = 0; z < 2; z++)
2287 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
2288 #endif
2289
2290 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
2291 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
2292
2293 /* EFX capture - capture the 16 EXTINS */
2294 if (emu->card_capabilities->sblive51) {
2295 for (z = 0; z < 16; z++) {
2296 s8 c = snd_emu10k1_sblive51_fxbus2_map[z];
2297 if (c != -1)
2298 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(c));
2299 }
2300 } else {
2301 for (z = 0; z < 16; z++)
2302 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2303 }
2304
2305
2306 if (gpr > tmp) {
2307 snd_BUG();
2308 err = -EIO;
2309 goto __err;
2310 }
2311 if (i > SND_EMU10K1_GPR_CONTROLS) {
2312 snd_BUG();
2313 err = -EIO;
2314 goto __err;
2315 }
2316
2317 /* clear remaining instruction memory */
2318 while (ptr < 0x200)
2319 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
2320
2321 err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size);
2322 if (err < 0)
2323 goto __err;
2324 icode->gpr_add_control_count = i;
2325 icode->gpr_add_controls = controls;
2326 emu->support_tlv = 1; /* support TLV */
2327 err = snd_emu10k1_icode_poke(emu, icode, true);
2328 emu->support_tlv = 0; /* clear again */
2329 if (err >= 0)
2330 err = snd_emu10k1_ipcm_poke(emu, ipcm);
2331 __err:
2332 kfree(ipcm);
2333 __err_ipcm:
2334 kfree(controls);
2335 __err_ctrls:
2336 kfree(icode->gpr_map);
2337 __err_gpr:
2338 kfree(icode);
2339 return err;
2340 }
2341
snd_emu10k1_init_efx(struct snd_emu10k1 * emu)2342 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
2343 {
2344 spin_lock_init(&emu->fx8010.irq_lock);
2345 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
2346 if (emu->audigy)
2347 return _snd_emu10k1_audigy_init_efx(emu);
2348 else
2349 return _snd_emu10k1_init_efx(emu);
2350 }
2351
snd_emu10k1_free_efx(struct snd_emu10k1 * emu)2352 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
2353 {
2354 /* stop processor */
2355 if (emu->audigy)
2356 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
2357 else
2358 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
2359 }
2360
2361 #if 0 /* FIXME: who use them? */
2362 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
2363 {
2364 if (output < 0 || output >= 6)
2365 return -EINVAL;
2366 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
2367 return 0;
2368 }
2369
2370 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
2371 {
2372 if (output < 0 || output >= 6)
2373 return -EINVAL;
2374 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
2375 return 0;
2376 }
2377 #endif
2378
snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 * emu,u32 size)2379 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
2380 {
2381 u8 size_reg = 0;
2382
2383 /* size is in samples */
2384 if (size != 0) {
2385 size = (size - 1) >> 13;
2386
2387 while (size) {
2388 size >>= 1;
2389 size_reg++;
2390 }
2391 size = 0x2000 << size_reg;
2392 }
2393 if ((emu->fx8010.etram_pages.bytes / 2) == size)
2394 return 0;
2395 scoped_guard(spinlock_irq, &emu->emu_lock) {
2396 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2397 }
2398 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
2399 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
2400 if (emu->fx8010.etram_pages.area != NULL) {
2401 snd_dma_free_pages(&emu->fx8010.etram_pages);
2402 emu->fx8010.etram_pages.area = NULL;
2403 emu->fx8010.etram_pages.bytes = 0;
2404 }
2405
2406 if (size > 0) {
2407 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev,
2408 size * 2, &emu->fx8010.etram_pages) < 0)
2409 return -ENOMEM;
2410 memset(emu->fx8010.etram_pages.area, 0, size * 2);
2411 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2412 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2413 scoped_guard(spinlock_irq, &emu->emu_lock) {
2414 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2415 }
2416 }
2417
2418 return 0;
2419 }
2420
snd_emu10k1_fx8010_open(struct snd_hwdep * hw,struct file * file)2421 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
2422 {
2423 return 0;
2424 }
2425
copy_string(char * dst,const char * src,const char * null,int idx)2426 static void copy_string(char *dst, const char *src, const char *null, int idx)
2427 {
2428 if (src == NULL)
2429 sprintf(dst, "%s %02X", null, idx);
2430 else
2431 strcpy(dst, src);
2432 }
2433
snd_emu10k1_fx8010_info(struct snd_emu10k1 * emu,struct snd_emu10k1_fx8010_info * info)2434 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
2435 struct snd_emu10k1_fx8010_info *info)
2436 {
2437 const char * const *fxbus, * const *extin, * const *extout;
2438 unsigned short extin_mask, extout_mask;
2439 int res;
2440
2441 info->internal_tram_size = emu->fx8010.itram_size;
2442 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
2443 fxbus = snd_emu10k1_fxbus;
2444 extin = emu->audigy ? snd_emu10k1_audigy_ins : snd_emu10k1_sblive_ins;
2445 extout = emu->audigy ? snd_emu10k1_audigy_outs : snd_emu10k1_sblive_outs;
2446 extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask;
2447 extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask;
2448 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
2449 copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res);
2450 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
2451 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2452 }
2453 for (res = 16; res < 32; res++, extout++)
2454 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2455 info->gpr_controls = emu->fx8010.gpr_count;
2456 }
2457
snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw,struct file * file,unsigned int cmd,unsigned long arg)2458 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
2459 {
2460 struct snd_emu10k1 *emu = hw->private_data;
2461 struct snd_emu10k1_fx8010_info *info;
2462 struct snd_emu10k1_fx8010_code *icode;
2463 struct snd_emu10k1_fx8010_pcm_rec *ipcm;
2464 unsigned int addr;
2465 void __user *argp = (void __user *)arg;
2466 int res;
2467
2468 switch (cmd) {
2469 case SNDRV_EMU10K1_IOCTL_PVERSION:
2470 emu->support_tlv = 1;
2471 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
2472 case SNDRV_EMU10K1_IOCTL_INFO:
2473 info = kzalloc(sizeof(*info), GFP_KERNEL);
2474 if (!info)
2475 return -ENOMEM;
2476 snd_emu10k1_fx8010_info(emu, info);
2477 if (copy_to_user(argp, info, sizeof(*info))) {
2478 kfree(info);
2479 return -EFAULT;
2480 }
2481 kfree(info);
2482 return 0;
2483 case SNDRV_EMU10K1_IOCTL_CODE_POKE:
2484 if (!capable(CAP_SYS_ADMIN))
2485 return -EPERM;
2486
2487 icode = memdup_user(argp, sizeof(*icode));
2488 if (IS_ERR(icode))
2489 return PTR_ERR(icode);
2490 res = snd_emu10k1_icode_poke(emu, icode, false);
2491 kfree(icode);
2492 return res;
2493 case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
2494 icode = memdup_user(argp, sizeof(*icode));
2495 if (IS_ERR(icode))
2496 return PTR_ERR(icode);
2497 res = snd_emu10k1_icode_peek(emu, icode);
2498 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
2499 kfree(icode);
2500 return -EFAULT;
2501 }
2502 kfree(icode);
2503 return res;
2504 case SNDRV_EMU10K1_IOCTL_PCM_POKE:
2505 ipcm = memdup_user(argp, sizeof(*ipcm));
2506 if (IS_ERR(ipcm))
2507 return PTR_ERR(ipcm);
2508 res = snd_emu10k1_ipcm_poke(emu, ipcm);
2509 kfree(ipcm);
2510 return res;
2511 case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
2512 ipcm = memdup_user(argp, sizeof(*ipcm));
2513 if (IS_ERR(ipcm))
2514 return PTR_ERR(ipcm);
2515 res = snd_emu10k1_ipcm_peek(emu, ipcm);
2516 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
2517 kfree(ipcm);
2518 return -EFAULT;
2519 }
2520 kfree(ipcm);
2521 return res;
2522 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
2523 if (!capable(CAP_SYS_ADMIN))
2524 return -EPERM;
2525 if (get_user(addr, (unsigned int __user *)argp))
2526 return -EFAULT;
2527 scoped_guard(mutex, &emu->fx8010.lock) {
2528 res = snd_emu10k1_fx8010_tram_setup(emu, addr);
2529 }
2530 return res;
2531 case SNDRV_EMU10K1_IOCTL_STOP:
2532 if (!capable(CAP_SYS_ADMIN))
2533 return -EPERM;
2534 if (emu->audigy)
2535 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2536 else
2537 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2538 return 0;
2539 case SNDRV_EMU10K1_IOCTL_CONTINUE:
2540 if (!capable(CAP_SYS_ADMIN))
2541 return -EPERM;
2542 if (emu->audigy)
2543 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
2544 else
2545 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
2546 return 0;
2547 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
2548 if (!capable(CAP_SYS_ADMIN))
2549 return -EPERM;
2550 if (emu->audigy)
2551 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
2552 else
2553 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
2554 udelay(10);
2555 if (emu->audigy)
2556 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2557 else
2558 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2559 return 0;
2560 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
2561 if (!capable(CAP_SYS_ADMIN))
2562 return -EPERM;
2563 if (get_user(addr, (unsigned int __user *)argp))
2564 return -EFAULT;
2565 if (emu->audigy) {
2566 if (addr > A_DBG_STEP_ADDR)
2567 return -EINVAL;
2568 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2569 udelay(10);
2570 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr);
2571 } else {
2572 if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR)
2573 return -EINVAL;
2574 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2575 udelay(10);
2576 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr);
2577 }
2578 return 0;
2579 case SNDRV_EMU10K1_IOCTL_DBG_READ:
2580 if (emu->audigy)
2581 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
2582 else
2583 addr = snd_emu10k1_ptr_read(emu, DBG, 0);
2584 if (put_user(addr, (unsigned int __user *)argp))
2585 return -EFAULT;
2586 return 0;
2587 }
2588 return -ENOTTY;
2589 }
2590
snd_emu10k1_fx8010_release(struct snd_hwdep * hw,struct file * file)2591 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
2592 {
2593 return 0;
2594 }
2595
snd_emu10k1_fx8010_new(struct snd_emu10k1 * emu,int device)2596 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
2597 {
2598 struct snd_hwdep *hw;
2599 int err;
2600
2601 err = snd_hwdep_new(emu->card, "FX8010", device, &hw);
2602 if (err < 0)
2603 return err;
2604 strscpy(hw->name, "EMU10K1 (FX8010)");
2605 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
2606 hw->ops.open = snd_emu10k1_fx8010_open;
2607 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
2608 hw->ops.release = snd_emu10k1_fx8010_release;
2609 hw->private_data = emu;
2610 return 0;
2611 }
2612
2613 #ifdef CONFIG_PM_SLEEP
snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 * emu)2614 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
2615 {
2616 int len;
2617
2618 len = emu->audigy ? 0x200 : 0x100;
2619 emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL);
2620 if (! emu->saved_gpr)
2621 return -ENOMEM;
2622 len = emu->audigy ? 0x100 : 0xa0;
2623 emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL);
2624 emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL);
2625 if (! emu->tram_val_saved || ! emu->tram_addr_saved)
2626 return -ENOMEM;
2627 len = emu->audigy ? 2 * 1024 : 2 * 512;
2628 emu->saved_icode = vmalloc(array_size(len, 4));
2629 if (! emu->saved_icode)
2630 return -ENOMEM;
2631 return 0;
2632 }
2633
snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 * emu)2634 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
2635 {
2636 kfree(emu->saved_gpr);
2637 kfree(emu->tram_val_saved);
2638 kfree(emu->tram_addr_saved);
2639 vfree(emu->saved_icode);
2640 }
2641
2642 /*
2643 * save/restore GPR, TRAM and codes
2644 */
snd_emu10k1_efx_suspend(struct snd_emu10k1 * emu)2645 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
2646 {
2647 int i, len;
2648
2649 len = emu->audigy ? 0x200 : 0x100;
2650 for (i = 0; i < len; i++)
2651 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
2652
2653 len = emu->audigy ? 0x100 : 0xa0;
2654 for (i = 0; i < len; i++) {
2655 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
2656 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
2657 if (emu->audigy) {
2658 emu->tram_addr_saved[i] >>= 12;
2659 emu->tram_addr_saved[i] |=
2660 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
2661 }
2662 }
2663
2664 len = emu->audigy ? 2 * 1024 : 2 * 512;
2665 for (i = 0; i < len; i++)
2666 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
2667 }
2668
snd_emu10k1_efx_resume(struct snd_emu10k1 * emu)2669 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
2670 {
2671 int i, len;
2672
2673 /* set up TRAM */
2674 if (emu->fx8010.etram_pages.bytes > 0) {
2675 unsigned size, size_reg = 0;
2676 size = emu->fx8010.etram_pages.bytes / 2;
2677 size = (size - 1) >> 13;
2678 while (size) {
2679 size >>= 1;
2680 size_reg++;
2681 }
2682 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2683 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2684 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2685 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2686 }
2687
2688 if (emu->audigy)
2689 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
2690 else
2691 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
2692
2693 len = emu->audigy ? 0x200 : 0x100;
2694 for (i = 0; i < len; i++)
2695 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
2696
2697 len = emu->audigy ? 0x100 : 0xa0;
2698 for (i = 0; i < len; i++) {
2699 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
2700 emu->tram_val_saved[i]);
2701 if (! emu->audigy)
2702 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2703 emu->tram_addr_saved[i]);
2704 else {
2705 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2706 emu->tram_addr_saved[i] << 12);
2707 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2708 emu->tram_addr_saved[i] >> 20);
2709 }
2710 }
2711
2712 len = emu->audigy ? 2 * 1024 : 2 * 512;
2713 for (i = 0; i < len; i++)
2714 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
2715
2716 /* start FX processor when the DSP code is updated */
2717 if (emu->audigy)
2718 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2719 else
2720 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2721 }
2722 #endif
2723