1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices LTC2947 high precision power and energy monitor 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bits.h> 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/hwmon.h> 12 #include <linux/module.h> 13 #include <linux/math64.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/property.h> 16 #include <linux/regmap.h> 17 18 #include "ltc2947.h" 19 20 /* register's */ 21 #define LTC2947_REG_PAGE_CTRL 0xFF 22 #define LTC2947_REG_CTRL 0xF0 23 #define LTC2947_REG_TBCTL 0xE9 24 #define LTC2947_CONT_MODE_MASK BIT(3) 25 #define LTC2947_CONT_MODE(x) FIELD_PREP(LTC2947_CONT_MODE_MASK, x) 26 #define LTC2947_PRE_MASK GENMASK(2, 0) 27 #define LTC2947_PRE(x) FIELD_PREP(LTC2947_PRE_MASK, x) 28 #define LTC2947_DIV_MASK GENMASK(7, 3) 29 #define LTC2947_DIV(x) FIELD_PREP(LTC2947_DIV_MASK, x) 30 #define LTC2947_SHUTDOWN_MASK BIT(0) 31 #define LTC2947_REG_ACCUM_POL 0xE1 32 #define LTC2947_ACCUM_POL_1_MASK GENMASK(1, 0) 33 #define LTC2947_ACCUM_POL_1(x) FIELD_PREP(LTC2947_ACCUM_POL_1_MASK, x) 34 #define LTC2947_ACCUM_POL_2_MASK GENMASK(3, 2) 35 #define LTC2947_ACCUM_POL_2(x) FIELD_PREP(LTC2947_ACCUM_POL_2_MASK, x) 36 #define LTC2947_REG_ACCUM_DEADBAND 0xE4 37 #define LTC2947_REG_GPIOSTATCTL 0x67 38 #define LTC2947_GPIO_EN_MASK BIT(0) 39 #define LTC2947_GPIO_EN(x) FIELD_PREP(LTC2947_GPIO_EN_MASK, x) 40 #define LTC2947_GPIO_FAN_EN_MASK BIT(6) 41 #define LTC2947_GPIO_FAN_EN(x) FIELD_PREP(LTC2947_GPIO_FAN_EN_MASK, x) 42 #define LTC2947_GPIO_FAN_POL_MASK BIT(7) 43 #define LTC2947_GPIO_FAN_POL(x) FIELD_PREP(LTC2947_GPIO_FAN_POL_MASK, x) 44 #define LTC2947_REG_GPIO_ACCUM 0xE3 45 /* 200Khz */ 46 #define LTC2947_CLK_MIN 200000 47 /* 25Mhz */ 48 #define LTC2947_CLK_MAX 25000000 49 #define LTC2947_PAGE0 0 50 #define LTC2947_PAGE1 1 51 /* Voltage registers */ 52 #define LTC2947_REG_VOLTAGE 0xA0 53 #define LTC2947_REG_VOLTAGE_MAX 0x50 54 #define LTC2947_REG_VOLTAGE_MIN 0x52 55 #define LTC2947_REG_VOLTAGE_THRE_H 0x90 56 #define LTC2947_REG_VOLTAGE_THRE_L 0x92 57 #define LTC2947_REG_DVCC 0xA4 58 #define LTC2947_REG_DVCC_MAX 0x58 59 #define LTC2947_REG_DVCC_MIN 0x5A 60 #define LTC2947_REG_DVCC_THRE_H 0x98 61 #define LTC2947_REG_DVCC_THRE_L 0x9A 62 #define LTC2947_VOLTAGE_GEN_CHAN 0 63 #define LTC2947_VOLTAGE_DVCC_CHAN 1 64 /* in mV */ 65 #define VOLTAGE_MAX 15500 66 #define VOLTAGE_MIN -300 67 #define VDVCC_MAX 15000 68 #define VDVCC_MIN 4750 69 /* Current registers */ 70 #define LTC2947_REG_CURRENT 0x90 71 #define LTC2947_REG_CURRENT_MAX 0x40 72 #define LTC2947_REG_CURRENT_MIN 0x42 73 #define LTC2947_REG_CURRENT_THRE_H 0x80 74 #define LTC2947_REG_CURRENT_THRE_L 0x82 75 /* in mA */ 76 #define CURRENT_MAX 30000 77 #define CURRENT_MIN -30000 78 /* Power registers */ 79 #define LTC2947_REG_POWER 0x93 80 #define LTC2947_REG_POWER_MAX 0x44 81 #define LTC2947_REG_POWER_MIN 0x46 82 #define LTC2947_REG_POWER_THRE_H 0x84 83 #define LTC2947_REG_POWER_THRE_L 0x86 84 /* in uW */ 85 #define POWER_MAX 450000000 86 #define POWER_MIN -450000000 87 /* Temperature registers */ 88 #define LTC2947_REG_TEMP 0xA2 89 #define LTC2947_REG_TEMP_MAX 0x54 90 #define LTC2947_REG_TEMP_MIN 0x56 91 #define LTC2947_REG_TEMP_THRE_H 0x94 92 #define LTC2947_REG_TEMP_THRE_L 0x96 93 #define LTC2947_REG_TEMP_FAN_THRE_H 0x9C 94 #define LTC2947_REG_TEMP_FAN_THRE_L 0x9E 95 #define LTC2947_TEMP_FAN_CHAN 1 96 /* in millidegress Celsius */ 97 #define TEMP_MAX 85000 98 #define TEMP_MIN -40000 99 /* Energy registers */ 100 #define LTC2947_REG_ENERGY1 0x06 101 #define LTC2947_REG_ENERGY2 0x16 102 /* Status/Alarm/Overflow registers */ 103 #define LTC2947_REG_STATUS 0x80 104 #define LTC2947_REG_STATVT 0x81 105 #define LTC2947_REG_STATIP 0x82 106 #define LTC2947_REG_STATVDVCC 0x87 107 108 #define LTC2947_ALERTS_SIZE (LTC2947_REG_STATVDVCC - LTC2947_REG_STATUS) 109 #define LTC2947_MAX_VOLTAGE_MASK BIT(0) 110 #define LTC2947_MIN_VOLTAGE_MASK BIT(1) 111 #define LTC2947_MAX_CURRENT_MASK BIT(0) 112 #define LTC2947_MIN_CURRENT_MASK BIT(1) 113 #define LTC2947_MAX_POWER_MASK BIT(2) 114 #define LTC2947_MIN_POWER_MASK BIT(3) 115 #define LTC2947_MAX_TEMP_MASK BIT(2) 116 #define LTC2947_MIN_TEMP_MASK BIT(3) 117 #define LTC2947_MAX_TEMP_FAN_MASK BIT(4) 118 #define LTC2947_MIN_TEMP_FAN_MASK BIT(5) 119 120 struct ltc2947_data { 121 struct regmap *map; 122 struct device *dev; 123 u32 lsb_energy; 124 bool gpio_out; 125 }; 126 127 static int __ltc2947_val_read16(const struct ltc2947_data *st, const u8 reg, 128 u64 *val) 129 { 130 __be16 __val = 0; 131 int ret; 132 133 ret = regmap_bulk_read(st->map, reg, &__val, 2); 134 if (ret) 135 return ret; 136 137 *val = be16_to_cpu(__val); 138 139 return 0; 140 } 141 142 static int __ltc2947_val_read24(const struct ltc2947_data *st, const u8 reg, 143 u64 *val) 144 { 145 __be32 __val = 0; 146 int ret; 147 148 ret = regmap_bulk_read(st->map, reg, &__val, 3); 149 if (ret) 150 return ret; 151 152 *val = be32_to_cpu(__val) >> 8; 153 154 return 0; 155 } 156 157 static int __ltc2947_val_read64(const struct ltc2947_data *st, const u8 reg, 158 u64 *val) 159 { 160 __be64 __val = 0; 161 int ret; 162 163 ret = regmap_bulk_read(st->map, reg, &__val, 6); 164 if (ret) 165 return ret; 166 167 *val = be64_to_cpu(__val) >> 16; 168 169 return 0; 170 } 171 172 static int ltc2947_val_read(struct ltc2947_data *st, const u8 reg, 173 const u8 page, const size_t size, s64 *val) 174 { 175 int ret; 176 u64 __val = 0; 177 178 ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, page); 179 if (ret) 180 return ret; 181 182 dev_dbg(st->dev, "Read val, reg:%02X, p:%d sz:%zu\n", reg, page, 183 size); 184 185 switch (size) { 186 case 2: 187 ret = __ltc2947_val_read16(st, reg, &__val); 188 break; 189 case 3: 190 ret = __ltc2947_val_read24(st, reg, &__val); 191 break; 192 case 6: 193 ret = __ltc2947_val_read64(st, reg, &__val); 194 break; 195 default: 196 ret = -EINVAL; 197 break; 198 } 199 200 if (ret) 201 return ret; 202 203 *val = sign_extend64(__val, (8 * size) - 1); 204 205 dev_dbg(st->dev, "Got s:%lld, u:%016llX\n", *val, __val); 206 207 return 0; 208 } 209 210 static int __ltc2947_val_write64(const struct ltc2947_data *st, const u8 reg, 211 const u64 val) 212 { 213 __be64 __val; 214 215 __val = cpu_to_be64(val << 16); 216 return regmap_bulk_write(st->map, reg, &__val, 6); 217 } 218 219 static int __ltc2947_val_write16(const struct ltc2947_data *st, const u8 reg, 220 const u16 val) 221 { 222 __be16 __val; 223 224 __val = cpu_to_be16(val); 225 return regmap_bulk_write(st->map, reg, &__val, 2); 226 } 227 228 static int ltc2947_val_write(struct ltc2947_data *st, const u8 reg, 229 const u8 page, const size_t size, const u64 val) 230 { 231 int ret; 232 233 /* set device on correct page */ 234 ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, page); 235 if (ret) 236 return ret; 237 238 dev_dbg(st->dev, "Write val, r:%02X, p:%d, sz:%zu, val:%016llX\n", 239 reg, page, size, val); 240 241 switch (size) { 242 case 2: 243 ret = __ltc2947_val_write16(st, reg, val); 244 break; 245 case 6: 246 ret = __ltc2947_val_write64(st, reg, val); 247 break; 248 default: 249 ret = -EINVAL; 250 break; 251 } 252 253 return ret; 254 } 255 256 static int ltc2947_reset_history(struct ltc2947_data *st, const u8 reg_h, 257 const u8 reg_l) 258 { 259 int ret; 260 /* 261 * let's reset the tracking register's. Tracking register's have all 262 * 2 bytes size 263 */ 264 ret = ltc2947_val_write(st, reg_h, LTC2947_PAGE0, 2, 0x8000U); 265 if (ret) 266 return ret; 267 268 return ltc2947_val_write(st, reg_l, LTC2947_PAGE0, 2, 0x7FFFU); 269 } 270 271 static int ltc2947_alarm_read(struct ltc2947_data *st, const u8 reg, 272 const u32 mask, long *val) 273 { 274 u8 offset = reg - LTC2947_REG_STATUS; 275 /* +1 to include status reg */ 276 char alarms[LTC2947_ALERTS_SIZE + 1]; 277 int ret = 0; 278 279 memset(alarms, 0, sizeof(alarms)); 280 281 ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, LTC2947_PAGE0); 282 if (ret) 283 return ret; 284 285 dev_dbg(st->dev, "Read alarm, reg:%02X, mask:%02X\n", reg, mask); 286 /* 287 * As stated in the datasheet, when Threshold and Overflow registers 288 * are used, the status and all alert registers must be read in one 289 * multi-byte transaction. 290 */ 291 ret = regmap_bulk_read(st->map, LTC2947_REG_STATUS, alarms, 292 sizeof(alarms)); 293 if (ret) 294 return ret; 295 296 /* get the alarm */ 297 *val = !!(alarms[offset] & mask); 298 return 0; 299 } 300 301 static int ltc2947_read_temp(struct device *dev, const u32 attr, long *val, 302 const int channel) 303 { 304 int ret; 305 struct ltc2947_data *st = dev_get_drvdata(dev); 306 s64 __val = 0; 307 308 switch (attr) { 309 case hwmon_temp_input: 310 ret = ltc2947_val_read(st, LTC2947_REG_TEMP, LTC2947_PAGE0, 311 2, &__val); 312 break; 313 case hwmon_temp_highest: 314 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_MAX, LTC2947_PAGE0, 315 2, &__val); 316 break; 317 case hwmon_temp_lowest: 318 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_MIN, LTC2947_PAGE0, 319 2, &__val); 320 break; 321 case hwmon_temp_max_alarm: 322 if (channel == LTC2947_TEMP_FAN_CHAN) 323 return ltc2947_alarm_read(st, LTC2947_REG_STATVT, 324 LTC2947_MAX_TEMP_FAN_MASK, 325 val); 326 327 return ltc2947_alarm_read(st, LTC2947_REG_STATVT, 328 LTC2947_MAX_TEMP_MASK, val); 329 case hwmon_temp_min_alarm: 330 if (channel == LTC2947_TEMP_FAN_CHAN) 331 return ltc2947_alarm_read(st, LTC2947_REG_STATVT, 332 LTC2947_MIN_TEMP_FAN_MASK, 333 val); 334 335 return ltc2947_alarm_read(st, LTC2947_REG_STATVT, 336 LTC2947_MIN_TEMP_MASK, val); 337 case hwmon_temp_max: 338 if (channel == LTC2947_TEMP_FAN_CHAN) 339 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_FAN_THRE_H, 340 LTC2947_PAGE1, 2, &__val); 341 else 342 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_THRE_H, 343 LTC2947_PAGE1, 2, &__val); 344 break; 345 case hwmon_temp_min: 346 if (channel == LTC2947_TEMP_FAN_CHAN) 347 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_FAN_THRE_L, 348 LTC2947_PAGE1, 2, &__val); 349 else 350 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_THRE_L, 351 LTC2947_PAGE1, 2, &__val); 352 break; 353 default: 354 return -ENOTSUPP; 355 } 356 357 if (ret) 358 return ret; 359 360 /* in milidegrees celcius, temp is given by: */ 361 *val = (__val * 204) + 5500; 362 363 return 0; 364 } 365 366 static int ltc2947_read_power(struct device *dev, const u32 attr, long *val) 367 { 368 struct ltc2947_data *st = dev_get_drvdata(dev); 369 int ret; 370 u32 lsb = 200000; /* in uW */ 371 s64 __val = 0; 372 373 switch (attr) { 374 case hwmon_power_input: 375 ret = ltc2947_val_read(st, LTC2947_REG_POWER, LTC2947_PAGE0, 376 3, &__val); 377 lsb = 50000; 378 break; 379 case hwmon_power_input_highest: 380 ret = ltc2947_val_read(st, LTC2947_REG_POWER_MAX, LTC2947_PAGE0, 381 2, &__val); 382 break; 383 case hwmon_power_input_lowest: 384 ret = ltc2947_val_read(st, LTC2947_REG_POWER_MIN, LTC2947_PAGE0, 385 2, &__val); 386 break; 387 case hwmon_power_max_alarm: 388 return ltc2947_alarm_read(st, LTC2947_REG_STATIP, 389 LTC2947_MAX_POWER_MASK, val); 390 case hwmon_power_min_alarm: 391 return ltc2947_alarm_read(st, LTC2947_REG_STATIP, 392 LTC2947_MIN_POWER_MASK, val); 393 case hwmon_power_max: 394 ret = ltc2947_val_read(st, LTC2947_REG_POWER_THRE_H, 395 LTC2947_PAGE1, 2, &__val); 396 break; 397 case hwmon_power_min: 398 ret = ltc2947_val_read(st, LTC2947_REG_POWER_THRE_L, 399 LTC2947_PAGE1, 2, &__val); 400 break; 401 default: 402 return -ENOTSUPP; 403 } 404 405 if (ret) 406 return ret; 407 408 *val = __val * lsb; 409 410 return 0; 411 } 412 413 static int ltc2947_read_curr(struct device *dev, const u32 attr, long *val) 414 { 415 struct ltc2947_data *st = dev_get_drvdata(dev); 416 int ret; 417 u8 lsb = 12; /* in mA */ 418 s64 __val = 0; 419 420 switch (attr) { 421 case hwmon_curr_input: 422 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT, 423 LTC2947_PAGE0, 3, &__val); 424 lsb = 3; 425 break; 426 case hwmon_curr_highest: 427 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_MAX, 428 LTC2947_PAGE0, 2, &__val); 429 break; 430 case hwmon_curr_lowest: 431 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_MIN, 432 LTC2947_PAGE0, 2, &__val); 433 break; 434 case hwmon_curr_max_alarm: 435 return ltc2947_alarm_read(st, LTC2947_REG_STATIP, 436 LTC2947_MAX_CURRENT_MASK, val); 437 case hwmon_curr_min_alarm: 438 return ltc2947_alarm_read(st, LTC2947_REG_STATIP, 439 LTC2947_MIN_CURRENT_MASK, val); 440 case hwmon_curr_max: 441 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_THRE_H, 442 LTC2947_PAGE1, 2, &__val); 443 break; 444 case hwmon_curr_min: 445 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_THRE_L, 446 LTC2947_PAGE1, 2, &__val); 447 break; 448 default: 449 return -ENOTSUPP; 450 } 451 452 if (ret) 453 return ret; 454 455 *val = __val * lsb; 456 457 return 0; 458 } 459 460 static int ltc2947_read_in(struct device *dev, const u32 attr, long *val, 461 const int channel) 462 { 463 struct ltc2947_data *st = dev_get_drvdata(dev); 464 int ret; 465 u8 lsb = 2; /* in mV */ 466 s64 __val = 0; 467 468 if (channel < 0 || channel > LTC2947_VOLTAGE_DVCC_CHAN) { 469 dev_err(st->dev, "Invalid chan%d for voltage", channel); 470 return -EINVAL; 471 } 472 473 switch (attr) { 474 case hwmon_in_input: 475 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) { 476 ret = ltc2947_val_read(st, LTC2947_REG_DVCC, 477 LTC2947_PAGE0, 2, &__val); 478 lsb = 145; 479 } else { 480 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE, 481 LTC2947_PAGE0, 2, &__val); 482 } 483 break; 484 case hwmon_in_highest: 485 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) { 486 ret = ltc2947_val_read(st, LTC2947_REG_DVCC_MAX, 487 LTC2947_PAGE0, 2, &__val); 488 lsb = 145; 489 } else { 490 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_MAX, 491 LTC2947_PAGE0, 2, &__val); 492 } 493 break; 494 case hwmon_in_lowest: 495 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) { 496 ret = ltc2947_val_read(st, LTC2947_REG_DVCC_MIN, 497 LTC2947_PAGE0, 2, &__val); 498 lsb = 145; 499 } else { 500 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_MIN, 501 LTC2947_PAGE0, 2, &__val); 502 } 503 break; 504 case hwmon_in_max_alarm: 505 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) 506 return ltc2947_alarm_read(st, LTC2947_REG_STATVDVCC, 507 LTC2947_MAX_VOLTAGE_MASK, 508 val); 509 510 return ltc2947_alarm_read(st, LTC2947_REG_STATVT, 511 LTC2947_MAX_VOLTAGE_MASK, val); 512 case hwmon_in_min_alarm: 513 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) 514 return ltc2947_alarm_read(st, LTC2947_REG_STATVDVCC, 515 LTC2947_MIN_VOLTAGE_MASK, 516 val); 517 518 return ltc2947_alarm_read(st, LTC2947_REG_STATVT, 519 LTC2947_MIN_VOLTAGE_MASK, val); 520 case hwmon_in_max: 521 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) { 522 ret = ltc2947_val_read(st, LTC2947_REG_DVCC_THRE_H, 523 LTC2947_PAGE1, 2, &__val); 524 lsb = 145; 525 } else { 526 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_THRE_H, 527 LTC2947_PAGE1, 2, &__val); 528 } 529 break; 530 case hwmon_in_min: 531 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) { 532 ret = ltc2947_val_read(st, LTC2947_REG_DVCC_THRE_L, 533 LTC2947_PAGE1, 2, &__val); 534 lsb = 145; 535 } else { 536 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_THRE_L, 537 LTC2947_PAGE1, 2, &__val); 538 } 539 break; 540 default: 541 return -ENOTSUPP; 542 } 543 544 if (ret) 545 return ret; 546 547 *val = __val * lsb; 548 549 return 0; 550 } 551 552 static int ltc2947_read_energy(struct device *dev, s64 *val, const int channel) 553 { 554 int reg = channel ? LTC2947_REG_ENERGY2 : LTC2947_REG_ENERGY1; 555 struct ltc2947_data *st = dev_get_drvdata(dev); 556 s64 __val = 0; 557 int ret; 558 559 ret = ltc2947_val_read(st, reg, LTC2947_PAGE0, 6, &__val); 560 if (ret) 561 return ret; 562 563 /* value in microJoule. st->lsb_energy was multiplied by 10E9 */ 564 *val = DIV_S64_ROUND_CLOSEST(__val * st->lsb_energy, 1000); 565 566 return 0; 567 } 568 569 static int ltc2947_read(struct device *dev, enum hwmon_sensor_types type, 570 u32 attr, int channel, long *val) 571 { 572 switch (type) { 573 case hwmon_in: 574 return ltc2947_read_in(dev, attr, val, channel); 575 case hwmon_curr: 576 return ltc2947_read_curr(dev, attr, val); 577 case hwmon_power: 578 return ltc2947_read_power(dev, attr, val); 579 case hwmon_temp: 580 return ltc2947_read_temp(dev, attr, val, channel); 581 case hwmon_energy64: 582 return ltc2947_read_energy(dev, (s64 *)val, channel); 583 default: 584 return -ENOTSUPP; 585 } 586 } 587 588 static int ltc2947_write_temp(struct device *dev, const u32 attr, 589 long val, const int channel) 590 { 591 struct ltc2947_data *st = dev_get_drvdata(dev); 592 593 if (channel < 0 || channel > LTC2947_TEMP_FAN_CHAN) { 594 dev_err(st->dev, "Invalid chan%d for temperature", channel); 595 return -EINVAL; 596 } 597 598 switch (attr) { 599 case hwmon_temp_reset_history: 600 if (val != 1) 601 return -EINVAL; 602 return ltc2947_reset_history(st, LTC2947_REG_TEMP_MAX, 603 LTC2947_REG_TEMP_MIN); 604 case hwmon_temp_max: 605 val = clamp_val(val, TEMP_MIN, TEMP_MAX); 606 if (channel == LTC2947_TEMP_FAN_CHAN) { 607 if (!st->gpio_out) 608 return -ENOTSUPP; 609 610 return ltc2947_val_write(st, 611 LTC2947_REG_TEMP_FAN_THRE_H, 612 LTC2947_PAGE1, 2, 613 DIV_ROUND_CLOSEST(val - 550, 204)); 614 } 615 616 return ltc2947_val_write(st, LTC2947_REG_TEMP_THRE_H, 617 LTC2947_PAGE1, 2, 618 DIV_ROUND_CLOSEST(val - 550, 204)); 619 case hwmon_temp_min: 620 val = clamp_val(val, TEMP_MIN, TEMP_MAX); 621 if (channel == LTC2947_TEMP_FAN_CHAN) { 622 if (!st->gpio_out) 623 return -ENOTSUPP; 624 625 return ltc2947_val_write(st, 626 LTC2947_REG_TEMP_FAN_THRE_L, 627 LTC2947_PAGE1, 2, 628 DIV_ROUND_CLOSEST(val - 550, 204)); 629 } 630 631 return ltc2947_val_write(st, LTC2947_REG_TEMP_THRE_L, 632 LTC2947_PAGE1, 2, 633 DIV_ROUND_CLOSEST(val - 550, 204)); 634 default: 635 return -ENOTSUPP; 636 } 637 } 638 639 static int ltc2947_write_power(struct device *dev, const u32 attr, 640 long val) 641 { 642 struct ltc2947_data *st = dev_get_drvdata(dev); 643 644 switch (attr) { 645 case hwmon_power_reset_history: 646 if (val != 1) 647 return -EINVAL; 648 return ltc2947_reset_history(st, LTC2947_REG_POWER_MAX, 649 LTC2947_REG_POWER_MIN); 650 case hwmon_power_max: 651 val = clamp_val(val, POWER_MIN, POWER_MAX); 652 return ltc2947_val_write(st, LTC2947_REG_POWER_THRE_H, 653 LTC2947_PAGE1, 2, 654 DIV_ROUND_CLOSEST(val, 200000)); 655 case hwmon_power_min: 656 val = clamp_val(val, POWER_MIN, POWER_MAX); 657 return ltc2947_val_write(st, LTC2947_REG_POWER_THRE_L, 658 LTC2947_PAGE1, 2, 659 DIV_ROUND_CLOSEST(val, 200000)); 660 default: 661 return -ENOTSUPP; 662 } 663 } 664 665 static int ltc2947_write_curr(struct device *dev, const u32 attr, 666 long val) 667 { 668 struct ltc2947_data *st = dev_get_drvdata(dev); 669 670 switch (attr) { 671 case hwmon_curr_reset_history: 672 if (val != 1) 673 return -EINVAL; 674 return ltc2947_reset_history(st, LTC2947_REG_CURRENT_MAX, 675 LTC2947_REG_CURRENT_MIN); 676 case hwmon_curr_max: 677 val = clamp_val(val, CURRENT_MIN, CURRENT_MAX); 678 return ltc2947_val_write(st, LTC2947_REG_CURRENT_THRE_H, 679 LTC2947_PAGE1, 2, 680 DIV_ROUND_CLOSEST(val, 12)); 681 case hwmon_curr_min: 682 val = clamp_val(val, CURRENT_MIN, CURRENT_MAX); 683 return ltc2947_val_write(st, LTC2947_REG_CURRENT_THRE_L, 684 LTC2947_PAGE1, 2, 685 DIV_ROUND_CLOSEST(val, 12)); 686 default: 687 return -ENOTSUPP; 688 } 689 } 690 691 static int ltc2947_write_in(struct device *dev, const u32 attr, long val, 692 const int channel) 693 { 694 struct ltc2947_data *st = dev_get_drvdata(dev); 695 696 if (channel > LTC2947_VOLTAGE_DVCC_CHAN) { 697 dev_err(st->dev, "Invalid chan%d for voltage", channel); 698 return -EINVAL; 699 } 700 701 switch (attr) { 702 case hwmon_in_reset_history: 703 if (val != 1) 704 return -EINVAL; 705 706 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) 707 return ltc2947_reset_history(st, LTC2947_REG_DVCC_MAX, 708 LTC2947_REG_DVCC_MIN); 709 710 return ltc2947_reset_history(st, LTC2947_REG_VOLTAGE_MAX, 711 LTC2947_REG_VOLTAGE_MIN); 712 case hwmon_in_max: 713 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) { 714 val = clamp_val(val, VDVCC_MIN, VDVCC_MAX); 715 return ltc2947_val_write(st, LTC2947_REG_DVCC_THRE_H, 716 LTC2947_PAGE1, 2, 717 DIV_ROUND_CLOSEST(val, 145)); 718 } 719 720 val = clamp_val(val, VOLTAGE_MIN, VOLTAGE_MAX); 721 return ltc2947_val_write(st, LTC2947_REG_VOLTAGE_THRE_H, 722 LTC2947_PAGE1, 2, 723 DIV_ROUND_CLOSEST(val, 2)); 724 case hwmon_in_min: 725 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) { 726 val = clamp_val(val, VDVCC_MIN, VDVCC_MAX); 727 return ltc2947_val_write(st, LTC2947_REG_DVCC_THRE_L, 728 LTC2947_PAGE1, 2, 729 DIV_ROUND_CLOSEST(val, 145)); 730 } 731 732 val = clamp_val(val, VOLTAGE_MIN, VOLTAGE_MAX); 733 return ltc2947_val_write(st, LTC2947_REG_VOLTAGE_THRE_L, 734 LTC2947_PAGE1, 2, 735 DIV_ROUND_CLOSEST(val, 2)); 736 default: 737 return -ENOTSUPP; 738 } 739 } 740 741 static int ltc2947_write(struct device *dev, 742 enum hwmon_sensor_types type, 743 u32 attr, int channel, long val) 744 { 745 switch (type) { 746 case hwmon_in: 747 return ltc2947_write_in(dev, attr, val, channel); 748 case hwmon_curr: 749 return ltc2947_write_curr(dev, attr, val); 750 case hwmon_power: 751 return ltc2947_write_power(dev, attr, val); 752 case hwmon_temp: 753 return ltc2947_write_temp(dev, attr, val, channel); 754 default: 755 return -ENOTSUPP; 756 } 757 } 758 759 static int ltc2947_read_labels(struct device *dev, 760 enum hwmon_sensor_types type, 761 u32 attr, int channel, const char **str) 762 { 763 switch (type) { 764 case hwmon_in: 765 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) 766 *str = "DVCC"; 767 else 768 *str = "VP-VM"; 769 return 0; 770 case hwmon_curr: 771 *str = "IP-IM"; 772 return 0; 773 case hwmon_temp: 774 if (channel == LTC2947_TEMP_FAN_CHAN) 775 *str = "TEMPFAN"; 776 else 777 *str = "Ambient"; 778 return 0; 779 case hwmon_power: 780 *str = "Power"; 781 return 0; 782 default: 783 return -ENOTSUPP; 784 } 785 } 786 787 static int ltc2947_in_is_visible(const u32 attr) 788 { 789 switch (attr) { 790 case hwmon_in_input: 791 case hwmon_in_highest: 792 case hwmon_in_lowest: 793 case hwmon_in_max_alarm: 794 case hwmon_in_min_alarm: 795 case hwmon_in_label: 796 return 0444; 797 case hwmon_in_reset_history: 798 return 0200; 799 case hwmon_in_max: 800 case hwmon_in_min: 801 return 0644; 802 default: 803 return 0; 804 } 805 } 806 807 static int ltc2947_curr_is_visible(const u32 attr) 808 { 809 switch (attr) { 810 case hwmon_curr_input: 811 case hwmon_curr_highest: 812 case hwmon_curr_lowest: 813 case hwmon_curr_max_alarm: 814 case hwmon_curr_min_alarm: 815 case hwmon_curr_label: 816 return 0444; 817 case hwmon_curr_reset_history: 818 return 0200; 819 case hwmon_curr_max: 820 case hwmon_curr_min: 821 return 0644; 822 default: 823 return 0; 824 } 825 } 826 827 static int ltc2947_power_is_visible(const u32 attr) 828 { 829 switch (attr) { 830 case hwmon_power_input: 831 case hwmon_power_input_highest: 832 case hwmon_power_input_lowest: 833 case hwmon_power_label: 834 case hwmon_power_max_alarm: 835 case hwmon_power_min_alarm: 836 return 0444; 837 case hwmon_power_reset_history: 838 return 0200; 839 case hwmon_power_max: 840 case hwmon_power_min: 841 return 0644; 842 default: 843 return 0; 844 } 845 } 846 847 static int ltc2947_temp_is_visible(const u32 attr) 848 { 849 switch (attr) { 850 case hwmon_temp_input: 851 case hwmon_temp_highest: 852 case hwmon_temp_lowest: 853 case hwmon_temp_max_alarm: 854 case hwmon_temp_min_alarm: 855 case hwmon_temp_label: 856 return 0444; 857 case hwmon_temp_reset_history: 858 return 0200; 859 case hwmon_temp_max: 860 case hwmon_temp_min: 861 return 0644; 862 default: 863 return 0; 864 } 865 } 866 867 static umode_t ltc2947_is_visible(const void *data, 868 enum hwmon_sensor_types type, 869 u32 attr, int channel) 870 { 871 switch (type) { 872 case hwmon_in: 873 return ltc2947_in_is_visible(attr); 874 case hwmon_curr: 875 return ltc2947_curr_is_visible(attr); 876 case hwmon_power: 877 return ltc2947_power_is_visible(attr); 878 case hwmon_temp: 879 return ltc2947_temp_is_visible(attr); 880 case hwmon_energy64: 881 return 0444; 882 default: 883 return 0; 884 } 885 } 886 887 static const struct hwmon_channel_info * const ltc2947_info[] = { 888 HWMON_CHANNEL_INFO(in, 889 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 890 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_RESET_HISTORY | 891 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM | 892 HWMON_I_LABEL, 893 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 894 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_RESET_HISTORY | 895 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM | 896 HWMON_I_LABEL), 897 HWMON_CHANNEL_INFO(curr, 898 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | 899 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_RESET_HISTORY | 900 HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM | 901 HWMON_C_LABEL), 902 HWMON_CHANNEL_INFO(power, 903 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | 904 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | 905 HWMON_P_RESET_HISTORY | HWMON_P_MAX_ALARM | 906 HWMON_P_MIN_ALARM | HWMON_P_LABEL), 907 HWMON_CHANNEL_INFO(temp, 908 HWMON_T_INPUT | HWMON_T_LOWEST | HWMON_T_HIGHEST | 909 HWMON_T_MAX | HWMON_T_MIN | HWMON_T_RESET_HISTORY | 910 HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | 911 HWMON_T_LABEL, 912 HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM | HWMON_T_MAX | 913 HWMON_T_MIN | HWMON_T_LABEL), 914 HWMON_CHANNEL_INFO(energy64, 915 HWMON_E_INPUT, 916 HWMON_E_INPUT), 917 NULL 918 }; 919 920 static const struct hwmon_ops ltc2947_hwmon_ops = { 921 .is_visible = ltc2947_is_visible, 922 .read = ltc2947_read, 923 .write = ltc2947_write, 924 .read_string = ltc2947_read_labels, 925 }; 926 927 static const struct hwmon_chip_info ltc2947_chip_info = { 928 .ops = <c2947_hwmon_ops, 929 .info = ltc2947_info, 930 }; 931 932 static int ltc2947_setup(struct ltc2947_data *st) 933 { 934 int ret; 935 struct clk *extclk; 936 u32 dummy, deadband, pol; 937 u32 accum[2]; 938 939 /* clear status register by reading it */ 940 ret = regmap_read(st->map, LTC2947_REG_STATUS, &dummy); 941 if (ret) 942 return ret; 943 /* 944 * Set max/min for power here since the default values x scale 945 * would overflow on 32bit arch 946 */ 947 ret = ltc2947_val_write(st, LTC2947_REG_POWER_THRE_H, LTC2947_PAGE1, 2, 948 POWER_MAX / 200000); 949 if (ret) 950 return ret; 951 952 ret = ltc2947_val_write(st, LTC2947_REG_POWER_THRE_L, LTC2947_PAGE1, 2, 953 POWER_MIN / 200000); 954 if (ret) 955 return ret; 956 957 /* check external clock presence */ 958 extclk = devm_clk_get_optional_enabled(st->dev, NULL); 959 if (IS_ERR(extclk)) 960 return dev_err_probe(st->dev, PTR_ERR(extclk), 961 "Failed to get external clock\n"); 962 963 if (extclk) { 964 unsigned long rate_hz; 965 u8 pre = 0, div, tbctl; 966 u64 aux; 967 968 /* let's calculate and set the right valus in TBCTL */ 969 rate_hz = clk_get_rate(extclk); 970 if (rate_hz < LTC2947_CLK_MIN || rate_hz > LTC2947_CLK_MAX) { 971 dev_err(st->dev, "Invalid rate:%lu for external clock", 972 rate_hz); 973 return -EINVAL; 974 } 975 976 /* as in table 1 of the datasheet */ 977 if (rate_hz >= LTC2947_CLK_MIN && rate_hz <= 1000000) 978 pre = 0; 979 else if (rate_hz > 1000000 && rate_hz <= 2000000) 980 pre = 1; 981 else if (rate_hz > 2000000 && rate_hz <= 4000000) 982 pre = 2; 983 else if (rate_hz > 4000000 && rate_hz <= 8000000) 984 pre = 3; 985 else if (rate_hz > 8000000 && rate_hz <= 16000000) 986 pre = 4; 987 else if (rate_hz > 16000000 && rate_hz <= LTC2947_CLK_MAX) 988 pre = 5; 989 /* 990 * Div is given by: 991 * floor(fref / (2^PRE * 32768)) 992 */ 993 div = rate_hz / ((1 << pre) * 32768); 994 tbctl = LTC2947_PRE(pre) | LTC2947_DIV(div); 995 996 ret = regmap_write(st->map, LTC2947_REG_TBCTL, tbctl); 997 if (ret) 998 return ret; 999 /* 1000 * The energy lsb is given by (in W*s): 1001 * 06416 * (1/fref) * 2^PRE * (DIV + 1) 1002 * The value is multiplied by 10E9 1003 */ 1004 aux = (div + 1) * ((1 << pre) * 641600000ULL); 1005 st->lsb_energy = DIV_ROUND_CLOSEST_ULL(aux, rate_hz); 1006 } else { 1007 /* 19.89E-6 * 10E9 */ 1008 st->lsb_energy = 19890; 1009 } 1010 ret = device_property_read_u32_array(st->dev, "adi,accumulator-ctl-pol", 1011 accum, ARRAY_SIZE(accum)); 1012 if (!ret) { 1013 u32 accum_reg = LTC2947_ACCUM_POL_1(accum[0]) | 1014 LTC2947_ACCUM_POL_2(accum[1]); 1015 1016 ret = regmap_write(st->map, LTC2947_REG_ACCUM_POL, accum_reg); 1017 if (ret) 1018 return ret; 1019 } 1020 ret = device_property_read_u32(st->dev, 1021 "adi,accumulation-deadband-microamp", 1022 &deadband); 1023 if (!ret) { 1024 /* the LSB is the same as the current, so 3mA */ 1025 ret = regmap_write(st->map, LTC2947_REG_ACCUM_DEADBAND, 1026 deadband / (1000 * 3)); 1027 if (ret) 1028 return ret; 1029 } 1030 /* check gpio cfg */ 1031 ret = device_property_read_u32(st->dev, "adi,gpio-out-pol", &pol); 1032 if (!ret) { 1033 /* setup GPIO as output */ 1034 u32 gpio_ctl = LTC2947_GPIO_EN(1) | LTC2947_GPIO_FAN_EN(1) | 1035 LTC2947_GPIO_FAN_POL(pol); 1036 1037 st->gpio_out = true; 1038 ret = regmap_write(st->map, LTC2947_REG_GPIOSTATCTL, gpio_ctl); 1039 if (ret) 1040 return ret; 1041 } 1042 ret = device_property_read_u32_array(st->dev, "adi,gpio-in-accum", 1043 accum, ARRAY_SIZE(accum)); 1044 if (!ret) { 1045 /* 1046 * Setup the accum options. The gpioctl is already defined as 1047 * input by default. 1048 */ 1049 u32 accum_val = LTC2947_ACCUM_POL_1(accum[0]) | 1050 LTC2947_ACCUM_POL_2(accum[1]); 1051 1052 if (st->gpio_out) { 1053 dev_err(st->dev, 1054 "Cannot have input gpio config if already configured as output"); 1055 return -EINVAL; 1056 } 1057 1058 ret = regmap_write(st->map, LTC2947_REG_GPIO_ACCUM, accum_val); 1059 if (ret) 1060 return ret; 1061 } 1062 1063 /* set continuos mode */ 1064 return regmap_update_bits(st->map, LTC2947_REG_CTRL, 1065 LTC2947_CONT_MODE_MASK, LTC2947_CONT_MODE(1)); 1066 } 1067 1068 int ltc2947_core_probe(struct regmap *map, const char *name) 1069 { 1070 struct ltc2947_data *st; 1071 struct device *dev = regmap_get_device(map); 1072 struct device *hwmon; 1073 int ret; 1074 1075 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 1076 if (!st) 1077 return -ENOMEM; 1078 1079 st->map = map; 1080 st->dev = dev; 1081 dev_set_drvdata(dev, st); 1082 1083 ret = ltc2947_setup(st); 1084 if (ret) 1085 return ret; 1086 1087 hwmon = devm_hwmon_device_register_with_info(dev, name, st, 1088 <c2947_chip_info, NULL); 1089 return PTR_ERR_OR_ZERO(hwmon); 1090 } 1091 EXPORT_SYMBOL_GPL(ltc2947_core_probe); 1092 1093 static int ltc2947_resume(struct device *dev) 1094 { 1095 struct ltc2947_data *st = dev_get_drvdata(dev); 1096 u32 ctrl = 0; 1097 int ret; 1098 1099 /* dummy read to wake the device */ 1100 ret = regmap_read(st->map, LTC2947_REG_CTRL, &ctrl); 1101 if (ret) 1102 return ret; 1103 /* 1104 * Wait for the device. It takes 100ms to wake up so, 10ms extra 1105 * should be enough. 1106 */ 1107 msleep(110); 1108 ret = regmap_read(st->map, LTC2947_REG_CTRL, &ctrl); 1109 if (ret) 1110 return ret; 1111 /* ctrl should be 0 */ 1112 if (ctrl != 0) { 1113 dev_err(st->dev, "Device failed to wake up, ctl:%02X\n", ctrl); 1114 return -ETIMEDOUT; 1115 } 1116 1117 /* set continuous mode */ 1118 return regmap_update_bits(st->map, LTC2947_REG_CTRL, 1119 LTC2947_CONT_MODE_MASK, LTC2947_CONT_MODE(1)); 1120 } 1121 1122 static int ltc2947_suspend(struct device *dev) 1123 { 1124 struct ltc2947_data *st = dev_get_drvdata(dev); 1125 1126 return regmap_update_bits(st->map, LTC2947_REG_CTRL, 1127 LTC2947_SHUTDOWN_MASK, 1); 1128 } 1129 1130 EXPORT_SIMPLE_DEV_PM_OPS(ltc2947_pm_ops, ltc2947_suspend, ltc2947_resume); 1131 1132 const struct of_device_id ltc2947_of_match[] = { 1133 { .compatible = "adi,ltc2947" }, 1134 {} 1135 }; 1136 EXPORT_SYMBOL_GPL(ltc2947_of_match); 1137 MODULE_DEVICE_TABLE(of, ltc2947_of_match); 1138 1139 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1140 MODULE_DESCRIPTION("LTC2947 power and energy monitor core driver"); 1141 MODULE_LICENSE("GPL"); 1142