1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 Regents of the University of California
4 */
5
6 #ifndef _ASM_RISCV_PGTABLE_H
7 #define _ASM_RISCV_PGTABLE_H
8
9 #include <linux/mmzone.h>
10 #include <linux/sizes.h>
11
12 #include <asm/pgtable-bits.h>
13
14 #ifndef CONFIG_MMU
15 #ifdef CONFIG_RELOCATABLE
16 #define KERNEL_LINK_ADDR UL(0)
17 #else
18 #define KERNEL_LINK_ADDR _AC(CONFIG_PHYS_RAM_BASE, UL)
19 #endif
20 #define KERN_VIRT_SIZE (UL(-1))
21 #else
22
23 #define ADDRESS_SPACE_END (UL(-1))
24
25 #ifdef CONFIG_64BIT
26 /* Leave 2GB for kernel and BPF at the end of the address space */
27 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1)
28 #else
29 #define KERNEL_LINK_ADDR PAGE_OFFSET
30 #endif
31
32 /* Number of entries in the page global directory */
33 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
34 /* Number of entries in the page table */
35 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t))
36
37 /*
38 * Half of the kernel address space (1/4 of the entries of the page global
39 * directory) is for the direct mapping.
40 */
41 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2)
42
43 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
44 #define VMALLOC_END PAGE_OFFSET
45 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
46
47 #define BPF_JIT_REGION_SIZE (SZ_128M)
48 #ifdef CONFIG_64BIT
49 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE)
50 #define BPF_JIT_REGION_END (MODULES_END)
51 #else
52 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE)
53 #define BPF_JIT_REGION_END (VMALLOC_END)
54 #endif
55
56 /* Modules always live before the kernel */
57 #ifdef CONFIG_64BIT
58 /* This is used to define the end of the KASAN shadow region */
59 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G)
60 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G)
61 #define MODULES_END (PFN_ALIGN((unsigned long)&_start))
62 #else
63 #define MODULES_VADDR VMALLOC_START
64 #define MODULES_END VMALLOC_END
65 #endif
66
67 /*
68 * Roughly size the vmemmap space to be large enough to fit enough
69 * struct pages to map half the virtual address space. Then
70 * position vmemmap directly below the VMALLOC region.
71 */
72 #define VA_BITS_SV32 32
73 #ifdef CONFIG_64BIT
74 #define VA_BITS_SV39 39
75 #define VA_BITS_SV48 48
76 #define VA_BITS_SV57 57
77
78 #define VA_BITS (pgtable_l5_enabled ? \
79 VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39))
80 #else
81 #define VA_BITS VA_BITS_SV32
82 #endif
83
84 #define VMEMMAP_SHIFT \
85 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT)
86 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT)
87 #define VMEMMAP_END VMALLOC_START
88 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE)
89
90 /*
91 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel
92 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled.
93 */
94 #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn)
95
96 #define PCI_IO_SIZE SZ_16M
97 #define PCI_IO_END VMEMMAP_START
98 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
99
100 #define FIXADDR_TOP PCI_IO_START
101 #ifdef CONFIG_64BIT
102 #define MAX_FDT_SIZE PMD_SIZE
103 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M)
104 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE)
105 #else
106 #define MAX_FDT_SIZE PGDIR_SIZE
107 #define FIX_FDT_SIZE MAX_FDT_SIZE
108 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE)
109 #endif
110 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
111
112 #endif
113
114 #ifndef __ASSEMBLER__
115
116 #include <asm/page.h>
117 #include <asm/tlbflush.h>
118 #include <linux/mm_types.h>
119 #include <asm/compat.h>
120 #include <asm/cpufeature.h>
121
122 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT)
123
124 #ifdef CONFIG_64BIT
125 #include <asm/pgtable-64.h>
126
127 #define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1))
128 #define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1))
129 #define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1))
130
131 #define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS)
132 #define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39)
133 #define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64)
134 #define MMAP_MIN_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_MIN_VA_BITS_64)
135 #else
136 #include <asm/pgtable-32.h>
137 #endif /* CONFIG_64BIT */
138
139 #include <linux/page_table_check.h>
140
141 #ifdef CONFIG_XIP_KERNEL
142 #define XIP_FIXUP(addr) ({ \
143 extern char _sdata[], _start[], _end[]; \
144 uintptr_t __rom_start_data = CONFIG_XIP_PHYS_ADDR \
145 + (uintptr_t)&_sdata - (uintptr_t)&_start; \
146 uintptr_t __rom_end_data = CONFIG_XIP_PHYS_ADDR \
147 + (uintptr_t)&_end - (uintptr_t)&_start; \
148 uintptr_t __a = (uintptr_t)(addr); \
149 (__a >= __rom_start_data && __a < __rom_end_data) ? \
150 __a - __rom_start_data + CONFIG_PHYS_RAM_BASE : __a; \
151 })
152 #else
153 #define XIP_FIXUP(addr) (addr)
154 #endif /* CONFIG_XIP_KERNEL */
155
156 struct pt_alloc_ops {
157 pte_t *(*get_pte_virt)(phys_addr_t pa);
158 phys_addr_t (*alloc_pte)(uintptr_t va);
159 #ifndef __PAGETABLE_PMD_FOLDED
160 pmd_t *(*get_pmd_virt)(phys_addr_t pa);
161 phys_addr_t (*alloc_pmd)(uintptr_t va);
162 pud_t *(*get_pud_virt)(phys_addr_t pa);
163 phys_addr_t (*alloc_pud)(uintptr_t va);
164 p4d_t *(*get_p4d_virt)(phys_addr_t pa);
165 phys_addr_t (*alloc_p4d)(uintptr_t va);
166 #endif
167 };
168
169 extern struct pt_alloc_ops pt_ops __meminitdata;
170
171 #ifdef CONFIG_MMU
172 /* Number of PGD entries that a user-mode program can use */
173 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
174
175 /* Page protection bits */
176 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER)
177
178 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ)
179 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ)
180 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE)
181 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC)
182 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
183 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \
184 _PAGE_EXEC | _PAGE_WRITE)
185
186 #define PAGE_COPY PAGE_READ
187 #define PAGE_COPY_EXEC PAGE_READ_EXEC
188 #define PAGE_SHARED PAGE_WRITE
189 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC
190
191 #define _PAGE_KERNEL (_PAGE_READ \
192 | _PAGE_WRITE \
193 | _PAGE_PRESENT \
194 | _PAGE_ACCESSED \
195 | _PAGE_DIRTY \
196 | _PAGE_GLOBAL)
197
198 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
199 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
200 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC)
201 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \
202 | _PAGE_EXEC)
203
204 #define PAGE_TABLE __pgprot(_PAGE_TABLE)
205
206 #define _PAGE_KERNEL_NC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)
207 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
208 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP)
209
210 extern pgd_t swapper_pg_dir[];
211 extern pgd_t trampoline_pg_dir[];
212 extern pgd_t early_pg_dir[];
213
214 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
pmd_present(pmd_t pmd)215 static inline int pmd_present(pmd_t pmd)
216 {
217 /*
218 * Checking for _PAGE_LEAF is needed too because:
219 * When splitting a THP, split_huge_page() will temporarily clear
220 * the present bit, in this situation, pmd_present() and
221 * pmd_trans_huge() still needs to return true.
222 */
223 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF));
224 }
225 #else
pmd_present(pmd_t pmd)226 static inline int pmd_present(pmd_t pmd)
227 {
228 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE));
229 }
230 #endif
231
pmd_none(pmd_t pmd)232 static inline int pmd_none(pmd_t pmd)
233 {
234 return (pmd_val(pmd) == 0);
235 }
236
pmd_bad(pmd_t pmd)237 static inline int pmd_bad(pmd_t pmd)
238 {
239 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF);
240 }
241
242 #define pmd_leaf pmd_leaf
pmd_leaf(pmd_t pmd)243 static inline bool pmd_leaf(pmd_t pmd)
244 {
245 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF);
246 }
247
set_pmd(pmd_t * pmdp,pmd_t pmd)248 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
249 {
250 WRITE_ONCE(*pmdp, pmd);
251 }
252
pmd_clear(pmd_t * pmdp)253 static inline void pmd_clear(pmd_t *pmdp)
254 {
255 set_pmd(pmdp, __pmd(0));
256 }
257
pfn_pgd(unsigned long pfn,pgprot_t prot)258 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot)
259 {
260 unsigned long prot_val = pgprot_val(prot);
261
262 ALT_THEAD_PMA(prot_val);
263
264 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val);
265 }
266
_pgd_pfn(pgd_t pgd)267 static inline unsigned long _pgd_pfn(pgd_t pgd)
268 {
269 return __page_val_to_pfn(pgd_val(pgd));
270 }
271
pmd_page(pmd_t pmd)272 static inline struct page *pmd_page(pmd_t pmd)
273 {
274 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd)));
275 }
276
pmd_page_vaddr(pmd_t pmd)277 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
278 {
279 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd)));
280 }
281
pmd_pte(pmd_t pmd)282 static inline pte_t pmd_pte(pmd_t pmd)
283 {
284 return __pte(pmd_val(pmd));
285 }
286
pud_pte(pud_t pud)287 static inline pte_t pud_pte(pud_t pud)
288 {
289 return __pte(pud_val(pud));
290 }
291
292 #ifdef CONFIG_RISCV_ISA_SVNAPOT
293
has_svnapot(void)294 static __always_inline bool has_svnapot(void)
295 {
296 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT);
297 }
298
pte_napot(pte_t pte)299 static inline unsigned long pte_napot(pte_t pte)
300 {
301 return pte_val(pte) & _PAGE_NAPOT;
302 }
303
pte_mknapot(pte_t pte,unsigned int order)304 static inline pte_t pte_mknapot(pte_t pte, unsigned int order)
305 {
306 int pos = order - 1 + _PAGE_PFN_SHIFT;
307 unsigned long napot_bit = BIT(pos);
308 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT);
309
310 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT);
311 }
312
313 #else
314
has_svnapot(void)315 static __always_inline bool has_svnapot(void) { return false; }
316
pte_napot(pte_t pte)317 static inline unsigned long pte_napot(pte_t pte)
318 {
319 return 0;
320 }
321
322 #endif /* CONFIG_RISCV_ISA_SVNAPOT */
323
324 /* Yields the page frame number (PFN) of a page table entry */
pte_pfn(pte_t pte)325 static inline unsigned long pte_pfn(pte_t pte)
326 {
327 unsigned long res = __page_val_to_pfn(pte_val(pte));
328
329 if (has_svnapot() && pte_napot(pte))
330 res = res & (res - 1UL);
331
332 return res;
333 }
334
335 #define pte_page(x) pfn_to_page(pte_pfn(x))
336
337 /* Constructs a page table entry */
pfn_pte(unsigned long pfn,pgprot_t prot)338 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
339 {
340 unsigned long prot_val = pgprot_val(prot);
341
342 ALT_THEAD_PMA(prot_val);
343
344 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val);
345 }
346
347 #define pte_pgprot pte_pgprot
pte_pgprot(pte_t pte)348 static inline pgprot_t pte_pgprot(pte_t pte)
349 {
350 unsigned long pfn = pte_pfn(pte);
351
352 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte));
353 }
354
pte_present(pte_t pte)355 static inline int pte_present(pte_t pte)
356 {
357 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE));
358 }
359
360 #define pte_accessible pte_accessible
pte_accessible(struct mm_struct * mm,pte_t a)361 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a)
362 {
363 if (pte_val(a) & _PAGE_PRESENT)
364 return true;
365
366 if ((pte_val(a) & _PAGE_PROT_NONE) &&
367 atomic_read(&mm->tlb_flush_pending))
368 return true;
369
370 return false;
371 }
372
pte_none(pte_t pte)373 static inline int pte_none(pte_t pte)
374 {
375 return (pte_val(pte) == 0);
376 }
377
pte_write(pte_t pte)378 static inline int pte_write(pte_t pte)
379 {
380 return pte_val(pte) & _PAGE_WRITE;
381 }
382
pte_exec(pte_t pte)383 static inline int pte_exec(pte_t pte)
384 {
385 return pte_val(pte) & _PAGE_EXEC;
386 }
387
pte_user(pte_t pte)388 static inline int pte_user(pte_t pte)
389 {
390 return pte_val(pte) & _PAGE_USER;
391 }
392
pte_huge(pte_t pte)393 static inline int pte_huge(pte_t pte)
394 {
395 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF);
396 }
397
pte_dirty(pte_t pte)398 static inline int pte_dirty(pte_t pte)
399 {
400 return pte_val(pte) & _PAGE_DIRTY;
401 }
402
pte_young(pte_t pte)403 static inline int pte_young(pte_t pte)
404 {
405 return pte_val(pte) & _PAGE_ACCESSED;
406 }
407
pte_special(pte_t pte)408 static inline int pte_special(pte_t pte)
409 {
410 return pte_val(pte) & _PAGE_SPECIAL;
411 }
412
413 /* static inline pte_t pte_rdprotect(pte_t pte) */
414
pte_wrprotect(pte_t pte)415 static inline pte_t pte_wrprotect(pte_t pte)
416 {
417 return __pte(pte_val(pte) & ~(_PAGE_WRITE));
418 }
419
420 /* static inline pte_t pte_mkread(pte_t pte) */
421
pte_mkwrite_novma(pte_t pte)422 static inline pte_t pte_mkwrite_novma(pte_t pte)
423 {
424 return __pte(pte_val(pte) | _PAGE_WRITE);
425 }
426
427 /* static inline pte_t pte_mkexec(pte_t pte) */
428
pte_mkdirty(pte_t pte)429 static inline pte_t pte_mkdirty(pte_t pte)
430 {
431 return __pte(pte_val(pte) | _PAGE_DIRTY);
432 }
433
pte_mkclean(pte_t pte)434 static inline pte_t pte_mkclean(pte_t pte)
435 {
436 return __pte(pte_val(pte) & ~(_PAGE_DIRTY));
437 }
438
pte_mkyoung(pte_t pte)439 static inline pte_t pte_mkyoung(pte_t pte)
440 {
441 return __pte(pte_val(pte) | _PAGE_ACCESSED);
442 }
443
pte_mkold(pte_t pte)444 static inline pte_t pte_mkold(pte_t pte)
445 {
446 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED));
447 }
448
pte_mkspecial(pte_t pte)449 static inline pte_t pte_mkspecial(pte_t pte)
450 {
451 return __pte(pte_val(pte) | _PAGE_SPECIAL);
452 }
453
pte_mkhuge(pte_t pte)454 static inline pte_t pte_mkhuge(pte_t pte)
455 {
456 return pte;
457 }
458
459 #ifdef CONFIG_RISCV_ISA_SVNAPOT
460 #define pte_leaf_size(pte) (pte_napot(pte) ? \
461 napot_cont_size(napot_cont_order(pte)) :\
462 PAGE_SIZE)
463 #endif
464
465 #ifdef CONFIG_NUMA_BALANCING
466 /*
467 * See the comment in include/asm-generic/pgtable.h
468 */
pte_protnone(pte_t pte)469 static inline int pte_protnone(pte_t pte)
470 {
471 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE;
472 }
473
pmd_protnone(pmd_t pmd)474 static inline int pmd_protnone(pmd_t pmd)
475 {
476 return pte_protnone(pmd_pte(pmd));
477 }
478 #endif
479
480 /* Modify page protection bits */
pte_modify(pte_t pte,pgprot_t newprot)481 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
482 {
483 unsigned long newprot_val = pgprot_val(newprot);
484
485 ALT_THEAD_PMA(newprot_val);
486
487 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val);
488 }
489
490 #define pgd_ERROR(e) \
491 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e))
492
493
494 /* Commit new configuration to MMU hardware */
update_mmu_cache_range(struct vm_fault * vmf,struct vm_area_struct * vma,unsigned long address,pte_t * ptep,unsigned int nr)495 static inline void update_mmu_cache_range(struct vm_fault *vmf,
496 struct vm_area_struct *vma, unsigned long address,
497 pte_t *ptep, unsigned int nr)
498 {
499 asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1)
500 : : : : svvptc);
501
502 /*
503 * The kernel assumes that TLBs don't cache invalid entries, but
504 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a
505 * cache flush; it is necessary even after writing invalid entries.
506 * Relying on flush_tlb_fix_spurious_fault would suffice, but
507 * the extra traps reduce performance. So, eagerly SFENCE.VMA.
508 */
509 while (nr--)
510 local_flush_tlb_page(address + nr * PAGE_SIZE);
511
512 svvptc:;
513 /*
514 * Svvptc guarantees that the new valid pte will be visible within
515 * a bounded timeframe, so when the uarch does not cache invalid
516 * entries, we don't have to do anything.
517 */
518 }
519 #define update_mmu_cache(vma, addr, ptep) \
520 update_mmu_cache_range(NULL, vma, addr, ptep, 1)
521
522 #define update_mmu_tlb_range(vma, addr, ptep, nr) \
523 update_mmu_cache_range(NULL, vma, addr, ptep, nr)
524
update_mmu_cache_pmd(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)525 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
526 unsigned long address, pmd_t *pmdp)
527 {
528 pte_t *ptep = (pte_t *)pmdp;
529
530 update_mmu_cache(vma, address, ptep);
531 }
532
533 #define __HAVE_ARCH_PTE_SAME
pte_same(pte_t pte_a,pte_t pte_b)534 static inline int pte_same(pte_t pte_a, pte_t pte_b)
535 {
536 return pte_val(pte_a) == pte_val(pte_b);
537 }
538
539 /*
540 * Certain architectures need to do special things when PTEs within
541 * a page table are directly modified. Thus, the following hook is
542 * made available.
543 */
set_pte(pte_t * ptep,pte_t pteval)544 static inline void set_pte(pte_t *ptep, pte_t pteval)
545 {
546 WRITE_ONCE(*ptep, pteval);
547 }
548
549 void flush_icache_pte(struct mm_struct *mm, pte_t pte);
550
__set_pte_at(struct mm_struct * mm,pte_t * ptep,pte_t pteval)551 static inline void __set_pte_at(struct mm_struct *mm, pte_t *ptep, pte_t pteval)
552 {
553 if (pte_present(pteval) && pte_exec(pteval))
554 flush_icache_pte(mm, pteval);
555
556 set_pte(ptep, pteval);
557 }
558
559 #define PFN_PTE_SHIFT _PAGE_PFN_SHIFT
560
set_ptes(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pteval,unsigned int nr)561 static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
562 pte_t *ptep, pte_t pteval, unsigned int nr)
563 {
564 page_table_check_ptes_set(mm, ptep, pteval, nr);
565
566 for (;;) {
567 __set_pte_at(mm, ptep, pteval);
568 if (--nr == 0)
569 break;
570 ptep++;
571 pte_val(pteval) += 1 << _PAGE_PFN_SHIFT;
572 }
573 }
574 #define set_ptes set_ptes
575
pte_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)576 static inline void pte_clear(struct mm_struct *mm,
577 unsigned long addr, pte_t *ptep)
578 {
579 __set_pte_at(mm, ptep, __pte(0));
580 }
581
582 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* defined in mm/pgtable.c */
583 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
584 pte_t *ptep, pte_t entry, int dirty);
585 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG /* defined in mm/pgtable.c */
586 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long address,
587 pte_t *ptep);
588
589 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long address,pte_t * ptep)590 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
591 unsigned long address, pte_t *ptep)
592 {
593 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0));
594
595 page_table_check_pte_clear(mm, pte);
596
597 return pte;
598 }
599
600 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long address,pte_t * ptep)601 static inline void ptep_set_wrprotect(struct mm_struct *mm,
602 unsigned long address, pte_t *ptep)
603 {
604 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep);
605 }
606
607 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
ptep_clear_flush_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)608 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
609 unsigned long address, pte_t *ptep)
610 {
611 /*
612 * This comment is borrowed from x86, but applies equally to RISC-V:
613 *
614 * Clearing the accessed bit without a TLB flush
615 * doesn't cause data corruption. [ It could cause incorrect
616 * page aging and the (mistaken) reclaim of hot pages, but the
617 * chance of that should be relatively low. ]
618 *
619 * So as a performance optimization don't flush the TLB when
620 * clearing the accessed bit, it will eventually be flushed by
621 * a context switch or a VM operation anyway. [ In the rare
622 * event of it not getting flushed for a long time the delay
623 * shouldn't really matter because there's no real memory
624 * pressure for swapout to react to. ]
625 */
626 return ptep_test_and_clear_young(vma, address, ptep);
627 }
628
629 #define pgprot_nx pgprot_nx
pgprot_nx(pgprot_t _prot)630 static inline pgprot_t pgprot_nx(pgprot_t _prot)
631 {
632 return __pgprot(pgprot_val(_prot) & ~_PAGE_EXEC);
633 }
634
635 #define pgprot_noncached pgprot_noncached
pgprot_noncached(pgprot_t _prot)636 static inline pgprot_t pgprot_noncached(pgprot_t _prot)
637 {
638 unsigned long prot = pgprot_val(_prot);
639
640 prot &= ~_PAGE_MTMASK;
641 prot |= _PAGE_IO;
642
643 return __pgprot(prot);
644 }
645
646 #define pgprot_writecombine pgprot_writecombine
pgprot_writecombine(pgprot_t _prot)647 static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
648 {
649 unsigned long prot = pgprot_val(_prot);
650
651 prot &= ~_PAGE_MTMASK;
652 prot |= _PAGE_NOCACHE;
653
654 return __pgprot(prot);
655 }
656
657 /*
658 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
659 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
660 * DT.
661 */
662 #define arch_has_hw_pte_young arch_has_hw_pte_young
arch_has_hw_pte_young(void)663 static inline bool arch_has_hw_pte_young(void)
664 {
665 return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
666 }
667
668 /*
669 * THP functions
670 */
pte_pmd(pte_t pte)671 static inline pmd_t pte_pmd(pte_t pte)
672 {
673 return __pmd(pte_val(pte));
674 }
675
pte_pud(pte_t pte)676 static inline pud_t pte_pud(pte_t pte)
677 {
678 return __pud(pte_val(pte));
679 }
680
pmd_mkhuge(pmd_t pmd)681 static inline pmd_t pmd_mkhuge(pmd_t pmd)
682 {
683 return pmd;
684 }
685
pmd_mkinvalid(pmd_t pmd)686 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
687 {
688 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE));
689 }
690
691 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT)
692
pmd_pfn(pmd_t pmd)693 static inline unsigned long pmd_pfn(pmd_t pmd)
694 {
695 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT);
696 }
697
698 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT)
699
700 #define pud_pfn pud_pfn
pud_pfn(pud_t pud)701 static inline unsigned long pud_pfn(pud_t pud)
702 {
703 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT);
704 }
705
706 #define pmd_pgprot pmd_pgprot
pmd_pgprot(pmd_t pmd)707 static inline pgprot_t pmd_pgprot(pmd_t pmd)
708 {
709 return pte_pgprot(pmd_pte(pmd));
710 }
711
712 #define pud_pgprot pud_pgprot
pud_pgprot(pud_t pud)713 static inline pgprot_t pud_pgprot(pud_t pud)
714 {
715 return pte_pgprot(pud_pte(pud));
716 }
717
pmd_modify(pmd_t pmd,pgprot_t newprot)718 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
719 {
720 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
721 }
722
723 #define pmd_write pmd_write
pmd_write(pmd_t pmd)724 static inline int pmd_write(pmd_t pmd)
725 {
726 return pte_write(pmd_pte(pmd));
727 }
728
729 #define pud_write pud_write
pud_write(pud_t pud)730 static inline int pud_write(pud_t pud)
731 {
732 return pte_write(pud_pte(pud));
733 }
734
735 #define pmd_dirty pmd_dirty
pmd_dirty(pmd_t pmd)736 static inline int pmd_dirty(pmd_t pmd)
737 {
738 return pte_dirty(pmd_pte(pmd));
739 }
740
741 #define pmd_young pmd_young
pmd_young(pmd_t pmd)742 static inline int pmd_young(pmd_t pmd)
743 {
744 return pte_young(pmd_pte(pmd));
745 }
746
pmd_user(pmd_t pmd)747 static inline int pmd_user(pmd_t pmd)
748 {
749 return pte_user(pmd_pte(pmd));
750 }
751
pmd_mkold(pmd_t pmd)752 static inline pmd_t pmd_mkold(pmd_t pmd)
753 {
754 return pte_pmd(pte_mkold(pmd_pte(pmd)));
755 }
756
pmd_mkyoung(pmd_t pmd)757 static inline pmd_t pmd_mkyoung(pmd_t pmd)
758 {
759 return pte_pmd(pte_mkyoung(pmd_pte(pmd)));
760 }
761
pmd_mkwrite_novma(pmd_t pmd)762 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd)
763 {
764 return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)));
765 }
766
pmd_wrprotect(pmd_t pmd)767 static inline pmd_t pmd_wrprotect(pmd_t pmd)
768 {
769 return pte_pmd(pte_wrprotect(pmd_pte(pmd)));
770 }
771
pmd_mkclean(pmd_t pmd)772 static inline pmd_t pmd_mkclean(pmd_t pmd)
773 {
774 return pte_pmd(pte_mkclean(pmd_pte(pmd)));
775 }
776
pmd_mkdirty(pmd_t pmd)777 static inline pmd_t pmd_mkdirty(pmd_t pmd)
778 {
779 return pte_pmd(pte_mkdirty(pmd_pte(pmd)));
780 }
781
782 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP
pmd_special(pmd_t pmd)783 static inline bool pmd_special(pmd_t pmd)
784 {
785 return pte_special(pmd_pte(pmd));
786 }
787
pmd_mkspecial(pmd_t pmd)788 static inline pmd_t pmd_mkspecial(pmd_t pmd)
789 {
790 return pte_pmd(pte_mkspecial(pmd_pte(pmd)));
791 }
792 #endif
793
794 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP
pud_special(pud_t pud)795 static inline bool pud_special(pud_t pud)
796 {
797 return pte_special(pud_pte(pud));
798 }
799
pud_mkspecial(pud_t pud)800 static inline pud_t pud_mkspecial(pud_t pud)
801 {
802 return pte_pud(pte_mkspecial(pud_pte(pud)));
803 }
804 #endif
805
set_pmd_at(struct mm_struct * mm,unsigned long addr,pmd_t * pmdp,pmd_t pmd)806 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
807 pmd_t *pmdp, pmd_t pmd)
808 {
809 page_table_check_pmd_set(mm, pmdp, pmd);
810 return __set_pte_at(mm, (pte_t *)pmdp, pmd_pte(pmd));
811 }
812
set_pud_at(struct mm_struct * mm,unsigned long addr,pud_t * pudp,pud_t pud)813 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
814 pud_t *pudp, pud_t pud)
815 {
816 page_table_check_pud_set(mm, pudp, pud);
817 return __set_pte_at(mm, (pte_t *)pudp, pud_pte(pud));
818 }
819
820 #ifdef CONFIG_PAGE_TABLE_CHECK
pte_user_accessible_page(pte_t pte)821 static inline bool pte_user_accessible_page(pte_t pte)
822 {
823 return pte_present(pte) && pte_user(pte);
824 }
825
pmd_user_accessible_page(pmd_t pmd)826 static inline bool pmd_user_accessible_page(pmd_t pmd)
827 {
828 return pmd_leaf(pmd) && pmd_user(pmd);
829 }
830
pud_user_accessible_page(pud_t pud)831 static inline bool pud_user_accessible_page(pud_t pud)
832 {
833 return pud_leaf(pud) && pud_user(pud);
834 }
835 #endif
836
837 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
pmd_trans_huge(pmd_t pmd)838 static inline int pmd_trans_huge(pmd_t pmd)
839 {
840 return pmd_leaf(pmd);
841 }
842
843 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
pmdp_set_access_flags(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t entry,int dirty)844 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
845 unsigned long address, pmd_t *pmdp,
846 pmd_t entry, int dirty)
847 {
848 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
849 }
850
851 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
pmdp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)852 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
853 unsigned long address, pmd_t *pmdp)
854 {
855 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
856 }
857
858 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
pmdp_huge_get_and_clear(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)859 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
860 unsigned long address, pmd_t *pmdp)
861 {
862 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0));
863
864 page_table_check_pmd_clear(mm, pmd);
865
866 return pmd;
867 }
868
869 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
pmdp_set_wrprotect(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)870 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
871 unsigned long address, pmd_t *pmdp)
872 {
873 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
874 }
875
876 #define pmdp_establish pmdp_establish
pmdp_establish(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t pmd)877 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
878 unsigned long address, pmd_t *pmdp, pmd_t pmd)
879 {
880 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd);
881 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd)));
882 }
883
884 #define pmdp_collapse_flush pmdp_collapse_flush
885 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
886 unsigned long address, pmd_t *pmdp);
887
pud_wrprotect(pud_t pud)888 static inline pud_t pud_wrprotect(pud_t pud)
889 {
890 return pte_pud(pte_wrprotect(pud_pte(pud)));
891 }
892
pud_trans_huge(pud_t pud)893 static inline int pud_trans_huge(pud_t pud)
894 {
895 return pud_leaf(pud);
896 }
897
pud_dirty(pud_t pud)898 static inline int pud_dirty(pud_t pud)
899 {
900 return pte_dirty(pud_pte(pud));
901 }
902
pud_mkyoung(pud_t pud)903 static inline pud_t pud_mkyoung(pud_t pud)
904 {
905 return pte_pud(pte_mkyoung(pud_pte(pud)));
906 }
907
pud_mkold(pud_t pud)908 static inline pud_t pud_mkold(pud_t pud)
909 {
910 return pte_pud(pte_mkold(pud_pte(pud)));
911 }
912
pud_mkdirty(pud_t pud)913 static inline pud_t pud_mkdirty(pud_t pud)
914 {
915 return pte_pud(pte_mkdirty(pud_pte(pud)));
916 }
917
pud_mkclean(pud_t pud)918 static inline pud_t pud_mkclean(pud_t pud)
919 {
920 return pte_pud(pte_mkclean(pud_pte(pud)));
921 }
922
pud_mkwrite(pud_t pud)923 static inline pud_t pud_mkwrite(pud_t pud)
924 {
925 return pte_pud(pte_mkwrite_novma(pud_pte(pud)));
926 }
927
pud_mkhuge(pud_t pud)928 static inline pud_t pud_mkhuge(pud_t pud)
929 {
930 return pud;
931 }
932
pudp_set_access_flags(struct vm_area_struct * vma,unsigned long address,pud_t * pudp,pud_t entry,int dirty)933 static inline int pudp_set_access_flags(struct vm_area_struct *vma,
934 unsigned long address, pud_t *pudp,
935 pud_t entry, int dirty)
936 {
937 return ptep_set_access_flags(vma, address, (pte_t *)pudp, pud_pte(entry), dirty);
938 }
939
pudp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pud_t * pudp)940 static inline int pudp_test_and_clear_young(struct vm_area_struct *vma,
941 unsigned long address, pud_t *pudp)
942 {
943 return ptep_test_and_clear_young(vma, address, (pte_t *)pudp);
944 }
945
946 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
pudp_huge_get_and_clear(struct mm_struct * mm,unsigned long address,pud_t * pudp)947 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
948 unsigned long address, pud_t *pudp)
949 {
950 #ifdef CONFIG_SMP
951 pud_t pud = __pud(xchg(&pudp->pud, 0));
952 #else
953 pud_t pud = *pudp;
954
955 pud_clear(pudp);
956 #endif
957
958 page_table_check_pud_clear(mm, pud);
959
960 return pud;
961 }
962
pud_young(pud_t pud)963 static inline int pud_young(pud_t pud)
964 {
965 return pte_young(pud_pte(pud));
966 }
967
update_mmu_cache_pud(struct vm_area_struct * vma,unsigned long address,pud_t * pudp)968 static inline void update_mmu_cache_pud(struct vm_area_struct *vma,
969 unsigned long address, pud_t *pudp)
970 {
971 pte_t *ptep = (pte_t *)pudp;
972
973 update_mmu_cache(vma, address, ptep);
974 }
975
pudp_establish(struct vm_area_struct * vma,unsigned long address,pud_t * pudp,pud_t pud)976 static inline pud_t pudp_establish(struct vm_area_struct *vma,
977 unsigned long address, pud_t *pudp, pud_t pud)
978 {
979 page_table_check_pud_set(vma->vm_mm, pudp, pud);
980 return __pud(atomic_long_xchg((atomic_long_t *)pudp, pud_val(pud)));
981 }
982
pud_mkinvalid(pud_t pud)983 static inline pud_t pud_mkinvalid(pud_t pud)
984 {
985 return __pud(pud_val(pud) & ~(_PAGE_PRESENT | _PAGE_PROT_NONE));
986 }
987
988 extern pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address,
989 pud_t *pudp);
990
pud_modify(pud_t pud,pgprot_t newprot)991 static inline pud_t pud_modify(pud_t pud, pgprot_t newprot)
992 {
993 return pte_pud(pte_modify(pud_pte(pud), newprot));
994 }
995
996 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
997
998 /*
999 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
1000 * are !pte_none() && !pte_present().
1001 *
1002 * Format of swap PTE:
1003 * bit 0: _PAGE_PRESENT (zero)
1004 * bit 1 to 3: _PAGE_LEAF (zero)
1005 * bit 5: _PAGE_PROT_NONE (zero)
1006 * bit 6: exclusive marker
1007 * bits 7 to 11: swap type
1008 * bits 12 to XLEN-1: swap offset
1009 */
1010 #define __SWP_TYPE_SHIFT 7
1011 #define __SWP_TYPE_BITS 5
1012 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1)
1013 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
1014
1015 #define MAX_SWAPFILES_CHECK() \
1016 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
1017
1018 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
1019 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
1020 #define __swp_entry(type, offset) ((swp_entry_t) \
1021 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
1022 ((offset) << __SWP_OFFSET_SHIFT) })
1023
1024 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1025 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1026
pte_swp_exclusive(pte_t pte)1027 static inline bool pte_swp_exclusive(pte_t pte)
1028 {
1029 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
1030 }
1031
pte_swp_mkexclusive(pte_t pte)1032 static inline pte_t pte_swp_mkexclusive(pte_t pte)
1033 {
1034 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE);
1035 }
1036
pte_swp_clear_exclusive(pte_t pte)1037 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
1038 {
1039 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE);
1040 }
1041
1042 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1043 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
1044 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
1045 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
1046
1047 /*
1048 * In the RV64 Linux scheme, we give the user half of the virtual-address space
1049 * and give the kernel the other (upper) half.
1050 */
1051 #ifdef CONFIG_64BIT
1052 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE)
1053 #else
1054 #define KERN_VIRT_START FIXADDR_START
1055 #endif
1056
1057 /*
1058 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32.
1059 * Note that PGDIR_SIZE must evenly divide TASK_SIZE.
1060 * Task size is:
1061 * - 0x9fc00000 (~2.5GB) for RV32.
1062 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu
1063 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu
1064 * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu
1065 *
1066 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V
1067 * Instruction Set Manual Volume II: Privileged Architecture" states that
1068 * "load and store effective addresses, which are 64bits, must have bits
1069 * 63–48 all equal to bit 47, or else a page-fault exception will occur."
1070 * Similarly for SV57, bits 63–57 must be equal to bit 56.
1071 */
1072 #ifdef CONFIG_64BIT
1073 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2)
1074
1075 #ifdef CONFIG_COMPAT
1076 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE)
1077 #define TASK_SIZE (is_compat_task() ? \
1078 TASK_SIZE_32 : TASK_SIZE_64)
1079 #else
1080 #define TASK_SIZE TASK_SIZE_64
1081 #endif
1082
1083 #else
1084 #define TASK_SIZE FIXADDR_START
1085 #endif
1086
1087 #else /* CONFIG_MMU */
1088
1089 #define PAGE_SHARED __pgprot(0)
1090 #define PAGE_KERNEL __pgprot(0)
1091 #define swapper_pg_dir NULL
1092 #define TASK_SIZE _AC(-1, UL)
1093 #define VMALLOC_START _AC(0, UL)
1094 #define VMALLOC_END TASK_SIZE
1095
1096 #endif /* !CONFIG_MMU */
1097
1098 extern char _start[];
1099 extern void *_dtb_early_va;
1100 extern uintptr_t _dtb_early_pa;
1101 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU)
1102 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va))
1103 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa))
1104 #else
1105 #define dtb_early_va _dtb_early_va
1106 #define dtb_early_pa _dtb_early_pa
1107 #endif /* CONFIG_XIP_KERNEL */
1108 extern u64 satp_mode;
1109
1110 void paging_init(void);
1111 void misc_mem_init(void);
1112
1113 /*
1114 * ZERO_PAGE is a global shared page that is always zero,
1115 * used for zero-mapped memory areas, etc.
1116 */
1117 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
1118 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
1119
1120 /*
1121 * Use set_p*_safe(), and elide TLB flushing, when confident that *no*
1122 * TLB flush will be required as a result of the "set". For example, use
1123 * in scenarios where it is known ahead of time that the routine is
1124 * setting non-present entries, or re-setting an existing entry to the
1125 * same value. Otherwise, use the typical "set" helpers and flush the
1126 * TLB.
1127 */
1128 #define set_p4d_safe(p4dp, p4d) \
1129 ({ \
1130 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \
1131 set_p4d(p4dp, p4d); \
1132 })
1133
1134 #define set_pgd_safe(pgdp, pgd) \
1135 ({ \
1136 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \
1137 set_pgd(pgdp, pgd); \
1138 })
1139 #endif /* !__ASSEMBLER__ */
1140
1141 #endif /* _ASM_RISCV_PGTABLE_H */
1142