1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* HWMON driver for Aquantia PHY
3 *
4 * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
5 * Author: Andrew Lunn <andrew@lunn.ch>
6 * Author: Heiner Kallweit <hkallweit1@gmail.com>
7 */
8
9 #ifndef AQUANTIA_H
10 #define AQUANTIA_H
11
12 #include <linux/device.h>
13 #include <linux/phy.h>
14
15 /* Vendor specific 1, MDIO_MMD_VEND1 */
16 #define VEND1_GLOBAL_SC 0x0
17 #define VEND1_GLOBAL_SC_SOFT_RESET BIT(15)
18 #define VEND1_GLOBAL_SC_LOW_POWER BIT(11)
19
20 #define VEND1_GLOBAL_FW_ID 0x0020
21 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
22 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
23
24 #define VEND1_GLOBAL_MAILBOX_INTERFACE1 0x0200
25 #define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE BIT(15)
26 #define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE BIT(14)
27 #define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET BIT(12)
28 #define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY BIT(8)
29
30 #define VEND1_GLOBAL_MAILBOX_INTERFACE2 0x0201
31 #define VEND1_GLOBAL_MAILBOX_INTERFACE3 0x0202
32 #define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK GENMASK(15, 0)
33 #define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK, (u16)((x) >> 16))
34 #define VEND1_GLOBAL_MAILBOX_INTERFACE4 0x0203
35 #define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK GENMASK(15, 2)
36 #define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK, (u16)(x))
37
38 #define VEND1_GLOBAL_MAILBOX_INTERFACE5 0x0204
39 #define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK GENMASK(15, 0)
40 #define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK, (u16)((x) >> 16))
41 #define VEND1_GLOBAL_MAILBOX_INTERFACE6 0x0205
42 #define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK GENMASK(15, 0)
43 #define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK, (u16)(x))
44
45 /* The following registers all have similar layouts; first the registers... */
46 #define VEND1_GLOBAL_CFG_10M 0x0310
47 #define VEND1_GLOBAL_CFG_100M 0x031b
48 #define VEND1_GLOBAL_CFG_1G 0x031c
49 #define VEND1_GLOBAL_CFG_2_5G 0x031d
50 #define VEND1_GLOBAL_CFG_5G 0x031e
51 #define VEND1_GLOBAL_CFG_10G 0x031f
52 /* ...and now the fields */
53 #define VEND1_GLOBAL_CFG_SERDES_MODE GENMASK(2, 0)
54 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI 0
55 #define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII 3
56 #define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII 4
57 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G 6
58 #define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
59 #define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
60 #define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
61 #define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
62
63 /* Vendor specific 1, MDIO_MMD_VEND2 */
64 #define VEND1_GLOBAL_CONTROL2 0xc001
65 #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST BIT(15)
66 #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD BIT(6)
67 #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL BIT(0)
68
69 #define VEND1_GLOBAL_LED_PROV 0xc430
70 #define AQR_LED_PROV(x) (VEND1_GLOBAL_LED_PROV + (x))
71 #define VEND1_GLOBAL_LED_PROV_LINK2500 BIT(14)
72 #define VEND1_GLOBAL_LED_PROV_LINK5000 BIT(15)
73 #define VEND1_GLOBAL_LED_PROV_FORCE_ON BIT(8)
74 #define VEND1_GLOBAL_LED_PROV_LINK10000 BIT(7)
75 #define VEND1_GLOBAL_LED_PROV_LINK1000 BIT(6)
76 #define VEND1_GLOBAL_LED_PROV_LINK100 BIT(5)
77 #define VEND1_GLOBAL_LED_PROV_RX_ACT BIT(3)
78 #define VEND1_GLOBAL_LED_PROV_TX_ACT BIT(2)
79 #define VEND1_GLOBAL_LED_PROV_ACT_STRETCH GENMASK(0, 1)
80
81 #define VEND1_GLOBAL_LED_PROV_LINK_MASK (VEND1_GLOBAL_LED_PROV_LINK100 | \
82 VEND1_GLOBAL_LED_PROV_LINK1000 | \
83 VEND1_GLOBAL_LED_PROV_LINK10000 | \
84 VEND1_GLOBAL_LED_PROV_LINK5000 | \
85 VEND1_GLOBAL_LED_PROV_LINK2500)
86
87 #define VEND1_GLOBAL_LED_DRIVE 0xc438
88 #define VEND1_GLOBAL_LED_DRIVE_VDD BIT(1)
89 #define AQR_LED_DRIVE(x) (VEND1_GLOBAL_LED_DRIVE + (x))
90
91 #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
92 #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
93 #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
94 #define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
95 #define VEND1_THERMAL_STAT1 0xc820
96 #define VEND1_THERMAL_STAT2 0xc821
97 #define VEND1_THERMAL_STAT2_VALID BIT(0)
98 #define VEND1_GENERAL_STAT1 0xc830
99 #define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
100 #define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
101 #define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
102 #define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
103
104 #define VEND1_GLOBAL_GEN_STAT2 0xc831
105 #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
106
107 #define VEND1_GLOBAL_RSVD_STAT1 0xc885
108 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
109 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
110
111 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d
112 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
113 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
114
115 /* MDIO_MMD_C22EXT */
116 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
117 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
118 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
119 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
120 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
121 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
122 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
123 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
124 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
125 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
126
127 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
128 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
129
130 #define VEND1_GLOBAL_INT_STD_MASK 0xff00
131 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
132 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
133 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
134 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
135 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
136 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
137 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
138 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
139 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
140 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
141 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
142
143 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01
144 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
145 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
146 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
147 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
148 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
149 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
150 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
151 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
152
153 #define AQR_MAX_LEDS 3
154
155 struct aqr107_hw_stat {
156 const char *name;
157 int reg;
158 int size;
159 };
160
161 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
162 static const struct aqr107_hw_stat aqr107_hw_stats[] = {
163 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
164 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
165 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
166 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
167 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
168 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
169 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
170 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
171 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
172 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
173 };
174
175 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
176
177 struct aqr107_priv {
178 u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
179 unsigned long leds_active_low;
180 };
181
182 #if IS_REACHABLE(CONFIG_HWMON)
183 int aqr_hwmon_probe(struct phy_device *phydev);
184 #else
aqr_hwmon_probe(struct phy_device * phydev)185 static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
186 #endif
187
188 int aqr_firmware_load(struct phy_device *phydev);
189
190 int aqr_phy_led_blink_set(struct phy_device *phydev, u8 index,
191 unsigned long *delay_on,
192 unsigned long *delay_off);
193 int aqr_phy_led_brightness_set(struct phy_device *phydev,
194 u8 index, enum led_brightness value);
195 int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
196 unsigned long rules);
197 int aqr_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
198 unsigned long *rules);
199 int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
200 unsigned long rules);
201 int aqr_phy_led_active_low_set(struct phy_device *phydev, int index, bool enable);
202 int aqr_phy_led_polarity_set(struct phy_device *phydev, int index,
203 unsigned long modes);
204 int aqr_wait_reset_complete(struct phy_device *phydev);
205
206 #endif /* AQUANTIA_H */
207