1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for IDT Versaclock 5
4 *
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8 /*
9 * Possible optimizations:
10 * - Use spread spectrum
11 * - Use integer divider in FOD if applicable
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/property.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25
26 #include <dt-bindings/clock/versaclock.h>
27
28 /* VersaClock5 registers */
29 #define VC5_OTP_CONTROL 0x00
30
31 /* Factory-reserved register block */
32 #define VC5_RSVD_DEVICE_ID 0x01
33 #define VC5_RSVD_ADC_GAIN_7_0 0x02
34 #define VC5_RSVD_ADC_GAIN_15_8 0x03
35 #define VC5_RSVD_ADC_OFFSET_7_0 0x04
36 #define VC5_RSVD_ADC_OFFSET_15_8 0x05
37 #define VC5_RSVD_TEMPY 0x06
38 #define VC5_RSVD_OFFSET_TBIN 0x07
39 #define VC5_RSVD_GAIN 0x08
40 #define VC5_RSVD_TEST_NP 0x09
41 #define VC5_RSVD_UNUSED 0x0a
42 #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
43 #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
44 #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
45 #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
46 #define VC5_RSVD_CLK_AMP_123 0x0f
47
48 /* Configuration register block */
49 #define VC5_PRIM_SRC_SHDN 0x10
50 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
51 #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
52 #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
53 #define VC5_PRIM_SRC_SHDN_SP BIT(1)
54 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
55
56 #define VC5_VCO_BAND 0x11
57 #define VC5_XTAL_X1_LOAD_CAP 0x12
58 #define VC5_XTAL_X2_LOAD_CAP 0x13
59 #define VC5_REF_DIVIDER 0x15
60 #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
61 #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
62
63 #define VC5_VCO_CTRL_AND_PREDIV 0x16
64 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
65
66 #define VC5_FEEDBACK_INT_DIV 0x17
67 #define VC5_FEEDBACK_INT_DIV_BITS 0x18
68 #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
69 #define VC5_RC_CONTROL0 0x1e
70 #define VC5_RC_CONTROL1 0x1f
71
72 /* These registers are named "Unused Factory Reserved Registers" */
73 #define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10))
74 #define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */
75
76 /* Output divider control for divider 1,2,3,4 */
77 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
78 #define VC5_OUT_DIV_CONTROL_RESET BIT(7)
79 #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
80 #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
81 #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
82 #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
83
84 #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
85 #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
86
87 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
88 #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
89 #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
90 #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
91 #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
92
93 /* Clock control register for clock 1,2 */
94 #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
95 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
96 #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
97
98 #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
99 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
100 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
101 #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
102 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
103 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
104 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
105
106 #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
107 #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
108 #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
109 #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
110 #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
111 #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
112 #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
113 #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
114 #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
115 #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
116 #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
117 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
118
119 #define VC5_CLK_OE_SHDN 0x68
120 #define VC5_CLK_OS_SHDN 0x69
121
122 #define VC5_GLOBAL_REGISTER 0x76
123 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
124
125 /* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */
126 #define VC5_PLL_VCO_MIN 2500000000UL
127
128 /* VC5 Input mux settings */
129 #define VC5_MUX_IN_XIN BIT(0)
130 #define VC5_MUX_IN_CLKIN BIT(1)
131
132 /* Maximum number of clk_out supported by this driver */
133 #define VC5_MAX_CLK_OUT_NUM 5
134
135 /* Maximum number of FODs supported by this driver */
136 #define VC5_MAX_FOD_NUM 4
137
138 /* flags to describe chip features */
139 /* chip has built-in oscillator */
140 #define VC5_HAS_INTERNAL_XTAL BIT(0)
141 /* chip has PFD requency doubler */
142 #define VC5_HAS_PFD_FREQ_DBL BIT(1)
143 /* chip has bits to disable FOD sync */
144 #define VC5_HAS_BYPASS_SYNC_BIT BIT(2)
145
146 /* Supported IDT VC5 models. */
147 enum vc5_model {
148 IDT_VC5_5P49V5923,
149 IDT_VC5_5P49V5925,
150 IDT_VC5_5P49V5933,
151 IDT_VC5_5P49V5935,
152 IDT_VC6_5P49V60,
153 IDT_VC6_5P49V6901,
154 IDT_VC6_5P49V6965,
155 IDT_VC6_5P49V6975,
156 };
157
158 /* Structure to describe features of a particular VC5 model */
159 struct vc5_chip_info {
160 const enum vc5_model model;
161 const unsigned int clk_fod_cnt;
162 const unsigned int clk_out_cnt;
163 const u32 flags;
164 const unsigned long vco_max;
165 };
166
167 struct vc5_driver_data;
168
169 struct vc5_hw_data {
170 struct clk_hw hw;
171 struct vc5_driver_data *vc5;
172 u32 div_int;
173 u32 div_frc;
174 unsigned int num;
175 };
176
177 struct vc5_out_data {
178 struct clk_hw hw;
179 struct vc5_driver_data *vc5;
180 unsigned int num;
181 unsigned int clk_output_cfg0;
182 unsigned int clk_output_cfg0_mask;
183 };
184
185 struct vc5_driver_data {
186 struct i2c_client *client;
187 struct regmap *regmap;
188 const struct vc5_chip_info *chip_info;
189
190 struct clk *pin_xin;
191 struct clk *pin_clkin;
192 unsigned char clk_mux_ins;
193 struct clk_hw clk_mux;
194 struct clk_hw clk_mul;
195 struct clk_hw clk_pfd;
196 struct vc5_hw_data clk_pll;
197 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
198 struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM];
199 };
200
201 /*
202 * VersaClock5 i2c regmap
203 */
vc5_regmap_is_writeable(struct device * dev,unsigned int reg)204 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
205 {
206 /* Factory reserved regs, make them read-only */
207 if (reg <= 0xf)
208 return false;
209
210 /* Factory reserved regs, make them read-only */
211 if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
212 return false;
213
214 return true;
215 }
216
217 static const struct regmap_config vc5_regmap_config = {
218 .reg_bits = 8,
219 .val_bits = 8,
220 .cache_type = REGCACHE_MAPLE,
221 .max_register = 0x76,
222 .writeable_reg = vc5_regmap_is_writeable,
223 };
224
225 /*
226 * VersaClock5 input multiplexer between XTAL and CLKIN divider
227 */
vc5_mux_get_parent(struct clk_hw * hw)228 static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
229 {
230 struct vc5_driver_data *vc5 =
231 container_of(hw, struct vc5_driver_data, clk_mux);
232 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
233 unsigned int src;
234 int ret;
235
236 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
237 if (ret)
238 return 0;
239
240 src &= mask;
241
242 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
243 return 0;
244
245 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
246 return 1;
247
248 dev_warn(&vc5->client->dev,
249 "Invalid clock input configuration (%02x)\n", src);
250 return 0;
251 }
252
vc5_mux_set_parent(struct clk_hw * hw,u8 index)253 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
254 {
255 struct vc5_driver_data *vc5 =
256 container_of(hw, struct vc5_driver_data, clk_mux);
257 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
258 u8 src;
259
260 if ((index > 1) || !vc5->clk_mux_ins)
261 return -EINVAL;
262
263 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
264 if (index == 0)
265 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
266 if (index == 1)
267 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
268 } else {
269 if (index != 0)
270 return -EINVAL;
271
272 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
273 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
274 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
275 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
276 else /* Invalid; should have been caught by vc5_probe() */
277 return -EINVAL;
278 }
279
280 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
281 }
282
283 static const struct clk_ops vc5_mux_ops = {
284 .determine_rate = clk_hw_determine_rate_no_reparent,
285 .set_parent = vc5_mux_set_parent,
286 .get_parent = vc5_mux_get_parent,
287 };
288
vc5_dbl_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)289 static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
290 unsigned long parent_rate)
291 {
292 struct vc5_driver_data *vc5 =
293 container_of(hw, struct vc5_driver_data, clk_mul);
294 unsigned int premul;
295 int ret;
296
297 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
298 if (ret)
299 return 0;
300
301 if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
302 parent_rate *= 2;
303
304 return parent_rate;
305 }
306
vc5_dbl_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)307 static int vc5_dbl_determine_rate(struct clk_hw *hw,
308 struct clk_rate_request *req)
309 {
310 if ((req->best_parent_rate == req->rate) || ((req->best_parent_rate * 2) == req->rate))
311 return 0;
312 else
313 return -EINVAL;
314 }
315
vc5_dbl_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)316 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
317 unsigned long parent_rate)
318 {
319 struct vc5_driver_data *vc5 =
320 container_of(hw, struct vc5_driver_data, clk_mul);
321 u32 mask;
322
323 if ((parent_rate * 2) == rate)
324 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
325 else
326 mask = 0;
327
328 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
329 VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
330 mask);
331 }
332
333 static const struct clk_ops vc5_dbl_ops = {
334 .recalc_rate = vc5_dbl_recalc_rate,
335 .determine_rate = vc5_dbl_determine_rate,
336 .set_rate = vc5_dbl_set_rate,
337 };
338
vc5_pfd_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)339 static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
340 unsigned long parent_rate)
341 {
342 struct vc5_driver_data *vc5 =
343 container_of(hw, struct vc5_driver_data, clk_pfd);
344 unsigned int prediv, div;
345 int ret;
346
347 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
348 if (ret)
349 return 0;
350
351 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
352 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
353 return parent_rate;
354
355 ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
356 if (ret)
357 return 0;
358
359 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
360 if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
361 return parent_rate / 2;
362 else
363 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
364 }
365
vc5_pfd_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)366 static int vc5_pfd_determine_rate(struct clk_hw *hw,
367 struct clk_rate_request *req)
368 {
369 unsigned long idiv;
370
371 /* PLL cannot operate with input clock above 50 MHz. */
372 if (req->rate > 50000000)
373 return -EINVAL;
374
375 /* CLKIN within range of PLL input, feed directly to PLL. */
376 if (req->best_parent_rate <= 50000000) {
377 req->rate = req->best_parent_rate;
378
379 return 0;
380 }
381
382 idiv = DIV_ROUND_UP(req->best_parent_rate, req->rate);
383 if (idiv > 127)
384 return -EINVAL;
385
386 req->rate = req->best_parent_rate / idiv;
387
388 return 0;
389 }
390
vc5_pfd_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)391 static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
392 unsigned long parent_rate)
393 {
394 struct vc5_driver_data *vc5 =
395 container_of(hw, struct vc5_driver_data, clk_pfd);
396 unsigned long idiv;
397 int ret;
398 u8 div;
399
400 /* CLKIN within range of PLL input, feed directly to PLL. */
401 if (parent_rate <= 50000000) {
402 ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
403 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
404 if (ret)
405 return ret;
406
407 return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
408 }
409
410 idiv = DIV_ROUND_UP(parent_rate, rate);
411
412 /* We have dedicated div-2 predivider. */
413 if (idiv == 2)
414 div = VC5_REF_DIVIDER_SEL_PREDIV2;
415 else
416 div = VC5_REF_DIVIDER_REF_DIV(idiv);
417
418 ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
419 if (ret)
420 return ret;
421
422 return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
423 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
424 }
425
426 static const struct clk_ops vc5_pfd_ops = {
427 .recalc_rate = vc5_pfd_recalc_rate,
428 .determine_rate = vc5_pfd_determine_rate,
429 .set_rate = vc5_pfd_set_rate,
430 };
431
432 /*
433 * VersaClock5 PLL/VCO
434 */
vc5_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)435 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
436 unsigned long parent_rate)
437 {
438 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
439 struct vc5_driver_data *vc5 = hwdata->vc5;
440 u32 div_int, div_frc;
441 u8 fb[5];
442
443 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
444
445 div_int = (fb[0] << 4) | (fb[1] >> 4);
446 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
447
448 /* The PLL divider has 12 integer bits and 24 fractional bits */
449 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
450 }
451
vc5_pll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)452 static int vc5_pll_determine_rate(struct clk_hw *hw,
453 struct clk_rate_request *req)
454 {
455 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
456 struct vc5_driver_data *vc5 = hwdata->vc5;
457 u32 div_int;
458 u64 div_frc;
459
460 req->rate = clamp(req->rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max);
461
462 /* Determine integer part, which is 12 bit wide */
463 div_int = req->rate / req->best_parent_rate;
464 if (div_int > 0xfff)
465 req->rate = req->best_parent_rate * 0xfff;
466
467 /* Determine best fractional part, which is 24 bit wide */
468 div_frc = req->rate % req->best_parent_rate;
469 div_frc *= BIT(24) - 1;
470 do_div(div_frc, req->best_parent_rate);
471
472 hwdata->div_int = div_int;
473 hwdata->div_frc = (u32)div_frc;
474
475 req->rate = (req->best_parent_rate * div_int) + ((req->best_parent_rate * div_frc) >> 24);
476
477 return 0;
478 }
479
vc5_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)480 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
481 unsigned long parent_rate)
482 {
483 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
484 struct vc5_driver_data *vc5 = hwdata->vc5;
485 u8 fb[5];
486
487 fb[0] = hwdata->div_int >> 4;
488 fb[1] = hwdata->div_int << 4;
489 fb[2] = hwdata->div_frc >> 16;
490 fb[3] = hwdata->div_frc >> 8;
491 fb[4] = hwdata->div_frc;
492
493 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
494 }
495
496 static const struct clk_ops vc5_pll_ops = {
497 .recalc_rate = vc5_pll_recalc_rate,
498 .determine_rate = vc5_pll_determine_rate,
499 .set_rate = vc5_pll_set_rate,
500 };
501
vc5_fod_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)502 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
503 unsigned long parent_rate)
504 {
505 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
506 struct vc5_driver_data *vc5 = hwdata->vc5;
507 /* VCO frequency is divided by two before entering FOD */
508 u32 f_in = parent_rate / 2;
509 u32 div_int, div_frc;
510 u8 od_int[2];
511 u8 od_frc[4];
512
513 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
514 od_int, 2);
515 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
516 od_frc, 4);
517
518 div_int = (od_int[0] << 4) | (od_int[1] >> 4);
519 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
520 (od_frc[2] << 6) | (od_frc[3] >> 2);
521
522 /* Avoid division by zero if the output is not configured. */
523 if (div_int == 0 && div_frc == 0)
524 return 0;
525
526 /* The PLL divider has 12 integer bits and 30 fractional bits */
527 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
528 }
529
vc5_fod_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)530 static int vc5_fod_determine_rate(struct clk_hw *hw,
531 struct clk_rate_request *req)
532 {
533 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
534 /* VCO frequency is divided by two before entering FOD */
535 u32 f_in = req->best_parent_rate / 2;
536 u32 div_int;
537 u64 div_frc;
538
539 /* Determine integer part, which is 12 bit wide */
540 div_int = f_in / req->rate;
541 /*
542 * WARNING: The clock chip does not output signal if the integer part
543 * of the divider is 0xfff and fractional part is non-zero.
544 * Clamp the divider at 0xffe to keep the code simple.
545 */
546 if (div_int > 0xffe) {
547 div_int = 0xffe;
548 req->rate = f_in / div_int;
549 }
550
551 /* Determine best fractional part, which is 30 bit wide */
552 div_frc = f_in % req->rate;
553 div_frc <<= 24;
554 do_div(div_frc, req->rate);
555
556 hwdata->div_int = div_int;
557 hwdata->div_frc = (u32)div_frc;
558
559 req->rate = div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
560
561 return 0;
562 }
563
vc5_fod_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)564 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
565 unsigned long parent_rate)
566 {
567 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
568 struct vc5_driver_data *vc5 = hwdata->vc5;
569 u8 data[14] = {
570 hwdata->div_frc >> 22, hwdata->div_frc >> 14,
571 hwdata->div_frc >> 6, hwdata->div_frc << 2,
572 0, 0, 0, 0, 0,
573 0, 0,
574 hwdata->div_int >> 4, hwdata->div_int << 4,
575 0
576 };
577 int ret;
578
579 ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
580 data, 14);
581 if (ret)
582 return ret;
583
584 /*
585 * Toggle magic bit in undocumented register for unknown reason.
586 * This is what the IDT timing commander tool does and the chip
587 * datasheet somewhat implies this is needed, but the register
588 * and the bit is not documented.
589 */
590 ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
591 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
592 if (ret)
593 return ret;
594
595 return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
596 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
597 }
598
599 static const struct clk_ops vc5_fod_ops = {
600 .recalc_rate = vc5_fod_recalc_rate,
601 .determine_rate = vc5_fod_determine_rate,
602 .set_rate = vc5_fod_set_rate,
603 };
604
vc5_clk_out_prepare(struct clk_hw * hw)605 static int vc5_clk_out_prepare(struct clk_hw *hw)
606 {
607 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
608 struct vc5_driver_data *vc5 = hwdata->vc5;
609 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
610 VC5_OUT_DIV_CONTROL_SEL_EXT |
611 VC5_OUT_DIV_CONTROL_EN_FOD;
612 unsigned int src;
613 int ret;
614
615 /*
616 * When enabling a FOD, all currently enabled FODs are briefly
617 * stopped in order to synchronize all of them. This causes a clock
618 * disruption to any unrelated chips that might be already using
619 * other clock outputs. Bypass the sync feature to avoid the issue,
620 * which is possible on the VersaClock 6E family via reserved
621 * registers.
622 */
623 if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
624 ret = regmap_set_bits(vc5->regmap,
625 VC5_RESERVED_X0(hwdata->num),
626 VC5_RESERVED_X0_BYPASS_SYNC);
627 if (ret)
628 return ret;
629 }
630
631 /*
632 * If the input mux is disabled, enable it first and
633 * select source from matching FOD.
634 */
635 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
636 if (ret)
637 return ret;
638
639 if ((src & mask) == 0) {
640 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
641 ret = regmap_update_bits(vc5->regmap,
642 VC5_OUT_DIV_CONTROL(hwdata->num),
643 mask | VC5_OUT_DIV_CONTROL_RESET, src);
644 if (ret)
645 return ret;
646 }
647
648 /* Enable the clock buffer */
649 ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
650 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
651 if (ret)
652 return ret;
653
654 if (hwdata->clk_output_cfg0_mask) {
655 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
656 hwdata->num, hwdata->clk_output_cfg0_mask,
657 hwdata->clk_output_cfg0);
658
659 ret = regmap_update_bits(vc5->regmap,
660 VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
661 hwdata->clk_output_cfg0_mask,
662 hwdata->clk_output_cfg0);
663 if (ret)
664 return ret;
665 }
666
667 return 0;
668 }
669
vc5_clk_out_unprepare(struct clk_hw * hw)670 static void vc5_clk_out_unprepare(struct clk_hw *hw)
671 {
672 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
673 struct vc5_driver_data *vc5 = hwdata->vc5;
674
675 /* Disable the clock buffer */
676 regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
677 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
678 }
679
vc5_clk_out_get_parent(struct clk_hw * hw)680 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
681 {
682 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
683 struct vc5_driver_data *vc5 = hwdata->vc5;
684 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
685 VC5_OUT_DIV_CONTROL_SEL_EXT |
686 VC5_OUT_DIV_CONTROL_EN_FOD;
687 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
688 VC5_OUT_DIV_CONTROL_EN_FOD;
689 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
690 VC5_OUT_DIV_CONTROL_SEL_EXT;
691 unsigned int src;
692 int ret;
693
694 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
695 if (ret)
696 return 0;
697
698 src &= mask;
699
700 if (src == 0) /* Input mux set to DISABLED */
701 return 0;
702
703 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
704 return 0;
705
706 if (src == extclk)
707 return 1;
708
709 dev_warn(&vc5->client->dev,
710 "Invalid clock output configuration (%02x)\n", src);
711 return 0;
712 }
713
vc5_clk_out_set_parent(struct clk_hw * hw,u8 index)714 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
715 {
716 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
717 struct vc5_driver_data *vc5 = hwdata->vc5;
718 const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
719 VC5_OUT_DIV_CONTROL_SELB_NORM |
720 VC5_OUT_DIV_CONTROL_SEL_EXT |
721 VC5_OUT_DIV_CONTROL_EN_FOD;
722 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
723 VC5_OUT_DIV_CONTROL_SEL_EXT;
724 u8 src = VC5_OUT_DIV_CONTROL_RESET;
725
726 if (index == 0)
727 src |= VC5_OUT_DIV_CONTROL_EN_FOD;
728 else
729 src |= extclk;
730
731 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
732 mask, src);
733 }
734
735 static const struct clk_ops vc5_clk_out_ops = {
736 .prepare = vc5_clk_out_prepare,
737 .unprepare = vc5_clk_out_unprepare,
738 .determine_rate = clk_hw_determine_rate_no_reparent,
739 .set_parent = vc5_clk_out_set_parent,
740 .get_parent = vc5_clk_out_get_parent,
741 };
742
vc5_of_clk_get(struct of_phandle_args * clkspec,void * data)743 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
744 void *data)
745 {
746 struct vc5_driver_data *vc5 = data;
747 unsigned int idx = clkspec->args[0];
748
749 if (idx >= vc5->chip_info->clk_out_cnt)
750 return ERR_PTR(-EINVAL);
751
752 return &vc5->clk_out[idx].hw;
753 }
754
vc5_map_index_to_output(const enum vc5_model model,const unsigned int n)755 static int vc5_map_index_to_output(const enum vc5_model model,
756 const unsigned int n)
757 {
758 switch (model) {
759 case IDT_VC5_5P49V5933:
760 return (n == 0) ? 0 : 3;
761 case IDT_VC5_5P49V5923:
762 case IDT_VC5_5P49V5925:
763 case IDT_VC5_5P49V5935:
764 case IDT_VC6_5P49V6901:
765 case IDT_VC6_5P49V6965:
766 case IDT_VC6_5P49V6975:
767 default:
768 return n;
769 }
770 }
771
vc5_update_mode(struct device_node * np_output,struct vc5_out_data * clk_out)772 static int vc5_update_mode(struct device_node *np_output,
773 struct vc5_out_data *clk_out)
774 {
775 u32 value;
776
777 if (!of_property_read_u32(np_output, "idt,mode", &value)) {
778 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
779 switch (value) {
780 case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
781 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
782 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
783 case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
784 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
785 case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
786 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
787 clk_out->clk_output_cfg0 |=
788 value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
789 break;
790 default:
791 return -EINVAL;
792 }
793 }
794 return 0;
795 }
796
vc5_update_power(struct device_node * np_output,struct vc5_out_data * clk_out)797 static int vc5_update_power(struct device_node *np_output,
798 struct vc5_out_data *clk_out)
799 {
800 u32 value;
801
802 if (!of_property_read_u32(np_output, "idt,voltage-microvolt",
803 &value)) {
804 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
805 switch (value) {
806 case 1800000:
807 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
808 break;
809 case 2500000:
810 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
811 break;
812 case 3300000:
813 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
814 break;
815 default:
816 return -EINVAL;
817 }
818 }
819 return 0;
820 }
821
vc5_map_cap_value(u32 femtofarads)822 static int vc5_map_cap_value(u32 femtofarads)
823 {
824 int mapped_value;
825
826 /*
827 * The datasheet explicitly states 9000 - 25000 with 0.5pF
828 * steps, but the Programmer's guide shows the steps are 0.430pF.
829 * After getting feedback from Renesas, the .5pF steps were the
830 * goal, but 430nF was the actual values.
831 * Because of this, the actual range goes to 22760 instead of 25000
832 */
833 if (femtofarads < 9000 || femtofarads > 22760)
834 return -EINVAL;
835
836 /*
837 * The Programmer's guide shows XTAL[5:0] but in reality,
838 * XTAL[0] and XTAL[1] are both LSB which makes the math
839 * strange. With clarfication from Renesas, setting the
840 * values should be simpler by ignoring XTAL[0]
841 */
842 mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430);
843
844 /*
845 * Since the calculation ignores XTAL[0], there is one
846 * special case where mapped_value = 32. In reality, this means
847 * the real mapped value should be 111111b. In other cases,
848 * the mapped_value needs to be shifted 1 to the left.
849 */
850 if (mapped_value > 31)
851 mapped_value = 0x3f;
852 else
853 mapped_value <<= 1;
854
855 return mapped_value;
856 }
vc5_update_cap_load(struct device_node * node,struct vc5_driver_data * vc5)857 static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5)
858 {
859 u32 value;
860 int mapped_value;
861 int ret;
862
863 if (of_property_read_u32(node, "idt,xtal-load-femtofarads", &value))
864 return 0;
865
866 mapped_value = vc5_map_cap_value(value);
867 if (mapped_value < 0)
868 return mapped_value;
869
870 /*
871 * The mapped_value is really the high 6 bits of
872 * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so
873 * shift the value 2 places.
874 */
875 ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03,
876 mapped_value << 2);
877 if (ret)
878 return ret;
879
880 return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03,
881 mapped_value << 2);
882 }
883
vc5_update_slew(struct device_node * np_output,struct vc5_out_data * clk_out)884 static int vc5_update_slew(struct device_node *np_output,
885 struct vc5_out_data *clk_out)
886 {
887 u32 value;
888
889 if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) {
890 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
891 switch (value) {
892 case 80:
893 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
894 break;
895 case 85:
896 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
897 break;
898 case 90:
899 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
900 break;
901 case 100:
902 clk_out->clk_output_cfg0 |=
903 VC5_CLK_OUTPUT_CFG0_SLEW_100;
904 break;
905 default:
906 return -EINVAL;
907 }
908 }
909 return 0;
910 }
911
vc5_get_output_config(struct i2c_client * client,struct vc5_out_data * clk_out)912 static int vc5_get_output_config(struct i2c_client *client,
913 struct vc5_out_data *clk_out)
914 {
915 struct device_node *np_output;
916 char *child_name;
917 int ret = 0;
918
919 child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1);
920 if (!child_name)
921 return -ENOMEM;
922
923 np_output = of_get_child_by_name(client->dev.of_node, child_name);
924 kfree(child_name);
925 if (!np_output)
926 return 0;
927
928 ret = vc5_update_mode(np_output, clk_out);
929 if (ret)
930 goto output_error;
931
932 ret = vc5_update_power(np_output, clk_out);
933 if (ret)
934 goto output_error;
935
936 ret = vc5_update_slew(np_output, clk_out);
937
938 output_error:
939 if (ret) {
940 dev_err(&client->dev,
941 "Invalid clock output configuration OUT%d\n",
942 clk_out->num + 1);
943 }
944
945 of_node_put(np_output);
946
947 return ret;
948 }
949
950 static const struct of_device_id clk_vc5_of_match[];
951
vc5_probe(struct i2c_client * client)952 static int vc5_probe(struct i2c_client *client)
953 {
954 unsigned int oe, sd, src_mask = 0, src_val = 0;
955 struct vc5_driver_data *vc5;
956 struct clk_init_data init;
957 const char *parent_names[2];
958 unsigned int n, idx = 0;
959 int ret;
960
961 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
962 if (!vc5)
963 return -ENOMEM;
964
965 i2c_set_clientdata(client, vc5);
966 vc5->client = client;
967 vc5->chip_info = i2c_get_match_data(client);
968
969 vc5->pin_xin = devm_clk_get(&client->dev, "xin");
970 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
971 return -EPROBE_DEFER;
972
973 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
974 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
975 return -EPROBE_DEFER;
976
977 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
978 if (IS_ERR(vc5->regmap))
979 return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap),
980 "failed to allocate register map\n");
981
982 ret = of_property_read_u32(client->dev.of_node, "idt,shutdown", &sd);
983 if (!ret) {
984 src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
985 if (sd)
986 src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
987 } else if (ret != -EINVAL) {
988 return dev_err_probe(&client->dev, ret,
989 "could not read idt,shutdown\n");
990 }
991
992 ret = of_property_read_u32(client->dev.of_node,
993 "idt,output-enable-active", &oe);
994 if (!ret) {
995 src_mask |= VC5_PRIM_SRC_SHDN_SP;
996 if (oe)
997 src_val |= VC5_PRIM_SRC_SHDN_SP;
998 } else if (ret != -EINVAL) {
999 return dev_err_probe(&client->dev, ret,
1000 "could not read idt,output-enable-active\n");
1001 }
1002
1003 ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask,
1004 src_val);
1005 if (ret)
1006 return ret;
1007
1008 /* Register clock input mux */
1009 memset(&init, 0, sizeof(init));
1010
1011 if (!IS_ERR(vc5->pin_xin)) {
1012 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1013 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1014 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
1015 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
1016 "internal-xtal", NULL,
1017 0, 25000000);
1018 if (IS_ERR(vc5->pin_xin))
1019 return PTR_ERR(vc5->pin_xin);
1020 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1021 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1022 }
1023
1024 if (!IS_ERR(vc5->pin_clkin)) {
1025 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
1026 parent_names[init.num_parents++] =
1027 __clk_get_name(vc5->pin_clkin);
1028 }
1029
1030 if (!init.num_parents)
1031 return dev_err_probe(&client->dev, -EINVAL,
1032 "no input clock specified!\n");
1033
1034 /* Configure Optional Loading Capacitance for external XTAL */
1035 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) {
1036 ret = vc5_update_cap_load(client->dev.of_node, vc5);
1037 if (ret)
1038 goto err_clk_register;
1039 }
1040
1041 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node);
1042 if (!init.name) {
1043 ret = -ENOMEM;
1044 goto err_clk;
1045 }
1046
1047 init.ops = &vc5_mux_ops;
1048 init.flags = 0;
1049 init.parent_names = parent_names;
1050 vc5->clk_mux.init = &init;
1051 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
1052 if (ret)
1053 goto err_clk_register;
1054 kfree(init.name); /* clock framework made a copy of the name */
1055
1056 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
1057 /* Register frequency doubler */
1058 memset(&init, 0, sizeof(init));
1059 init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl",
1060 client->dev.of_node);
1061 if (!init.name) {
1062 ret = -ENOMEM;
1063 goto err_clk;
1064 }
1065 init.ops = &vc5_dbl_ops;
1066 init.flags = CLK_SET_RATE_PARENT;
1067 init.parent_names = parent_names;
1068 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1069 init.num_parents = 1;
1070 vc5->clk_mul.init = &init;
1071 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
1072 if (ret)
1073 goto err_clk_register;
1074 kfree(init.name); /* clock framework made a copy of the name */
1075 }
1076
1077 /* Register PFD */
1078 memset(&init, 0, sizeof(init));
1079 init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node);
1080 if (!init.name) {
1081 ret = -ENOMEM;
1082 goto err_clk;
1083 }
1084 init.ops = &vc5_pfd_ops;
1085 init.flags = CLK_SET_RATE_PARENT;
1086 init.parent_names = parent_names;
1087 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
1088 parent_names[0] = clk_hw_get_name(&vc5->clk_mul);
1089 else
1090 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1091 init.num_parents = 1;
1092 vc5->clk_pfd.init = &init;
1093 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
1094 if (ret)
1095 goto err_clk_register;
1096 kfree(init.name); /* clock framework made a copy of the name */
1097
1098 /* Register PLL */
1099 memset(&init, 0, sizeof(init));
1100 init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node);
1101 if (!init.name) {
1102 ret = -ENOMEM;
1103 goto err_clk;
1104 }
1105 init.ops = &vc5_pll_ops;
1106 init.flags = CLK_SET_RATE_PARENT;
1107 init.parent_names = parent_names;
1108 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd);
1109 init.num_parents = 1;
1110 vc5->clk_pll.num = 0;
1111 vc5->clk_pll.vc5 = vc5;
1112 vc5->clk_pll.hw.init = &init;
1113 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
1114 if (ret)
1115 goto err_clk_register;
1116 kfree(init.name); /* clock framework made a copy of the name */
1117
1118 /* Register FODs */
1119 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
1120 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
1121 memset(&init, 0, sizeof(init));
1122 init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d",
1123 client->dev.of_node, idx);
1124 if (!init.name) {
1125 ret = -ENOMEM;
1126 goto err_clk;
1127 }
1128 init.ops = &vc5_fod_ops;
1129 init.flags = CLK_SET_RATE_PARENT;
1130 init.parent_names = parent_names;
1131 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw);
1132 init.num_parents = 1;
1133 vc5->clk_fod[n].num = idx;
1134 vc5->clk_fod[n].vc5 = vc5;
1135 vc5->clk_fod[n].hw.init = &init;
1136 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
1137 if (ret)
1138 goto err_clk_register;
1139 kfree(init.name); /* clock framework made a copy of the name */
1140 }
1141
1142 /* Register MUX-connected OUT0_I2C_SELB output */
1143 memset(&init, 0, sizeof(init));
1144 init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb",
1145 client->dev.of_node);
1146 if (!init.name) {
1147 ret = -ENOMEM;
1148 goto err_clk;
1149 }
1150 init.ops = &vc5_clk_out_ops;
1151 init.flags = CLK_SET_RATE_PARENT;
1152 init.parent_names = parent_names;
1153 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1154 init.num_parents = 1;
1155 vc5->clk_out[0].num = idx;
1156 vc5->clk_out[0].vc5 = vc5;
1157 vc5->clk_out[0].hw.init = &init;
1158 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
1159 if (ret)
1160 goto err_clk_register;
1161 kfree(init.name); /* clock framework made a copy of the name */
1162
1163 /* Register FOD-connected OUTx outputs */
1164 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
1165 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
1166 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw);
1167 if (n == 1)
1168 parent_names[1] = clk_hw_get_name(&vc5->clk_mux);
1169 else
1170 parent_names[1] =
1171 clk_hw_get_name(&vc5->clk_out[n - 1].hw);
1172
1173 memset(&init, 0, sizeof(init));
1174 init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d",
1175 client->dev.of_node, idx + 1);
1176 if (!init.name) {
1177 ret = -ENOMEM;
1178 goto err_clk;
1179 }
1180 init.ops = &vc5_clk_out_ops;
1181 init.flags = CLK_SET_RATE_PARENT;
1182 init.parent_names = parent_names;
1183 init.num_parents = 2;
1184 vc5->clk_out[n].num = idx;
1185 vc5->clk_out[n].vc5 = vc5;
1186 vc5->clk_out[n].hw.init = &init;
1187 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
1188 if (ret)
1189 goto err_clk_register;
1190 kfree(init.name); /* clock framework made a copy of the name */
1191
1192 /* Fetch Clock Output configuration from DT (if specified) */
1193 ret = vc5_get_output_config(client, &vc5->clk_out[n]);
1194 if (ret)
1195 goto err_clk;
1196 }
1197
1198 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
1199 if (ret) {
1200 dev_err_probe(&client->dev, ret,
1201 "unable to add clk provider\n");
1202 goto err_clk;
1203 }
1204
1205 return 0;
1206
1207 err_clk_register:
1208 dev_err_probe(&client->dev, ret,
1209 "unable to register %s\n", init.name);
1210 kfree(init.name); /* clock framework made a copy of the name */
1211 err_clk:
1212 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1213 clk_unregister_fixed_rate(vc5->pin_xin);
1214 return ret;
1215 }
1216
vc5_remove(struct i2c_client * client)1217 static void vc5_remove(struct i2c_client *client)
1218 {
1219 struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
1220
1221 of_clk_del_provider(client->dev.of_node);
1222
1223 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1224 clk_unregister_fixed_rate(vc5->pin_xin);
1225 }
1226
vc5_suspend(struct device * dev)1227 static int __maybe_unused vc5_suspend(struct device *dev)
1228 {
1229 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1230
1231 regcache_cache_only(vc5->regmap, true);
1232 regcache_mark_dirty(vc5->regmap);
1233
1234 return 0;
1235 }
1236
vc5_resume(struct device * dev)1237 static int __maybe_unused vc5_resume(struct device *dev)
1238 {
1239 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1240 int ret;
1241
1242 regcache_cache_only(vc5->regmap, false);
1243 ret = regcache_sync(vc5->regmap);
1244 if (ret)
1245 dev_err(dev, "Failed to restore register map: %d\n", ret);
1246 return ret;
1247 }
1248
1249 static const struct vc5_chip_info idt_5p49v5923_info = {
1250 .model = IDT_VC5_5P49V5923,
1251 .clk_fod_cnt = 2,
1252 .clk_out_cnt = 3,
1253 .flags = 0,
1254 .vco_max = 3000000000UL,
1255 };
1256
1257 static const struct vc5_chip_info idt_5p49v5925_info = {
1258 .model = IDT_VC5_5P49V5925,
1259 .clk_fod_cnt = 4,
1260 .clk_out_cnt = 5,
1261 .flags = 0,
1262 .vco_max = 3000000000UL,
1263 };
1264
1265 static const struct vc5_chip_info idt_5p49v5933_info = {
1266 .model = IDT_VC5_5P49V5933,
1267 .clk_fod_cnt = 2,
1268 .clk_out_cnt = 3,
1269 .flags = VC5_HAS_INTERNAL_XTAL,
1270 .vco_max = 3000000000UL,
1271 };
1272
1273 static const struct vc5_chip_info idt_5p49v5935_info = {
1274 .model = IDT_VC5_5P49V5935,
1275 .clk_fod_cnt = 4,
1276 .clk_out_cnt = 5,
1277 .flags = VC5_HAS_INTERNAL_XTAL,
1278 .vco_max = 3000000000UL,
1279 };
1280
1281 static const struct vc5_chip_info idt_5p49v60_info = {
1282 .model = IDT_VC6_5P49V60,
1283 .clk_fod_cnt = 4,
1284 .clk_out_cnt = 5,
1285 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
1286 .vco_max = 2700000000UL,
1287 };
1288
1289 static const struct vc5_chip_info idt_5p49v6901_info = {
1290 .model = IDT_VC6_5P49V6901,
1291 .clk_fod_cnt = 4,
1292 .clk_out_cnt = 5,
1293 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
1294 .vco_max = 3000000000UL,
1295 };
1296
1297 static const struct vc5_chip_info idt_5p49v6965_info = {
1298 .model = IDT_VC6_5P49V6965,
1299 .clk_fod_cnt = 4,
1300 .clk_out_cnt = 5,
1301 .flags = VC5_HAS_BYPASS_SYNC_BIT,
1302 .vco_max = 3000000000UL,
1303 };
1304
1305 static const struct vc5_chip_info idt_5p49v6975_info = {
1306 .model = IDT_VC6_5P49V6975,
1307 .clk_fod_cnt = 4,
1308 .clk_out_cnt = 5,
1309 .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL,
1310 .vco_max = 3000000000UL,
1311 };
1312
1313 static const struct i2c_device_id vc5_id[] = {
1314 { "5p49v5923", .driver_data = (kernel_ulong_t)&idt_5p49v5923_info },
1315 { "5p49v5925", .driver_data = (kernel_ulong_t)&idt_5p49v5925_info },
1316 { "5p49v5933", .driver_data = (kernel_ulong_t)&idt_5p49v5933_info },
1317 { "5p49v5935", .driver_data = (kernel_ulong_t)&idt_5p49v5935_info },
1318 { "5p49v60", .driver_data = (kernel_ulong_t)&idt_5p49v60_info },
1319 { "5p49v6901", .driver_data = (kernel_ulong_t)&idt_5p49v6901_info },
1320 { "5p49v6965", .driver_data = (kernel_ulong_t)&idt_5p49v6965_info },
1321 { "5p49v6975", .driver_data = (kernel_ulong_t)&idt_5p49v6975_info },
1322 { }
1323 };
1324 MODULE_DEVICE_TABLE(i2c, vc5_id);
1325
1326 static const struct of_device_id clk_vc5_of_match[] = {
1327 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
1328 { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
1329 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1330 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
1331 { .compatible = "idt,5p49v60", .data = &idt_5p49v60_info },
1332 { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
1333 { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
1334 { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
1335 { },
1336 };
1337 MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
1338
1339 static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume);
1340
1341 static struct i2c_driver vc5_driver = {
1342 .driver = {
1343 .name = "vc5",
1344 .pm = &vc5_pm_ops,
1345 .of_match_table = clk_vc5_of_match,
1346 },
1347 .probe = vc5_probe,
1348 .remove = vc5_remove,
1349 .id_table = vc5_id,
1350 };
1351 module_i2c_driver(vc5_driver);
1352
1353 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
1354 MODULE_DESCRIPTION("IDT VersaClock 5 driver");
1355 MODULE_LICENSE("GPL");
1356