1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/display/drm_hdmi_state_helper.h>
36 #include <drm/display/drm_scdc_helper.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_drv.h>
39 #include <drm/drm_edid.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_simple_kms_helper.h>
42 #include <linux/clk.h>
43 #include <linux/component.h>
44 #include <linux/gpio/consumer.h>
45 #include <linux/i2c.h>
46 #include <linux/of.h>
47 #include <linux/of_address.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/rational.h>
50 #include <linux/reset.h>
51 #include <sound/dmaengine_pcm.h>
52 #include <sound/hdmi-codec.h>
53 #include <sound/pcm_drm_eld.h>
54 #include <sound/pcm_params.h>
55 #include <sound/soc.h>
56 #include "media/cec.h"
57 #include "vc4_drv.h"
58 #include "vc4_hdmi.h"
59 #include "vc4_hdmi_regs.h"
60 #include "vc4_regs.h"
61
62 #define VC5_HDMI_HORZA_HFP_SHIFT 16
63 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
64 #define VC5_HDMI_HORZA_VPOS BIT(15)
65 #define VC5_HDMI_HORZA_HPOS BIT(14)
66 #define VC5_HDMI_HORZA_HAP_SHIFT 0
67 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
68
69 #define VC5_HDMI_HORZB_HBP_SHIFT 16
70 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
71 #define VC5_HDMI_HORZB_HSP_SHIFT 0
72 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
73
74 #define VC5_HDMI_VERTA_VSP_SHIFT 24
75 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
76 #define VC5_HDMI_VERTA_VFP_SHIFT 16
77 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
78 #define VC5_HDMI_VERTA_VAL_SHIFT 0
79 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
80
81 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
82 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
83
84 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
86 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
87 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
88
89 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
90
91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
93
94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
96
97 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
98
99 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
101
102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
105
106 # define VC4_HD_M_SW_RST BIT(2)
107 # define VC4_HD_M_ENABLE BIT(0)
108
109 #define HSM_MIN_CLOCK_FREQ 120000000
110 #define CEC_CLOCK_FREQ 40000
111
112 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
113
vc4_hdmi_supports_scrambling(struct vc4_hdmi * vc4_hdmi)114 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
115 {
116 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
117
118 lockdep_assert_held(&vc4_hdmi->mutex);
119
120 if (!display->is_hdmi)
121 return false;
122
123 if (!display->hdmi.scdc.supported ||
124 !display->hdmi.scdc.scrambling.supported)
125 return false;
126
127 return true;
128 }
129
vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode * mode,unsigned int bpc,enum hdmi_colorspace fmt)130 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
131 unsigned int bpc,
132 enum hdmi_colorspace fmt)
133 {
134 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
135
136 return clock > HDMI_14_MAX_TMDS_CLK;
137 }
138
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)139 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
140 {
141 struct drm_debugfs_entry *entry = m->private;
142 struct vc4_hdmi *vc4_hdmi = entry->file.data;
143 struct drm_device *drm = vc4_hdmi->connector.dev;
144 struct drm_printer p = drm_seq_file_printer(m);
145 int idx;
146
147 if (!drm_dev_enter(drm, &idx))
148 return -ENODEV;
149
150 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
151 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
152 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
153 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
154 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
155 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
156 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
157 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
158
159 drm_dev_exit(idx);
160
161 return 0;
162 }
163
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)164 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
165 {
166 struct drm_device *drm = vc4_hdmi->connector.dev;
167 unsigned long flags;
168 int idx;
169
170 /*
171 * We can be called by our bind callback, when the
172 * connector->dev pointer might not be initialised yet.
173 */
174 if (drm && !drm_dev_enter(drm, &idx))
175 return;
176
177 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
178
179 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
180 udelay(1);
181 HDMI_WRITE(HDMI_M_CTL, 0);
182
183 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
184
185 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
186 VC4_HDMI_SW_RESET_HDMI |
187 VC4_HDMI_SW_RESET_FORMAT_DETECT);
188
189 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
190
191 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
192
193 if (drm)
194 drm_dev_exit(idx);
195 }
196
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)197 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
198 {
199 struct drm_device *drm = vc4_hdmi->connector.dev;
200 unsigned long flags;
201 int idx;
202
203 /*
204 * We can be called by our bind callback, when the
205 * connector->dev pointer might not be initialised yet.
206 */
207 if (drm && !drm_dev_enter(drm, &idx))
208 return;
209
210 reset_control_reset(vc4_hdmi->reset);
211
212 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
213
214 HDMI_WRITE(HDMI_DVP_CTL, 0);
215
216 HDMI_WRITE(HDMI_CLOCK_STOP,
217 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
218
219 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
220
221 if (drm)
222 drm_dev_exit(idx);
223 }
224
225 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)226 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
227 {
228 struct drm_device *drm = vc4_hdmi->connector.dev;
229 unsigned long cec_rate;
230 unsigned long flags;
231 u16 clk_cnt;
232 u32 value;
233 int idx;
234
235 /*
236 * This function is called by our runtime_resume implementation
237 * and thus at bind time, when we haven't registered our
238 * connector yet and thus don't have a pointer to the DRM
239 * device.
240 */
241 if (drm && !drm_dev_enter(drm, &idx))
242 return;
243
244 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
245
246 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
247
248 value = HDMI_READ(HDMI_CEC_CNTRL_1);
249 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
250
251 /*
252 * Set the clock divider: the hsm_clock rate and this divider
253 * setting will give a 40 kHz CEC clock.
254 */
255 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
256 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
257 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
258
259 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
260
261 if (drm)
262 drm_dev_exit(idx);
263 }
264 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)265 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
266 #endif
267
reset_pipe(struct drm_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)268 static int reset_pipe(struct drm_crtc *crtc,
269 struct drm_modeset_acquire_ctx *ctx)
270 {
271 struct drm_atomic_state *state;
272 struct drm_crtc_state *crtc_state;
273 int ret;
274
275 state = drm_atomic_state_alloc(crtc->dev);
276 if (!state)
277 return -ENOMEM;
278
279 state->acquire_ctx = ctx;
280
281 crtc_state = drm_atomic_get_crtc_state(state, crtc);
282 if (IS_ERR(crtc_state)) {
283 ret = PTR_ERR(crtc_state);
284 goto out;
285 }
286
287 crtc_state->connectors_changed = true;
288
289 ret = drm_atomic_commit(state);
290 out:
291 drm_atomic_state_put(state);
292
293 return ret;
294 }
295
vc4_hdmi_reset_link(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx)296 static int vc4_hdmi_reset_link(struct drm_connector *connector,
297 struct drm_modeset_acquire_ctx *ctx)
298 {
299 struct drm_device *drm;
300 struct vc4_hdmi *vc4_hdmi;
301 struct drm_connector_state *conn_state;
302 struct drm_crtc_state *crtc_state;
303 struct drm_crtc *crtc;
304 bool scrambling_needed;
305 u8 config;
306 int ret;
307
308 if (!connector)
309 return 0;
310
311 drm = connector->dev;
312 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
313 if (ret)
314 return ret;
315
316 conn_state = connector->state;
317 crtc = conn_state->crtc;
318 if (!crtc)
319 return 0;
320
321 ret = drm_modeset_lock(&crtc->mutex, ctx);
322 if (ret)
323 return ret;
324
325 crtc_state = crtc->state;
326 if (!crtc_state->active)
327 return 0;
328
329 vc4_hdmi = connector_to_vc4_hdmi(connector);
330 mutex_lock(&vc4_hdmi->mutex);
331
332 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
333 mutex_unlock(&vc4_hdmi->mutex);
334 return 0;
335 }
336
337 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
338 vc4_hdmi->output_bpc,
339 vc4_hdmi->output_format);
340 if (!scrambling_needed) {
341 mutex_unlock(&vc4_hdmi->mutex);
342 return 0;
343 }
344
345 if (conn_state->commit &&
346 !try_wait_for_completion(&conn_state->commit->hw_done)) {
347 mutex_unlock(&vc4_hdmi->mutex);
348 return 0;
349 }
350
351 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
352 if (ret < 0) {
353 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
354 mutex_unlock(&vc4_hdmi->mutex);
355 return 0;
356 }
357
358 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
359 mutex_unlock(&vc4_hdmi->mutex);
360 return 0;
361 }
362
363 mutex_unlock(&vc4_hdmi->mutex);
364
365 /*
366 * HDMI 2.0 says that one should not send scrambled data
367 * prior to configuring the sink scrambling, and that
368 * TMDS clock/data transmission should be suspended when
369 * changing the TMDS clock rate in the sink. So let's
370 * just do a full modeset here, even though some sinks
371 * would be perfectly happy if were to just reconfigure
372 * the SCDC settings on the fly.
373 */
374 return reset_pipe(crtc, ctx);
375 }
376
vc4_hdmi_handle_hotplug(struct vc4_hdmi * vc4_hdmi,struct drm_modeset_acquire_ctx * ctx,enum drm_connector_status status)377 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
378 struct drm_modeset_acquire_ctx *ctx,
379 enum drm_connector_status status)
380 {
381 struct drm_connector *connector = &vc4_hdmi->connector;
382 const struct drm_edid *drm_edid;
383 int ret;
384
385 /*
386 * NOTE: This function should really be called with vc4_hdmi->mutex
387 * held, but doing so results in reentrancy issues since
388 * cec_s_phys_addr() might call .adap_enable, which leads to that
389 * funtion being called with our mutex held.
390 *
391 * A similar situation occurs with vc4_hdmi_reset_link() that
392 * will call into our KMS hooks if the scrambling was enabled.
393 *
394 * Concurrency isn't an issue at the moment since we don't share
395 * any state with any of the other frameworks so we can ignore
396 * the lock for now.
397 */
398
399 if (status == connector_status_disconnected) {
400 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
401 return;
402 }
403
404 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
405
406 drm_edid_connector_update(connector, drm_edid);
407 cec_s_phys_addr(vc4_hdmi->cec_adap,
408 connector->display_info.source_physical_address, false);
409
410 if (!drm_edid)
411 return;
412
413 drm_edid_free(drm_edid);
414
415 for (;;) {
416 ret = vc4_hdmi_reset_link(connector, ctx);
417 if (ret == -EDEADLK) {
418 drm_modeset_backoff(ctx);
419 continue;
420 }
421
422 break;
423 }
424 }
425
vc4_hdmi_connector_detect_ctx(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)426 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
427 struct drm_modeset_acquire_ctx *ctx,
428 bool force)
429 {
430 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
431 enum drm_connector_status status = connector_status_disconnected;
432 int ret;
433
434 /*
435 * NOTE: This function should really take vc4_hdmi->mutex, but
436 * doing so results in reentrancy issues since
437 * vc4_hdmi_handle_hotplug() can call into other functions that
438 * would take the mutex while it's held here.
439 *
440 * Concurrency isn't an issue at the moment since we don't share
441 * any state with any of the other frameworks so we can ignore
442 * the lock for now.
443 */
444
445 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
446 if (ret) {
447 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
448 ret);
449 return connector_status_unknown;
450 }
451
452 if (vc4_hdmi->hpd_gpio) {
453 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
454 status = connector_status_connected;
455 } else {
456 if (vc4_hdmi->variant->hp_detect &&
457 vc4_hdmi->variant->hp_detect(vc4_hdmi))
458 status = connector_status_connected;
459 }
460
461 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
462 pm_runtime_put(&vc4_hdmi->pdev->dev);
463
464 return status;
465 }
466
vc4_hdmi_connector_get_modes(struct drm_connector * connector)467 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
468 {
469 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
470 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
471 const struct drm_edid *drm_edid;
472 int ret = 0;
473
474 /*
475 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
476 * results in reentrancy issues since cec_s_phys_addr() might call
477 * .adap_enable, which leads to that funtion being called with our mutex
478 * held.
479 *
480 * Concurrency isn't an issue at the moment since we don't share
481 * any state with any of the other frameworks so we can ignore
482 * the lock for now.
483 */
484
485 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
486 drm_edid_connector_update(connector, drm_edid);
487 cec_s_phys_addr(vc4_hdmi->cec_adap,
488 connector->display_info.source_physical_address, false);
489 if (!drm_edid)
490 return 0;
491
492 ret = drm_edid_connector_add_modes(connector);
493 drm_edid_free(drm_edid);
494
495 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
496 struct drm_device *drm = connector->dev;
497 const struct drm_display_mode *mode;
498
499 list_for_each_entry(mode, &connector->probed_modes, head) {
500 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) {
501 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
502 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
503 }
504 }
505 }
506
507 return ret;
508 }
509
vc4_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)510 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
511 struct drm_atomic_state *state)
512 {
513 struct drm_connector_state *old_state =
514 drm_atomic_get_old_connector_state(state, connector);
515 struct drm_connector_state *new_state =
516 drm_atomic_get_new_connector_state(state, connector);
517 struct drm_crtc *crtc = new_state->crtc;
518
519 if (!crtc)
520 return 0;
521
522 if (old_state->tv.margins.left != new_state->tv.margins.left ||
523 old_state->tv.margins.right != new_state->tv.margins.right ||
524 old_state->tv.margins.top != new_state->tv.margins.top ||
525 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
526 struct drm_crtc_state *crtc_state;
527 int ret;
528
529 crtc_state = drm_atomic_get_crtc_state(state, crtc);
530 if (IS_ERR(crtc_state))
531 return PTR_ERR(crtc_state);
532
533 /*
534 * Strictly speaking, we should be calling
535 * drm_atomic_helper_check_planes() after our call to
536 * drm_atomic_add_affected_planes(). However, the
537 * connector atomic_check is called as part of
538 * drm_atomic_helper_check_modeset() that already
539 * happens before a call to
540 * drm_atomic_helper_check_planes() in
541 * drm_atomic_helper_check().
542 */
543 ret = drm_atomic_add_affected_planes(state, crtc);
544 if (ret)
545 return ret;
546 }
547
548 if (old_state->colorspace != new_state->colorspace) {
549 struct drm_crtc_state *crtc_state;
550
551 crtc_state = drm_atomic_get_crtc_state(state, crtc);
552 if (IS_ERR(crtc_state))
553 return PTR_ERR(crtc_state);
554
555 crtc_state->mode_changed = true;
556 }
557
558 return drm_atomic_helper_connector_hdmi_check(connector, state);
559 }
560
vc4_hdmi_connector_reset(struct drm_connector * connector)561 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
562 {
563 drm_atomic_helper_connector_reset(connector);
564 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
565 drm_atomic_helper_connector_tv_margins_reset(connector);
566 }
567
568 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
569 .fill_modes = drm_helper_probe_single_connector_modes,
570 .reset = vc4_hdmi_connector_reset,
571 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
572 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
573 };
574
575 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
576 .detect_ctx = vc4_hdmi_connector_detect_ctx,
577 .get_modes = vc4_hdmi_connector_get_modes,
578 .atomic_check = vc4_hdmi_connector_atomic_check,
579 };
580
581 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs;
582
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)583 static int vc4_hdmi_connector_init(struct drm_device *dev,
584 struct vc4_hdmi *vc4_hdmi)
585 {
586 struct drm_connector *connector = &vc4_hdmi->connector;
587 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
588 unsigned int max_bpc = 8;
589 int ret;
590
591 if (vc4_hdmi->variant->supports_hdr)
592 max_bpc = 12;
593
594 ret = drmm_connector_hdmi_init(dev, connector,
595 "Broadcom", "Videocore",
596 &vc4_hdmi_connector_funcs,
597 &vc4_hdmi_hdmi_connector_funcs,
598 DRM_MODE_CONNECTOR_HDMIA,
599 vc4_hdmi->ddc,
600 BIT(HDMI_COLORSPACE_RGB) |
601 BIT(HDMI_COLORSPACE_YUV422) |
602 BIT(HDMI_COLORSPACE_YUV444),
603 max_bpc);
604 if (ret)
605 return ret;
606
607 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
608
609 /*
610 * Some of the properties below require access to state, like bpc.
611 * Allocate some default initial connector state with our reset helper.
612 */
613 if (connector->funcs->reset)
614 connector->funcs->reset(connector);
615
616 /* Create and attach TV margin props to this connector. */
617 ret = drm_mode_create_tv_margin_properties(dev);
618 if (ret)
619 return ret;
620
621 ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
622 if (ret)
623 return ret;
624
625 drm_connector_attach_colorspace_property(connector);
626 drm_connector_attach_tv_margin_properties(connector);
627
628 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
629 DRM_CONNECTOR_POLL_DISCONNECT);
630
631 connector->interlace_allowed = 1;
632 connector->doublescan_allowed = 0;
633 connector->stereo_allowed = 1;
634
635 ret = drm_connector_attach_broadcast_rgb_property(connector);
636 if (ret)
637 return ret;
638
639 drm_connector_attach_encoder(connector, encoder);
640
641 return 0;
642 }
643
vc4_hdmi_stop_packet(struct vc4_hdmi * vc4_hdmi,enum hdmi_infoframe_type type,bool poll)644 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi,
645 enum hdmi_infoframe_type type,
646 bool poll)
647 {
648 struct drm_device *drm = vc4_hdmi->connector.dev;
649 u32 packet_id = type - 0x80;
650 unsigned long flags;
651 int ret = 0;
652 int idx;
653
654 if (!drm_dev_enter(drm, &idx))
655 return -ENODEV;
656
657 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
658 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
659 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
660 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
661
662 if (poll) {
663 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
664 BIT(packet_id)), 100);
665 }
666
667 drm_dev_exit(idx);
668 return ret;
669 }
670
vc4_hdmi_write_infoframe(struct drm_connector * connector,enum hdmi_infoframe_type type,const u8 * infoframe,size_t len)671 static int vc4_hdmi_write_infoframe(struct drm_connector *connector,
672 enum hdmi_infoframe_type type,
673 const u8 *infoframe, size_t len)
674 {
675 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
676 struct drm_device *drm = connector->dev;
677 u32 packet_id = type - 0x80;
678 const struct vc4_hdmi_register *ram_packet_start =
679 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
680 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
681 u32 packet_reg_next = ram_packet_start->offset +
682 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
683 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
684 ram_packet_start->reg);
685 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
686 unsigned long flags;
687 ssize_t i;
688 int ret;
689 int idx;
690
691 if (!drm_dev_enter(drm, &idx))
692 return 0;
693
694 if (len > sizeof(buffer)) {
695 ret = -ENOMEM;
696 goto out;
697 }
698
699 memcpy(buffer, infoframe, len);
700
701 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
702 VC4_HDMI_RAM_PACKET_ENABLE),
703 "Packet RAM has to be on to store the packet.");
704
705 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
706 if (ret) {
707 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
708 goto out;
709 }
710
711 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
712
713 for (i = 0; i < len; i += 7) {
714 writel(buffer[i + 0] << 0 |
715 buffer[i + 1] << 8 |
716 buffer[i + 2] << 16,
717 base + packet_reg);
718 packet_reg += 4;
719
720 writel(buffer[i + 3] << 0 |
721 buffer[i + 4] << 8 |
722 buffer[i + 5] << 16 |
723 buffer[i + 6] << 24,
724 base + packet_reg);
725 packet_reg += 4;
726 }
727
728 /*
729 * clear remainder of packet ram as it's included in the
730 * infoframe and triggers a checksum error on hdmi analyser
731 */
732 for (; packet_reg < packet_reg_next; packet_reg += 4)
733 writel(0, base + packet_reg);
734
735 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
736 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
737
738 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
739
740 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
741 BIT(packet_id)), 100);
742 if (ret)
743 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
744
745 out:
746 drm_dev_exit(idx);
747 return ret;
748 }
749
750 #define SCRAMBLING_POLLING_DELAY_MS 1000
751
vc4_hdmi_enable_scrambling(struct drm_encoder * encoder)752 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
753 {
754 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
755 struct drm_connector *connector = &vc4_hdmi->connector;
756 struct drm_device *drm = connector->dev;
757 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
758 unsigned long flags;
759 int idx;
760
761 lockdep_assert_held(&vc4_hdmi->mutex);
762
763 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
764 return;
765
766 if (!vc4_hdmi_mode_needs_scrambling(mode,
767 vc4_hdmi->output_bpc,
768 vc4_hdmi->output_format))
769 return;
770
771 if (!drm_dev_enter(drm, &idx))
772 return;
773
774 drm_scdc_set_high_tmds_clock_ratio(connector, true);
775 drm_scdc_set_scrambling(connector, true);
776
777 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
778 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
779 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
780 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
781
782 drm_dev_exit(idx);
783
784 vc4_hdmi->scdc_enabled = true;
785
786 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
787 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
788 }
789
vc4_hdmi_disable_scrambling(struct drm_encoder * encoder)790 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
791 {
792 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
793 struct drm_connector *connector = &vc4_hdmi->connector;
794 struct drm_device *drm = connector->dev;
795 unsigned long flags;
796 int idx;
797
798 lockdep_assert_held(&vc4_hdmi->mutex);
799
800 if (!vc4_hdmi->scdc_enabled)
801 return;
802
803 vc4_hdmi->scdc_enabled = false;
804
805 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
806 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
807
808 if (!drm_dev_enter(drm, &idx))
809 return;
810
811 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
812 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
813 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
814 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
815
816 drm_scdc_set_scrambling(connector, false);
817 drm_scdc_set_high_tmds_clock_ratio(connector, false);
818
819 drm_dev_exit(idx);
820 }
821
vc4_hdmi_scrambling_wq(struct work_struct * work)822 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
823 {
824 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
825 struct vc4_hdmi,
826 scrambling_work);
827 struct drm_connector *connector = &vc4_hdmi->connector;
828
829 if (drm_scdc_get_scrambling_status(connector))
830 return;
831
832 drm_scdc_set_high_tmds_clock_ratio(connector, true);
833 drm_scdc_set_scrambling(connector, true);
834
835 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
836 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
837 }
838
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)839 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
840 struct drm_atomic_state *state)
841 {
842 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
843 struct drm_device *drm = vc4_hdmi->connector.dev;
844 unsigned long flags;
845 int idx;
846
847 mutex_lock(&vc4_hdmi->mutex);
848
849 vc4_hdmi->packet_ram_enabled = false;
850
851 if (!drm_dev_enter(drm, &idx))
852 goto out;
853
854 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
855
856 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
857
858 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
859
860 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
861
862 mdelay(1);
863
864 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
865 HDMI_WRITE(HDMI_VID_CTL,
866 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
867 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
868
869 vc4_hdmi_disable_scrambling(encoder);
870
871 drm_dev_exit(idx);
872
873 out:
874 mutex_unlock(&vc4_hdmi->mutex);
875 }
876
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder,struct drm_atomic_state * state)877 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
878 struct drm_atomic_state *state)
879 {
880 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
881 struct drm_device *drm = vc4_hdmi->connector.dev;
882 unsigned long flags;
883 int ret;
884 int idx;
885
886 mutex_lock(&vc4_hdmi->mutex);
887
888 if (!drm_dev_enter(drm, &idx))
889 goto out;
890
891 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
892 HDMI_WRITE(HDMI_VID_CTL,
893 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
894 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
895
896 if (vc4_hdmi->variant->phy_disable)
897 vc4_hdmi->variant->phy_disable(vc4_hdmi);
898
899 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
900 clk_disable_unprepare(vc4_hdmi->pixel_clock);
901
902 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
903 if (ret < 0)
904 drm_err(drm, "Failed to release power domain: %d\n", ret);
905
906 drm_dev_exit(idx);
907
908 out:
909 mutex_unlock(&vc4_hdmi->mutex);
910 }
911
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)912 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
913 struct drm_connector_state *state,
914 const struct drm_display_mode *mode)
915 {
916 struct drm_device *drm = vc4_hdmi->connector.dev;
917 unsigned long flags;
918 u32 csc_ctl;
919 int idx;
920
921 if (!drm_dev_enter(drm, &idx))
922 return;
923
924 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
925
926 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
927 VC4_HD_CSC_CTL_ORDER);
928
929 if (state->hdmi.is_limited_range) {
930 /* CEA VICs other than #1 requre limited range RGB
931 * output unless overridden by an AVI infoframe.
932 * Apply a colorspace conversion to squash 0-255 down
933 * to 16-235. The matrix here is:
934 *
935 * [ 0 0 0.8594 16]
936 * [ 0 0.8594 0 16]
937 * [ 0.8594 0 0 16]
938 * [ 0 0 0 1]
939 */
940 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
941 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
942 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
943 VC4_HD_CSC_CTL_MODE);
944
945 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
946 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
947 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
948 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
949 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
950 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
951 }
952
953 /* The RGB order applies even when CSC is disabled. */
954 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
955
956 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
957
958 drm_dev_exit(idx);
959 }
960
961 /*
962 * Matrices for (internal) RGB to RGB output.
963 *
964 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
965 */
966 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
967 {
968 /*
969 * Full range - unity
970 *
971 * [ 1 0 0 0]
972 * [ 0 1 0 0]
973 * [ 0 0 1 0]
974 */
975 { 0x2000, 0x0000, 0x0000, 0x0000 },
976 { 0x0000, 0x2000, 0x0000, 0x0000 },
977 { 0x0000, 0x0000, 0x2000, 0x0000 },
978 },
979 {
980 /*
981 * Limited range
982 *
983 * CEA VICs other than #1 require limited range RGB
984 * output unless overridden by an AVI infoframe. Apply a
985 * colorspace conversion to squash 0-255 down to 16-235.
986 * The matrix here is:
987 *
988 * [ 0.8594 0 0 16]
989 * [ 0 0.8594 0 16]
990 * [ 0 0 0.8594 16]
991 */
992 { 0x1b80, 0x0000, 0x0000, 0x0400 },
993 { 0x0000, 0x1b80, 0x0000, 0x0400 },
994 { 0x0000, 0x0000, 0x1b80, 0x0400 },
995 },
996 };
997
998 /*
999 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1000 *
1001 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1002 */
1003 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1004 {
1005 /*
1006 * Full Range
1007 *
1008 * [ 0.299000 0.587000 0.114000 0 ]
1009 * [ -0.168736 -0.331264 0.500000 128 ]
1010 * [ 0.500000 -0.418688 -0.081312 128 ]
1011 */
1012 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1013 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1014 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1015 },
1016 {
1017 /* Limited Range
1018 *
1019 * [ 0.255785 0.502160 0.097523 16 ]
1020 * [ -0.147644 -0.289856 0.437500 128 ]
1021 * [ 0.437500 -0.366352 -0.071148 128 ]
1022 */
1023 { 0x082f, 0x1012, 0x031f, 0x0400 },
1024 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1025 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1026 },
1027 };
1028
1029 /*
1030 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1031 *
1032 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1033 */
1034 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1035 {
1036 /*
1037 * Full Range
1038 *
1039 * [ 0.212600 0.715200 0.072200 0 ]
1040 * [ -0.114572 -0.385428 0.500000 128 ]
1041 * [ 0.500000 -0.454153 -0.045847 128 ]
1042 */
1043 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1044 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1045 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1046 },
1047 {
1048 /*
1049 * Limited Range
1050 *
1051 * [ 0.181906 0.611804 0.061758 16 ]
1052 * [ -0.100268 -0.337232 0.437500 128 ]
1053 * [ 0.437500 -0.397386 -0.040114 128 ]
1054 */
1055 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1056 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1057 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1058 },
1059 };
1060
1061 /*
1062 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1063 *
1064 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1065 */
1066 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1067 {
1068 /*
1069 * Full Range
1070 *
1071 * [ 0.262700 0.678000 0.059300 0 ]
1072 * [ -0.139630 -0.360370 0.500000 128 ]
1073 * [ 0.500000 -0.459786 -0.040214 128 ]
1074 */
1075 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1076 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1077 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1078 },
1079 {
1080 /* Limited Range
1081 *
1082 * [ 0.224732 0.580008 0.050729 16 ]
1083 * [ -0.122176 -0.315324 0.437500 128 ]
1084 * [ 0.437500 -0.402312 -0.035188 128 ]
1085 */
1086 { 0x082f, 0x1012, 0x031f, 0x0400 },
1087 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1088 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1089 },
1090 };
1091
vc5_hdmi_set_csc_coeffs(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1092 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1093 const u16 coeffs[3][4])
1094 {
1095 lockdep_assert_held(&vc4_hdmi->hw_lock);
1096
1097 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1098 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1099 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1100 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1101 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1102 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1103 }
1104
vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1105 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1106 const u16 coeffs[3][4])
1107 {
1108 lockdep_assert_held(&vc4_hdmi->hw_lock);
1109
1110 /* YUV444 needs the CSC matrices using the channels in a different order */
1111 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1112 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1113 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1114 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1115 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1116 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1117 }
1118
1119 static const u16
vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi * vc4_hdmi,u32 colorspace,bool limited)1120 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1121 {
1122 switch (colorspace) {
1123 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1124 case DRM_MODE_COLORIMETRY_XVYCC_601:
1125 case DRM_MODE_COLORIMETRY_SYCC_601:
1126 case DRM_MODE_COLORIMETRY_OPYCC_601:
1127 case DRM_MODE_COLORIMETRY_BT601_YCC:
1128 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1129
1130 default:
1131 case DRM_MODE_COLORIMETRY_NO_DATA:
1132 case DRM_MODE_COLORIMETRY_BT709_YCC:
1133 case DRM_MODE_COLORIMETRY_XVYCC_709:
1134 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1135 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1136 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1137
1138 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1139 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1140 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1141 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1142 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1143 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1144 }
1145 }
1146
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1147 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1148 struct drm_connector_state *state,
1149 const struct drm_display_mode *mode)
1150 {
1151 struct drm_device *drm = vc4_hdmi->connector.dev;
1152 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0;
1153 unsigned long flags;
1154 const u16 (*csc)[4];
1155 u32 if_cfg = 0;
1156 u32 if_xbar = 0x543210;
1157 u32 csc_chan_ctl = 0;
1158 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1159 VC5_MT_CP_CSC_CTL_MODE);
1160 int idx;
1161
1162 if (!drm_dev_enter(drm, &idx))
1163 return;
1164
1165 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1166
1167 switch (state->hdmi.output_format) {
1168 case HDMI_COLORSPACE_YUV444:
1169 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1170
1171 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1172 break;
1173
1174 case HDMI_COLORSPACE_YUV422:
1175 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1176
1177 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1178 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1179 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1180 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1181
1182 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1183 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1184
1185 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1186 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1187
1188 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1189 break;
1190
1191 case HDMI_COLORSPACE_RGB:
1192 if_xbar = 0x354021;
1193
1194 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1195 break;
1196
1197 default:
1198 break;
1199 }
1200
1201 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1202 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1203 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1204 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1205
1206 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1207
1208 drm_dev_exit(idx);
1209 }
1210
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1211 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1212 struct drm_connector_state *state,
1213 const struct drm_display_mode *mode)
1214 {
1215 struct drm_device *drm = vc4_hdmi->connector.dev;
1216 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1217 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1218 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1219 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1220 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1221 VC4_HDMI_VERTA_VSP) |
1222 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1223 VC4_HDMI_VERTA_VFP) |
1224 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1225 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1226 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1227 interlaced,
1228 VC4_HDMI_VERTB_VBP));
1229 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1230 VC4_SET_FIELD(mode->crtc_vtotal -
1231 mode->crtc_vsync_end,
1232 VC4_HDMI_VERTB_VBP));
1233 unsigned long flags;
1234 u32 reg;
1235 int idx;
1236
1237 if (!drm_dev_enter(drm, &idx))
1238 return;
1239
1240 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1241
1242 HDMI_WRITE(HDMI_HORZA,
1243 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1244 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1245 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1246 VC4_HDMI_HORZA_HAP));
1247
1248 HDMI_WRITE(HDMI_HORZB,
1249 VC4_SET_FIELD((mode->htotal -
1250 mode->hsync_end) * pixel_rep,
1251 VC4_HDMI_HORZB_HBP) |
1252 VC4_SET_FIELD((mode->hsync_end -
1253 mode->hsync_start) * pixel_rep,
1254 VC4_HDMI_HORZB_HSP) |
1255 VC4_SET_FIELD((mode->hsync_start -
1256 mode->hdisplay) * pixel_rep,
1257 VC4_HDMI_HORZB_HFP));
1258
1259 HDMI_WRITE(HDMI_VERTA0, verta);
1260 HDMI_WRITE(HDMI_VERTA1, verta);
1261
1262 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1263 HDMI_WRITE(HDMI_VERTB1, vertb);
1264
1265 reg = HDMI_READ(HDMI_MISC_CONTROL);
1266 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1267 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1268 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1269
1270 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1271
1272 drm_dev_exit(idx);
1273 }
1274
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1275 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1276 struct drm_connector_state *state,
1277 const struct drm_display_mode *mode)
1278 {
1279 struct drm_device *drm = vc4_hdmi->connector.dev;
1280 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1281 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1282 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1283 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1284 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1285 VC5_HDMI_VERTA_VSP) |
1286 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1287 VC5_HDMI_VERTA_VFP) |
1288 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1289 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1290 VC5_HDMI_VERTB_VSPO) |
1291 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1292 interlaced,
1293 VC4_HDMI_VERTB_VBP));
1294 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1295 VC4_SET_FIELD(mode->crtc_vtotal -
1296 mode->crtc_vsync_end,
1297 VC4_HDMI_VERTB_VBP));
1298 unsigned long flags;
1299 unsigned char gcp;
1300 u32 reg;
1301 int idx;
1302
1303 if (!drm_dev_enter(drm, &idx))
1304 return;
1305
1306 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1307
1308 HDMI_WRITE(HDMI_HORZA,
1309 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1310 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1311 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1312 VC5_HDMI_HORZA_HAP) |
1313 VC4_SET_FIELD((mode->hsync_start -
1314 mode->hdisplay) * pixel_rep,
1315 VC5_HDMI_HORZA_HFP));
1316
1317 HDMI_WRITE(HDMI_HORZB,
1318 VC4_SET_FIELD((mode->htotal -
1319 mode->hsync_end) * pixel_rep,
1320 VC5_HDMI_HORZB_HBP) |
1321 VC4_SET_FIELD((mode->hsync_end -
1322 mode->hsync_start) * pixel_rep,
1323 VC5_HDMI_HORZB_HSP));
1324
1325 HDMI_WRITE(HDMI_VERTA0, verta);
1326 HDMI_WRITE(HDMI_VERTA1, verta);
1327
1328 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1329 HDMI_WRITE(HDMI_VERTB1, vertb);
1330
1331 switch (state->hdmi.output_bpc) {
1332 case 12:
1333 gcp = 6;
1334 break;
1335 case 10:
1336 gcp = 5;
1337 break;
1338 case 8:
1339 default:
1340 gcp = 0;
1341 break;
1342 }
1343
1344 /*
1345 * YCC422 is always 36-bit and not considered deep colour so
1346 * doesn't signal in GCP.
1347 */
1348 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) {
1349 gcp = 0;
1350 }
1351
1352 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1353 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1354 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1355 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1356 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1357 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1358
1359 reg = HDMI_READ(HDMI_GCP_WORD_1);
1360 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1361 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1362 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1363 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1364 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1365
1366 reg = HDMI_READ(HDMI_GCP_CONFIG);
1367 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1368 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1369
1370 reg = HDMI_READ(HDMI_MISC_CONTROL);
1371 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1372 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1373 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1374
1375 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1376
1377 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1378
1379 drm_dev_exit(idx);
1380 }
1381
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)1382 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1383 {
1384 struct drm_device *drm = vc4_hdmi->connector.dev;
1385 unsigned long flags;
1386 u32 drift;
1387 int ret;
1388 int idx;
1389
1390 if (!drm_dev_enter(drm, &idx))
1391 return;
1392
1393 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1394
1395 drift = HDMI_READ(HDMI_FIFO_CTL);
1396 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1397
1398 HDMI_WRITE(HDMI_FIFO_CTL,
1399 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1400 HDMI_WRITE(HDMI_FIFO_CTL,
1401 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1402
1403 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1404
1405 usleep_range(1000, 1100);
1406
1407 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1408
1409 HDMI_WRITE(HDMI_FIFO_CTL,
1410 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1411 HDMI_WRITE(HDMI_FIFO_CTL,
1412 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1413
1414 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1415
1416 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1417 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1418 WARN_ONCE(ret, "Timeout waiting for "
1419 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1420
1421 drm_dev_exit(idx);
1422 }
1423
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder,struct drm_atomic_state * state)1424 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1425 struct drm_atomic_state *state)
1426 {
1427 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1428 struct drm_device *drm = vc4_hdmi->connector.dev;
1429 struct drm_connector *connector = &vc4_hdmi->connector;
1430 struct drm_connector_state *conn_state =
1431 drm_atomic_get_new_connector_state(state, connector);
1432 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1433 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate;
1434 unsigned long bvb_rate, hsm_rate;
1435 unsigned long flags;
1436 int ret;
1437 int idx;
1438
1439 mutex_lock(&vc4_hdmi->mutex);
1440
1441 if (!drm_dev_enter(drm, &idx))
1442 goto out;
1443
1444 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1445 if (ret < 0) {
1446 drm_err(drm, "Failed to retain power domain: %d\n", ret);
1447 goto err_dev_exit;
1448 }
1449
1450 /*
1451 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1452 * be faster than pixel clock, infinitesimally faster, tested in
1453 * simulation. Otherwise, exact value is unimportant for HDMI
1454 * operation." This conflicts with bcm2835's vc4 documentation, which
1455 * states HSM's clock has to be at least 108% of the pixel clock.
1456 *
1457 * Real life tests reveal that vc4's firmware statement holds up, and
1458 * users are able to use pixel clocks closer to HSM's, namely for
1459 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1460 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1461 * 162MHz.
1462 *
1463 * Additionally, the AXI clock needs to be at least 25% of
1464 * pixel clock, but HSM ends up being the limiting factor.
1465 */
1466 hsm_rate = max_t(unsigned long,
1467 HSM_MIN_CLOCK_FREQ,
1468 div_u64(tmds_char_rate, 100) * 101);
1469 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1470 if (ret) {
1471 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1472 goto err_put_runtime_pm;
1473 }
1474
1475 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1476 if (ret) {
1477 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1478 goto err_put_runtime_pm;
1479 }
1480
1481 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1482 if (ret) {
1483 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1484 goto err_put_runtime_pm;
1485 }
1486
1487
1488 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1489
1490 if (tmds_char_rate > 297000000)
1491 bvb_rate = 300000000;
1492 else if (tmds_char_rate > 148500000)
1493 bvb_rate = 150000000;
1494 else
1495 bvb_rate = 75000000;
1496
1497 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1498 if (ret) {
1499 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1500 goto err_disable_pixel_clock;
1501 }
1502
1503 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1504 if (ret) {
1505 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1506 goto err_disable_pixel_clock;
1507 }
1508
1509 if (vc4_hdmi->variant->phy_init)
1510 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state);
1511
1512 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1513
1514 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1515 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1516 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1517 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1518
1519 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1520
1521 if (vc4_hdmi->variant->set_timings)
1522 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1523
1524 drm_dev_exit(idx);
1525
1526 mutex_unlock(&vc4_hdmi->mutex);
1527
1528 return;
1529
1530 err_disable_pixel_clock:
1531 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1532 err_put_runtime_pm:
1533 pm_runtime_put(&vc4_hdmi->pdev->dev);
1534 err_dev_exit:
1535 drm_dev_exit(idx);
1536 out:
1537 mutex_unlock(&vc4_hdmi->mutex);
1538 return;
1539 }
1540
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1541 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1542 struct drm_atomic_state *state)
1543 {
1544 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1545 struct drm_device *drm = vc4_hdmi->connector.dev;
1546 struct drm_connector *connector = &vc4_hdmi->connector;
1547 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1548 struct drm_connector_state *conn_state =
1549 drm_atomic_get_new_connector_state(state, connector);
1550 unsigned long flags;
1551 int idx;
1552
1553 mutex_lock(&vc4_hdmi->mutex);
1554
1555 if (!drm_dev_enter(drm, &idx))
1556 goto out;
1557
1558 if (vc4_hdmi->variant->csc_setup)
1559 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1560
1561 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1562 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1563 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1564
1565 drm_dev_exit(idx);
1566
1567 out:
1568 mutex_unlock(&vc4_hdmi->mutex);
1569 }
1570
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1571 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1572 struct drm_atomic_state *state)
1573 {
1574 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1575 struct drm_connector *connector = &vc4_hdmi->connector;
1576 struct drm_device *drm = connector->dev;
1577 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1578 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1579 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1580 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1581 unsigned long flags;
1582 int ret;
1583 int idx;
1584
1585 mutex_lock(&vc4_hdmi->mutex);
1586
1587 if (!drm_dev_enter(drm, &idx))
1588 goto out;
1589
1590 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1591
1592 HDMI_WRITE(HDMI_VID_CTL,
1593 VC4_HD_VID_CTL_ENABLE |
1594 VC4_HD_VID_CTL_CLRRGB |
1595 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1596 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1597 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1598 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1599
1600 HDMI_WRITE(HDMI_VID_CTL,
1601 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1602
1603 if (display->is_hdmi) {
1604 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1605 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1606 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1607
1608 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1609
1610 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1611 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1612 WARN_ONCE(ret, "Timeout waiting for "
1613 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1614 } else {
1615 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1616 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1617 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1618 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1619 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1620 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1621
1622 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1623
1624 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1625 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1626 WARN_ONCE(ret, "Timeout waiting for "
1627 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1628 }
1629
1630 if (display->is_hdmi) {
1631 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1632
1633 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1634 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1635
1636 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1637 VC4_HDMI_RAM_PACKET_ENABLE);
1638
1639 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1640 vc4_hdmi->packet_ram_enabled = true;
1641
1642 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
1643 }
1644
1645 vc4_hdmi_recenter_fifo(vc4_hdmi);
1646 vc4_hdmi_enable_scrambling(encoder);
1647
1648 drm_dev_exit(idx);
1649
1650 out:
1651 mutex_unlock(&vc4_hdmi->mutex);
1652 }
1653
vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1654 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1655 struct drm_crtc_state *crtc_state,
1656 struct drm_connector_state *conn_state)
1657 {
1658 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1659
1660 mutex_lock(&vc4_hdmi->mutex);
1661 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1662 &crtc_state->adjusted_mode);
1663 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc;
1664 vc4_hdmi->output_format = conn_state->hdmi.output_format;
1665 mutex_unlock(&vc4_hdmi->mutex);
1666 }
1667
1668 static enum drm_mode_status
vc4_hdmi_connector_clock_valid(const struct drm_connector * connector,const struct drm_display_mode * mode,unsigned long long clock)1669 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector,
1670 const struct drm_display_mode *mode,
1671 unsigned long long clock)
1672 {
1673 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1674 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1675
1676 if (clock > vc4_hdmi->variant->max_pixel_clock)
1677 return MODE_CLOCK_HIGH;
1678
1679 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1680 return MODE_CLOCK_HIGH;
1681
1682 /* 4096x2160@60 is not reliable without overclocking core */
1683 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1684 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1685 drm_mode_vrefresh(mode) >= 50)
1686 return MODE_CLOCK_HIGH;
1687
1688 return MODE_OK;
1689 }
1690
1691 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = {
1692 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid,
1693 .write_infoframe = vc4_hdmi_write_infoframe,
1694 };
1695
1696 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1697 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1698
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1699 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1700 struct drm_crtc_state *crtc_state,
1701 struct drm_connector_state *conn_state)
1702 {
1703 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1704 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1705 unsigned long long tmds_char_rate = mode->clock * 1000;
1706 unsigned long long tmds_bit_rate;
1707
1708 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1709 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1710 /* Only try to fixup DBLCLK modes to get 480i and 576i
1711 * working.
1712 * A generic solution for all modes with odd horizontal
1713 * timing values seems impossible based on trying to
1714 * solve it for 1366x768 monitors.
1715 */
1716 if ((mode->hsync_start - mode->hdisplay) & 1)
1717 mode->hsync_start--;
1718 if ((mode->hsync_end - mode->hsync_start) & 1)
1719 mode->hsync_end--;
1720 }
1721
1722 /* Now check whether we still have odd values remaining */
1723 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1724 (mode->hsync_end % 2) || (mode->htotal % 2))
1725 return -EINVAL;
1726 }
1727
1728 /*
1729 * The 1440p@60 pixel rate is in the same range than the first
1730 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1731 * bandwidth). Slightly lower the frequency to bring it out of
1732 * the WiFi range.
1733 */
1734 tmds_bit_rate = tmds_char_rate * 10;
1735 if (vc4_hdmi->disable_wifi_frequencies &&
1736 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1737 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1738 mode->clock = 238560;
1739 tmds_char_rate = mode->clock * 1000;
1740 }
1741
1742 return 0;
1743 }
1744
1745 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)1746 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1747 const struct drm_display_mode *mode)
1748 {
1749 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1750 unsigned long long rate;
1751
1752 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1753 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1754 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1755 (mode->hsync_end % 2) || (mode->htotal % 2)))
1756 return MODE_H_ILLEGAL;
1757
1758 rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
1759 return vc4_hdmi_connector_clock_valid(&vc4_hdmi->connector, mode, rate);
1760 }
1761
1762 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1763 .atomic_check = vc4_hdmi_encoder_atomic_check,
1764 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1765 .mode_valid = vc4_hdmi_encoder_mode_valid,
1766 };
1767
vc4_hdmi_late_register(struct drm_encoder * encoder)1768 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1769 {
1770 struct drm_device *drm = encoder->dev;
1771 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1772 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1773
1774 drm_debugfs_add_file(drm, variant->debugfs_name,
1775 vc4_hdmi_debugfs_regs, vc4_hdmi);
1776
1777 return 0;
1778 }
1779
1780 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1781 .late_register = vc4_hdmi_late_register,
1782 };
1783
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1784 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1785 {
1786 int i;
1787 u32 channel_map = 0;
1788
1789 for (i = 0; i < 8; i++) {
1790 if (channel_mask & BIT(i))
1791 channel_map |= i << (3 * i);
1792 }
1793 return channel_map;
1794 }
1795
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1796 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1797 {
1798 int i;
1799 u32 channel_map = 0;
1800
1801 for (i = 0; i < 8; i++) {
1802 if (channel_mask & BIT(i))
1803 channel_map |= i << (4 * i);
1804 }
1805 return channel_map;
1806 }
1807
vc5_hdmi_hp_detect(struct vc4_hdmi * vc4_hdmi)1808 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1809 {
1810 struct drm_device *drm = vc4_hdmi->connector.dev;
1811 unsigned long flags;
1812 u32 hotplug;
1813 int idx;
1814
1815 if (!drm_dev_enter(drm, &idx))
1816 return false;
1817
1818 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1819 hotplug = HDMI_READ(HDMI_HOTPLUG);
1820 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1821
1822 drm_dev_exit(idx);
1823
1824 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1825 }
1826
1827 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1828 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1829 unsigned int samplerate)
1830 {
1831 struct drm_device *drm = vc4_hdmi->connector.dev;
1832 u32 hsm_clock;
1833 unsigned long flags;
1834 unsigned long n, m;
1835 int idx;
1836
1837 if (!drm_dev_enter(drm, &idx))
1838 return;
1839
1840 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1841 rational_best_approximation(hsm_clock, samplerate,
1842 VC4_HD_MAI_SMP_N_MASK >>
1843 VC4_HD_MAI_SMP_N_SHIFT,
1844 (VC4_HD_MAI_SMP_M_MASK >>
1845 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1846 &n, &m);
1847
1848 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1849 HDMI_WRITE(HDMI_MAI_SMP,
1850 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1851 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1852 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1853
1854 drm_dev_exit(idx);
1855 }
1856
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1857 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1858 {
1859 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1860 u32 n, cts;
1861 u64 tmp;
1862
1863 lockdep_assert_held(&vc4_hdmi->mutex);
1864 lockdep_assert_held(&vc4_hdmi->hw_lock);
1865
1866 n = 128 * samplerate / 1000;
1867 tmp = (u64)(mode->clock * 1000) * n;
1868 do_div(tmp, 128 * samplerate);
1869 cts = tmp;
1870
1871 HDMI_WRITE(HDMI_CRP_CFG,
1872 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1873 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1874
1875 /*
1876 * We could get slightly more accurate clocks in some cases by
1877 * providing a CTS_1 value. The two CTS values are alternated
1878 * between based on the period fields
1879 */
1880 HDMI_WRITE(HDMI_CTS_0, cts);
1881 HDMI_WRITE(HDMI_CTS_1, cts);
1882 }
1883
dai_to_hdmi(struct snd_soc_dai * dai)1884 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1885 {
1886 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1887
1888 return snd_soc_card_get_drvdata(card);
1889 }
1890
vc4_hdmi_audio_can_stream(struct vc4_hdmi * vc4_hdmi)1891 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1892 {
1893 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1894
1895 lockdep_assert_held(&vc4_hdmi->mutex);
1896
1897 /*
1898 * If the encoder is currently in DVI mode, treat the codec DAI
1899 * as missing.
1900 */
1901 if (!display->is_hdmi)
1902 return false;
1903
1904 return true;
1905 }
1906
vc4_hdmi_audio_startup(struct device * dev,void * data)1907 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1908 {
1909 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1910 struct drm_device *drm = vc4_hdmi->connector.dev;
1911 unsigned long flags;
1912 int ret = 0;
1913 int idx;
1914
1915 mutex_lock(&vc4_hdmi->mutex);
1916
1917 if (!drm_dev_enter(drm, &idx)) {
1918 ret = -ENODEV;
1919 goto out;
1920 }
1921
1922 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1923 ret = -ENODEV;
1924 goto out_dev_exit;
1925 }
1926
1927 vc4_hdmi->audio.streaming = true;
1928
1929 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1930 HDMI_WRITE(HDMI_MAI_CTL,
1931 VC4_HD_MAI_CTL_RESET |
1932 VC4_HD_MAI_CTL_FLUSH |
1933 VC4_HD_MAI_CTL_DLATE |
1934 VC4_HD_MAI_CTL_ERRORE |
1935 VC4_HD_MAI_CTL_ERRORF);
1936 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1937
1938 if (vc4_hdmi->variant->phy_rng_enable)
1939 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1940
1941 out_dev_exit:
1942 drm_dev_exit(idx);
1943 out:
1944 mutex_unlock(&vc4_hdmi->mutex);
1945
1946 return ret;
1947 }
1948
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)1949 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1950 {
1951 struct device *dev = &vc4_hdmi->pdev->dev;
1952 unsigned long flags;
1953 int ret;
1954
1955 lockdep_assert_held(&vc4_hdmi->mutex);
1956
1957 vc4_hdmi->audio.streaming = false;
1958 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false);
1959 if (ret)
1960 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1961
1962 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1963
1964 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1965 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1966 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1967
1968 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1969 }
1970
vc4_hdmi_audio_shutdown(struct device * dev,void * data)1971 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1972 {
1973 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1974 struct drm_device *drm = vc4_hdmi->connector.dev;
1975 unsigned long flags;
1976 int idx;
1977
1978 mutex_lock(&vc4_hdmi->mutex);
1979
1980 if (!drm_dev_enter(drm, &idx))
1981 goto out;
1982
1983 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1984
1985 HDMI_WRITE(HDMI_MAI_CTL,
1986 VC4_HD_MAI_CTL_DLATE |
1987 VC4_HD_MAI_CTL_ERRORE |
1988 VC4_HD_MAI_CTL_ERRORF);
1989
1990 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1991
1992 if (vc4_hdmi->variant->phy_rng_disable)
1993 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1994
1995 vc4_hdmi->audio.streaming = false;
1996 vc4_hdmi_audio_reset(vc4_hdmi);
1997
1998 drm_dev_exit(idx);
1999
2000 out:
2001 mutex_unlock(&vc4_hdmi->mutex);
2002 }
2003
sample_rate_to_mai_fmt(int samplerate)2004 static int sample_rate_to_mai_fmt(int samplerate)
2005 {
2006 switch (samplerate) {
2007 case 8000:
2008 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2009 case 11025:
2010 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2011 case 12000:
2012 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2013 case 16000:
2014 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2015 case 22050:
2016 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2017 case 24000:
2018 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2019 case 32000:
2020 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2021 case 44100:
2022 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2023 case 48000:
2024 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2025 case 64000:
2026 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2027 case 88200:
2028 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2029 case 96000:
2030 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2031 case 128000:
2032 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2033 case 176400:
2034 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2035 case 192000:
2036 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2037 default:
2038 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2039 }
2040 }
2041
2042 /* HDMI audio codec callbacks */
vc4_hdmi_audio_prepare(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2043 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2044 struct hdmi_codec_daifmt *daifmt,
2045 struct hdmi_codec_params *params)
2046 {
2047 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2048 struct drm_device *drm = vc4_hdmi->connector.dev;
2049 struct drm_connector *connector = &vc4_hdmi->connector;
2050 unsigned int sample_rate = params->sample_rate;
2051 unsigned int channels = params->channels;
2052 unsigned long flags;
2053 u32 audio_packet_config, channel_mask;
2054 u32 channel_map;
2055 u32 mai_audio_format;
2056 u32 mai_sample_rate;
2057 int ret = 0;
2058 int idx;
2059
2060 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2061 sample_rate, params->sample_width, channels);
2062
2063 mutex_lock(&vc4_hdmi->mutex);
2064
2065 if (!drm_dev_enter(drm, &idx)) {
2066 ret = -ENODEV;
2067 goto out;
2068 }
2069
2070 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2071 ret = -EINVAL;
2072 goto out_dev_exit;
2073 }
2074
2075 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2076
2077 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2078 HDMI_WRITE(HDMI_MAI_CTL,
2079 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2080 VC4_HD_MAI_CTL_WHOLSMP |
2081 VC4_HD_MAI_CTL_CHALIGN |
2082 VC4_HD_MAI_CTL_ENABLE);
2083
2084 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2085 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2086 params->channels == 8)
2087 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2088 else
2089 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2090 HDMI_WRITE(HDMI_MAI_FMT,
2091 VC4_SET_FIELD(mai_sample_rate,
2092 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2093 VC4_SET_FIELD(mai_audio_format,
2094 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2095
2096 /* The B frame identifier should match the value used by alsa-lib (8) */
2097 audio_packet_config =
2098 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2099 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2100 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2101
2102 channel_mask = GENMASK(channels - 1, 0);
2103 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2104 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2105
2106 /* Set the MAI threshold */
2107 HDMI_WRITE(HDMI_MAI_THR,
2108 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2109 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2110 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2111 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2112
2113 HDMI_WRITE(HDMI_MAI_CONFIG,
2114 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2115 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2116 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2117
2118 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2119 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2120 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2121
2122 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2123
2124 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2125
2126 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
2127 ¶ms->cea);
2128 if (ret)
2129 goto out_dev_exit;
2130
2131 out_dev_exit:
2132 drm_dev_exit(idx);
2133 out:
2134 mutex_unlock(&vc4_hdmi->mutex);
2135
2136 return ret;
2137 }
2138
2139 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2140 .name = "vc4-hdmi-cpu-dai-component",
2141 .legacy_dai_naming = 1,
2142 };
2143
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)2144 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2145 {
2146 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2147
2148 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2149
2150 return 0;
2151 }
2152
2153 static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2154 .probe = vc4_hdmi_audio_cpu_dai_probe,
2155 };
2156
2157 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2158 .name = "vc4-hdmi-cpu-dai",
2159 .ops = &vc4_snd_dai_ops,
2160 .playback = {
2161 .stream_name = "Playback",
2162 .channels_min = 1,
2163 .channels_max = 8,
2164 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2165 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2166 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2167 SNDRV_PCM_RATE_192000,
2168 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2169 },
2170 };
2171
2172 static const struct snd_dmaengine_pcm_config pcm_conf = {
2173 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2174 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2175 };
2176
vc4_hdmi_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)2177 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2178 uint8_t *buf, size_t len)
2179 {
2180 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2181 struct drm_connector *connector = &vc4_hdmi->connector;
2182
2183 mutex_lock(&vc4_hdmi->mutex);
2184 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2185 mutex_unlock(&vc4_hdmi->mutex);
2186
2187 return 0;
2188 }
2189
2190 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2191 .get_eld = vc4_hdmi_audio_get_eld,
2192 .prepare = vc4_hdmi_audio_prepare,
2193 .audio_shutdown = vc4_hdmi_audio_shutdown,
2194 .audio_startup = vc4_hdmi_audio_startup,
2195 };
2196
2197 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2198 .ops = &vc4_hdmi_codec_ops,
2199 .max_i2s_channels = 8,
2200 .i2s = 1,
2201 };
2202
vc4_hdmi_audio_codec_release(void * ptr)2203 static void vc4_hdmi_audio_codec_release(void *ptr)
2204 {
2205 struct vc4_hdmi *vc4_hdmi = ptr;
2206
2207 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2208 vc4_hdmi->audio.codec_pdev = NULL;
2209 }
2210
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)2211 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2212 {
2213 const struct vc4_hdmi_register *mai_data =
2214 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2215 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2216 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2217 struct device *dev = &vc4_hdmi->pdev->dev;
2218 struct platform_device *codec_pdev;
2219 const __be32 *addr;
2220 int index, len;
2221 int ret;
2222
2223 /*
2224 * ASoC makes it a bit hard to retrieve a pointer to the
2225 * vc4_hdmi structure. Registering the card will overwrite our
2226 * device drvdata with a pointer to the snd_soc_card structure,
2227 * which can then be used to retrieve whatever drvdata we want
2228 * to associate.
2229 *
2230 * However, that doesn't fly in the case where we wouldn't
2231 * register an ASoC card (because of an old DT that is missing
2232 * the dmas properties for example), then the card isn't
2233 * registered and the device drvdata wouldn't be set.
2234 *
2235 * We can deal with both cases by making sure a snd_soc_card
2236 * pointer and a vc4_hdmi structure are pointing to the same
2237 * memory address, so we can treat them indistinctly without any
2238 * issue.
2239 */
2240 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2241 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2242
2243 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2244 dev_warn(dev,
2245 "'dmas' DT property is missing or empty, no HDMI audio\n");
2246 return 0;
2247 }
2248
2249 if (mai_data->reg != VC4_HD) {
2250 WARN_ONCE(true, "MAI isn't in the HD block\n");
2251 return -EINVAL;
2252 }
2253
2254 /*
2255 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2256 * the bus address specified in the DT, because the physical address
2257 * (the one returned by platform_get_resource()) is not appropriate
2258 * for DMA transfers.
2259 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2260 */
2261 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2262 /* Before BCM2711, we don't have a named register range */
2263 if (index < 0)
2264 index = 1;
2265
2266 addr = of_get_address(dev->of_node, index, NULL, NULL);
2267 if (!addr)
2268 return -EINVAL;
2269
2270 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2271 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2272 vc4_hdmi->audio.dma_data.maxburst = 2;
2273
2274 /*
2275 * NOTE: Strictly speaking, we should probably use a DRM-managed
2276 * registration there to avoid removing all the audio components
2277 * by the time the driver doesn't have any user anymore.
2278 *
2279 * However, the ASoC core uses a number of devm_kzalloc calls
2280 * when registering, even when using non-device-managed
2281 * functions (such as in snd_soc_register_component()).
2282 *
2283 * If we call snd_soc_unregister_component() in a DRM-managed
2284 * action, the device-managed actions have already been executed
2285 * and thus we would access memory that has been freed.
2286 *
2287 * Using device-managed hooks here probably leaves us open to a
2288 * bunch of issues if userspace still has a handle on the ALSA
2289 * device when the device is removed. However, this is mitigated
2290 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2291 * path to prevent the access to the device resources if it
2292 * isn't there anymore.
2293 *
2294 * Then, the vc4_hdmi structure is DRM-managed and thus only
2295 * freed whenever the last user has closed the DRM device file.
2296 * It should thus outlive ALSA in most situations.
2297 */
2298 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2299 if (ret) {
2300 dev_err(dev, "Could not register PCM component: %d\n", ret);
2301 return ret;
2302 }
2303
2304 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2305 &vc4_hdmi_audio_cpu_dai_drv, 1);
2306 if (ret) {
2307 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2308 return ret;
2309 }
2310
2311 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2312 PLATFORM_DEVID_AUTO,
2313 &vc4_hdmi_codec_pdata,
2314 sizeof(vc4_hdmi_codec_pdata));
2315 if (IS_ERR(codec_pdev)) {
2316 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2317 return PTR_ERR(codec_pdev);
2318 }
2319 vc4_hdmi->audio.codec_pdev = codec_pdev;
2320
2321 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2322 if (ret)
2323 return ret;
2324
2325 dai_link->cpus = &vc4_hdmi->audio.cpu;
2326 dai_link->codecs = &vc4_hdmi->audio.codec;
2327 dai_link->platforms = &vc4_hdmi->audio.platform;
2328
2329 dai_link->num_cpus = 1;
2330 dai_link->num_codecs = 1;
2331 dai_link->num_platforms = 1;
2332
2333 dai_link->name = "MAI";
2334 dai_link->stream_name = "MAI PCM";
2335 dai_link->codecs->dai_name = "i2s-hifi";
2336 dai_link->cpus->dai_name = dev_name(dev);
2337 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2338 dai_link->platforms->name = dev_name(dev);
2339
2340 card->dai_link = dai_link;
2341 card->num_links = 1;
2342 card->name = vc4_hdmi->variant->card_name;
2343 card->driver_name = "vc4-hdmi";
2344 card->dev = dev;
2345 card->owner = THIS_MODULE;
2346
2347 /*
2348 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2349 * stores a pointer to the snd card object in dev->driver_data. This
2350 * means we cannot use it for something else. The hdmi back-pointer is
2351 * now stored in card->drvdata and should be retrieved with
2352 * snd_soc_card_get_drvdata() if needed.
2353 */
2354 snd_soc_card_set_drvdata(card, vc4_hdmi);
2355 ret = devm_snd_soc_register_card(dev, card);
2356 if (ret)
2357 dev_err_probe(dev, ret, "Could not register sound card\n");
2358
2359 return ret;
2360
2361 }
2362
vc4_hdmi_hpd_irq_thread(int irq,void * priv)2363 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2364 {
2365 struct vc4_hdmi *vc4_hdmi = priv;
2366 struct drm_connector *connector = &vc4_hdmi->connector;
2367 struct drm_device *dev = connector->dev;
2368
2369 if (dev && dev->registered)
2370 drm_connector_helper_hpd_irq_event(connector);
2371
2372 return IRQ_HANDLED;
2373 }
2374
vc4_hdmi_hotplug_init(struct vc4_hdmi * vc4_hdmi)2375 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2376 {
2377 struct drm_connector *connector = &vc4_hdmi->connector;
2378 struct platform_device *pdev = vc4_hdmi->pdev;
2379 int ret;
2380
2381 if (vc4_hdmi->variant->external_irq_controller) {
2382 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2383 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2384
2385 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2386 NULL,
2387 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2388 "vc4 hdmi hpd connected", vc4_hdmi);
2389 if (ret)
2390 return ret;
2391
2392 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2393 NULL,
2394 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2395 "vc4 hdmi hpd disconnected", vc4_hdmi);
2396 if (ret)
2397 return ret;
2398
2399 connector->polled = DRM_CONNECTOR_POLL_HPD;
2400 }
2401
2402 return 0;
2403 }
2404
2405 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_rx_thread(int irq,void * priv)2406 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2407 {
2408 struct vc4_hdmi *vc4_hdmi = priv;
2409
2410 if (vc4_hdmi->cec_rx_msg.len)
2411 cec_received_msg(vc4_hdmi->cec_adap,
2412 &vc4_hdmi->cec_rx_msg);
2413
2414 return IRQ_HANDLED;
2415 }
2416
vc4_cec_irq_handler_tx_thread(int irq,void * priv)2417 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2418 {
2419 struct vc4_hdmi *vc4_hdmi = priv;
2420
2421 if (vc4_hdmi->cec_tx_ok) {
2422 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2423 0, 0, 0, 0);
2424 } else {
2425 /*
2426 * This CEC implementation makes 1 retry, so if we
2427 * get a NACK, then that means it made 2 attempts.
2428 */
2429 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2430 0, 2, 0, 0);
2431 }
2432 return IRQ_HANDLED;
2433 }
2434
vc4_cec_irq_handler_thread(int irq,void * priv)2435 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2436 {
2437 struct vc4_hdmi *vc4_hdmi = priv;
2438 irqreturn_t ret;
2439
2440 if (vc4_hdmi->cec_irq_was_rx)
2441 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2442 else
2443 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2444
2445 return ret;
2446 }
2447
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)2448 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2449 {
2450 struct drm_device *dev = vc4_hdmi->connector.dev;
2451 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2452 unsigned int i;
2453
2454 lockdep_assert_held(&vc4_hdmi->hw_lock);
2455
2456 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2457 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2458
2459 if (msg->len > 16) {
2460 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2461 return;
2462 }
2463
2464 for (i = 0; i < msg->len; i += 4) {
2465 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2466
2467 msg->msg[i] = val & 0xff;
2468 msg->msg[i + 1] = (val >> 8) & 0xff;
2469 msg->msg[i + 2] = (val >> 16) & 0xff;
2470 msg->msg[i + 3] = (val >> 24) & 0xff;
2471 }
2472 }
2473
vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi * vc4_hdmi)2474 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2475 {
2476 u32 cntrl1;
2477
2478 /*
2479 * We don't need to protect the register access using
2480 * drm_dev_enter() there because the interrupt handler lifetime
2481 * is tied to the device itself, and not to the DRM device.
2482 *
2483 * So when the device will be gone, one of the first thing we
2484 * will be doing will be to unregister the interrupt handler,
2485 * and then unregister the DRM device. drm_dev_enter() would
2486 * thus always succeed if we are here.
2487 */
2488
2489 lockdep_assert_held(&vc4_hdmi->hw_lock);
2490
2491 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2492 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2493 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2494 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2495
2496 return IRQ_WAKE_THREAD;
2497 }
2498
vc4_cec_irq_handler_tx_bare(int irq,void * priv)2499 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2500 {
2501 struct vc4_hdmi *vc4_hdmi = priv;
2502 irqreturn_t ret;
2503
2504 spin_lock(&vc4_hdmi->hw_lock);
2505 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2506 spin_unlock(&vc4_hdmi->hw_lock);
2507
2508 return ret;
2509 }
2510
vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi * vc4_hdmi)2511 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2512 {
2513 u32 cntrl1;
2514
2515 lockdep_assert_held(&vc4_hdmi->hw_lock);
2516
2517 /*
2518 * We don't need to protect the register access using
2519 * drm_dev_enter() there because the interrupt handler lifetime
2520 * is tied to the device itself, and not to the DRM device.
2521 *
2522 * So when the device will be gone, one of the first thing we
2523 * will be doing will be to unregister the interrupt handler,
2524 * and then unregister the DRM device. drm_dev_enter() would
2525 * thus always succeed if we are here.
2526 */
2527
2528 vc4_hdmi->cec_rx_msg.len = 0;
2529 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2530 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2531 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2532 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2533 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2534
2535 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2536
2537 return IRQ_WAKE_THREAD;
2538 }
2539
vc4_cec_irq_handler_rx_bare(int irq,void * priv)2540 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2541 {
2542 struct vc4_hdmi *vc4_hdmi = priv;
2543 irqreturn_t ret;
2544
2545 spin_lock(&vc4_hdmi->hw_lock);
2546 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2547 spin_unlock(&vc4_hdmi->hw_lock);
2548
2549 return ret;
2550 }
2551
vc4_cec_irq_handler(int irq,void * priv)2552 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2553 {
2554 struct vc4_hdmi *vc4_hdmi = priv;
2555 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2556 irqreturn_t ret;
2557 u32 cntrl5;
2558
2559 /*
2560 * We don't need to protect the register access using
2561 * drm_dev_enter() there because the interrupt handler lifetime
2562 * is tied to the device itself, and not to the DRM device.
2563 *
2564 * So when the device will be gone, one of the first thing we
2565 * will be doing will be to unregister the interrupt handler,
2566 * and then unregister the DRM device. drm_dev_enter() would
2567 * thus always succeed if we are here.
2568 */
2569
2570 if (!(stat & VC4_HDMI_CPU_CEC))
2571 return IRQ_NONE;
2572
2573 spin_lock(&vc4_hdmi->hw_lock);
2574 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2575 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2576 if (vc4_hdmi->cec_irq_was_rx)
2577 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2578 else
2579 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2580
2581 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2582 spin_unlock(&vc4_hdmi->hw_lock);
2583
2584 return ret;
2585 }
2586
vc4_hdmi_cec_enable(struct cec_adapter * adap)2587 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2588 {
2589 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2590 struct drm_device *drm = vc4_hdmi->connector.dev;
2591 /* clock period in microseconds */
2592 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2593 unsigned long flags;
2594 u32 val;
2595 int ret;
2596 int idx;
2597
2598 if (!drm_dev_enter(drm, &idx))
2599 /*
2600 * We can't return an error code, because the CEC
2601 * framework will emit WARN_ON messages at unbind
2602 * otherwise.
2603 */
2604 return 0;
2605
2606 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2607 if (ret) {
2608 drm_dev_exit(idx);
2609 return ret;
2610 }
2611
2612 mutex_lock(&vc4_hdmi->mutex);
2613
2614 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2615
2616 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2617 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2618 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2619 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2620 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2621 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2622
2623 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2624 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2625 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2626 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2627 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2628 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2629 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2630 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2631 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2632 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2633 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2634 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2635 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2636 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2637 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2638 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2639 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2640 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2641 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2642
2643 if (!vc4_hdmi->variant->external_irq_controller)
2644 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2645
2646 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2647
2648 mutex_unlock(&vc4_hdmi->mutex);
2649 drm_dev_exit(idx);
2650
2651 return 0;
2652 }
2653
vc4_hdmi_cec_disable(struct cec_adapter * adap)2654 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2655 {
2656 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2657 struct drm_device *drm = vc4_hdmi->connector.dev;
2658 unsigned long flags;
2659 int idx;
2660
2661 if (!drm_dev_enter(drm, &idx))
2662 /*
2663 * We can't return an error code, because the CEC
2664 * framework will emit WARN_ON messages at unbind
2665 * otherwise.
2666 */
2667 return 0;
2668
2669 mutex_lock(&vc4_hdmi->mutex);
2670
2671 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2672
2673 if (!vc4_hdmi->variant->external_irq_controller)
2674 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2675
2676 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2677 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2678
2679 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2680
2681 mutex_unlock(&vc4_hdmi->mutex);
2682
2683 pm_runtime_put(&vc4_hdmi->pdev->dev);
2684
2685 drm_dev_exit(idx);
2686
2687 return 0;
2688 }
2689
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)2690 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2691 {
2692 if (enable)
2693 return vc4_hdmi_cec_enable(adap);
2694 else
2695 return vc4_hdmi_cec_disable(adap);
2696 }
2697
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)2698 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2699 {
2700 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2701 struct drm_device *drm = vc4_hdmi->connector.dev;
2702 unsigned long flags;
2703 int idx;
2704
2705 if (!drm_dev_enter(drm, &idx))
2706 /*
2707 * We can't return an error code, because the CEC
2708 * framework will emit WARN_ON messages at unbind
2709 * otherwise.
2710 */
2711 return 0;
2712
2713 mutex_lock(&vc4_hdmi->mutex);
2714 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2715 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2716 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2717 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2718 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2719 mutex_unlock(&vc4_hdmi->mutex);
2720
2721 drm_dev_exit(idx);
2722
2723 return 0;
2724 }
2725
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)2726 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2727 u32 signal_free_time, struct cec_msg *msg)
2728 {
2729 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2730 struct drm_device *dev = vc4_hdmi->connector.dev;
2731 unsigned long flags;
2732 u32 val;
2733 unsigned int i;
2734 int idx;
2735
2736 if (!drm_dev_enter(dev, &idx))
2737 return -ENODEV;
2738
2739 if (msg->len > 16) {
2740 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2741 drm_dev_exit(idx);
2742 return -ENOMEM;
2743 }
2744
2745 mutex_lock(&vc4_hdmi->mutex);
2746
2747 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2748
2749 for (i = 0; i < msg->len; i += 4)
2750 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2751 (msg->msg[i]) |
2752 (msg->msg[i + 1] << 8) |
2753 (msg->msg[i + 2] << 16) |
2754 (msg->msg[i + 3] << 24));
2755
2756 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2757 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2758 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2759 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2760 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2761 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2762
2763 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2764
2765 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2766 mutex_unlock(&vc4_hdmi->mutex);
2767 drm_dev_exit(idx);
2768
2769 return 0;
2770 }
2771
2772 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2773 .adap_enable = vc4_hdmi_cec_adap_enable,
2774 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2775 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2776 };
2777
vc4_hdmi_cec_release(void * ptr)2778 static void vc4_hdmi_cec_release(void *ptr)
2779 {
2780 struct vc4_hdmi *vc4_hdmi = ptr;
2781
2782 cec_unregister_adapter(vc4_hdmi->cec_adap);
2783 vc4_hdmi->cec_adap = NULL;
2784 }
2785
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)2786 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2787 {
2788 struct cec_connector_info conn_info;
2789 struct platform_device *pdev = vc4_hdmi->pdev;
2790 struct device *dev = &pdev->dev;
2791 int ret;
2792
2793 if (!of_property_present(dev->of_node, "interrupts")) {
2794 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2795 return 0;
2796 }
2797
2798 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2799 vc4_hdmi,
2800 vc4_hdmi->variant->card_name,
2801 CEC_CAP_DEFAULTS |
2802 CEC_CAP_CONNECTOR_INFO, 1);
2803 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2804 if (ret < 0)
2805 return ret;
2806
2807 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2808 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2809
2810 if (vc4_hdmi->variant->external_irq_controller) {
2811 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2812 vc4_cec_irq_handler_rx_bare,
2813 vc4_cec_irq_handler_rx_thread, 0,
2814 "vc4 hdmi cec rx", vc4_hdmi);
2815 if (ret)
2816 goto err_delete_cec_adap;
2817
2818 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2819 vc4_cec_irq_handler_tx_bare,
2820 vc4_cec_irq_handler_tx_thread, 0,
2821 "vc4 hdmi cec tx", vc4_hdmi);
2822 if (ret)
2823 goto err_delete_cec_adap;
2824 } else {
2825 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2826 vc4_cec_irq_handler,
2827 vc4_cec_irq_handler_thread, 0,
2828 "vc4 hdmi cec", vc4_hdmi);
2829 if (ret)
2830 goto err_delete_cec_adap;
2831 }
2832
2833 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2834 if (ret < 0)
2835 goto err_delete_cec_adap;
2836
2837 /*
2838 * NOTE: Strictly speaking, we should probably use a DRM-managed
2839 * registration there to avoid removing the CEC adapter by the
2840 * time the DRM driver doesn't have any user anymore.
2841 *
2842 * However, the CEC framework already cleans up the CEC adapter
2843 * only when the last user has closed its file descriptor, so we
2844 * don't need to handle it in DRM.
2845 *
2846 * By the time the device-managed hook is executed, we will give
2847 * up our reference to the CEC adapter and therefore don't
2848 * really care when it's actually freed.
2849 *
2850 * There's still a problematic sequence: if we unregister our
2851 * CEC adapter, but the userspace keeps a handle on the CEC
2852 * adapter but not the DRM device for some reason. In such a
2853 * case, our vc4_hdmi structure will be freed, but the
2854 * cec_adapter structure will have a dangling pointer to what
2855 * used to be our HDMI controller. If we get a CEC call at that
2856 * moment, we could end up with a use-after-free. Fortunately,
2857 * the CEC framework already handles this too, by calling
2858 * cec_is_registered() in cec_ioctl() and cec_poll().
2859 */
2860 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2861 if (ret)
2862 return ret;
2863
2864 return 0;
2865
2866 err_delete_cec_adap:
2867 cec_delete_adapter(vc4_hdmi->cec_adap);
2868
2869 return ret;
2870 }
2871 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)2872 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2873 {
2874 return 0;
2875 }
2876 #endif
2877
vc4_hdmi_free_regset(struct drm_device * drm,void * ptr)2878 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2879 {
2880 struct debugfs_reg32 *regs = ptr;
2881
2882 kfree(regs);
2883 }
2884
vc4_hdmi_build_regset(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)2885 static int vc4_hdmi_build_regset(struct drm_device *drm,
2886 struct vc4_hdmi *vc4_hdmi,
2887 struct debugfs_regset32 *regset,
2888 enum vc4_hdmi_regs reg)
2889 {
2890 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2891 struct debugfs_reg32 *regs, *new_regs;
2892 unsigned int count = 0;
2893 unsigned int i;
2894 int ret;
2895
2896 regs = kcalloc(variant->num_registers, sizeof(*regs),
2897 GFP_KERNEL);
2898 if (!regs)
2899 return -ENOMEM;
2900
2901 for (i = 0; i < variant->num_registers; i++) {
2902 const struct vc4_hdmi_register *field = &variant->registers[i];
2903
2904 if (field->reg != reg)
2905 continue;
2906
2907 regs[count].name = field->name;
2908 regs[count].offset = field->offset;
2909 count++;
2910 }
2911
2912 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2913 if (!new_regs)
2914 return -ENOMEM;
2915
2916 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2917 regset->regs = new_regs;
2918 regset->nregs = count;
2919
2920 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
2921 if (ret)
2922 return ret;
2923
2924 return 0;
2925 }
2926
vc4_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)2927 static int vc4_hdmi_init_resources(struct drm_device *drm,
2928 struct vc4_hdmi *vc4_hdmi)
2929 {
2930 struct platform_device *pdev = vc4_hdmi->pdev;
2931 struct device *dev = &pdev->dev;
2932 int ret;
2933
2934 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2935 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2936 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2937
2938 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2939 if (IS_ERR(vc4_hdmi->hd_regs))
2940 return PTR_ERR(vc4_hdmi->hd_regs);
2941
2942 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2943 if (ret)
2944 return ret;
2945
2946 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2947 if (ret)
2948 return ret;
2949
2950 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2951 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2952 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2953 if (ret != -EPROBE_DEFER)
2954 drm_err(drm, "Failed to get pixel clock\n");
2955 return ret;
2956 }
2957
2958 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2959 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2960 drm_err(drm, "Failed to get HDMI state machine clock\n");
2961 return PTR_ERR(vc4_hdmi->hsm_clock);
2962 }
2963 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2964 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2965
2966 return 0;
2967 }
2968
vc5_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)2969 static int vc5_hdmi_init_resources(struct drm_device *drm,
2970 struct vc4_hdmi *vc4_hdmi)
2971 {
2972 struct platform_device *pdev = vc4_hdmi->pdev;
2973 struct device *dev = &pdev->dev;
2974 struct resource *res;
2975 int ret;
2976
2977 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2978 if (!res)
2979 return -ENODEV;
2980
2981 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2982 resource_size(res));
2983 if (!vc4_hdmi->hdmicore_regs)
2984 return -ENOMEM;
2985
2986 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2987 if (!res)
2988 return -ENODEV;
2989
2990 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2991 if (!vc4_hdmi->hd_regs)
2992 return -ENOMEM;
2993
2994 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2995 if (!res)
2996 return -ENODEV;
2997
2998 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2999 if (!vc4_hdmi->cec_regs)
3000 return -ENOMEM;
3001
3002 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3003 if (!res)
3004 return -ENODEV;
3005
3006 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3007 if (!vc4_hdmi->csc_regs)
3008 return -ENOMEM;
3009
3010 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3011 if (!res)
3012 return -ENODEV;
3013
3014 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3015 if (!vc4_hdmi->dvp_regs)
3016 return -ENOMEM;
3017
3018 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3019 if (!res)
3020 return -ENODEV;
3021
3022 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3023 if (!vc4_hdmi->phy_regs)
3024 return -ENOMEM;
3025
3026 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3027 if (!res)
3028 return -ENODEV;
3029
3030 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3031 if (!vc4_hdmi->ram_regs)
3032 return -ENOMEM;
3033
3034 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3035 if (!res)
3036 return -ENODEV;
3037
3038 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3039 if (!vc4_hdmi->rm_regs)
3040 return -ENOMEM;
3041
3042 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3043 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3044 drm_err(drm, "Failed to get HDMI state machine clock\n");
3045 return PTR_ERR(vc4_hdmi->hsm_clock);
3046 }
3047
3048 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3049 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3050 drm_err(drm, "Failed to get pixel bvb clock\n");
3051 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3052 }
3053
3054 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3055 if (IS_ERR(vc4_hdmi->audio_clock)) {
3056 drm_err(drm, "Failed to get audio clock\n");
3057 return PTR_ERR(vc4_hdmi->audio_clock);
3058 }
3059
3060 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3061 if (IS_ERR(vc4_hdmi->cec_clock)) {
3062 drm_err(drm, "Failed to get CEC clock\n");
3063 return PTR_ERR(vc4_hdmi->cec_clock);
3064 }
3065
3066 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3067 if (IS_ERR(vc4_hdmi->reset)) {
3068 drm_err(drm, "Failed to get HDMI reset line\n");
3069 return PTR_ERR(vc4_hdmi->reset);
3070 }
3071
3072 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3073 if (ret)
3074 return ret;
3075
3076 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3077 if (ret)
3078 return ret;
3079
3080 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3081 if (ret)
3082 return ret;
3083
3084 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3085 if (ret)
3086 return ret;
3087
3088 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3089 if (ret)
3090 return ret;
3091
3092 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3093 if (ret)
3094 return ret;
3095
3096 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3097 if (ret)
3098 return ret;
3099
3100 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3101 if (ret)
3102 return ret;
3103
3104 return 0;
3105 }
3106
vc4_hdmi_runtime_suspend(struct device * dev)3107 static int vc4_hdmi_runtime_suspend(struct device *dev)
3108 {
3109 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3110
3111 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3112
3113 return 0;
3114 }
3115
vc4_hdmi_runtime_resume(struct device * dev)3116 static int vc4_hdmi_runtime_resume(struct device *dev)
3117 {
3118 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3119 unsigned long __maybe_unused flags;
3120 u32 __maybe_unused value;
3121 unsigned long rate;
3122 int ret;
3123
3124 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3125 if (ret)
3126 return ret;
3127
3128 /*
3129 * Whenever the RaspberryPi boots without an HDMI monitor
3130 * plugged in, the firmware won't have initialized the HSM clock
3131 * rate and it will be reported as 0.
3132 *
3133 * If we try to access a register of the controller in such a
3134 * case, it will lead to a silent CPU stall. Let's make sure we
3135 * prevent such a case.
3136 */
3137 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3138 if (!rate) {
3139 ret = -EINVAL;
3140 goto err_disable_clk;
3141 }
3142
3143 if (vc4_hdmi->variant->reset)
3144 vc4_hdmi->variant->reset(vc4_hdmi);
3145
3146 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3147 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3148 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3149 /* Set the logical address to Unregistered */
3150 value |= VC4_HDMI_CEC_ADDR_MASK;
3151 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3152 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3153
3154 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3155
3156 if (!vc4_hdmi->variant->external_irq_controller) {
3157 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3158 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3159 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3160 }
3161 #endif
3162
3163 return 0;
3164
3165 err_disable_clk:
3166 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3167 return ret;
3168 }
3169
vc4_hdmi_put_ddc_device(void * ptr)3170 static void vc4_hdmi_put_ddc_device(void *ptr)
3171 {
3172 struct vc4_hdmi *vc4_hdmi = ptr;
3173
3174 put_device(&vc4_hdmi->ddc->dev);
3175 }
3176
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)3177 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3178 {
3179 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3180 struct platform_device *pdev = to_platform_device(dev);
3181 struct drm_device *drm = dev_get_drvdata(master);
3182 struct vc4_hdmi *vc4_hdmi;
3183 struct drm_encoder *encoder;
3184 struct device_node *ddc_node;
3185 int ret;
3186
3187 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3188 if (!vc4_hdmi)
3189 return -ENOMEM;
3190
3191 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3192 if (ret)
3193 return ret;
3194
3195 spin_lock_init(&vc4_hdmi->hw_lock);
3196 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3197
3198 dev_set_drvdata(dev, vc4_hdmi);
3199 encoder = &vc4_hdmi->encoder.base;
3200 vc4_hdmi->encoder.type = variant->encoder_type;
3201 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3202 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3203 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3204 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3205 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3206 vc4_hdmi->pdev = pdev;
3207 vc4_hdmi->variant = variant;
3208
3209 /*
3210 * Since we don't know the state of the controller and its
3211 * display (if any), let's assume it's always enabled.
3212 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3213 * sure it's disabled, and avoid any inconsistency.
3214 */
3215 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3216 vc4_hdmi->scdc_enabled = true;
3217
3218 ret = variant->init_resources(drm, vc4_hdmi);
3219 if (ret)
3220 return ret;
3221
3222 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3223 if (!ddc_node) {
3224 drm_err(drm, "Failed to find ddc node in device tree\n");
3225 return -ENODEV;
3226 }
3227
3228 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3229 of_node_put(ddc_node);
3230 if (!vc4_hdmi->ddc) {
3231 drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3232 return -EPROBE_DEFER;
3233 }
3234
3235 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3236 if (ret)
3237 return ret;
3238
3239 /* Only use the GPIO HPD pin if present in the DT, otherwise
3240 * we'll use the HDMI core's register.
3241 */
3242 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3243 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3244 return PTR_ERR(vc4_hdmi->hpd_gpio);
3245 }
3246
3247 vc4_hdmi->disable_wifi_frequencies =
3248 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3249
3250 ret = devm_pm_runtime_enable(dev);
3251 if (ret)
3252 return ret;
3253
3254 /*
3255 * We need to have the device powered up at this point to call
3256 * our reset hook and for the CEC init.
3257 */
3258 ret = pm_runtime_resume_and_get(dev);
3259 if (ret)
3260 return ret;
3261
3262 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3263 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3264 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3265 clk_prepare_enable(vc4_hdmi->pixel_clock);
3266 clk_prepare_enable(vc4_hdmi->hsm_clock);
3267 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3268 }
3269
3270 ret = drmm_encoder_init(drm, encoder,
3271 &vc4_hdmi_encoder_funcs,
3272 DRM_MODE_ENCODER_TMDS,
3273 NULL);
3274 if (ret)
3275 goto err_put_runtime_pm;
3276
3277 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3278
3279 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3280 if (ret)
3281 goto err_put_runtime_pm;
3282
3283 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3284 if (ret)
3285 goto err_put_runtime_pm;
3286
3287 ret = vc4_hdmi_cec_init(vc4_hdmi);
3288 if (ret)
3289 goto err_put_runtime_pm;
3290
3291 ret = vc4_hdmi_audio_init(vc4_hdmi);
3292 if (ret)
3293 goto err_put_runtime_pm;
3294
3295 pm_runtime_put_sync(dev);
3296
3297 return 0;
3298
3299 err_put_runtime_pm:
3300 pm_runtime_put_sync(dev);
3301
3302 return ret;
3303 }
3304
3305 static const struct component_ops vc4_hdmi_ops = {
3306 .bind = vc4_hdmi_bind,
3307 };
3308
vc4_hdmi_dev_probe(struct platform_device * pdev)3309 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3310 {
3311 return component_add(&pdev->dev, &vc4_hdmi_ops);
3312 }
3313
vc4_hdmi_dev_remove(struct platform_device * pdev)3314 static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3315 {
3316 component_del(&pdev->dev, &vc4_hdmi_ops);
3317 }
3318
3319 static const struct vc4_hdmi_variant bcm2835_variant = {
3320 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3321 .debugfs_name = "hdmi_regs",
3322 .card_name = "vc4-hdmi",
3323 .max_pixel_clock = 162000000,
3324 .registers = vc4_hdmi_fields,
3325 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3326
3327 .init_resources = vc4_hdmi_init_resources,
3328 .csc_setup = vc4_hdmi_csc_setup,
3329 .reset = vc4_hdmi_reset,
3330 .set_timings = vc4_hdmi_set_timings,
3331 .phy_init = vc4_hdmi_phy_init,
3332 .phy_disable = vc4_hdmi_phy_disable,
3333 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3334 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3335 .channel_map = vc4_hdmi_channel_map,
3336 .supports_hdr = false,
3337 };
3338
3339 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3340 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3341 .debugfs_name = "hdmi0_regs",
3342 .card_name = "vc4-hdmi-0",
3343 .max_pixel_clock = 600000000,
3344 .registers = vc5_hdmi_hdmi0_fields,
3345 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3346 .phy_lane_mapping = {
3347 PHY_LANE_0,
3348 PHY_LANE_1,
3349 PHY_LANE_2,
3350 PHY_LANE_CK,
3351 },
3352 .unsupported_odd_h_timings = true,
3353 .external_irq_controller = true,
3354
3355 .init_resources = vc5_hdmi_init_resources,
3356 .csc_setup = vc5_hdmi_csc_setup,
3357 .reset = vc5_hdmi_reset,
3358 .set_timings = vc5_hdmi_set_timings,
3359 .phy_init = vc5_hdmi_phy_init,
3360 .phy_disable = vc5_hdmi_phy_disable,
3361 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3362 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3363 .channel_map = vc5_hdmi_channel_map,
3364 .supports_hdr = true,
3365 .hp_detect = vc5_hdmi_hp_detect,
3366 };
3367
3368 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3369 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3370 .debugfs_name = "hdmi1_regs",
3371 .card_name = "vc4-hdmi-1",
3372 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3373 .registers = vc5_hdmi_hdmi1_fields,
3374 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3375 .phy_lane_mapping = {
3376 PHY_LANE_1,
3377 PHY_LANE_0,
3378 PHY_LANE_CK,
3379 PHY_LANE_2,
3380 },
3381 .unsupported_odd_h_timings = true,
3382 .external_irq_controller = true,
3383
3384 .init_resources = vc5_hdmi_init_resources,
3385 .csc_setup = vc5_hdmi_csc_setup,
3386 .reset = vc5_hdmi_reset,
3387 .set_timings = vc5_hdmi_set_timings,
3388 .phy_init = vc5_hdmi_phy_init,
3389 .phy_disable = vc5_hdmi_phy_disable,
3390 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3391 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3392 .channel_map = vc5_hdmi_channel_map,
3393 .supports_hdr = true,
3394 .hp_detect = vc5_hdmi_hp_detect,
3395 };
3396
3397 static const struct of_device_id vc4_hdmi_dt_match[] = {
3398 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3399 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3400 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3401 {}
3402 };
3403
3404 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3405 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3406 vc4_hdmi_runtime_resume,
3407 NULL)
3408 };
3409
3410 struct platform_driver vc4_hdmi_driver = {
3411 .probe = vc4_hdmi_dev_probe,
3412 .remove_new = vc4_hdmi_dev_remove,
3413 .driver = {
3414 .name = "vc4_hdmi",
3415 .of_match_table = vc4_hdmi_dt_match,
3416 .pm = &vc4_hdmi_pm_ops,
3417 },
3418 };
3419