1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
5 *
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
7 * Copyright (C) 1999 ARM Limited
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
9 *
10 * Contributors to the old driver include:
11 * Russell King <linux@armlinux.org.uk>
12 * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite)
13 * Rob Herring <robh@kernel.org>
14 * Liviu Dudau <Liviu.Dudau@arm.com>
15 * Grant Likely <grant.likely@secretlab.ca>
16 * Arnd Bergmann <arnd@arndb.de>
17 * Bjorn Helgaas <bhelgaas@google.com>
18 */
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/of.h>
24 #include <linux/of_pci.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/bitops.h>
29 #include <linux/irq.h>
30 #include <linux/mfd/syscon.h>
31 #include <linux/regmap.h>
32 #include <linux/clk.h>
33
34 #include "../pci.h"
35
36 #define V3_PCI_VENDOR 0x00000000
37 #define V3_PCI_DEVICE 0x00000002
38 #define V3_PCI_CMD 0x00000004
39 #define V3_PCI_STAT 0x00000006
40 #define V3_PCI_CC_REV 0x00000008
41 #define V3_PCI_HDR_CFG 0x0000000C
42 #define V3_PCI_IO_BASE 0x00000010
43 #define V3_PCI_BASE0 0x00000014
44 #define V3_PCI_BASE1 0x00000018
45 #define V3_PCI_SUB_VENDOR 0x0000002C
46 #define V3_PCI_SUB_ID 0x0000002E
47 #define V3_PCI_ROM 0x00000030
48 #define V3_PCI_BPARAM 0x0000003C
49 #define V3_PCI_MAP0 0x00000040
50 #define V3_PCI_MAP1 0x00000044
51 #define V3_PCI_INT_STAT 0x00000048
52 #define V3_PCI_INT_CFG 0x0000004C
53 #define V3_LB_BASE0 0x00000054
54 #define V3_LB_BASE1 0x00000058
55 #define V3_LB_MAP0 0x0000005E
56 #define V3_LB_MAP1 0x00000062
57 #define V3_LB_BASE2 0x00000064
58 #define V3_LB_MAP2 0x00000066
59 #define V3_LB_SIZE 0x00000068
60 #define V3_LB_IO_BASE 0x0000006E
61 #define V3_FIFO_CFG 0x00000070
62 #define V3_FIFO_PRIORITY 0x00000072
63 #define V3_FIFO_STAT 0x00000074
64 #define V3_LB_ISTAT 0x00000076
65 #define V3_LB_IMASK 0x00000077
66 #define V3_SYSTEM 0x00000078
67 #define V3_LB_CFG 0x0000007A
68 #define V3_PCI_CFG 0x0000007C
69 #define V3_DMA_PCI_ADR0 0x00000080
70 #define V3_DMA_PCI_ADR1 0x00000090
71 #define V3_DMA_LOCAL_ADR0 0x00000084
72 #define V3_DMA_LOCAL_ADR1 0x00000094
73 #define V3_DMA_LENGTH0 0x00000088
74 #define V3_DMA_LENGTH1 0x00000098
75 #define V3_DMA_CSR0 0x0000008B
76 #define V3_DMA_CSR1 0x0000009B
77 #define V3_DMA_CTLB_ADR0 0x0000008C
78 #define V3_DMA_CTLB_ADR1 0x0000009C
79 #define V3_DMA_DELAY 0x000000E0
80 #define V3_MAIL_DATA 0x000000C0
81 #define V3_PCI_MAIL_IEWR 0x000000D0
82 #define V3_PCI_MAIL_IERD 0x000000D2
83 #define V3_LB_MAIL_IEWR 0x000000D4
84 #define V3_LB_MAIL_IERD 0x000000D6
85 #define V3_MAIL_WR_STAT 0x000000D8
86 #define V3_MAIL_RD_STAT 0x000000DA
87 #define V3_QBA_MAP 0x000000DC
88
89 /* PCI STATUS bits */
90 #define V3_PCI_STAT_PAR_ERR BIT(15)
91 #define V3_PCI_STAT_SYS_ERR BIT(14)
92 #define V3_PCI_STAT_M_ABORT_ERR BIT(13)
93 #define V3_PCI_STAT_T_ABORT_ERR BIT(12)
94
95 /* LB ISTAT bits */
96 #define V3_LB_ISTAT_MAILBOX BIT(7)
97 #define V3_LB_ISTAT_PCI_RD BIT(6)
98 #define V3_LB_ISTAT_PCI_WR BIT(5)
99 #define V3_LB_ISTAT_PCI_INT BIT(4)
100 #define V3_LB_ISTAT_PCI_PERR BIT(3)
101 #define V3_LB_ISTAT_I2O_QWR BIT(2)
102 #define V3_LB_ISTAT_DMA1 BIT(1)
103 #define V3_LB_ISTAT_DMA0 BIT(0)
104
105 /* PCI COMMAND bits */
106 #define V3_COMMAND_M_FBB_EN BIT(9)
107 #define V3_COMMAND_M_SERR_EN BIT(8)
108 #define V3_COMMAND_M_PAR_EN BIT(6)
109 #define V3_COMMAND_M_MASTER_EN BIT(2)
110 #define V3_COMMAND_M_MEM_EN BIT(1)
111 #define V3_COMMAND_M_IO_EN BIT(0)
112
113 /* SYSTEM bits */
114 #define V3_SYSTEM_M_RST_OUT BIT(15)
115 #define V3_SYSTEM_M_LOCK BIT(14)
116 #define V3_SYSTEM_UNLOCK 0xa05f
117
118 /* PCI CFG bits */
119 #define V3_PCI_CFG_M_I2O_EN BIT(15)
120 #define V3_PCI_CFG_M_IO_REG_DIS BIT(14)
121 #define V3_PCI_CFG_M_IO_DIS BIT(13)
122 #define V3_PCI_CFG_M_EN3V BIT(12)
123 #define V3_PCI_CFG_M_RETRY_EN BIT(10)
124 #define V3_PCI_CFG_M_AD_LOW1 BIT(9)
125 #define V3_PCI_CFG_M_AD_LOW0 BIT(8)
126 /*
127 * This is the value applied to C/BE[3:1], with bit 0 always held 0
128 * during DMA access.
129 */
130 #define V3_PCI_CFG_M_RTYPE_SHIFT 5
131 #define V3_PCI_CFG_M_WTYPE_SHIFT 1
132 #define V3_PCI_CFG_TYPE_DEFAULT 0x3
133
134 /* PCI BASE bits (PCI -> Local Bus) */
135 #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000U
136 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00U
137 #define V3_PCI_BASE_M_PREFETCH BIT(3)
138 #define V3_PCI_BASE_M_TYPE (3 << 1)
139 #define V3_PCI_BASE_M_IO BIT(0)
140
141 /* PCI MAP bits (PCI -> Local bus) */
142 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000U
143 #define V3_PCI_MAP_M_RD_POST_INH BIT(15)
144 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
145 #define V3_PCI_MAP_M_SWAP (3 << 8)
146 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0U
147 #define V3_PCI_MAP_M_REG_EN BIT(1)
148 #define V3_PCI_MAP_M_ENABLE BIT(0)
149
150 /* LB_BASE0,1 bits (Local bus -> PCI) */
151 #define V3_LB_BASE_ADR_BASE 0xfff00000U
152 #define V3_LB_BASE_SWAP (3 << 8)
153 #define V3_LB_BASE_ADR_SIZE (15 << 4)
154 #define V3_LB_BASE_PREFETCH BIT(3)
155 #define V3_LB_BASE_ENABLE BIT(0)
156
157 #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
158 #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
159 #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
160 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
161 #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
162 #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
163 #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
164 #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
165 #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
166 #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
167 #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
168 #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
169
170 #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
171
172 /* LB_MAP0,1 bits (Local bus -> PCI) */
173 #define V3_LB_MAP_MAP_ADR 0xfff0U
174 #define V3_LB_MAP_TYPE (7 << 1)
175 #define V3_LB_MAP_AD_LOW_EN BIT(0)
176
177 #define V3_LB_MAP_TYPE_IACK (0 << 1)
178 #define V3_LB_MAP_TYPE_IO (1 << 1)
179 #define V3_LB_MAP_TYPE_MEM (3 << 1)
180 #define V3_LB_MAP_TYPE_CONFIG (5 << 1)
181 #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
182
183 #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
184
185 /* LB_BASE2 bits (Local bus -> PCI IO) */
186 #define V3_LB_BASE2_ADR_BASE 0xff00U
187 #define V3_LB_BASE2_SWAP_AUTO (3 << 6)
188 #define V3_LB_BASE2_ENABLE BIT(0)
189
190 #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
191
192 /* LB_MAP2 bits (Local bus -> PCI IO) */
193 #define V3_LB_MAP2_MAP_ADR 0xff00U
194
195 #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
196
197 /* FIFO priority bits */
198 #define V3_FIFO_PRIO_LOCAL BIT(12)
199 #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB BIT(10)
200 #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 BIT(11)
201 #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY (BIT(10)|BIT(11))
202 #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB BIT(8)
203 #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 BIT(9)
204 #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY (BIT(8)|BIT(9))
205 #define V3_FIFO_PRIO_PCI BIT(4)
206 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB BIT(2)
207 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 BIT(3)
208 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY (BIT(2)|BIT(3))
209 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB BIT(0)
210 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1 BIT(1)
211 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY (BIT(0)|BIT(1))
212
213 /* Local bus configuration bits */
214 #define V3_LB_CFG_LB_TO_64_CYCLES 0x0000
215 #define V3_LB_CFG_LB_TO_256_CYCLES BIT(13)
216 #define V3_LB_CFG_LB_TO_512_CYCLES BIT(14)
217 #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14))
218 #define V3_LB_CFG_LB_RST BIT(12)
219 #define V3_LB_CFG_LB_PPC_RDY BIT(11)
220 #define V3_LB_CFG_LB_LB_INT BIT(10)
221 #define V3_LB_CFG_LB_ERR_EN BIT(9)
222 #define V3_LB_CFG_LB_RDY_EN BIT(8)
223 #define V3_LB_CFG_LB_BE_IMODE BIT(7)
224 #define V3_LB_CFG_LB_BE_OMODE BIT(6)
225 #define V3_LB_CFG_LB_ENDIAN BIT(5)
226 #define V3_LB_CFG_LB_PARK_EN BIT(4)
227 #define V3_LB_CFG_LB_FBB_DIS BIT(2)
228
229 /* ARM Integrator-specific extended control registers */
230 #define INTEGRATOR_SC_PCI_OFFSET 0x18
231 #define INTEGRATOR_SC_PCI_ENABLE BIT(0)
232 #define INTEGRATOR_SC_PCI_INTCLR BIT(1)
233 #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
234 #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
235
236 struct v3_pci {
237 struct device *dev;
238 void __iomem *base;
239 void __iomem *config_base;
240 u32 config_mem;
241 u32 non_pre_mem;
242 u32 pre_mem;
243 phys_addr_t non_pre_bus_addr;
244 phys_addr_t pre_bus_addr;
245 struct regmap *map;
246 };
247
248 /*
249 * The V3 PCI interface chip in Integrator provides several windows from
250 * local bus memory into the PCI memory areas. Unfortunately, there
251 * are not really enough windows for our usage, therefore we reuse
252 * one of the windows for access to PCI configuration space. On the
253 * Integrator/AP, the memory map is as follows:
254 *
255 * Local Bus Memory Usage
256 *
257 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
258 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
259 * 60000000 - 60FFFFFF PCI IO. 16M
260 * 61000000 - 61FFFFFF PCI Configuration. 16M
261 *
262 * There are three V3 windows, each described by a pair of V3 registers.
263 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
264 * Base0 and Base1 can be used for any type of PCI memory access. Base2
265 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
266 * uses this only for PCI IO space.
267 *
268 * Normally these spaces are mapped using the following base registers:
269 *
270 * Usage Local Bus Memory Base/Map registers used
271 *
272 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
273 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
274 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
275 * Cfg 61000000 - 61FFFFFF
276 *
277 * This means that I20 and PCI configuration space accesses will fail.
278 * When PCI configuration accesses are needed (via the uHAL PCI
279 * configuration space primitives) we must remap the spaces as follows:
280 *
281 * Usage Local Bus Memory Base/Map registers used
282 *
283 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
284 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
285 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
286 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
287 *
288 * To make this work, the code depends on overlapping windows working.
289 * The V3 chip translates an address by checking its range within
290 * each of the BASE/MAP pairs in turn (in ascending register number
291 * order). It will use the first matching pair. So, for example,
292 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
293 * LB_BASE1/LB_MAP1, the V3 will use the translation from
294 * LB_BASE0/LB_MAP0.
295 *
296 * To allow PCI Configuration space access, the code enlarges the
297 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
298 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
299 * be remapped for use by configuration cycles.
300 *
301 * At the end of the PCI Configuration space accesses,
302 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
303 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
304 * reveal the now restored LB_BASE1/LB_MAP1 window.
305 *
306 * NOTE: We do not set up I2O mapping. I suspect that this is only
307 * for an intelligent (target) device. Using I2O disables most of
308 * the mappings into PCI memory.
309 */
v3_map_bus(struct pci_bus * bus,unsigned int devfn,int offset)310 static void __iomem *v3_map_bus(struct pci_bus *bus,
311 unsigned int devfn, int offset)
312 {
313 struct v3_pci *v3 = bus->sysdata;
314 unsigned int address, mapaddress, busnr;
315
316 busnr = bus->number;
317 if (busnr == 0) {
318 int slot = PCI_SLOT(devfn);
319
320 /*
321 * local bus segment so need a type 0 config cycle
322 *
323 * build the PCI configuration "address" with one-hot in
324 * A31-A11
325 *
326 * mapaddress:
327 * 3:1 = config cycle (101)
328 * 0 = PCI A1 & A0 are 0 (0)
329 */
330 address = PCI_FUNC(devfn) << 8;
331 mapaddress = V3_LB_MAP_TYPE_CONFIG;
332
333 if (slot > 12)
334 /*
335 * high order bits are handled by the MAP register
336 */
337 mapaddress |= BIT(slot - 5);
338 else
339 /*
340 * low order bits handled directly in the address
341 */
342 address |= BIT(slot + 11);
343 } else {
344 /*
345 * not the local bus segment so need a type 1 config cycle
346 *
347 * address:
348 * 23:16 = bus number
349 * 15:11 = slot number (7:3 of devfn)
350 * 10:8 = func number (2:0 of devfn)
351 *
352 * mapaddress:
353 * 3:1 = config cycle (101)
354 * 0 = PCI A1 & A0 from host bus (1)
355 */
356 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
357 address = (busnr << 16) | (devfn << 8);
358 }
359
360 /*
361 * Set up base0 to see all 512Mbytes of memory space (not
362 * prefetchable), this frees up base1 for re-use by
363 * configuration memory
364 */
365 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
366 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE,
367 v3->base + V3_LB_BASE0);
368
369 /*
370 * Set up base1/map1 to point into configuration space.
371 * The config mem is always 16MB.
372 */
373 writel(v3_addr_to_lb_base(v3->config_mem) |
374 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE,
375 v3->base + V3_LB_BASE1);
376 writew(mapaddress, v3->base + V3_LB_MAP1);
377
378 return v3->config_base + address + offset;
379 }
380
v3_unmap_bus(struct v3_pci * v3)381 static void v3_unmap_bus(struct v3_pci *v3)
382 {
383 /*
384 * Reassign base1 for use by prefetchable PCI memory
385 */
386 writel(v3_addr_to_lb_base(v3->pre_mem) |
387 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
388 V3_LB_BASE_ENABLE,
389 v3->base + V3_LB_BASE1);
390 writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
391 V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */
392 v3->base + V3_LB_MAP1);
393
394 /*
395 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
396 */
397 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
398 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE,
399 v3->base + V3_LB_BASE0);
400 }
401
v3_pci_read_config(struct pci_bus * bus,unsigned int fn,int config,int size,u32 * value)402 static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn,
403 int config, int size, u32 *value)
404 {
405 struct v3_pci *v3 = bus->sysdata;
406 int ret;
407
408 dev_dbg(&bus->dev,
409 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
410 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
411 ret = pci_generic_config_read(bus, fn, config, size, value);
412 v3_unmap_bus(v3);
413 return ret;
414 }
415
v3_pci_write_config(struct pci_bus * bus,unsigned int fn,int config,int size,u32 value)416 static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn,
417 int config, int size, u32 value)
418 {
419 struct v3_pci *v3 = bus->sysdata;
420 int ret;
421
422 dev_dbg(&bus->dev,
423 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
424 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
425 ret = pci_generic_config_write(bus, fn, config, size, value);
426 v3_unmap_bus(v3);
427 return ret;
428 }
429
430 static struct pci_ops v3_pci_ops = {
431 .map_bus = v3_map_bus,
432 .read = v3_pci_read_config,
433 .write = v3_pci_write_config,
434 };
435
v3_irq(int irq,void * data)436 static irqreturn_t v3_irq(int irq, void *data)
437 {
438 struct v3_pci *v3 = data;
439 struct device *dev = v3->dev;
440 u32 status;
441
442 status = readw(v3->base + V3_PCI_STAT);
443 if (status & V3_PCI_STAT_PAR_ERR)
444 dev_err(dev, "parity error interrupt\n");
445 if (status & V3_PCI_STAT_SYS_ERR)
446 dev_err(dev, "system error interrupt\n");
447 if (status & V3_PCI_STAT_M_ABORT_ERR)
448 dev_err(dev, "master abort error interrupt\n");
449 if (status & V3_PCI_STAT_T_ABORT_ERR)
450 dev_err(dev, "target abort error interrupt\n");
451 writew(status, v3->base + V3_PCI_STAT);
452
453 status = readb(v3->base + V3_LB_ISTAT);
454 if (status & V3_LB_ISTAT_MAILBOX)
455 dev_info(dev, "PCI mailbox interrupt\n");
456 if (status & V3_LB_ISTAT_PCI_RD)
457 dev_err(dev, "PCI target LB->PCI READ abort interrupt\n");
458 if (status & V3_LB_ISTAT_PCI_WR)
459 dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n");
460 if (status & V3_LB_ISTAT_PCI_INT)
461 dev_info(dev, "PCI pin interrupt\n");
462 if (status & V3_LB_ISTAT_PCI_PERR)
463 dev_err(dev, "PCI parity error interrupt\n");
464 if (status & V3_LB_ISTAT_I2O_QWR)
465 dev_info(dev, "I2O inbound post queue interrupt\n");
466 if (status & V3_LB_ISTAT_DMA1)
467 dev_info(dev, "DMA channel 1 interrupt\n");
468 if (status & V3_LB_ISTAT_DMA0)
469 dev_info(dev, "DMA channel 0 interrupt\n");
470 /* Clear all possible interrupts on the local bus */
471 writeb(0, v3->base + V3_LB_ISTAT);
472 if (v3->map)
473 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
474 INTEGRATOR_SC_PCI_ENABLE |
475 INTEGRATOR_SC_PCI_INTCLR);
476
477 return IRQ_HANDLED;
478 }
479
v3_integrator_init(struct v3_pci * v3)480 static int v3_integrator_init(struct v3_pci *v3)
481 {
482 unsigned int val;
483
484 v3->map =
485 syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon");
486 if (IS_ERR(v3->map)) {
487 dev_err(v3->dev, "no syscon\n");
488 return -ENODEV;
489 }
490
491 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val);
492 /* Take the PCI bridge out of reset, clear IRQs */
493 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
494 INTEGRATOR_SC_PCI_ENABLE |
495 INTEGRATOR_SC_PCI_INTCLR);
496
497 if (!(val & INTEGRATOR_SC_PCI_ENABLE)) {
498 /* If we were in reset we need to sleep a bit */
499 msleep(230);
500
501 /* Set the physical base for the controller itself */
502 writel(0x6200, v3->base + V3_LB_IO_BASE);
503
504 /* Wait for the mailbox to settle after reset */
505 do {
506 writeb(0xaa, v3->base + V3_MAIL_DATA);
507 writeb(0x55, v3->base + V3_MAIL_DATA + 4);
508 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa &&
509 readb(v3->base + V3_MAIL_DATA) != 0x55);
510 }
511
512 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n");
513
514 return 0;
515 }
516
v3_pci_setup_resource(struct v3_pci * v3,struct pci_host_bridge * host,struct resource_entry * win)517 static int v3_pci_setup_resource(struct v3_pci *v3,
518 struct pci_host_bridge *host,
519 struct resource_entry *win)
520 {
521 struct device *dev = v3->dev;
522 struct resource *mem;
523 struct resource *io;
524
525 switch (resource_type(win->res)) {
526 case IORESOURCE_IO:
527 io = win->res;
528
529 /* Setup window 2 - PCI I/O */
530 writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) |
531 V3_LB_BASE2_ENABLE,
532 v3->base + V3_LB_BASE2);
533 writew(v3_addr_to_lb_map2(io->start - win->offset),
534 v3->base + V3_LB_MAP2);
535 break;
536 case IORESOURCE_MEM:
537 mem = win->res;
538 if (mem->flags & IORESOURCE_PREFETCH) {
539 mem->name = "V3 PCI PRE-MEM";
540 v3->pre_mem = mem->start;
541 v3->pre_bus_addr = mem->start - win->offset;
542 dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n",
543 mem, &v3->pre_bus_addr);
544 if (resource_size(mem) != SZ_256M) {
545 dev_err(dev, "prefetchable memory range is not 256MB\n");
546 return -EINVAL;
547 }
548 if (v3->non_pre_mem &&
549 (mem->start != v3->non_pre_mem + SZ_256M)) {
550 dev_err(dev,
551 "prefetchable memory is not adjacent to non-prefetchable memory\n");
552 return -EINVAL;
553 }
554 /* Setup window 1 - PCI prefetchable memory */
555 writel(v3_addr_to_lb_base(v3->pre_mem) |
556 V3_LB_BASE_ADR_SIZE_256MB |
557 V3_LB_BASE_PREFETCH |
558 V3_LB_BASE_ENABLE,
559 v3->base + V3_LB_BASE1);
560 writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
561 V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */
562 v3->base + V3_LB_MAP1);
563 } else {
564 mem->name = "V3 PCI NON-PRE-MEM";
565 v3->non_pre_mem = mem->start;
566 v3->non_pre_bus_addr = mem->start - win->offset;
567 dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n",
568 mem, &v3->non_pre_bus_addr);
569 if (resource_size(mem) != SZ_256M) {
570 dev_err(dev,
571 "non-prefetchable memory range is not 256MB\n");
572 return -EINVAL;
573 }
574 /* Setup window 0 - PCI non-prefetchable memory */
575 writel(v3_addr_to_lb_base(v3->non_pre_mem) |
576 V3_LB_BASE_ADR_SIZE_256MB |
577 V3_LB_BASE_ENABLE,
578 v3->base + V3_LB_BASE0);
579 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) |
580 V3_LB_MAP_TYPE_MEM,
581 v3->base + V3_LB_MAP0);
582 }
583 break;
584 case IORESOURCE_BUS:
585 break;
586 default:
587 dev_info(dev, "Unknown resource type %lu\n",
588 resource_type(win->res));
589 break;
590 }
591
592 return 0;
593 }
594
v3_get_dma_range_config(struct v3_pci * v3,struct resource_entry * entry,u32 * pci_base,u32 * pci_map)595 static int v3_get_dma_range_config(struct v3_pci *v3,
596 struct resource_entry *entry,
597 u32 *pci_base, u32 *pci_map)
598 {
599 struct device *dev = v3->dev;
600 u64 cpu_addr = entry->res->start;
601 u64 cpu_end = entry->res->end;
602 u64 pci_end = cpu_end - entry->offset;
603 u64 pci_addr = entry->res->start - entry->offset;
604 u32 val;
605
606 if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) {
607 dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n");
608 return -EINVAL;
609 }
610 val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE;
611 *pci_base = val;
612
613 if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) {
614 dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n");
615 return -EINVAL;
616 }
617 val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR;
618
619 switch (resource_size(entry->res)) {
620 case SZ_1M:
621 val |= V3_LB_BASE_ADR_SIZE_1MB;
622 break;
623 case SZ_2M:
624 val |= V3_LB_BASE_ADR_SIZE_2MB;
625 break;
626 case SZ_4M:
627 val |= V3_LB_BASE_ADR_SIZE_4MB;
628 break;
629 case SZ_8M:
630 val |= V3_LB_BASE_ADR_SIZE_8MB;
631 break;
632 case SZ_16M:
633 val |= V3_LB_BASE_ADR_SIZE_16MB;
634 break;
635 case SZ_32M:
636 val |= V3_LB_BASE_ADR_SIZE_32MB;
637 break;
638 case SZ_64M:
639 val |= V3_LB_BASE_ADR_SIZE_64MB;
640 break;
641 case SZ_128M:
642 val |= V3_LB_BASE_ADR_SIZE_128MB;
643 break;
644 case SZ_256M:
645 val |= V3_LB_BASE_ADR_SIZE_256MB;
646 break;
647 case SZ_512M:
648 val |= V3_LB_BASE_ADR_SIZE_512MB;
649 break;
650 case SZ_1G:
651 val |= V3_LB_BASE_ADR_SIZE_1GB;
652 break;
653 case SZ_2G:
654 val |= V3_LB_BASE_ADR_SIZE_2GB;
655 break;
656 default:
657 dev_err(v3->dev, "illegal dma memory chunk size\n");
658 return -EINVAL;
659 }
660 val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE;
661 *pci_map = val;
662
663 dev_dbg(dev,
664 "DMA MEM CPU: 0x%016llx -> 0x%016llx => "
665 "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n",
666 cpu_addr, cpu_end,
667 pci_addr, pci_end,
668 *pci_base, *pci_map);
669
670 return 0;
671 }
672
v3_pci_parse_map_dma_ranges(struct v3_pci * v3,struct device_node * np)673 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3,
674 struct device_node *np)
675 {
676 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3);
677 struct device *dev = v3->dev;
678 struct resource_entry *entry;
679 int i = 0;
680
681 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
682 int ret;
683 u32 pci_base, pci_map;
684
685 ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map);
686 if (ret)
687 return ret;
688
689 if (i == 0) {
690 writel(pci_base, v3->base + V3_PCI_BASE0);
691 writel(pci_map, v3->base + V3_PCI_MAP0);
692 } else if (i == 1) {
693 writel(pci_base, v3->base + V3_PCI_BASE1);
694 writel(pci_map, v3->base + V3_PCI_MAP1);
695 } else {
696 dev_err(dev, "too many ranges, only two supported\n");
697 dev_err(dev, "range %d ignored\n", i);
698 }
699 i++;
700 }
701 return 0;
702 }
703
v3_pci_probe(struct platform_device * pdev)704 static int v3_pci_probe(struct platform_device *pdev)
705 {
706 struct device *dev = &pdev->dev;
707 struct device_node *np = dev->of_node;
708 struct resource *regs;
709 struct resource_entry *win;
710 struct v3_pci *v3;
711 struct pci_host_bridge *host;
712 struct clk *clk;
713 u16 val;
714 int irq;
715 int ret;
716
717 host = devm_pci_alloc_host_bridge(dev, sizeof(*v3));
718 if (!host)
719 return -ENOMEM;
720
721 host->ops = &v3_pci_ops;
722 v3 = pci_host_bridge_priv(host);
723 host->sysdata = v3;
724 v3->dev = dev;
725
726 /* Get and enable host clock */
727 clk = devm_clk_get(dev, NULL);
728 if (IS_ERR(clk)) {
729 dev_err(dev, "clock not found\n");
730 return PTR_ERR(clk);
731 }
732 ret = clk_prepare_enable(clk);
733 if (ret) {
734 dev_err(dev, "unable to enable clock\n");
735 return ret;
736 }
737
738 v3->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
739 if (IS_ERR(v3->base))
740 return PTR_ERR(v3->base);
741 /*
742 * The hardware has a register with the physical base address
743 * of the V3 controller itself, verify that this is the same
744 * as the physical memory we've remapped it from.
745 */
746 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16))
747 dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n",
748 readl(v3->base + V3_LB_IO_BASE), regs);
749
750 /* Configuration space is 16MB directly mapped */
751 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
752 if (resource_size(regs) != SZ_16M) {
753 dev_err(dev, "config mem is not 16MB!\n");
754 return -EINVAL;
755 }
756 v3->config_mem = regs->start;
757 v3->config_base = devm_ioremap_resource(dev, regs);
758 if (IS_ERR(v3->config_base))
759 return PTR_ERR(v3->config_base);
760
761 /* Get and request error IRQ resource */
762 irq = platform_get_irq(pdev, 0);
763 if (irq < 0)
764 return irq;
765
766 ret = devm_request_irq(dev, irq, v3_irq, 0,
767 "PCIv3 error", v3);
768 if (ret < 0) {
769 dev_err(dev,
770 "unable to request PCIv3 error IRQ %d (%d)\n",
771 irq, ret);
772 return ret;
773 }
774
775 /*
776 * Unlock V3 registers, but only if they were previously locked.
777 */
778 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
779 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM);
780
781 /* Disable all slave access while we set up the windows */
782 val = readw(v3->base + V3_PCI_CMD);
783 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
784 writew(val, v3->base + V3_PCI_CMD);
785
786 /* Put the PCI bus into reset */
787 val = readw(v3->base + V3_SYSTEM);
788 val &= ~V3_SYSTEM_M_RST_OUT;
789 writew(val, v3->base + V3_SYSTEM);
790
791 /* Retry until we're ready */
792 val = readw(v3->base + V3_PCI_CFG);
793 val |= V3_PCI_CFG_M_RETRY_EN;
794 writew(val, v3->base + V3_PCI_CFG);
795
796 /* Set up the local bus protocol */
797 val = readw(v3->base + V3_LB_CFG);
798 val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */
799 val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */
800 val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */
801 val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */
802 writew(val, v3->base + V3_LB_CFG);
803
804 /* Enable the PCI bus master */
805 val = readw(v3->base + V3_PCI_CMD);
806 val |= PCI_COMMAND_MASTER;
807 writew(val, v3->base + V3_PCI_CMD);
808
809 /* Get the I/O and memory ranges from DT */
810 resource_list_for_each_entry(win, &host->windows) {
811 ret = v3_pci_setup_resource(v3, host, win);
812 if (ret) {
813 dev_err(dev, "error setting up resources\n");
814 return ret;
815 }
816 }
817 ret = v3_pci_parse_map_dma_ranges(v3, np);
818 if (ret)
819 return ret;
820
821 /*
822 * Disable PCI to host IO cycles, enable I/O buffers @3.3V,
823 * set AD_LOW0 to 1 if one of the LB_MAP registers choose
824 * to use this (should be unused).
825 */
826 writel(0x00000000, v3->base + V3_PCI_IO_BASE);
827 val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS |
828 V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0;
829 /*
830 * DMA read and write from PCI bus commands types
831 */
832 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT;
833 val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT;
834 writew(val, v3->base + V3_PCI_CFG);
835
836 /*
837 * Set the V3 FIFO such that writes have higher priority than
838 * reads, and local bus write causes local bus read fifo flush
839 * on aperture 1. Same for PCI.
840 */
841 writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 |
842 V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 |
843 V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 |
844 V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1,
845 v3->base + V3_FIFO_PRIORITY);
846
847
848 /*
849 * Clear any error interrupts, and enable parity and write error
850 * interrupts
851 */
852 writeb(0, v3->base + V3_LB_ISTAT);
853 val = readw(v3->base + V3_LB_CFG);
854 val |= V3_LB_CFG_LB_LB_INT;
855 writew(val, v3->base + V3_LB_CFG);
856 writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
857 v3->base + V3_LB_IMASK);
858
859 /* Special Integrator initialization */
860 if (of_device_is_compatible(np, "arm,integrator-ap-pci")) {
861 ret = v3_integrator_init(v3);
862 if (ret)
863 return ret;
864 }
865
866 /* Post-init: enable PCI memory and invalidate (master already on) */
867 val = readw(v3->base + V3_PCI_CMD);
868 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE;
869 writew(val, v3->base + V3_PCI_CMD);
870
871 /* Clear pending interrupts */
872 writeb(0, v3->base + V3_LB_ISTAT);
873 /* Read or write errors and parity errors cause interrupts */
874 writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
875 v3->base + V3_LB_IMASK);
876
877 /* Take the PCI bus out of reset so devices can initialize */
878 val = readw(v3->base + V3_SYSTEM);
879 val |= V3_SYSTEM_M_RST_OUT;
880 writew(val, v3->base + V3_SYSTEM);
881
882 /*
883 * Re-lock the system register.
884 */
885 val = readw(v3->base + V3_SYSTEM);
886 val |= V3_SYSTEM_M_LOCK;
887 writew(val, v3->base + V3_SYSTEM);
888
889 return pci_host_probe(host);
890 }
891
892 static const struct of_device_id v3_pci_of_match[] = {
893 {
894 .compatible = "v3,v360epc-pci",
895 },
896 {},
897 };
898
899 static struct platform_driver v3_pci_driver = {
900 .driver = {
901 .name = "pci-v3-semi",
902 .of_match_table = v3_pci_of_match,
903 .suppress_bind_attrs = true,
904 },
905 .probe = v3_pci_probe,
906 };
907 builtin_platform_driver(v3_pci_driver);
908