/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYISelDAGToDAG.cpp | 198 SDValue V0 = N->getOperand(i + 1); in selectInlineAsm() local 383 SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsMachineFunction.cpp | 83 Register V0 = RegInfo.createVirtualRegister(RC); initGlobalBaseReg() local [all...] |
H A D | Mips16ISelDAGToDAG.cpp | 75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); in initGlobalBaseReg() local
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/freebsd/lib/msun/src/ |
H A D | e_j1.c | 130 static const double V0[5] = { variable
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H A D | e_j1f.c | 93 static const float V0[5] = { variable
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | VectorCombine.cpp | 542 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtCmp() local 560 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtBinop() local 586 Value *V0, *V1; in foldExtractExtract() local 698 Value *V0, *V1; in foldBitcastShuffle() local 932 Value *V0 = nullptr, *V1 = nullptr; in scalarizeBinopOrCmp() local 1492 Value *V0, *V1; in foldShuffleOfCastops() local 1597 Value *V0, *V1; in foldShuffleOfShuffles() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 232 SDValue V0 = N->getOperand(i+1); in tryInlineAsm() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1853 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() 1864 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createSRegPairNode() 1875 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() 1886 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createQRegPairNode() 1897 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadSRegsNode() 1912 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadDRegsNode() 1927 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadQRegsNode() 2318 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local 2374 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local 2493 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVLDSTLane() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineAddSub.cpp | 391 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local 469 Value *V0 = I->getOperand(0); in simplify() local 2284 Value *V0, *V1; in visitSub() local 2967 Value *A0, *A1, *V0, *V1; in visitFSub() local
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H A D | InstCombineVectorOps.cpp | 84 Value *V0, *V1; in cheapToScalarize() local 2609 Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); in foldShuffleWithInsert() local
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H A D | InstCombineCalls.cpp | 2823 Value *V0 = Builder.CreateIntCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 5702 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_SPLICE() local 5712 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE() local 5829 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_REVERSE() local 5842 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_SHUFFLE() local 6027 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_INSERT_VECTOR_ELT() local 6073 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntOp_EXTRACT_VECTOR_ELT() local 6089 SDValue V0 = N->getOperand(0); in PromoteIntOp_INSERT_SUBVECTOR() local 6102 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntOp_EXTRACT_SUBVECTOR() local
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/freebsd/crypto/openssl/crypto/aria/ |
H A D | aria.c | 54 #define MAKE_U32(V0, V1, V2, V3) ( \ argument
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | Reassociate.cpp | 132 Value *V0 = I->getOperand(0); in XorOpnd() local 988 Value *V0 = Sub->getOperand(0); in ShouldBreakUpSubtract() local
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H A D | ConstraintElimination.cpp | 1708 Value *V0 = B.isConditionFact() ? B.Cond.Op0 : B.Inst->getOperand(0); in eliminateConstraints() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 1371 SDValue V0, V1; insertHvxSubvectorReg() local 1622 SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG); LowerHvxBuildVector() local 1733 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, LowerHvxConcatVectors() local 3530 SDValue V0 = Op.getOperand(0); combineConcatVectorsBeforeLegal() local [all...] |
H A D | HexagonISelDAGToDAG.cpp | 2315 SDValue V0 = L0.Value; in balanceSubTree() local 2373 SDValue V0 = NewRoot.getOperand(0); in balanceSubTree() local
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H A D | HexagonLoopIdiomRecognition.cpp | 1761 uint32_t V0 = C0->getZExtValue(); in setupPostSimplifier() local
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | VectorUtils.cpp | 1004 Value *V0 = ResList[i], *V1 = ResList[i + 1]; in concatenateVectors() local
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/freebsd/sys/geom/raid/ |
H A D | md_ddf.h | 267 uint8_t V0[32]; member
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/freebsd/contrib/llvm-project/clang/lib/Headers/ |
H A D | hexagon_types.h | 2549 HVX_Vector V0(void) { return HEXAGON_HVX_GET_V0(data); }; in V0() function 2558 HVX_Vect V0(HVX_Vector v) { return HVX_Vect(HEXAGON_HVX_PUT_V0(data, v)); }; in V0() function
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 3598 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32), in LowerFP_TO_FP16() local 5273 APFloat V0 = FTZ(N0CFP->getValueAPF()); in PerformDAGCombine() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 2062 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0)); in EmitTest() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 1755 SDValue V0 = CurDAG->getRegister(RISCV::V0, VT); in Select() local
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/freebsd/contrib/llvm-project/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 3043 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); in upgradeX86IntrinsicCall() local
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