1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22 #ifndef _vcn_3_0_0_SH_MASK_HEADER 23 #define _vcn_3_0_0_SH_MASK_HEADER 24 25 // addressBlock: uvd0_mmsch_dec 26 //MMSCH_UCODE_ADDR 27 #define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 28 #define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 29 #define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 30 #define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 31 //MMSCH_UCODE_DATA 32 #define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 33 #define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 34 //MMSCH_SRAM_ADDR 35 #define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 36 #define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 37 #define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 38 #define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 39 //MMSCH_SRAM_DATA 40 #define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 41 #define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 42 //MMSCH_VF_SRAM_OFFSET 43 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 44 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 45 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 46 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 47 //MMSCH_DB_SRAM_OFFSET 48 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 49 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 50 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 51 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 52 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 53 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 54 //MMSCH_CTX_SRAM_OFFSET 55 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 56 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 57 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 58 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 59 //MMSCH_CTL 60 #define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0 61 #define MMSCH_CTL__P_RESET__SHIFT 0x1 62 #define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4 63 #define MMSCH_CTL__P_LOCK__SHIFT 0x1f 64 #define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L 65 #define MMSCH_CTL__P_RESET_MASK 0x00000002L 66 #define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L 67 #define MMSCH_CTL__P_LOCK_MASK 0x80000000L 68 //MMSCH_INTR 69 #define MMSCH_INTR__INTR__SHIFT 0x0 70 #define MMSCH_INTR__INTR_MASK 0x00001FFFL 71 //MMSCH_INTR_ACK 72 #define MMSCH_INTR_ACK__INTR__SHIFT 0x0 73 #define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 74 //MMSCH_INTR_STATUS 75 #define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 76 #define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 77 //MMSCH_VF_VMID 78 #define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 79 #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 80 #define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 81 #define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 82 //MMSCH_VF_CTX_ADDR_LO 83 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 84 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 85 //MMSCH_VF_CTX_ADDR_HI 86 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 87 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 88 //MMSCH_VF_CTX_SIZE 89 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 90 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 91 //MMSCH_VF_GPCOM_ADDR_LO 92 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 93 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 94 //MMSCH_VF_GPCOM_ADDR_HI 95 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 96 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 97 //MMSCH_VF_GPCOM_SIZE 98 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 99 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 100 //MMSCH_VF_MAILBOX_HOST 101 #define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 102 #define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 103 //MMSCH_VF_MAILBOX_RESP 104 #define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 105 #define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 106 //MMSCH_VF_MAILBOX_0 107 #define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 108 #define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 109 //MMSCH_VF_MAILBOX_0_RESP 110 #define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 111 #define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 112 //MMSCH_VF_MAILBOX_1 113 #define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 114 #define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 115 //MMSCH_VF_MAILBOX_1_RESP 116 #define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 117 #define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 118 //MMSCH_CNTL 119 #define MMSCH_CNTL__CLK_EN__SHIFT 0x0 120 #define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 121 #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 122 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 123 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 124 #define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 125 #define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 126 #define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 127 #define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 128 #define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 129 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 130 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 131 #define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 132 #define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 133 //MMSCH_NONCACHE_OFFSET0 134 #define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 135 #define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 136 //MMSCH_NONCACHE_SIZE0 137 #define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 138 #define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 139 //MMSCH_NONCACHE_OFFSET1 140 #define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 141 #define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 142 //MMSCH_NONCACHE_SIZE1 143 #define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 144 #define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 145 //MMSCH_PROC_STATE1 146 #define MMSCH_PROC_STATE1__PC__SHIFT 0x0 147 #define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 148 //MMSCH_LAST_MC_ADDR 149 #define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 150 #define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 151 #define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 152 #define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 153 //MMSCH_LAST_MEM_ACCESS_HI 154 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 155 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 156 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 157 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 158 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 159 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 160 //MMSCH_LAST_MEM_ACCESS_LO 161 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 162 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 163 //MMSCH_IOV_ACTIVE_FCN_ID 164 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 165 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 166 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL 167 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 168 //MMSCH_SCRATCH_0 169 #define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 170 #define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 171 //MMSCH_SCRATCH_1 172 #define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 173 #define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 174 //MMSCH_GPUIOV_SCH_BLOCK_0 175 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 176 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 177 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 178 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 179 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 180 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 181 //MMSCH_GPUIOV_CMD_CONTROL_0 182 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 183 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 184 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 185 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 186 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 187 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 188 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 189 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 190 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 191 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 192 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 193 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 194 //MMSCH_GPUIOV_CMD_STATUS_0 195 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 196 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 197 //MMSCH_GPUIOV_VM_BUSY_STATUS_0 198 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 199 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 200 //MMSCH_GPUIOV_ACTIVE_FCNS_0 201 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 202 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 203 //MMSCH_GPUIOV_ACTIVE_FCN_ID_0 204 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 205 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 206 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 207 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 208 //MMSCH_GPUIOV_DW6_0 209 #define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 210 #define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 211 //MMSCH_GPUIOV_DW7_0 212 #define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 213 #define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 214 //MMSCH_GPUIOV_DW8_0 215 #define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 216 #define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 217 //MMSCH_GPUIOV_SCH_BLOCK_1 218 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 219 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 220 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 221 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 222 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 223 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 224 //MMSCH_GPUIOV_CMD_CONTROL_1 225 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 226 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 227 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 228 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 229 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 230 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 231 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 232 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 233 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 234 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 235 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 236 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 237 //MMSCH_GPUIOV_CMD_STATUS_1 238 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 239 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 240 //MMSCH_GPUIOV_VM_BUSY_STATUS_1 241 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 242 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 243 //MMSCH_GPUIOV_ACTIVE_FCNS_1 244 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 245 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 246 //MMSCH_GPUIOV_ACTIVE_FCN_ID_1 247 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 248 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 249 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 250 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 251 //MMSCH_GPUIOV_DW6_1 252 #define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 253 #define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 254 //MMSCH_GPUIOV_DW7_1 255 #define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 256 #define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 257 //MMSCH_GPUIOV_DW8_1 258 #define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 259 #define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 260 //MMSCH_GPUIOV_CNTXT 261 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 262 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 263 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 264 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 265 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 266 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 267 //MMSCH_SCRATCH_2 268 #define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 269 #define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 270 //MMSCH_SCRATCH_3 271 #define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 272 #define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 273 //MMSCH_SCRATCH_4 274 #define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 275 #define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 276 //MMSCH_SCRATCH_5 277 #define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 278 #define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 279 //MMSCH_SCRATCH_6 280 #define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 281 #define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 282 //MMSCH_SCRATCH_7 283 #define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 284 #define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 285 //MMSCH_VFID_FIFO_HEAD_0 286 #define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 287 #define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 288 //MMSCH_VFID_FIFO_TAIL_0 289 #define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 290 #define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 291 //MMSCH_VFID_FIFO_HEAD_1 292 #define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 293 #define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 294 //MMSCH_VFID_FIFO_TAIL_1 295 #define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 296 #define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 297 //MMSCH_NACK_STATUS 298 #define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 299 #define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 300 #define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 301 #define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 302 //MMSCH_VF_MAILBOX0_DATA 303 #define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 304 #define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 305 //MMSCH_VF_MAILBOX1_DATA 306 #define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 307 #define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 308 //MMSCH_GPUIOV_SCH_BLOCK_IP_0 309 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 310 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 311 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 312 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 313 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 314 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 315 //MMSCH_GPUIOV_CMD_STATUS_IP_0 316 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 317 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 318 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 319 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 320 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 321 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 322 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 323 //MMSCH_GPUIOV_SCH_BLOCK_IP_1 324 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 325 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 326 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 327 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 328 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 329 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 330 //MMSCH_GPUIOV_CMD_STATUS_IP_1 331 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 332 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 333 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 334 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 335 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 336 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 337 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 338 //MMSCH_GPUIOV_CNTXT_IP 339 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 340 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 341 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 342 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 343 //MMSCH_GPUIOV_SCH_BLOCK_2 344 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 345 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 346 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 347 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 348 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 349 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 350 //MMSCH_GPUIOV_CMD_CONTROL_2 351 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 352 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 353 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 354 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 355 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 356 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 357 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 358 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 359 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 360 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 361 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 362 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 363 //MMSCH_GPUIOV_CMD_STATUS_2 364 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 365 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 366 //MMSCH_GPUIOV_VM_BUSY_STATUS_2 367 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 368 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 369 //MMSCH_GPUIOV_ACTIVE_FCNS_2 370 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 371 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 372 //MMSCH_GPUIOV_ACTIVE_FCN_ID_2 373 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 374 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 375 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 376 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 377 //MMSCH_GPUIOV_DW6_2 378 #define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 379 #define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 380 //MMSCH_GPUIOV_DW7_2 381 #define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 382 #define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 383 //MMSCH_GPUIOV_DW8_2 384 #define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 385 #define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 386 //MMSCH_GPUIOV_SCH_BLOCK_IP_2 387 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 388 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 389 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 390 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 391 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 392 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 393 //MMSCH_GPUIOV_CMD_STATUS_IP_2 394 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 395 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 396 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 397 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 398 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 399 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 400 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 401 //MMSCH_VFID_FIFO_HEAD_2 402 #define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 403 #define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 404 //MMSCH_VFID_FIFO_TAIL_2 405 #define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 406 #define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 407 //MMSCH_VM_BUSY_STATUS_0 408 #define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 409 #define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 410 //MMSCH_VM_BUSY_STATUS_1 411 #define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 412 #define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 413 //MMSCH_VM_BUSY_STATUS_2 414 #define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 415 #define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 416 417 418 // addressBlock: uvd0_jpegnpdec 419 //UVD_JPEG_CNTL 420 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 421 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 422 #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 423 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 424 #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 425 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 426 #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 427 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 428 //UVD_JPEG_RB_BASE 429 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 430 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 431 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 432 #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 433 //UVD_JPEG_RB_WPTR 434 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 435 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 436 //UVD_JPEG_RB_RPTR 437 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 438 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 439 //UVD_JPEG_RB_SIZE 440 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 441 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 442 //UVD_JPEG_DEC_CNT 443 #define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 444 #define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL 445 //UVD_JPEG_SPS_INFO 446 #define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 447 #define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 448 #define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL 449 #define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L 450 //UVD_JPEG_SPS1_INFO 451 #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 452 #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 453 #define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 454 #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L 455 #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L 456 #define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L 457 //UVD_JPEG_RE_TIMER 458 #define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 459 #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 460 #define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL 461 #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L 462 //UVD_JPEG_DEC_SCRATCH0 463 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 464 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 465 //UVD_JPEG_INT_EN 466 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 467 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 468 #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 469 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 470 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 471 #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 472 #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 473 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 474 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 475 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 476 #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 477 #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 478 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 479 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 480 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 481 #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 482 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 483 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 484 #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 485 #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 486 #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 487 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 488 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 489 #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 490 #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 491 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 492 //UVD_JPEG_INT_STAT 493 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 494 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 495 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 496 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 497 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 498 #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 499 #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 500 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 501 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 502 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 503 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 504 #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 505 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 506 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 507 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 508 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 509 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 510 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 511 #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 512 #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 513 #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 514 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 515 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 516 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 517 #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 518 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 519 //UVD_JPEG_TIER_CNTL0 520 #define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 521 #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 522 #define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 523 #define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 524 #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 525 #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb 526 #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe 527 #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 528 #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 529 #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 530 #define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a 531 #define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c 532 #define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e 533 #define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L 534 #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL 535 #define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L 536 #define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L 537 #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L 538 #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L 539 #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L 540 #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L 541 #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L 542 #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L 543 #define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L 544 #define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L 545 #define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L 546 //UVD_JPEG_TIER_CNTL1 547 #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 548 #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 549 #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL 550 #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L 551 //UVD_JPEG_TIER_CNTL2 552 #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 553 #define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 554 #define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 555 #define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 556 #define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 557 #define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 558 #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa 559 #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe 560 #define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 561 #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L 562 #define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L 563 #define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL 564 #define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L 565 #define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L 566 #define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L 567 #define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L 568 #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L 569 #define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L 570 //UVD_JPEG_TIER_STATUS 571 #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 572 #define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 573 #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L 574 #define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L 575 //UVD_JPEG_OUTBUF_CNTL 576 #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 577 #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 578 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 579 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 580 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 581 #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L 582 #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L 583 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L 584 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L 585 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L 586 //UVD_JPEG_OUTBUF_WPTR 587 #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 588 #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL 589 //UVD_JPEG_OUTBUF_RPTR 590 #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 591 #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL 592 //UVD_JPEG_PITCH 593 #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 594 #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 595 //UVD_JPEG_UV_PITCH 596 #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 597 #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 598 //JPEG_DEC_Y_GFX10_TILING_SURFACE 599 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 600 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 601 //JPEG_DEC_UV_GFX10_TILING_SURFACE 602 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 603 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 604 //JPEG_DEC_GFX10_ADDR_CONFIG 605 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 606 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 607 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 608 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 609 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 610 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 611 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 612 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 613 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 614 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 615 //JPEG_DEC_ADDR_MODE 616 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 617 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 618 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 619 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 620 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 621 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 622 //UVD_JPEG_OUTPUT_XY 623 #define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 624 #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 625 #define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL 626 #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L 627 //UVD_JPEG_GPCOM_CMD 628 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 629 #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 630 //UVD_JPEG_GPCOM_DATA0 631 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 632 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 633 //UVD_JPEG_GPCOM_DATA1 634 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 635 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 636 //UVD_JPEG_INDEX 637 #define UVD_JPEG_INDEX__INDEX__SHIFT 0x0 638 #define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL 639 //UVD_JPEG_DATA 640 #define UVD_JPEG_DATA__DATA__SHIFT 0x0 641 #define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL 642 //UVD_JPEG_SCRATCH1 643 #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 644 #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 645 //UVD_JPEG_DEC_SOFT_RST 646 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 647 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 648 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 649 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 650 651 652 // addressBlock: uvd0_uvd_jpeg_enc_dec 653 //UVD_JPEG_ENC_ECS_VALID_BYTES 654 #define UVD_JPEG_ENC_ECS_VALID_BYTES__TOTAL_NUM_BYTES__SHIFT 0x0 655 #define UVD_JPEG_ENC_ECS_VALID_BYTES__TOTAL_NUM_BYTES_MASK 0xFFFFFFFFL 656 //UVD_JPEG_ENC_INT_EN 657 #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 658 #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 659 #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 660 #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 661 #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 662 #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 663 #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 664 #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L 665 #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L 666 #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L 667 #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L 668 #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L 669 #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L 670 #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L 671 //UVD_JPEG_ENC_INT_STATUS 672 #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 673 #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 674 #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 675 #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 676 #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 677 #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 678 #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 679 #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L 680 #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L 681 #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L 682 #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L 683 #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L 684 #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L 685 #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L 686 //UVD_JPEG_ENC_PEL_CNTL 687 #define UVD_JPEG_ENC_PEL_CNTL__LUMA_PAD_DATA__SHIFT 0x0 688 #define UVD_JPEG_ENC_PEL_CNTL__CHROMAU_PAD_DATA__SHIFT 0x8 689 #define UVD_JPEG_ENC_PEL_CNTL__CHROMAV_PAD_DATA__SHIFT 0x10 690 #define UVD_JPEG_ENC_PEL_CNTL__USER_MODE_SEL__SHIFT 0x18 691 #define UVD_JPEG_ENC_PEL_CNTL__LUMA_PAD_DATA_MASK 0x000000FFL 692 #define UVD_JPEG_ENC_PEL_CNTL__CHROMAU_PAD_DATA_MASK 0x0000FF00L 693 #define UVD_JPEG_ENC_PEL_CNTL__CHROMAV_PAD_DATA_MASK 0x00FF0000L 694 #define UVD_JPEG_ENC_PEL_CNTL__USER_MODE_SEL_MASK 0x03000000L 695 //UVD_JPEG_ENC_RESTART_MARKER_CNTL 696 #define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_INTERVAL__SHIFT 0x0 697 #define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_MARKER_ENABLE__SHIFT 0x10 698 #define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_INTERVAL_MASK 0x0000FFFFL 699 #define UVD_JPEG_ENC_RESTART_MARKER_CNTL__RESTART_MARKER_ENABLE_MASK 0x00010000L 700 //UVD_JPEG_ENC_ENGINE_CNTL 701 #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 702 #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 703 #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 704 #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 705 #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 706 #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 707 #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L 708 #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L 709 #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L 710 #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L 711 #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L 712 #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L 713 //UVD_JPEG_ENC_SCALAR_DST_IMG_INFO 714 #define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_WIDTH__SHIFT 0x0 715 #define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_HEIGHT__SHIFT 0x9 716 #define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_WIDTH_MASK 0x000001FFL 717 #define UVD_JPEG_ENC_SCALAR_DST_IMG_INFO__DST_HEIGHT_MASK 0x0003FE00L 718 //UVD_JPEG_ENC_HUFF_TBL 719 #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_DATA__SHIFT 0x0 720 #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_ADDR__SHIFT 0x14 721 #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_WRITE__SHIFT 0x1f 722 #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_DATA_MASK 0x000FFFFFL 723 #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_ADDR_MASK 0x1FF00000L 724 #define UVD_JPEG_ENC_HUFF_TBL__HUFF_TBL_WRITE_MASK 0x80000000L 725 //UVD_JPEG_ENC_HUFF_TBL_RDATA 726 #define UVD_JPEG_ENC_HUFF_TBL_RDATA__HUFF_TBL_RDATA__SHIFT 0x0 727 #define UVD_JPEG_ENC_HUFF_TBL_RDATA__HUFF_TBL_RDATA_MASK 0x000FFFFFL 728 //UVD_JPEG_ENC_QUANT_TBL 729 #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_READ__SHIFT 0x0 730 #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_ADDR__SHIFT 0x1 731 #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_IDX__SHIFT 0x7 732 #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_READ_MASK 0x00000001L 733 #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_ADDR_MASK 0x0000007EL 734 #define UVD_JPEG_ENC_QUANT_TBL__QUANT_TBL_IDX_MASK 0x00000180L 735 //UVD_JPEG_ENC_QUANT_TBL_RDATA 736 #define UVD_JPEG_ENC_QUANT_TBL_RDATA__QUANT_TBL_RDATA__SHIFT 0x0 737 #define UVD_JPEG_ENC_QUANT_TBL_RDATA__QUANT_TBL_RDATA_MASK 0x0000FFFFL 738 //UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET 739 #define UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET__SCLR_CHROMAU_OFFSET__SHIFT 0x0 740 #define UVD_JPEG_ENC_SCLR_CHROMAU_OFFSET__SCLR_CHROMAU_OFFSET_MASK 0x003FFFFFL 741 //UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET 742 #define UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET__SCLR_CHROMAV_OFFSET__SHIFT 0x0 743 #define UVD_JPEG_ENC_SCLR_CHROMAV_OFFSET__SCLR_CHROMAV_OFFSET_MASK 0x003FFFFFL 744 //UVD_JPEG_ENC_SCLR_PITCH 745 #define UVD_JPEG_ENC_SCLR_PITCH__PITCH__SHIFT 0x0 746 #define UVD_JPEG_ENC_SCLR_PITCH__PITCH_MASK 0x0000003FL 747 //UVD_JPEG_ENC_SCRATCH1 748 #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 749 #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 750 751 752 // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 753 //UVD_JPEG_ENC_SPS_INFO 754 #define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT__SHIFT 0x0 755 #define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT__SHIFT 0x3 756 #define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422__SHIFT 0x4 757 #define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT_MASK 0x00000007L 758 #define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT_MASK 0x00000008L 759 #define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422_MASK 0x00000010L 760 //UVD_JPEG_ENC_SPS_INFO1 761 #define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH__SHIFT 0x0 762 #define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT__SHIFT 0x10 763 #define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH_MASK 0x0000FFFFL 764 #define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT_MASK 0xFFFF0000L 765 //UVD_JPEG_ENC_TBL_SIZE 766 #define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE__SHIFT 0x6 767 #define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE_MASK 0x00000FC0L 768 //UVD_JPEG_ENC_TBL_CNTL 769 #define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL__SHIFT 0x0 770 #define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE__SHIFT 0x1 771 #define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE__SHIFT 0x2 772 #define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN__SHIFT 0x4 773 #define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL_MASK 0x00000001L 774 #define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE_MASK 0x00000002L 775 #define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE_MASK 0x0000000CL 776 #define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN_MASK 0x00000010L 777 //UVD_JPEG_ENC_MC_REQ_CNTL 778 #define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK__SHIFT 0x0 779 #define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK_MASK 0x0000003FL 780 //UVD_JPEG_ENC_STATUS 781 #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 782 #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 783 #define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 784 #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 785 #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L 786 #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L 787 #define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L 788 #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L 789 //UVD_JPEG_ENC_PITCH 790 #define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 791 #define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 792 #define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL 793 #define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L 794 //UVD_JPEG_ENC_LUMA_BASE 795 #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 796 #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL 797 //UVD_JPEG_ENC_CHROMAU_BASE 798 #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 799 #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL 800 //UVD_JPEG_ENC_CHROMAV_BASE 801 #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 802 #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL 803 //JPEG_ENC_Y_GFX10_TILING_SURFACE 804 #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 805 #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 806 //JPEG_ENC_UV_GFX10_TILING_SURFACE 807 #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 808 #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 809 //JPEG_ENC_GFX10_ADDR_CONFIG 810 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 811 #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 812 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 813 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 814 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 815 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 816 #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 817 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 818 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 819 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 820 //JPEG_ENC_ADDR_MODE 821 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 822 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 823 #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 824 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 825 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 826 #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 827 //UVD_JPEG_ENC_GPCOM_CMD 828 #define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 829 #define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL 830 //UVD_JPEG_ENC_GPCOM_DATA0 831 #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 832 #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 833 //UVD_JPEG_ENC_GPCOM_DATA1 834 #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 835 #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 836 //UVD_JPEG_TBL_DAT0 837 #define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0__SHIFT 0x0 838 #define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0_MASK 0xFFFFFFFFL 839 //UVD_JPEG_TBL_DAT1 840 #define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32__SHIFT 0x0 841 #define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32_MASK 0xFFFFFFFFL 842 //UVD_JPEG_TBL_IDX 843 #define UVD_JPEG_TBL_IDX__TBL_IDX__SHIFT 0x0 844 #define UVD_JPEG_TBL_IDX__TBL_IDX_MASK 0x000000FFL 845 //UVD_JPEG_ENC_CGC_CNTL 846 #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 847 #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L 848 //UVD_JPEG_ENC_SCRATCH0 849 #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 850 #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 851 //UVD_JPEG_ENC_SOFT_RST 852 #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 853 #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 854 #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L 855 #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 856 857 858 // addressBlock: uvd0_uvd_jrbc_dec 859 //UVD_JRBC_RB_WPTR 860 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 861 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 862 //UVD_JRBC_RB_CNTL 863 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 864 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 865 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 866 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 867 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 868 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 869 //UVD_JRBC_IB_SIZE 870 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 871 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 872 //UVD_JRBC_URGENT_CNTL 873 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 874 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 875 //UVD_JRBC_RB_REF_DATA 876 #define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 877 #define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 878 //UVD_JRBC_RB_COND_RD_TIMER 879 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 880 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 881 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 882 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 883 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 884 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 885 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 886 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 887 //UVD_JRBC_SOFT_RESET 888 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 889 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 890 #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 891 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 892 //UVD_JRBC_STATUS 893 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 894 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 895 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 896 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 897 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 898 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 899 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 900 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 901 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 902 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 903 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 904 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 905 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 906 #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 907 #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 908 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 909 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 910 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 911 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 912 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 913 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 914 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 915 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 916 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 917 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 918 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 919 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 920 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 921 #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 922 #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 923 //UVD_JRBC_RB_RPTR 924 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 925 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 926 //UVD_JRBC_RB_BUF_STATUS 927 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 928 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 929 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 930 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 931 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 932 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 933 //UVD_JRBC_IB_BUF_STATUS 934 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 935 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 936 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 937 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 938 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 939 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 940 //UVD_JRBC_IB_SIZE_UPDATE 941 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 942 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 943 //UVD_JRBC_IB_COND_RD_TIMER 944 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 945 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 946 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 947 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 948 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 949 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 950 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 951 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 952 //UVD_JRBC_IB_REF_DATA 953 #define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 954 #define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 955 //UVD_JPEG_PREEMPT_CMD 956 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 957 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 958 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 959 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 960 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 961 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 962 //UVD_JPEG_PREEMPT_FENCE_DATA0 963 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 964 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 965 //UVD_JPEG_PREEMPT_FENCE_DATA1 966 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 967 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 968 //UVD_JRBC_RB_SIZE 969 #define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 970 #define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 971 //UVD_JRBC_SCRATCH0 972 #define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 973 #define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 974 975 976 // addressBlock: uvd0_uvd_jrbc_enc_dec 977 //UVD_JRBC_ENC_RB_WPTR 978 #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 979 #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 980 //UVD_JRBC_ENC_RB_CNTL 981 #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 982 #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 983 #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 984 #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 985 #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 986 #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 987 //UVD_JRBC_ENC_IB_SIZE 988 #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 989 #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 990 //UVD_JRBC_ENC_URGENT_CNTL 991 #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 992 #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 993 //UVD_JRBC_ENC_RB_REF_DATA 994 #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 995 #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 996 //UVD_JRBC_ENC_RB_COND_RD_TIMER 997 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 998 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 999 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 1000 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 1001 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 1002 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 1003 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 1004 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 1005 //UVD_JRBC_ENC_SOFT_RESET 1006 #define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 1007 #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 1008 #define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L 1009 #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 1010 //UVD_JRBC_ENC_STATUS 1011 #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 1012 #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 1013 #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 1014 #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 1015 #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 1016 #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 1017 #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 1018 #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 1019 #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 1020 #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 1021 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 1022 #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb 1023 #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 1024 #define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 1025 #define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 1026 #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L 1027 #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L 1028 #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 1029 #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 1030 #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 1031 #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 1032 #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 1033 #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 1034 #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 1035 #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 1036 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 1037 #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 1038 #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 1039 #define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L 1040 #define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L 1041 //UVD_JRBC_ENC_RB_RPTR 1042 #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 1043 #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 1044 //UVD_JRBC_ENC_RB_BUF_STATUS 1045 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 1046 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 1047 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 1048 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 1049 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 1050 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 1051 //UVD_JRBC_ENC_IB_BUF_STATUS 1052 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 1053 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 1054 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 1055 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 1056 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 1057 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 1058 //UVD_JRBC_ENC_IB_SIZE_UPDATE 1059 #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 1060 #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 1061 //UVD_JRBC_ENC_IB_COND_RD_TIMER 1062 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 1063 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 1064 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 1065 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 1066 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 1067 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 1068 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 1069 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 1070 //UVD_JRBC_ENC_IB_REF_DATA 1071 #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 1072 #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 1073 //UVD_JPEG_ENC_PREEMPT_CMD 1074 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 1075 #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 1076 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 1077 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 1078 #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 1079 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 1080 //UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 1081 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 1082 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 1083 //UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 1084 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 1085 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 1086 //UVD_JRBC_ENC_RB_SIZE 1087 #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 1088 #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 1089 //UVD_JRBC_ENC_SCRATCH0 1090 #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 1091 #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 1092 1093 1094 // addressBlock: uvd0_uvd_jmi_dec 1095 //UVD_JADP_MCIF_URGENT_CTRL 1096 #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 1097 #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 1098 #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb 1099 #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 1100 #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 1101 #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 1102 #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a 1103 #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL 1104 #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L 1105 #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L 1106 #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L 1107 #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L 1108 #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L 1109 #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L 1110 //UVD_JMI_URGENT_CTRL 1111 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 1112 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 1113 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 1114 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 1115 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 1116 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L 1117 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L 1118 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L 1119 //UVD_JPEG_DEC_PF_CTRL 1120 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 1121 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 1122 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 1123 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 1124 //UVD_JPEG_ENC_PF_CTRL 1125 #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0 1126 #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1 1127 #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L 1128 #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L 1129 //UVD_JMI_CTRL 1130 #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 1131 #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 1132 #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 1133 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 1134 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 1135 #define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 1136 #define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 1137 #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 1138 #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 1139 #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 1140 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 1141 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 1142 #define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 1143 #define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 1144 //UVD_LMI_JRBC_CTRL 1145 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1146 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1147 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 1148 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 1149 #define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 1150 #define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 1151 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1152 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1153 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1154 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1155 #define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 1156 #define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 1157 //UVD_LMI_JPEG_CTRL 1158 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1159 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1160 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 1161 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 1162 #define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 1163 #define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 1164 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1165 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1166 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1167 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1168 #define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 1169 #define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1170 //UVD_JMI_EJRBC_CTRL 1171 #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1172 #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1173 #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 1174 #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 1175 #define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 1176 #define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 1177 #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1178 #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1179 #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1180 #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1181 #define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 1182 #define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 1183 //UVD_LMI_EJPEG_CTRL 1184 #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1185 #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1186 #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 1187 #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 1188 #define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 1189 #define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 1190 #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1191 #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1192 #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1193 #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1194 #define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 1195 #define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1196 //UVD_JMI_SCALER_CTRL 1197 #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 1198 #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 1199 #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4 1200 #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8 1201 #define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14 1202 #define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16 1203 #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1204 #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1205 #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1206 #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1207 #define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L 1208 #define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L 1209 //JPEG_LMI_DROP 1210 #define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 1211 #define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 1212 #define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 1213 #define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 1214 #define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 1215 #define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 1216 #define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 1217 #define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 1218 //UVD_JMI_EJPEG_DROP 1219 #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0 1220 #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1 1221 #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2 1222 #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3 1223 #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4 1224 #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5 1225 #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L 1226 #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L 1227 #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L 1228 #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L 1229 #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L 1230 #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L 1231 //JPEG_MEMCHECK_CLAMPING 1232 #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd 1233 #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe 1234 #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16 1235 #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17 1236 #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19 1237 #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a 1238 #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 1239 #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L 1240 #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L 1241 #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L 1242 #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L 1243 #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L 1244 #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L 1245 #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 1246 //UVD_JMI_EJPEG_MEMCHECK_CLAMPING 1247 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0 1248 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1 1249 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2 1250 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3 1251 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4 1252 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5 1253 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 1254 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L 1255 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L 1256 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L 1257 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L 1258 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L 1259 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L 1260 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 1261 //UVD_LMI_JRBC_IB_VMID 1262 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1263 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1264 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1265 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1266 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1267 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1268 //UVD_LMI_JRBC_RB_VMID 1269 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1270 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1271 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1272 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1273 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1274 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1275 //UVD_LMI_JPEG_VMID 1276 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 1277 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 1278 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 1279 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 1280 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 1281 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 1282 //UVD_JMI_ENC_JRBC_IB_VMID 1283 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1284 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1285 #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1286 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1287 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1288 #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1289 //UVD_JMI_ENC_JRBC_RB_VMID 1290 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1291 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1292 #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1293 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1294 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1295 #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1296 //UVD_JMI_ENC_JPEG_VMID 1297 #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 1298 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 1299 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 1300 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 1301 #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 1302 #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 1303 #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 1304 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 1305 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 1306 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 1307 #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 1308 #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 1309 //JPEG_MEMCHECK_SAFE_ADDR 1310 #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 1311 #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL 1312 //JPEG_MEMCHECK_SAFE_ADDR_64BIT 1313 #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 1314 #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL 1315 //UVD_JMI_LAT_CTRL 1316 #define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 1317 #define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 1318 #define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 1319 #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa 1320 #define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 1321 #define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 1322 #define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL 1323 #define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L 1324 #define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L 1325 #define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L 1326 #define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 1327 #define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L 1328 //UVD_JMI_LAT_CNTR 1329 #define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 1330 #define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 1331 #define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 1332 #define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 1333 //UVD_JMI_AVG_LAT_CNTR 1334 #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 1335 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 1336 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 1337 #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 1338 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 1339 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 1340 //UVD_JMI_PERFMON_CTRL 1341 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1342 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1343 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1344 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 1345 //UVD_JMI_PERFMON_COUNT_LO 1346 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1347 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1348 //UVD_JMI_PERFMON_COUNT_HI 1349 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1350 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1351 //UVD_JMI_CLEAN_STATUS 1352 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 1353 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 1354 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 1355 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 1356 #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4 1357 #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5 1358 #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6 1359 #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7 1360 #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8 1361 #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9 1362 #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa 1363 #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb 1364 #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc 1365 #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd 1366 #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe 1367 #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf 1368 #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10 1369 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L 1370 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L 1371 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L 1372 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L 1373 #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L 1374 #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L 1375 #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L 1376 #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L 1377 #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L 1378 #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L 1379 #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L 1380 #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L 1381 #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L 1382 #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L 1383 #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L 1384 #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L 1385 #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L 1386 //UVD_LMI_JPEG_READ_64BIT_BAR_LOW 1387 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1388 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1389 //UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 1390 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1391 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1392 //UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 1393 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1394 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1395 //UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 1396 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1397 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1398 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1399 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1400 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1401 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1402 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1403 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1404 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 1405 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1406 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1407 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 1408 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1409 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1410 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW 1411 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1412 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1413 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 1414 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1415 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1416 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 1417 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1418 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1419 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 1420 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1421 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1422 //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1423 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1424 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1425 //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1426 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1427 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1428 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 1429 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1430 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1431 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 1432 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1433 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1434 //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 1435 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1436 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1437 //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 1438 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1439 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1440 //UVD_JMI_PEL_RD_64BIT_BAR_LOW 1441 #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1442 #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1443 //UVD_JMI_PEL_RD_64BIT_BAR_HIGH 1444 #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1445 #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1446 //UVD_JMI_BS_WR_64BIT_BAR_LOW 1447 #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1448 #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1449 //UVD_JMI_BS_WR_64BIT_BAR_HIGH 1450 #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1451 #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1452 //UVD_JMI_SCALAR_RD_64BIT_BAR_LOW 1453 #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1454 #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1455 //UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 1456 #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1457 #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1458 //UVD_JMI_SCALAR_WR_64BIT_BAR_LOW 1459 #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1460 #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1461 //UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 1462 #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1463 #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1464 //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1465 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1466 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1467 //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1468 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1469 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1470 //UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 1471 #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1472 #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1473 //UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 1474 #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1475 #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1476 //UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 1477 #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1478 #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1479 //UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 1480 #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1481 #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1482 //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 1483 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1484 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1485 //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 1486 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1487 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1488 //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 1489 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1490 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1491 //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 1492 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1493 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1494 //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 1495 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1496 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1497 //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 1498 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1499 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1500 //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 1501 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1502 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1503 //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 1504 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1505 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1506 //UVD_LMI_JPEG_PREEMPT_VMID 1507 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1508 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1509 //UVD_LMI_ENC_JPEG_PREEMPT_VMID 1510 #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1511 #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1512 //UVD_LMI_JPEG2_VMID 1513 #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 1514 #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 1515 #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 1516 #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 1517 //UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 1518 #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1519 #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1520 //UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 1521 #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1522 #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1523 //UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 1524 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1525 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1526 //UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 1527 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1528 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1529 //UVD_LMI_JPEG_CTRL2 1530 #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 1531 #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 1532 #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 1533 #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 1534 #define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 1535 #define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 1536 #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 1537 #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 1538 #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 1539 #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 1540 #define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 1541 #define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 1542 //UVD_JMI_DEC_SWAP_CNTL 1543 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1544 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1545 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1546 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1547 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1548 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1549 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1550 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 1551 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 1552 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1553 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1554 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1555 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1556 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1557 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1558 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1559 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 1560 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 1561 //UVD_JMI_ENC_SWAP_CNTL 1562 #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1563 #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1564 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1565 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1566 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1567 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1568 #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1569 #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 1570 #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 1571 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 1572 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 1573 #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 1574 #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1575 #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1576 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1577 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1578 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1579 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1580 #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1581 #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 1582 #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 1583 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 1584 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 1585 #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 1586 //UVD_JMI_CNTL 1587 #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 1588 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 1589 #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 1590 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 1591 //UVD_JMI_ATOMIC_CNTL 1592 #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 1593 #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 1594 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 1595 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 1596 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 1597 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 1598 #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 1599 #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 1600 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 1601 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 1602 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 1603 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 1604 //UVD_JMI_ATOMIC_CNTL2 1605 #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 1606 #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 1607 #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 1608 #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 1609 //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 1610 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1611 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1612 //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 1613 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1614 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1615 //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 1616 #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1617 #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1618 //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 1619 #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1620 #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1621 //JPEG2_LMI_DROP 1622 #define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0 1623 #define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1 1624 #define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L 1625 #define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L 1626 //UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 1627 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1628 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1629 //UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 1630 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1631 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1632 //UVD_JMI_DEC_SWAP_CNTL2 1633 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 1634 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 1635 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 1636 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 1637 //UVD_JPEG_DEC2_PF_CTRL 1638 #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_HANDLING_DIS__SHIFT 0x0 1639 #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_SW_GATING__SHIFT 0x1 1640 #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_HANDLING_DIS_MASK 0x00000001L 1641 #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_SW_GATING_MASK 0x00000002L 1642 1643 1644 // addressBlock: uvd0_uvd_jpeg_common_dec 1645 //JPEG_SOFT_RESET_STATUS 1646 #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 1647 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 1648 #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 1649 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 1650 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 1651 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 1652 #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 1653 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 1654 #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 1655 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 1656 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 1657 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 1658 //JPEG_SYS_INT_EN 1659 #define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 1660 #define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 1661 #define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 1662 #define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 1663 #define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 1664 #define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 1665 #define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 1666 #define JPEG_SYS_INT_EN__DJPEG2_PF_RPT__SHIFT 0x7 1667 #define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 1668 #define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 1669 #define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 1670 #define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 1671 #define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 1672 #define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 1673 #define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 1674 #define JPEG_SYS_INT_EN__DJPEG2_PF_RPT_MASK 0x00000080L 1675 //JPEG_SYS_INT_STATUS 1676 #define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 1677 #define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 1678 #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 1679 #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 1680 #define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 1681 #define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 1682 #define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 1683 #define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT__SHIFT 0x7 1684 #define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 1685 #define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 1686 #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 1687 #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 1688 #define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 1689 #define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 1690 #define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 1691 #define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT_MASK 0x00000080L 1692 //JPEG_SYS_INT_ACK 1693 #define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 1694 #define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 1695 #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 1696 #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 1697 #define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 1698 #define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 1699 #define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 1700 #define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT__SHIFT 0x7 1701 #define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 1702 #define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 1703 #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 1704 #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 1705 #define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 1706 #define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 1707 #define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 1708 #define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT_MASK 0x00000080L 1709 //JPEG_MEMCHECK_SYS_INT_EN 1710 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0 1711 #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1 1712 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2 1713 #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3 1714 #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4 1715 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5 1716 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6 1717 #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7 1718 #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8 1719 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9 1720 #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa 1721 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb 1722 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L 1723 #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L 1724 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L 1725 #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L 1726 #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L 1727 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L 1728 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L 1729 #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L 1730 #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L 1731 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L 1732 #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L 1733 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L 1734 //JPEG_MEMCHECK_SYS_INT_STAT 1735 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0 1736 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1 1737 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2 1738 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3 1739 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4 1740 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5 1741 #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6 1742 #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7 1743 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8 1744 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9 1745 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa 1746 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb 1747 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc 1748 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd 1749 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe 1750 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf 1751 #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10 1752 #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11 1753 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12 1754 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13 1755 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14 1756 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15 1757 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16 1758 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17 1759 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L 1760 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L 1761 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L 1762 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L 1763 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L 1764 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L 1765 #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L 1766 #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L 1767 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L 1768 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L 1769 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L 1770 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L 1771 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L 1772 #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L 1773 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L 1774 #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L 1775 #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L 1776 #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L 1777 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L 1778 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L 1779 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L 1780 #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L 1781 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L 1782 #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L 1783 //JPEG_MEMCHECK_SYS_INT_ACK 1784 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0 1785 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1 1786 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2 1787 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3 1788 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4 1789 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5 1790 #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6 1791 #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7 1792 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8 1793 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9 1794 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa 1795 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb 1796 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc 1797 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd 1798 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe 1799 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf 1800 #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10 1801 #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11 1802 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12 1803 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13 1804 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14 1805 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15 1806 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16 1807 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17 1808 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L 1809 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L 1810 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L 1811 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L 1812 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L 1813 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L 1814 #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L 1815 #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L 1816 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L 1817 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L 1818 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L 1819 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L 1820 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L 1821 #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L 1822 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L 1823 #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L 1824 #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L 1825 #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L 1826 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L 1827 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L 1828 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L 1829 #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L 1830 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L 1831 #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L 1832 //UVD_JPEG_IOV_ACTIVE_FCN_ID 1833 #define UVD_JPEG_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 1834 #define UVD_JPEG_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 1835 #define UVD_JPEG_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL 1836 #define UVD_JPEG_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 1837 //JPEG_MASTINT_EN 1838 #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 1839 #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 1840 #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 1841 #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 1842 //JPEG_IH_CTRL 1843 #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 1844 #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 1845 #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 1846 #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 1847 #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 1848 #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 1849 #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 1850 #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 1851 #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 1852 #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 1853 #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 1854 #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 1855 //JRBBM_ARB_CTRL 1856 #define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 1857 #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 1858 #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 1859 #define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 1860 #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 1861 #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 1862 1863 1864 // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 1865 //JPEG_CGC_GATE 1866 #define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 1867 #define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 1868 #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 1869 #define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 1870 #define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 1871 #define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 1872 #define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 1873 #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 1874 #define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 1875 #define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 1876 //JPEG_CGC_CTRL 1877 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1878 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 1879 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 1880 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa 1881 #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb 1882 #define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc 1883 #define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 1884 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 1885 #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 1886 #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 1887 #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 1888 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1889 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 1890 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L 1891 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L 1892 #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L 1893 #define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L 1894 #define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 1895 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 1896 #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 1897 #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 1898 #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 1899 //JPEG_CGC_STATUS 1900 #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 1901 #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 1902 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 1903 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 1904 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 1905 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 1906 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 1907 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 1908 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 1909 #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 1910 #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 1911 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 1912 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 1913 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 1914 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 1915 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 1916 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 1917 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 1918 //JPEG_COMN_CGC_MEM_CTRL 1919 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 1920 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 1921 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 1922 #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 1923 #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 1924 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 1925 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 1926 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 1927 #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 1928 #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 1929 //JPEG_DEC_CGC_MEM_CTRL 1930 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 1931 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 1932 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 1933 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 1934 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 1935 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 1936 //JPEG2_DEC_CGC_MEM_CTRL 1937 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 1938 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 1939 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 1940 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 1941 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 1942 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 1943 //JPEG_ENC_CGC_MEM_CTRL 1944 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 1945 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 1946 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 1947 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 1948 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 1949 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 1950 //JPEG_SOFT_RESET2 1951 #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1952 #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1953 //JPEG_PERF_BANK_CONF 1954 #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 1955 #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 1956 #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 1957 #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 1958 #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 1959 #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 1960 //JPEG_PERF_BANK_EVENT_SEL 1961 #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 1962 #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 1963 #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 1964 #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 1965 #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 1966 #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 1967 #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 1968 #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 1969 //JPEG_PERF_BANK_COUNT0 1970 #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 1971 #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 1972 //JPEG_PERF_BANK_COUNT1 1973 #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 1974 #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 1975 //JPEG_PERF_BANK_COUNT2 1976 #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 1977 #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 1978 //JPEG_PERF_BANK_COUNT3 1979 #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 1980 #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 1981 1982 1983 // addressBlock: uvd0_uvd_pg_dec 1984 //UVD_PGFSM_CONFIG 1985 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 1986 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 1987 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 1988 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 1989 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 1990 #define UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 0xa 1991 #define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 0xc 1992 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 1993 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 1994 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 1995 #define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 0x14 1996 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 1997 #define UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 0x18 1998 #define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 0x1a 1999 #define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT 0x1c 2000 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 2001 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 2002 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 2003 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 2004 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 2005 #define UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG_MASK 0x00000C00L 2006 #define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG_MASK 0x00003000L 2007 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 2008 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 2009 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 2010 #define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG_MASK 0x00300000L 2011 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 2012 #define UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG_MASK 0x03000000L 2013 #define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG_MASK 0x0C000000L 2014 #define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG_MASK 0x30000000L 2015 //UVD_PGFSM_STATUS 2016 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 2017 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 2018 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 2019 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 2020 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 2021 #define UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 0xa 2022 #define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 0xc 2023 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 2024 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 2025 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 2026 #define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 0x14 2027 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 2028 #define UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 0x18 2029 #define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 0x1a 2030 #define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT 0x1c 2031 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 2032 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 2033 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 2034 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 2035 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 2036 #define UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS_MASK 0x00000C00L 2037 #define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS_MASK 0x00003000L 2038 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 2039 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 2040 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 2041 #define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS_MASK 0x00300000L 2042 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 2043 #define UVD_PGFSM_STATUS__UVDATD_PWR_STATUS_MASK 0x03000000L 2044 #define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS_MASK 0x0C000000L 2045 #define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS_MASK 0x30000000L 2046 //UVD_POWER_STATUS 2047 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 2048 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 2049 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 2050 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 2051 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 2052 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 2053 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 2054 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 2055 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 2056 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 2057 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 2058 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 2059 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 2060 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 2061 //UVD_PG_IND_INDEX 2062 #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 2063 #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 2064 //UVD_PG_IND_DATA 2065 #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 2066 #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 2067 //CC_UVD_HARVESTING 2068 #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 2069 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 2070 #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 2071 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 2072 //UVD_JPEG_POWER_STATUS 2073 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 2074 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 2075 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 2076 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 2077 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 2078 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 2079 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 2080 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 2081 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 2082 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 2083 //UVD_MC_DJPEG_RD_SPACE 2084 #define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE__SHIFT 0x0 2085 #define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE_MASK 0x0003FFFFL 2086 //UVD_MC_DJPEG_WR_SPACE 2087 #define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE__SHIFT 0x0 2088 #define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE_MASK 0x0003FFFFL 2089 //UVD_MC_EJPEG_RD_SPACE 2090 #define UVD_MC_EJPEG_RD_SPACE__EJPEG_RD_SPACE__SHIFT 0x0 2091 #define UVD_MC_EJPEG_RD_SPACE__EJPEG_RD_SPACE_MASK 0x0003FFFFL 2092 //UVD_MC_EJPEG_WR_SPACE 2093 #define UVD_MC_EJPEG_WR_SPACE__EJPEG_WR_SPACE__SHIFT 0x0 2094 #define UVD_MC_EJPEG_WR_SPACE__EJPEG_WR_SPACE_MASK 0x0003FFFFL 2095 //UVD_DPG_LMA_CTL 2096 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 2097 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 2098 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 2099 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 2100 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 2101 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 2102 #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 2103 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 2104 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 2105 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 2106 //UVD_DPG_LMA_DATA 2107 #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 2108 #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 2109 //UVD_DPG_LMA_MASK 2110 #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 2111 #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 2112 //UVD_DPG_PAUSE 2113 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 2114 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 2115 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 2116 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 2117 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 2118 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 2119 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 2120 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 2121 //UVD_SCRATCH1 2122 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 2123 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 2124 //UVD_SCRATCH2 2125 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 2126 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 2127 //UVD_SCRATCH3 2128 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 2129 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 2130 //UVD_SCRATCH4 2131 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 2132 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 2133 //UVD_SCRATCH5 2134 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 2135 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 2136 //UVD_SCRATCH6 2137 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 2138 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 2139 //UVD_SCRATCH7 2140 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 2141 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 2142 //UVD_SCRATCH8 2143 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 2144 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 2145 //UVD_SCRATCH9 2146 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 2147 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 2148 //UVD_SCRATCH10 2149 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 2150 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 2151 //UVD_SCRATCH11 2152 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 2153 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 2154 //UVD_SCRATCH12 2155 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 2156 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 2157 //UVD_SCRATCH13 2158 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 2159 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 2160 //UVD_SCRATCH14 2161 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 2162 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 2163 //UVD_FREE_COUNTER_REG 2164 #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 2165 #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 2166 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 2167 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 2168 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 2169 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 2170 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 2171 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 2172 //UVD_DPG_VCPU_CACHE_OFFSET0 2173 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 2174 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 2175 //UVD_DPG_LMI_VCPU_CACHE_VMID 2176 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 2177 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 2178 //UVD_REG_FILTER_EN 2179 #define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN__SHIFT 0x0 2180 #define UVD_REG_FILTER_EN__MMSCH_HI_PRIV__SHIFT 0x1 2181 #define UVD_REG_FILTER_EN__VIDEO_PRIV_EN__SHIFT 0x2 2182 #define UVD_REG_FILTER_EN__JPEG_PRIV_EN__SHIFT 0x3 2183 #define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN_MASK 0x00000001L 2184 #define UVD_REG_FILTER_EN__MMSCH_HI_PRIV_MASK 0x00000002L 2185 #define UVD_REG_FILTER_EN__VIDEO_PRIV_EN_MASK 0x00000004L 2186 #define UVD_REG_FILTER_EN__JPEG_PRIV_EN_MASK 0x00000008L 2187 //CC_UVD_VCPU_ERR_DETECT_BOT_LO 2188 #define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO__SHIFT 0xc 2189 #define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO_MASK 0xFFFFF000L 2190 //CC_UVD_VCPU_ERR_DETECT_BOT_HI 2191 #define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI__SHIFT 0x0 2192 #define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI_MASK 0x0000FFFFL 2193 //CC_UVD_VCPU_ERR_DETECT_TOP_LO 2194 #define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO__SHIFT 0xc 2195 #define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO_MASK 0xFFFFF000L 2196 //CC_UVD_VCPU_ERR_DETECT_TOP_HI 2197 #define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI__SHIFT 0x0 2198 #define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI_MASK 0x0000FFFFL 2199 //CC_UVD_VCPU_ERR 2200 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS__SHIFT 0x0 2201 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR__SHIFT 0x1 2202 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN__SHIFT 0x2 2203 #define CC_UVD_VCPU_ERR__RESET_ON_FAULT__SHIFT 0x4 2204 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS_MASK 0x00000001L 2205 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR_MASK 0x00000002L 2206 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN_MASK 0x00000004L 2207 #define CC_UVD_VCPU_ERR__RESET_ON_FAULT_MASK 0x00000010L 2208 //CC_UVD_VCPU_ERR_INST_ADDR_LO 2209 #define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO__SHIFT 0x0 2210 #define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO_MASK 0xFFFFFFFFL 2211 //CC_UVD_VCPU_ERR_INST_ADDR_HI 2212 #define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI__SHIFT 0x0 2213 #define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI_MASK 0x0000FFFFL 2214 //UVD_PF_STATUS 2215 #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 2216 #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 2217 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 2218 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 2219 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 2220 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 2221 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 2222 #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 2223 #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 2224 #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 2225 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 2226 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 2227 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 2228 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 2229 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 2230 #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 2231 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 2232 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 2233 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 2234 #define UVD_PF_STATUS__JPEG2_PF_OCCURED__SHIFT 0x13 2235 #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED__SHIFT 0x14 2236 #define UVD_PF_STATUS__JPEG2_PF_CLEAR__SHIFT 0x15 2237 #define UVD_PF_STATUS__ENCODER5_PF_OCCURED__SHIFT 0x16 2238 #define UVD_PF_STATUS__ENCODER5_PF_CLEAR__SHIFT 0x17 2239 #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 2240 #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 2241 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 2242 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 2243 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 2244 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 2245 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 2246 #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 2247 #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 2248 #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 2249 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 2250 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 2251 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 2252 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 2253 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 2254 #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 2255 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 2256 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 2257 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 2258 #define UVD_PF_STATUS__JPEG2_PF_OCCURED_MASK 0x00080000L 2259 #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED_MASK 0x00100000L 2260 #define UVD_PF_STATUS__JPEG2_PF_CLEAR_MASK 0x00200000L 2261 #define UVD_PF_STATUS__ENCODER5_PF_OCCURED_MASK 0x00400000L 2262 #define UVD_PF_STATUS__ENCODER5_PF_CLEAR_MASK 0x00800000L 2263 //UVD_FW_VERSION 2264 #define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 2265 #define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL 2266 //UVD_DPG_CLK_EN_VCPU_REPORT 2267 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 2268 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 2269 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 2270 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 2271 //UVD_SECURITY_REG_VIO_REPORT 2272 #define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO__SHIFT 0x0 2273 #define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO__SHIFT 0x1 2274 #define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO__SHIFT 0x2 2275 #define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO__SHIFT 0x3 2276 #define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO__SHIFT 0x4 2277 #define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO__SHIFT 0x5 2278 #define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO_MASK 0x00000001L 2279 #define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO_MASK 0x00000002L 2280 #define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO_MASK 0x00000004L 2281 #define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO_MASK 0x00000008L 2282 #define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO_MASK 0x00000010L 2283 #define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO_MASK 0x00000020L 2284 //UVD_LMI_MMSCH_NC_SPACE 2285 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE__SHIFT 0x0 2286 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE__SHIFT 0x3 2287 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE__SHIFT 0x6 2288 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE__SHIFT 0x9 2289 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE__SHIFT 0xc 2290 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE__SHIFT 0xf 2291 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE__SHIFT 0x12 2292 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE__SHIFT 0x15 2293 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE_MASK 0x00000007L 2294 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE_MASK 0x00000038L 2295 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE_MASK 0x000001C0L 2296 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE_MASK 0x00000E00L 2297 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE_MASK 0x00007000L 2298 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE_MASK 0x00038000L 2299 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE_MASK 0x001C0000L 2300 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE_MASK 0x00E00000L 2301 //UVD_LMI_ATOMIC_SPACE 2302 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE__SHIFT 0x0 2303 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE__SHIFT 0x3 2304 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE__SHIFT 0x6 2305 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE__SHIFT 0x9 2306 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE_MASK 0x00000007L 2307 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE_MASK 0x00000038L 2308 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE_MASK 0x000001C0L 2309 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE_MASK 0x00000E00L 2310 //UVD_GFX10_ADDR_CONFIG 2311 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 2312 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 2313 #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 2314 #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 2315 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 2316 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 2317 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 2318 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 2319 #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 2320 #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 2321 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 2322 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 2323 //UVD_GPCNT2_CNTL 2324 #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 2325 #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 2326 #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 2327 #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 2328 #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 2329 #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 2330 //UVD_GPCNT2_TARGET_LOWER 2331 #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 2332 #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 2333 //UVD_GPCNT2_STATUS_LOWER 2334 #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 2335 #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 2336 //UVD_GPCNT2_TARGET_UPPER 2337 #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 2338 #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 2339 //UVD_GPCNT2_STATUS_UPPER 2340 #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 2341 #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 2342 //UVD_GPCNT3_CNTL 2343 #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 2344 #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 2345 #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 2346 #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 2347 #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 2348 #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 2349 #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 2350 #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 2351 #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 2352 #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 2353 //UVD_GPCNT3_TARGET_LOWER 2354 #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 2355 #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 2356 //UVD_GPCNT3_STATUS_LOWER 2357 #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 2358 #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 2359 //UVD_GPCNT3_TARGET_UPPER 2360 #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 2361 #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 2362 //UVD_GPCNT3_STATUS_UPPER 2363 #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 2364 #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 2365 //UVD_VCLK_DS_CNTL 2366 #define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 2367 #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 2368 #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 2369 #define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L 2370 #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L 2371 #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 2372 //UVD_DCLK_DS_CNTL 2373 #define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 2374 #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 2375 #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 2376 #define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L 2377 #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L 2378 #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 2379 //UVD_TSC_LOWER 2380 #define UVD_TSC_LOWER__COUNT__SHIFT 0x0 2381 #define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL 2382 //UVD_TSC_UPPER 2383 #define UVD_TSC_UPPER__COUNT__SHIFT 0x0 2384 #define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL 2385 //VCN_FEATURES 2386 #define VCN_FEATURES__HAS_VIDEO_DEC__SHIFT 0x0 2387 #define VCN_FEATURES__HAS_VIDEO_ENC__SHIFT 0x1 2388 #define VCN_FEATURES__HAS_MJPEG_DEC__SHIFT 0x2 2389 #define VCN_FEATURES__HAS_MJPEG_ENC__SHIFT 0x3 2390 #define VCN_FEATURES__HAS_VIDEO_VIRT__SHIFT 0x4 2391 #define VCN_FEATURES__HAS_H264_LEGACY_DEC__SHIFT 0x5 2392 #define VCN_FEATURES__HAS_UDEC_DEC__SHIFT 0x6 2393 #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC__SHIFT 0x7 2394 #define VCN_FEATURES__HAS_SCLR_DEC__SHIFT 0x8 2395 #define VCN_FEATURES__HAS_VP9_DEC__SHIFT 0x9 2396 #define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa 2397 #define VCN_FEATURES__HAS_EFC_ENC__SHIFT 0xb 2398 #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC__SHIFT 0xc 2399 #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC__SHIFT 0xd 2400 #define VCN_FEATURES__INSTANCE_ID__SHIFT 0x1c 2401 #define VCN_FEATURES__HAS_VIDEO_DEC_MASK 0x00000001L 2402 #define VCN_FEATURES__HAS_VIDEO_ENC_MASK 0x00000002L 2403 #define VCN_FEATURES__HAS_MJPEG_DEC_MASK 0x00000004L 2404 #define VCN_FEATURES__HAS_MJPEG_ENC_MASK 0x00000008L 2405 #define VCN_FEATURES__HAS_VIDEO_VIRT_MASK 0x00000010L 2406 #define VCN_FEATURES__HAS_H264_LEGACY_DEC_MASK 0x00000020L 2407 #define VCN_FEATURES__HAS_UDEC_DEC_MASK 0x00000040L 2408 #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC_MASK 0x00000080L 2409 #define VCN_FEATURES__HAS_SCLR_DEC_MASK 0x00000100L 2410 #define VCN_FEATURES__HAS_VP9_DEC_MASK 0x00000200L 2411 #define VCN_FEATURES__HAS_AV1_DEC_MASK 0x00000400L 2412 #define VCN_FEATURES__HAS_EFC_ENC_MASK 0x00000800L 2413 #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC_MASK 0x00001000L 2414 #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC_MASK 0x00002000L 2415 #define VCN_FEATURES__INSTANCE_ID_MASK 0xF0000000L 2416 //UVD_GPUIOV_STATUS 2417 #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE__SHIFT 0x0 2418 #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE_MASK 0x00000001L 2419 2420 2421 // addressBlock: uvd0_uvddec 2422 //UVD_STATUS 2423 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 2424 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 2425 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 2426 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 2427 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 2428 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 2429 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 2430 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 2431 //UVD_ENC_PIPE_BUSY 2432 #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 2433 #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 2434 #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 2435 #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 2436 #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 2437 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 2438 #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 2439 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 2440 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 2441 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 2442 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 2443 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 2444 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 2445 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 2446 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 2447 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 2448 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 2449 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 2450 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 2451 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 2452 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 2453 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 2454 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 2455 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 2456 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 2457 #define UVD_ENC_PIPE_BUSY__SAOE_BUSY__SHIFT 0x1f 2458 #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 2459 #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 2460 #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 2461 #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 2462 #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 2463 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 2464 #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 2465 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 2466 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 2467 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 2468 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 2469 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 2470 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 2471 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 2472 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 2473 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 2474 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 2475 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 2476 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 2477 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 2478 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 2479 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 2480 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 2481 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 2482 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 2483 #define UVD_ENC_PIPE_BUSY__SAOE_BUSY_MASK 0x80000000L 2484 //UVD_FW_POWER_STATUS 2485 #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 2486 #define UVD_FW_POWER_STATUS__UVDC_PWR_OFF__SHIFT 0x1 2487 #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 2488 #define UVD_FW_POWER_STATUS__UVDIRL_PWR_OFF__SHIFT 0x3 2489 #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x4 2490 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x5 2491 #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x6 2492 #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF__SHIFT 0x7 2493 #define UVD_FW_POWER_STATUS__UVDATD_PWR_OFF__SHIFT 0x8 2494 #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF__SHIFT 0x9 2495 #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF__SHIFT 0xa 2496 #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L 2497 #define UVD_FW_POWER_STATUS__UVDC_PWR_OFF_MASK 0x00000002L 2498 #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L 2499 #define UVD_FW_POWER_STATUS__UVDIRL_PWR_OFF_MASK 0x00000008L 2500 #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000010L 2501 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000020L 2502 #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000040L 2503 #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF_MASK 0x00000080L 2504 #define UVD_FW_POWER_STATUS__UVDATD_PWR_OFF_MASK 0x00000100L 2505 #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF_MASK 0x00000200L 2506 #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF_MASK 0x00000400L 2507 //UVD_CNTL 2508 #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 2509 #define UVD_CNTL__SUVD_EN__SHIFT 0x13 2510 #define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c 2511 #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f 2512 #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 2513 #define UVD_CNTL__SUVD_EN_MASK 0x00080000L 2514 #define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L 2515 #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L 2516 //UVD_SOFT_RESET 2517 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 2518 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 2519 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 2520 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 2521 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 2522 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 2523 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 2524 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 2525 #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 2526 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 2527 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 2528 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 2529 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 2530 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 2531 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 2532 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 2533 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 2534 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 2535 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 2536 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 2537 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 2538 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 2539 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 2540 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 2541 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 2542 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 2543 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 2544 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 2545 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 2546 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 2547 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 2548 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 2549 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 2550 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 2551 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 2552 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 2553 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 2554 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 2555 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 2556 #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 2557 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 2558 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 2559 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 2560 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 2561 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 2562 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 2563 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 2564 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 2565 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 2566 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 2567 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 2568 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 2569 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 2570 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 2571 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 2572 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 2573 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 2574 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 2575 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 2576 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 2577 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 2578 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 2579 //UVD_SOFT_RESET2 2580 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 2581 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 2582 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 2583 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 2584 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 2585 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 2586 //UVD_MMSCH_SOFT_RESET 2587 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 2588 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 2589 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 2590 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 2591 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 2592 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 2593 //UVD_WIG_CTRL 2594 #define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 2595 #define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 2596 #define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 2597 #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 2598 #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 2599 #define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L 2600 #define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L 2601 #define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L 2602 #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L 2603 #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L 2604 //UVD_CGC_GATE 2605 #define UVD_CGC_GATE__SYS__SHIFT 0x0 2606 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 2607 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 2608 #define UVD_CGC_GATE__REGS__SHIFT 0x3 2609 #define UVD_CGC_GATE__RBC__SHIFT 0x4 2610 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 2611 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 2612 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 2613 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 2614 #define UVD_CGC_GATE__MPC__SHIFT 0x9 2615 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 2616 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 2617 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 2618 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 2619 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 2620 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 2621 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 2622 #define UVD_CGC_GATE__WCB__SHIFT 0x11 2623 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 2624 #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 2625 #define UVD_CGC_GATE__SYS_MASK 0x00000001L 2626 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 2627 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 2628 #define UVD_CGC_GATE__REGS_MASK 0x00000008L 2629 #define UVD_CGC_GATE__RBC_MASK 0x00000010L 2630 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 2631 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 2632 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 2633 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 2634 #define UVD_CGC_GATE__MPC_MASK 0x00000200L 2635 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 2636 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 2637 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 2638 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 2639 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 2640 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 2641 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 2642 #define UVD_CGC_GATE__WCB_MASK 0x00020000L 2643 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 2644 #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 2645 //UVD_CGC_STATUS 2646 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 2647 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 2648 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 2649 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 2650 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 2651 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 2652 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 2653 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 2654 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 2655 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 2656 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 2657 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 2658 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 2659 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 2660 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 2661 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 2662 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 2663 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 2664 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 2665 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 2666 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 2667 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 2668 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 2669 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 2670 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 2671 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 2672 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 2673 #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 2674 #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 2675 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 2676 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 2677 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 2678 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 2679 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 2680 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 2681 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 2682 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 2683 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 2684 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 2685 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 2686 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 2687 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 2688 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 2689 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 2690 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 2691 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 2692 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 2693 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 2694 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 2695 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 2696 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 2697 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 2698 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 2699 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 2700 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 2701 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 2702 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 2703 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 2704 #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 2705 #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 2706 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 2707 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 2708 //UVD_CGC_CTRL 2709 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 2710 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 2711 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 2712 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 2713 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 2714 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 2715 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 2716 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 2717 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 2718 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 2719 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 2720 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 2721 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 2722 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 2723 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 2724 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 2725 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 2726 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 2727 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 2728 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 2729 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 2730 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 2731 #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 2732 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 2733 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 2734 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 2735 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 2736 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 2737 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 2738 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 2739 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 2740 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 2741 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 2742 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 2743 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 2744 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 2745 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 2746 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 2747 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 2748 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 2749 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 2750 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 2751 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 2752 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 2753 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 2754 #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 2755 //UVD_CGC_UDEC_STATUS 2756 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 2757 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 2758 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 2759 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 2760 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 2761 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 2762 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 2763 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 2764 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 2765 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 2766 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 2767 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 2768 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 2769 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 2770 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 2771 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 2772 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 2773 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 2774 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 2775 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 2776 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 2777 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 2778 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 2779 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 2780 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 2781 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 2782 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 2783 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 2784 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 2785 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 2786 //UVD_SUVD_CGC_GATE 2787 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 2788 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 2789 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 2790 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 2791 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 2792 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 2793 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 2794 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 2795 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 2796 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 2797 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 2798 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 2799 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 2800 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 2801 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 2802 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 2803 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 2804 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 2805 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 2806 #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 2807 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 2808 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 2809 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 2810 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 2811 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 2812 #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 2813 #define UVD_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 2814 #define UVD_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 2815 #define UVD_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 2816 #define UVD_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 2817 #define UVD_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 2818 #define UVD_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 2819 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 2820 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 2821 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 2822 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 2823 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 2824 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 2825 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 2826 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 2827 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 2828 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 2829 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 2830 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 2831 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 2832 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 2833 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 2834 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 2835 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 2836 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 2837 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 2838 #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 2839 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 2840 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 2841 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 2842 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 2843 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 2844 #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 2845 #define UVD_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 2846 #define UVD_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 2847 #define UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 2848 #define UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 2849 #define UVD_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 2850 #define UVD_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 2851 //UVD_SUVD_CGC_STATUS 2852 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 2853 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 2854 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 2855 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 2856 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 2857 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 2858 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 2859 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 2860 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 2861 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 2862 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 2863 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 2864 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 2865 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 2866 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 2867 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 2868 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 2869 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 2870 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 2871 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 2872 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 2873 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 2874 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 2875 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 2876 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 2877 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 2878 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 2879 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 2880 #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 2881 #define UVD_SUVD_CGC_STATUS__SAOE_DCLK__SHIFT 0x1d 2882 #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK__SHIFT 0x1e 2883 #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK__SHIFT 0x1f 2884 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 2885 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 2886 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 2887 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 2888 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 2889 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 2890 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 2891 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 2892 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 2893 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 2894 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 2895 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 2896 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 2897 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 2898 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 2899 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 2900 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 2901 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 2902 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 2903 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 2904 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 2905 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 2906 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 2907 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 2908 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 2909 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 2910 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 2911 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 2912 #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 2913 #define UVD_SUVD_CGC_STATUS__SAOE_DCLK_MASK 0x20000000L 2914 #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK_MASK 0x40000000L 2915 #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK_MASK 0x80000000L 2916 //UVD_SUVD_CGC_CTRL 2917 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2918 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2919 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2920 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2921 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2922 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2923 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2924 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2925 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2926 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2927 #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2928 #define UVD_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2929 #define UVD_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2930 #define UVD_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2931 #define UVD_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2932 #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2933 #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2934 #define UVD_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2935 #define UVD_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2936 #define UVD_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2937 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2938 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2939 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2940 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2941 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2942 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2943 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2944 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2945 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2946 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2947 #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2948 #define UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2949 #define UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2950 #define UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2951 #define UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2952 #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2953 #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2954 #define UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2955 #define UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2956 #define UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2957 //UVD_GPCOM_VCPU_CMD 2958 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 2959 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 2960 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 2961 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 2962 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 2963 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 2964 //UVD_GPCOM_VCPU_DATA0 2965 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 2966 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 2967 //UVD_GPCOM_VCPU_DATA1 2968 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 2969 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 2970 //UVD_GPCOM_SYS_CMD 2971 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2972 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2973 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2974 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2975 #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2976 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2977 //UVD_GPCOM_SYS_DATA0 2978 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2979 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2980 //UVD_GPCOM_SYS_DATA1 2981 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2982 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2983 //UVD_VCPU_INT_EN 2984 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2985 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2986 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2987 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2988 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2989 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2990 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2991 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2992 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2993 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2994 #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2995 #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2996 #define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf 2997 #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2998 #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2999 #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 3000 #define UVD_VCPU_INT_EN__CNN_3D_BLOCK_DONE_INT_EN__SHIFT 0x13 3001 #define UVD_VCPU_INT_EN__CNN_MIF_DMA_DONE_INT_EN__SHIFT 0x15 3002 #define UVD_VCPU_INT_EN__CNN_FEATURE_THRESHOLD_DONE_INT_EN__SHIFT 0x16 3003 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 3004 #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 3005 #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 3006 #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 3007 #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 3008 #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 3009 #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 3010 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 3011 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 3012 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 3013 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 3014 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 3015 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 3016 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 3017 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 3018 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 3019 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 3020 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 3021 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 3022 #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 3023 #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 3024 #define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L 3025 #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 3026 #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 3027 #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 3028 #define UVD_VCPU_INT_EN__CNN_3D_BLOCK_DONE_INT_EN_MASK 0x00080000L 3029 #define UVD_VCPU_INT_EN__CNN_MIF_DMA_DONE_INT_EN_MASK 0x00200000L 3030 #define UVD_VCPU_INT_EN__CNN_FEATURE_THRESHOLD_DONE_INT_EN_MASK 0x00400000L 3031 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3032 #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 3033 #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 3034 #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 3035 #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3036 #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3037 #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3038 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 3039 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 3040 //UVD_VCPU_INT_STATUS 3041 #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 3042 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 3043 #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 3044 #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 3045 #define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 3046 #define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 3047 #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 3048 #define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 3049 #define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 3050 #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa 3051 #define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb 3052 #define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc 3053 #define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf 3054 #define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 3055 #define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 3056 #define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 3057 #define UVD_VCPU_INT_STATUS__CNN_3D_BLOCK_DONE_INT__SHIFT 0x13 3058 #define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 3059 #define UVD_VCPU_INT_STATUS__CNN_MIF_DMA_DONE_INT__SHIFT 0x15 3060 #define UVD_VCPU_INT_STATUS__CNN_FEATURE_THRESHOLD_DONE_INT__SHIFT 0x16 3061 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3062 #define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 3063 #define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 3064 #define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a 3065 #define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3066 #define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3067 #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3068 #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e 3069 #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f 3070 #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3071 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3072 #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3073 #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L 3074 #define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L 3075 #define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L 3076 #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3077 #define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L 3078 #define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L 3079 #define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L 3080 #define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L 3081 #define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L 3082 #define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L 3083 #define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L 3084 #define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L 3085 #define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L 3086 #define UVD_VCPU_INT_STATUS__CNN_3D_BLOCK_DONE_INT_MASK 0x00080000L 3087 #define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L 3088 #define UVD_VCPU_INT_STATUS__CNN_MIF_DMA_DONE_INT_MASK 0x00200000L 3089 #define UVD_VCPU_INT_STATUS__CNN_FEATURE_THRESHOLD_DONE_INT_MASK 0x00400000L 3090 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3091 #define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L 3092 #define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L 3093 #define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L 3094 #define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3095 #define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3096 #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3097 #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L 3098 #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L 3099 //UVD_VCPU_INT_ACK 3100 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3101 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3102 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 3103 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 3104 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 3105 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 3106 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 3107 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 3108 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 3109 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 3110 #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 3111 #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 3112 #define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf 3113 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 3114 #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 3115 #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 3116 #define UVD_VCPU_INT_ACK__CNN_3D_BLOCK_DONE_INT_ACK__SHIFT 0x13 3117 #define UVD_VCPU_INT_ACK__CNN_MIF_DMA_DONE_INT_ACK__SHIFT 0x15 3118 #define UVD_VCPU_INT_ACK__CNN_FEATURE_THRESHOLD_DONE_INT_ACK__SHIFT 0x16 3119 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 3120 #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 3121 #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 3122 #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 3123 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 3124 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 3125 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 3126 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 3127 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 3128 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 3129 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 3130 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 3131 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 3132 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 3133 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 3134 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 3135 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 3136 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 3137 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 3138 #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 3139 #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 3140 #define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L 3141 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 3142 #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 3143 #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 3144 #define UVD_VCPU_INT_ACK__CNN_3D_BLOCK_DONE_INT_ACK_MASK 0x00080000L 3145 #define UVD_VCPU_INT_ACK__CNN_MIF_DMA_DONE_INT_ACK_MASK 0x00200000L 3146 #define UVD_VCPU_INT_ACK__CNN_FEATURE_THRESHOLD_DONE_INT_ACK_MASK 0x00400000L 3147 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 3148 #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 3149 #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 3150 #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 3151 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 3152 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 3153 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 3154 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 3155 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 3156 //UVD_VCPU_INT_ROUTE 3157 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 3158 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 3159 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 3160 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 3161 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 3162 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 3163 //UVD_DRV_FW_MSG 3164 #define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 3165 #define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL 3166 //UVD_FW_DRV_MSG_ACK 3167 #define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 3168 #define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L 3169 //UVD_SUVD_INT_EN 3170 #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 3171 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 3172 #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 3173 #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb 3174 #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc 3175 #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 3176 #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 3177 #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 3178 #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 3179 #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d 3180 #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN__SHIFT 0x1e 3181 #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL 3182 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L 3183 #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L 3184 #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L 3185 #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L 3186 #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L 3187 #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L 3188 #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L 3189 #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L 3190 #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L 3191 #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN_MASK 0x40000000L 3192 //UVD_SUVD_INT_STATUS 3193 #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 3194 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 3195 #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 3196 #define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb 3197 #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc 3198 #define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 3199 #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 3200 #define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 3201 #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 3202 #define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d 3203 #define UVD_SUVD_INT_STATUS__FBC_ERR_INT__SHIFT 0x1e 3204 #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL 3205 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L 3206 #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L 3207 #define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L 3208 #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L 3209 #define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L 3210 #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L 3211 #define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L 3212 #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L 3213 #define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L 3214 #define UVD_SUVD_INT_STATUS__FBC_ERR_INT_MASK 0x40000000L 3215 //UVD_SUVD_INT_ACK 3216 #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 3217 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 3218 #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 3219 #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb 3220 #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc 3221 #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 3222 #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 3223 #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 3224 #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 3225 #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d 3226 #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK__SHIFT 0x1e 3227 #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL 3228 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L 3229 #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L 3230 #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L 3231 #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L 3232 #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L 3233 #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L 3234 #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L 3235 #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L 3236 #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L 3237 #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK_MASK 0x40000000L 3238 //UVD_ENC_VCPU_INT_EN 3239 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 3240 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 3241 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 3242 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 3243 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 3244 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 3245 //UVD_ENC_VCPU_INT_STATUS 3246 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 3247 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 3248 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 3249 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L 3250 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L 3251 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L 3252 //UVD_ENC_VCPU_INT_ACK 3253 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 3254 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 3255 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 3256 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 3257 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 3258 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 3259 //UVD_MASTINT_EN 3260 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 3261 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 3262 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 3263 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 3264 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 3265 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 3266 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 3267 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 3268 //UVD_SYS_INT_EN 3269 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 3270 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 3271 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 3272 #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 3273 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 3274 #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 3275 #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 3276 #define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf 3277 #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 3278 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 3279 #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 3280 #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 3281 #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 3282 #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 3283 #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 3284 #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 3285 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 3286 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 3287 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 3288 #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 3289 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 3290 #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 3291 #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 3292 #define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L 3293 #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 3294 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3295 #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 3296 #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 3297 #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3298 #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3299 #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3300 #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 3301 //UVD_SYS_INT_STATUS 3302 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 3303 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 3304 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 3305 #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 3306 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 3307 #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 3308 #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 3309 #define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf 3310 #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 3311 #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 3312 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3313 #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 3314 #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 3315 #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3316 #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3317 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3318 #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 3319 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3320 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3321 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3322 #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 3323 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3324 #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 3325 #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 3326 #define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L 3327 #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 3328 #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 3329 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3330 #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 3331 #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 3332 #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3333 #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3334 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3335 #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 3336 //UVD_SYS_INT_ACK 3337 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3338 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3339 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 3340 #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 3341 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 3342 #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 3343 #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 3344 #define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf 3345 #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 3346 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 3347 #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 3348 #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 3349 #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 3350 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 3351 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 3352 #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 3353 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 3354 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 3355 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 3356 #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 3357 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 3358 #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 3359 #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 3360 #define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L 3361 #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 3362 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 3363 #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 3364 #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 3365 #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 3366 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 3367 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 3368 #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 3369 //UVD_JOB_DONE 3370 #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 3371 #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 3372 //UVD_CBUF_ID 3373 #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 3374 #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 3375 //UVD_CONTEXT_ID 3376 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 3377 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 3378 //UVD_CONTEXT_ID2 3379 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 3380 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 3381 //UVD_NO_OP 3382 #define UVD_NO_OP__NO_OP__SHIFT 0x0 3383 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 3384 //UVD_RB_BASE_LO 3385 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3386 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3387 //UVD_RB_BASE_HI 3388 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3389 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3390 //UVD_RB_SIZE 3391 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 3392 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3393 //UVD_RB_RPTR 3394 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 3395 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3396 //UVD_RB_WPTR 3397 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 3398 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3399 //UVD_RB_BASE_LO2 3400 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 3401 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 3402 //UVD_RB_BASE_HI2 3403 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 3404 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 3405 //UVD_RB_SIZE2 3406 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 3407 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 3408 //UVD_RB_RPTR2 3409 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 3410 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 3411 //UVD_RB_WPTR2 3412 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 3413 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 3414 //UVD_RB_BASE_LO3 3415 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 3416 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 3417 //UVD_RB_BASE_HI3 3418 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 3419 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 3420 //UVD_RB_SIZE3 3421 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 3422 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 3423 //UVD_RB_RPTR3 3424 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 3425 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 3426 //UVD_RB_WPTR3 3427 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 3428 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 3429 //UVD_RB_BASE_LO4 3430 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 3431 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 3432 //UVD_RB_BASE_HI4 3433 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 3434 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 3435 //UVD_RB_SIZE4 3436 #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 3437 #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 3438 //UVD_RB_RPTR4 3439 #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 3440 #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 3441 //UVD_RB_WPTR4 3442 #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 3443 #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 3444 //UVD_OUT_RB_BASE_LO 3445 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3446 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3447 //UVD_OUT_RB_BASE_HI 3448 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3449 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3450 //UVD_OUT_RB_SIZE 3451 #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 3452 #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3453 //UVD_OUT_RB_RPTR 3454 #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 3455 #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3456 //UVD_OUT_RB_WPTR 3457 #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 3458 #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3459 //UVD_IOV_ACTIVE_FCN_ID 3460 #define UVD_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 3461 #define UVD_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 3462 #define UVD_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL 3463 #define UVD_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 3464 //UVD_IOV_MAILBOX 3465 #define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 3466 #define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL 3467 //UVD_IOV_MAILBOX_RESP 3468 #define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 3469 #define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 3470 //UVD_RB_ARB_CTRL 3471 #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 3472 #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 3473 #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 3474 #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 3475 #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 3476 #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 3477 #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 3478 #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 3479 #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 3480 #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 3481 #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 3482 #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 3483 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 3484 #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 3485 #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 3486 #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 3487 #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 3488 #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 3489 //UVD_CTX_INDEX 3490 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 3491 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 3492 //UVD_CTX_DATA 3493 #define UVD_CTX_DATA__DATA__SHIFT 0x0 3494 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 3495 //UVD_CXW_WR 3496 #define UVD_CXW_WR__DAT__SHIFT 0x0 3497 #define UVD_CXW_WR__STAT__SHIFT 0x1f 3498 #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 3499 #define UVD_CXW_WR__STAT_MASK 0x80000000L 3500 //UVD_CXW_WR_INT_ID 3501 #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 3502 #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 3503 //UVD_CXW_WR_INT_CTX_ID 3504 #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 3505 #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 3506 //UVD_CXW_INT_ID 3507 #define UVD_CXW_INT_ID__ID__SHIFT 0x0 3508 #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 3509 //UVD_MPEG2_ERROR 3510 #define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 3511 #define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL 3512 //UVD_TOP_CTRL 3513 #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 3514 #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 3515 #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 3516 #define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L 3517 //UVD_YBASE 3518 #define UVD_YBASE__DUM__SHIFT 0x0 3519 #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 3520 //UVD_UVBASE 3521 #define UVD_UVBASE__DUM__SHIFT 0x0 3522 #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 3523 //UVD_PITCH 3524 #define UVD_PITCH__DUM__SHIFT 0x0 3525 #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 3526 //UVD_WIDTH 3527 #define UVD_WIDTH__DUM__SHIFT 0x0 3528 #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 3529 //UVD_HEIGHT 3530 #define UVD_HEIGHT__DUM__SHIFT 0x0 3531 #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 3532 //UVD_PICCOUNT 3533 #define UVD_PICCOUNT__DUM__SHIFT 0x0 3534 #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 3535 //UVD_MPRD_INITIAL_XY 3536 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 3537 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 3538 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL 3539 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L 3540 //UVD_MPEG2_CTRL 3541 #define UVD_MPEG2_CTRL__EN__SHIFT 0x0 3542 #define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 3543 #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 3544 #define UVD_MPEG2_CTRL__EN_MASK 0x00000001L 3545 #define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L 3546 #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L 3547 //UVD_MB_CTL_BUF_BASE 3548 #define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 3549 #define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3550 //UVD_PIC_CTL_BUF_BASE 3551 #define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 3552 #define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3553 //UVD_DXVA_BUF_SIZE 3554 #define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 3555 #define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 3556 #define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL 3557 #define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L 3558 //UVD_SCRATCH_NP 3559 #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 3560 #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 3561 //UVD_CLK_SWT_HANDSHAKE 3562 #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 3563 #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 3564 #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L 3565 #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L 3566 //UVD_VERSION 3567 #define UVD_VERSION__VARIANT_TYPE__SHIFT 0x0 3568 #define UVD_VERSION__MINOR_VERSION__SHIFT 0x8 3569 #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 3570 #define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c 3571 #define UVD_VERSION__VARIANT_TYPE_MASK 0x000000FFL 3572 #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FF00L 3573 #define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 3574 #define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L 3575 //UVD_GP_SCRATCH0 3576 #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 3577 #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 3578 //UVD_GP_SCRATCH1 3579 #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 3580 #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 3581 //UVD_GP_SCRATCH2 3582 #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 3583 #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 3584 //UVD_GP_SCRATCH3 3585 #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 3586 #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 3587 //UVD_GP_SCRATCH4 3588 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 3589 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 3590 //UVD_GP_SCRATCH5 3591 #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 3592 #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 3593 //UVD_GP_SCRATCH6 3594 #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 3595 #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 3596 //UVD_GP_SCRATCH7 3597 #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 3598 #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 3599 //UVD_GP_SCRATCH8 3600 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 3601 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 3602 //UVD_GP_SCRATCH9 3603 #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 3604 #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 3605 //UVD_GP_SCRATCH10 3606 #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 3607 #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 3608 //UVD_GP_SCRATCH11 3609 #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 3610 #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 3611 //UVD_GP_SCRATCH12 3612 #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 3613 #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 3614 //UVD_GP_SCRATCH13 3615 #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 3616 #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 3617 //UVD_GP_SCRATCH14 3618 #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 3619 #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 3620 //UVD_GP_SCRATCH15 3621 #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 3622 #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 3623 //UVD_GP_SCRATCH16 3624 #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 3625 #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 3626 //UVD_GP_SCRATCH17 3627 #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 3628 #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 3629 //UVD_GP_SCRATCH18 3630 #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 3631 #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 3632 //UVD_GP_SCRATCH19 3633 #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 3634 #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 3635 //UVD_GP_SCRATCH20 3636 #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 3637 #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 3638 //UVD_GP_SCRATCH21 3639 #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 3640 #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 3641 //UVD_GP_SCRATCH22 3642 #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 3643 #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 3644 //UVD_GP_SCRATCH23 3645 #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 3646 #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 3647 //UVD_AUDIO_RB_BASE_LO 3648 #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3649 #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3650 //UVD_AUDIO_RB_BASE_HI 3651 #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3652 #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3653 //UVD_AUDIO_RB_SIZE 3654 #define UVD_AUDIO_RB_SIZE__RB_SIZE__SHIFT 0x4 3655 #define UVD_AUDIO_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3656 //UVD_AUDIO_RB_RPTR 3657 #define UVD_AUDIO_RB_RPTR__RB_RPTR__SHIFT 0x4 3658 #define UVD_AUDIO_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3659 //UVD_AUDIO_RB_WPTR 3660 #define UVD_AUDIO_RB_WPTR__RB_WPTR__SHIFT 0x4 3661 #define UVD_AUDIO_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3662 //UVD_VCPU_INT_STATUS2 3663 #define UVD_VCPU_INT_STATUS2__SW_RB6_INT__SHIFT 0x0 3664 #define UVD_VCPU_INT_STATUS2__SW_RB6_INT_MASK 0x00000001L 3665 //UVD_VCPU_INT_ACK2 3666 #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK__SHIFT 0x0 3667 #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK_MASK 0x00000001L 3668 //UVD_VCPU_INT_EN2 3669 #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN__SHIFT 0x0 3670 #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN_MASK 0x00000001L 3671 //UVD_SUVD_CGC_STATUS2 3672 #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK__SHIFT 0x0 3673 #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK__SHIFT 0x1 3674 #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK__SHIFT 0x3 3675 #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK__SHIFT 0x4 3676 #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK__SHIFT 0x5 3677 #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK__SHIFT 0x6 3678 #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK__SHIFT 0x7 3679 #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK__SHIFT 0x8 3680 #define UVD_SUVD_CGC_STATUS2__FBC_PCLK__SHIFT 0x1c 3681 #define UVD_SUVD_CGC_STATUS2__FBC_CCLK__SHIFT 0x1d 3682 #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK_MASK 0x00000001L 3683 #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK_MASK 0x00000002L 3684 #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK_MASK 0x00000008L 3685 #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK_MASK 0x00000010L 3686 #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK_MASK 0x00000020L 3687 #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK_MASK 0x00000040L 3688 #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK_MASK 0x00000080L 3689 #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK_MASK 0x00000100L 3690 #define UVD_SUVD_CGC_STATUS2__FBC_PCLK_MASK 0x10000000L 3691 #define UVD_SUVD_CGC_STATUS2__FBC_CCLK_MASK 0x20000000L 3692 //UVD_SUVD_CGC_GATE2 3693 #define UVD_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 3694 #define UVD_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 3695 #define UVD_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 3696 #define UVD_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 3697 #define UVD_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 3698 #define UVD_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 3699 #define UVD_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 3700 #define UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 3701 #define UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 3702 #define UVD_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 3703 //UVD_SUVD_INT_STATUS2 3704 #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT__SHIFT 0x0 3705 #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT__SHIFT 0x5 3706 #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT__SHIFT 0x6 3707 #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT__SHIFT 0xb 3708 #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT_MASK 0x0000001FL 3709 #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT_MASK 0x00000020L 3710 #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT_MASK 0x000007C0L 3711 #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT_MASK 0x00000800L 3712 //UVD_SUVD_INT_EN2 3713 #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN__SHIFT 0x0 3714 #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN__SHIFT 0x5 3715 #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN__SHIFT 0x6 3716 #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN__SHIFT 0xb 3717 #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN_MASK 0x0000001FL 3718 #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN_MASK 0x00000020L 3719 #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN_MASK 0x000007C0L 3720 #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN_MASK 0x00000800L 3721 //UVD_SUVD_INT_ACK2 3722 #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK__SHIFT 0x0 3723 #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK__SHIFT 0x5 3724 #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK__SHIFT 0x6 3725 #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK__SHIFT 0xb 3726 #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK_MASK 0x0000001FL 3727 #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK_MASK 0x00000020L 3728 #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK_MASK 0x000007C0L 3729 #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK_MASK 0x00000800L 3730 3731 3732 // addressBlock: uvd0_ecpudec 3733 //UVD_VCPU_CACHE_OFFSET0 3734 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 3735 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 3736 //UVD_VCPU_CACHE_SIZE0 3737 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 3738 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 3739 //UVD_VCPU_CACHE_OFFSET1 3740 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 3741 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 3742 //UVD_VCPU_CACHE_SIZE1 3743 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 3744 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 3745 //UVD_VCPU_CACHE_OFFSET2 3746 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 3747 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 3748 //UVD_VCPU_CACHE_SIZE2 3749 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 3750 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 3751 //UVD_VCPU_CACHE_OFFSET3 3752 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 3753 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 3754 //UVD_VCPU_CACHE_SIZE3 3755 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 3756 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 3757 //UVD_VCPU_CACHE_OFFSET4 3758 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 3759 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 3760 //UVD_VCPU_CACHE_SIZE4 3761 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 3762 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 3763 //UVD_VCPU_CACHE_OFFSET5 3764 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 3765 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 3766 //UVD_VCPU_CACHE_SIZE5 3767 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 3768 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 3769 //UVD_VCPU_CACHE_OFFSET6 3770 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 3771 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 3772 //UVD_VCPU_CACHE_SIZE6 3773 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 3774 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 3775 //UVD_VCPU_CACHE_OFFSET7 3776 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 3777 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 3778 //UVD_VCPU_CACHE_SIZE7 3779 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 3780 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 3781 //UVD_VCPU_CACHE_OFFSET8 3782 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 3783 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 3784 //UVD_VCPU_CACHE_SIZE8 3785 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 3786 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 3787 //UVD_VCPU_NONCACHE_OFFSET0 3788 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 3789 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 3790 //UVD_VCPU_NONCACHE_SIZE0 3791 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 3792 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 3793 //UVD_VCPU_NONCACHE_OFFSET1 3794 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 3795 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 3796 //UVD_VCPU_NONCACHE_SIZE1 3797 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 3798 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 3799 //UVD_VCPU_CNTL 3800 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 3801 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 3802 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 3803 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 3804 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 3805 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 3806 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 3807 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 3808 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 3809 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 3810 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 3811 #define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 3812 #define UVD_VCPU_CNTL__RUNSTALL__SHIFT 0x1d 3813 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 3814 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 3815 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 3816 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 3817 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 3818 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 3819 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 3820 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 3821 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 3822 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 3823 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 3824 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 3825 #define UVD_VCPU_CNTL__RUNSTALL_MASK 0x20000000L 3826 //UVD_VCPU_PRID 3827 #define UVD_VCPU_PRID__PRID__SHIFT 0x0 3828 #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 3829 //UVD_VCPU_TRCE 3830 #define UVD_VCPU_TRCE__PC__SHIFT 0x0 3831 #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 3832 //UVD_VCPU_TRCE_RD 3833 #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 3834 #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 3835 //UVD_VCPU_IND_INDEX 3836 #define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 3837 #define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL 3838 //UVD_VCPU_IND_DATA 3839 #define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 3840 #define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL 3841 3842 3843 // addressBlock: uvd0_uvd_mpcdec 3844 //UVD_MP_SWAP_CNTL 3845 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 3846 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 3847 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 3848 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 3849 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 3850 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 3851 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 3852 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 3853 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 3854 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 3855 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 3856 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 3857 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 3858 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 3859 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 3860 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 3861 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 3862 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 3863 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 3864 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 3865 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 3866 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 3867 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 3868 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 3869 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 3870 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 3871 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 3872 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 3873 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 3874 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 3875 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 3876 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 3877 //UVD_MP_SWAP_CNTL2 3878 #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0 3879 #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L 3880 //UVD_MPC_LUMA_SRCH 3881 #define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 3882 #define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 3883 //UVD_MPC_LUMA_HIT 3884 #define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 3885 #define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 3886 //UVD_MPC_LUMA_HITPEND 3887 #define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 3888 #define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 3889 //UVD_MPC_CHROMA_SRCH 3890 #define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 3891 #define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 3892 //UVD_MPC_CHROMA_HIT 3893 #define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 3894 #define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 3895 //UVD_MPC_CHROMA_HITPEND 3896 #define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 3897 #define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 3898 //UVD_MPC_CNTL 3899 #define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0 3900 #define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT__SHIFT 0x1 3901 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 3902 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 3903 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 3904 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 3905 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 3906 #define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 3907 #define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L 3908 #define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT_MASK 0x00000002L 3909 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 3910 #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 3911 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 3912 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 3913 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 3914 #define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L 3915 //UVD_MPC_PITCH 3916 #define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 3917 #define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 3918 //UVD_MPC_SET_MUXA0 3919 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 3920 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 3921 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 3922 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 3923 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 3924 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 3925 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 3926 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 3927 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 3928 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 3929 //UVD_MPC_SET_MUXA1 3930 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 3931 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 3932 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 3933 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 3934 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 3935 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 3936 //UVD_MPC_SET_MUXB0 3937 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 3938 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 3939 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 3940 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 3941 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 3942 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 3943 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 3944 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 3945 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 3946 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 3947 //UVD_MPC_SET_MUXB1 3948 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 3949 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 3950 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 3951 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 3952 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 3953 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 3954 //UVD_MPC_SET_MUX 3955 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 3956 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 3957 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 3958 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 3959 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 3960 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 3961 //UVD_MPC_SET_ALU 3962 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 3963 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 3964 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 3965 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 3966 //UVD_MPC_PERF0 3967 #define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 3968 #define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 3969 //UVD_MPC_PERF1 3970 #define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 3971 #define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 3972 //UVD_MPC_IND_INDEX 3973 #define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0 3974 #define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL 3975 //UVD_MPC_IND_DATA 3976 #define UVD_MPC_IND_DATA__DATA__SHIFT 0x0 3977 #define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL 3978 3979 3980 // addressBlock: uvd0_uvd_rbcdec 3981 //UVD_RBC_IB_SIZE 3982 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 3983 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 3984 //UVD_RBC_IB_SIZE_UPDATE 3985 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 3986 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 3987 //UVD_RBC_RB_CNTL 3988 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 3989 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 3990 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 3991 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 3992 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 3993 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 3994 #define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d 3995 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 3996 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 3997 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 3998 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 3999 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 4000 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 4001 #define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L 4002 //UVD_RBC_RB_RPTR_ADDR 4003 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 4004 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 4005 //UVD_RBC_RB_RPTR 4006 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 4007 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 4008 //UVD_RBC_RB_WPTR 4009 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 4010 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 4011 //UVD_RBC_VCPU_ACCESS 4012 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 4013 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 4014 //UVD_FW_SEMAPHORE_CNTL 4015 #define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0 4016 #define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8 4017 #define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9 4018 #define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L 4019 #define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L 4020 #define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L 4021 //UVD_RBC_READ_REQ_URGENT_CNTL 4022 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 4023 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 4024 //UVD_RBC_RB_WPTR_CNTL 4025 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 4026 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 4027 //UVD_RBC_WPTR_STATUS 4028 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 4029 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 4030 //UVD_RBC_WPTR_POLL_CNTL 4031 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 4032 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4033 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 4034 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4035 //UVD_RBC_WPTR_POLL_ADDR 4036 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 4037 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 4038 //UVD_SEMA_CMD 4039 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 4040 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 4041 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 4042 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 4043 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 4044 #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 4045 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 4046 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L 4047 #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 4048 #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 4049 //UVD_SEMA_ADDR_LOW 4050 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 4051 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 4052 //UVD_SEMA_ADDR_HIGH 4053 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 4054 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 4055 //UVD_ENGINE_CNTL 4056 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 4057 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 4058 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 4059 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 4060 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 4061 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 4062 //UVD_SEMA_TIMEOUT_STATUS 4063 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 4064 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 4065 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 4066 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 4067 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 4068 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 4069 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 4070 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 4071 //UVD_SEMA_CNTL 4072 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 4073 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 4074 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 4075 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 4076 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 4077 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 4078 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 4079 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4080 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 4081 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 4082 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4083 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 4084 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 4085 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 4086 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4087 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 4088 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 4089 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4090 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 4091 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 4092 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 4093 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4094 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 4095 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 4096 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4097 //UVD_JOB_START 4098 #define UVD_JOB_START__JOB_START__SHIFT 0x0 4099 #define UVD_JOB_START__JOB_START_MASK 0x00000001L 4100 //UVD_RBC_BUF_STATUS 4101 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 4102 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 4103 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 4104 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 4105 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 4106 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 4107 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 4108 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 4109 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 4110 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 4111 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 4112 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 4113 //UVD_RBC_SWAP_CNTL 4114 #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 4115 #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 4116 #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 4117 #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 4118 #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 4119 #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 4120 #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 4121 #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 4122 4123 4124 // addressBlock: uvd0_lmi_adpdec 4125 //UVD_LMI_RE_64BIT_BAR_LOW 4126 #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4127 #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4128 //UVD_LMI_RE_64BIT_BAR_HIGH 4129 #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4130 #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4131 //UVD_LMI_IT_64BIT_BAR_LOW 4132 #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4133 #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4134 //UVD_LMI_IT_64BIT_BAR_HIGH 4135 #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4136 #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4137 //UVD_LMI_MP_64BIT_BAR_LOW 4138 #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4139 #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4140 //UVD_LMI_MP_64BIT_BAR_HIGH 4141 #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4142 #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4143 //UVD_LMI_CM_64BIT_BAR_LOW 4144 #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4145 #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4146 //UVD_LMI_CM_64BIT_BAR_HIGH 4147 #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4148 #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4149 //UVD_LMI_DB_64BIT_BAR_LOW 4150 #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4151 #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4152 //UVD_LMI_DB_64BIT_BAR_HIGH 4153 #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4154 #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4155 //UVD_LMI_DBW_64BIT_BAR_LOW 4156 #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4157 #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4158 //UVD_LMI_DBW_64BIT_BAR_HIGH 4159 #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4160 #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4161 //UVD_LMI_IDCT_64BIT_BAR_LOW 4162 #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4163 #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4164 //UVD_LMI_IDCT_64BIT_BAR_HIGH 4165 #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4166 #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4167 //UVD_LMI_MPRD_S0_64BIT_BAR_LOW 4168 #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4169 #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4170 //UVD_LMI_MPRD_S0_64BIT_BAR_HIGH 4171 #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4172 #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4173 //UVD_LMI_MPRD_S1_64BIT_BAR_LOW 4174 #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4175 #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4176 //UVD_LMI_MPRD_S1_64BIT_BAR_HIGH 4177 #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4178 #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4179 //UVD_LMI_MPRD_DBW_64BIT_BAR_LOW 4180 #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4181 #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4182 //UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 4183 #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4184 #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4185 //UVD_LMI_MPC_64BIT_BAR_LOW 4186 #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4187 #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4188 //UVD_LMI_MPC_64BIT_BAR_HIGH 4189 #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4190 #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4191 //UVD_LMI_RBC_RB_64BIT_BAR_LOW 4192 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4193 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4194 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 4195 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4196 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4197 //UVD_LMI_RBC_IB_64BIT_BAR_LOW 4198 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4199 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4200 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 4201 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4202 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4203 //UVD_LMI_LBSI_64BIT_BAR_LOW 4204 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4205 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4206 //UVD_LMI_LBSI_64BIT_BAR_HIGH 4207 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4208 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4209 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 4210 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4211 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4212 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 4213 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4214 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4215 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 4216 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4217 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4218 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 4219 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4220 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4221 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 4222 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4223 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4224 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 4225 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4226 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4227 //UVD_LMI_CENC_64BIT_BAR_LOW 4228 #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4229 #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4230 //UVD_LMI_CENC_64BIT_BAR_HIGH 4231 #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4232 #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4233 //UVD_LMI_SRE_64BIT_BAR_LOW 4234 #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4235 #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4236 //UVD_LMI_SRE_64BIT_BAR_HIGH 4237 #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4238 #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4239 //UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 4240 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4241 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4242 //UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 4243 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4244 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4245 //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 4246 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4247 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4248 //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 4249 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4250 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4251 //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 4252 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4253 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4254 //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 4255 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4256 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4257 //UVD_LMI_MIF_REF_64BIT_BAR_LOW 4258 #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4259 #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4260 //UVD_LMI_MIF_REF_64BIT_BAR_HIGH 4261 #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4262 #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4263 //UVD_LMI_MIF_DBW_64BIT_BAR_LOW 4264 #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4265 #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4266 //UVD_LMI_MIF_DBW_64BIT_BAR_HIGH 4267 #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4268 #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4269 //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 4270 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4271 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4272 //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 4273 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4274 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4275 //UVD_LMI_MIF_BSP0_64BIT_BAR_LOW 4276 #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4277 #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4278 //UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 4279 #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4280 #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4281 //UVD_LMI_MIF_BSP1_64BIT_BAR_LOW 4282 #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4283 #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4284 //UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 4285 #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4286 #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4287 //UVD_LMI_MIF_BSP2_64BIT_BAR_LOW 4288 #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4289 #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4290 //UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 4291 #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4292 #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4293 //UVD_LMI_MIF_BSP3_64BIT_BAR_LOW 4294 #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4295 #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4296 //UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 4297 #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4298 #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4299 //UVD_LMI_MIF_BSD0_64BIT_BAR_LOW 4300 #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4301 #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4302 //UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 4303 #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4304 #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4305 //UVD_LMI_MIF_BSD1_64BIT_BAR_LOW 4306 #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4307 #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4308 //UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 4309 #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4310 #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4311 //UVD_LMI_MIF_BSD2_64BIT_BAR_LOW 4312 #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4313 #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4314 //UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 4315 #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4316 #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4317 //UVD_LMI_MIF_BSD3_64BIT_BAR_LOW 4318 #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4319 #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4320 //UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 4321 #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4322 #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4323 //UVD_LMI_MIF_BSD4_64BIT_BAR_LOW 4324 #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4325 #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4326 //UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 4327 #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4328 #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4329 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 4330 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4331 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4332 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 4333 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4334 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4335 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 4336 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4337 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4338 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 4339 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4340 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4341 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 4342 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4343 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4344 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 4345 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4346 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4347 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 4348 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4349 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4350 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 4351 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4352 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4353 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 4354 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4355 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4356 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 4357 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4358 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4359 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 4360 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4361 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4362 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 4363 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4364 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4365 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 4366 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4367 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4368 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 4369 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4370 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4371 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 4372 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4373 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4374 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 4375 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4376 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4377 //UVD_LMI_MIF_SCLR_64BIT_BAR_LOW 4378 #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4379 #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4380 //UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 4381 #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4382 #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4383 //UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 4384 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4385 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4386 //UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 4387 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4388 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4389 //UVD_LMI_SPH_64BIT_BAR_HIGH 4390 #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4391 #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4392 //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 4393 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4394 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4395 //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 4396 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4397 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4398 //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 4399 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4400 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4401 //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 4402 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4403 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4404 //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 4405 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4406 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4407 //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 4408 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4409 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4410 //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 4411 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4412 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4413 //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 4414 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4415 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4416 //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 4417 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4418 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4419 //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 4420 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4421 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4422 //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 4423 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4424 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4425 //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 4426 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4427 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4428 //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 4429 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4430 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4431 //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 4432 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4433 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4434 //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 4435 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4436 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4437 //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 4438 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4439 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4440 //UVD_LMI_MMSCH_NC_VMID 4441 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 4442 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 4443 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 4444 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 4445 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 4446 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 4447 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 4448 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 4449 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 4450 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 4451 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 4452 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 4453 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 4454 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 4455 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 4456 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 4457 //UVD_LMI_MMSCH_CTRL 4458 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 4459 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 4460 #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 4461 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 4462 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 4463 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 4464 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 4465 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 4466 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 4467 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 4468 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 4469 #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L 4470 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 4471 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 4472 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 4473 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 4474 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 4475 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 4476 //UVD_MMSCH_LMI_STATUS 4477 #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 4478 #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd 4479 #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe 4480 #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L 4481 #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L 4482 #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L 4483 //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 4484 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4485 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4486 //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 4487 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4488 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4489 //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 4490 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4491 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4492 //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 4493 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4494 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4495 //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 4496 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4497 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4498 //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 4499 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4500 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4501 //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 4502 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4503 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4504 //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 4505 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4506 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4507 //UVD_ADP_ATOMIC_CONFIG 4508 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 4509 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 4510 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 4511 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc 4512 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 4513 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL 4514 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L 4515 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L 4516 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L 4517 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L 4518 //UVD_LMI_ARB_CTRL2 4519 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 4520 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 4521 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 4522 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 4523 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 4524 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 4525 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 4526 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 4527 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 4528 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 4529 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 4530 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 4531 //UVD_LMI_VCPU_CACHE_VMIDS_MULTI 4532 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 4533 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 4534 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 4535 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 4536 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 4537 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 4538 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 4539 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 4540 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 4541 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 4542 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 4543 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 4544 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 4545 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 4546 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 4547 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 4548 //UVD_LMI_VCPU_NC_VMIDS_MULTI 4549 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 4550 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 4551 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 4552 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 4553 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 4554 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 4555 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 4556 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 4557 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 4558 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 4559 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 4560 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 4561 //UVD_LMI_LAT_CTRL 4562 #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 4563 #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 4564 #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 4565 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 4566 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 4567 #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 4568 #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 4569 #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 4570 #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 4571 #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 4572 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 4573 #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 4574 //UVD_LMI_LAT_CNTR 4575 #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 4576 #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 4577 #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 4578 #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 4579 //UVD_LMI_AVG_LAT_CNTR 4580 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 4581 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 4582 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 4583 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 4584 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 4585 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 4586 //UVD_LMI_SPH 4587 #define UVD_LMI_SPH__ADDR__SHIFT 0x0 4588 #define UVD_LMI_SPH__STS__SHIFT 0x1c 4589 #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 4590 #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 4591 #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 4592 #define UVD_LMI_SPH__STS_MASK 0x30000000L 4593 #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 4594 #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 4595 //UVD_LMI_VCPU_CACHE_VMID 4596 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 4597 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 4598 //UVD_LMI_CTRL2 4599 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 4600 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 4601 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 4602 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 4603 #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 4604 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 4605 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 4606 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 4607 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 4608 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 4609 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 4610 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 4611 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 4612 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 4613 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 4614 #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 4615 #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 4616 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 4617 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 4618 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 4619 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 4620 #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 4621 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 4622 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 4623 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 4624 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 4625 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 4626 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 4627 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 4628 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 4629 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 4630 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 4631 #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 4632 #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 4633 //UVD_LMI_URGENT_CTRL 4634 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 4635 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 4636 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 4637 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 4638 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 4639 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 4640 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 4641 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 4642 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 4643 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 4644 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 4645 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 4646 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 4647 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 4648 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 4649 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 4650 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 4651 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 4652 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 4653 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 4654 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 4655 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 4656 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 4657 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 4658 //UVD_LMI_CTRL 4659 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 4660 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 4661 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 4662 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 4663 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 4664 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 4665 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 4666 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 4667 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 4668 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 4669 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 4670 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 4671 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 4672 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 4673 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 4674 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 4675 #define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c 4676 #define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d 4677 #define UVD_LMI_CTRL__RFU__SHIFT 0x1e 4678 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 4679 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 4680 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 4681 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 4682 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 4683 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 4684 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 4685 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 4686 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L 4687 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 4688 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 4689 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 4690 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 4691 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 4692 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 4693 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 4694 #define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L 4695 #define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L 4696 #define UVD_LMI_CTRL__RFU_MASK 0xC0000000L 4697 //UVD_LMI_STATUS 4698 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 4699 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 4700 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 4701 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 4702 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 4703 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 4704 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 4705 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 4706 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 4707 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 4708 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 4709 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 4710 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 4711 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 4712 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 4713 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 4714 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 4715 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 4716 #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 4717 #define UVD_LMI_STATUS__DPB_MPC2_NO_HIT__SHIFT 0x1c 4718 #define UVD_LMI_STATUS__DPB_MPC2_MULTI_HIT__SHIFT 0x1d 4719 #define UVD_LMI_STATUS__DPB_MPC_NO_HIT__SHIFT 0x1e 4720 #define UVD_LMI_STATUS__DPB_MPC_MULTI_HIT__SHIFT 0x1f 4721 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 4722 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 4723 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 4724 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 4725 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 4726 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 4727 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 4728 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 4729 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 4730 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 4731 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 4732 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 4733 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 4734 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 4735 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 4736 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 4737 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 4738 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 4739 #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 4740 #define UVD_LMI_STATUS__DPB_MPC2_NO_HIT_MASK 0x10000000L 4741 #define UVD_LMI_STATUS__DPB_MPC2_MULTI_HIT_MASK 0x20000000L 4742 #define UVD_LMI_STATUS__DPB_MPC_NO_HIT_MASK 0x40000000L 4743 #define UVD_LMI_STATUS__DPB_MPC_MULTI_HIT_MASK 0x80000000L 4744 //UVD_LMI_PERFMON_CTRL 4745 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 4746 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 4747 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 4748 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 4749 //UVD_LMI_PERFMON_COUNT_LO 4750 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 4751 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 4752 //UVD_LMI_PERFMON_COUNT_HI 4753 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 4754 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 4755 //UVD_LMI_ADP_SWAP_CNTL 4756 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 4757 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 4758 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 4759 #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 4760 #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 4761 #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 4762 #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 4763 #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP__SHIFT 0x14 4764 #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 4765 #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 4766 #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 4767 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 4768 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 4769 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 4770 #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 4771 #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 4772 #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 4773 #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 4774 #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP_MASK 0x00300000L 4775 #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 4776 #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 4777 #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 4778 //UVD_LMI_RBC_RB_VMID 4779 #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 4780 #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 4781 //UVD_LMI_RBC_IB_VMID 4782 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 4783 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 4784 //UVD_LMI_MC_CREDITS 4785 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 4786 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 4787 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 4788 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 4789 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 4790 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 4791 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 4792 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 4793 //UVD_LMI_ADP_IND_INDEX 4794 #define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 4795 #define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL 4796 //UVD_LMI_ADP_IND_DATA 4797 #define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 4798 #define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL 4799 //UVD_LMI_ADP_PF_EN 4800 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN__SHIFT 0x0 4801 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN__SHIFT 0x1 4802 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN__SHIFT 0x2 4803 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN_MASK 0x00000001L 4804 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN_MASK 0x00000002L 4805 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN_MASK 0x00000004L 4806 //UVD_LMI_ADP_CNN_CTRL 4807 #define UVD_LMI_ADP_CNN_CTRL__CNN_MODE_EN__SHIFT 0x0 4808 #define UVD_LMI_ADP_CNN_CTRL__CNN_MODE_EN_MASK 0x00000001L 4809 //UVD_LMI_PREF_CTRL 4810 #define UVD_LMI_PREF_CTRL__PREF_RST__SHIFT 0x0 4811 #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS__SHIFT 0x1 4812 #define UVD_LMI_PREF_CTRL__PREF_WSTRB__SHIFT 0x2 4813 #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE__SHIFT 0x3 4814 #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE__SHIFT 0x4 4815 #define UVD_LMI_PREF_CTRL__PREF_SIZE__SHIFT 0x13 4816 #define UVD_LMI_PREF_CTRL__PREF_RST_MASK 0x00000001L 4817 #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS_MASK 0x00000002L 4818 #define UVD_LMI_PREF_CTRL__PREF_WSTRB_MASK 0x00000004L 4819 #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE_MASK 0x00000008L 4820 #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE_MASK 0x00000070L 4821 #define UVD_LMI_PREF_CTRL__PREF_SIZE_MASK 0xFFF80000L 4822 //UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW 4823 #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4824 #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4825 //UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH 4826 #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4827 #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4828 4829 4830 // addressBlock: uvdctxind 4831 //UVD_CGC_MEM_CTRL 4832 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 4833 #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 4834 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 4835 #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 4836 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 4837 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 4838 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 4839 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 4840 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 4841 #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 4842 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 4843 #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 4844 #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 4845 #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN__SHIFT 0xe 4846 #define UVD_CGC_MEM_CTRL__MPC1_LS_EN__SHIFT 0xf 4847 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 4848 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 4849 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L 4850 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L 4851 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L 4852 #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L 4853 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L 4854 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L 4855 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L 4856 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L 4857 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L 4858 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L 4859 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L 4860 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L 4861 #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L 4862 #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN_MASK 0x00004000L 4863 #define UVD_CGC_MEM_CTRL__MPC1_LS_EN_MASK 0x00008000L 4864 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 4865 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 4866 //UVD_CGC_CTRL2 4867 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 4868 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 4869 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 4870 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 4871 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 4872 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001CL 4873 //UVD_CGC_MEM_DS_CTRL 4874 #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN__SHIFT 0x0 4875 #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN__SHIFT 0x1 4876 #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN__SHIFT 0x2 4877 #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN__SHIFT 0x3 4878 #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN__SHIFT 0x4 4879 #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5 4880 #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN__SHIFT 0x6 4881 #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN__SHIFT 0x7 4882 #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN__SHIFT 0x8 4883 #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN__SHIFT 0x9 4884 #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa 4885 #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN__SHIFT 0xc 4886 #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN__SHIFT 0xd 4887 #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN__SHIFT 0xe 4888 #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN__SHIFT 0xf 4889 #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN_MASK 0x00000001L 4890 #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN_MASK 0x00000002L 4891 #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN_MASK 0x00000004L 4892 #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN_MASK 0x00000008L 4893 #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN_MASK 0x00000010L 4894 #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN_MASK 0x00000020L 4895 #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN_MASK 0x00000040L 4896 #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN_MASK 0x00000080L 4897 #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN_MASK 0x00000100L 4898 #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN_MASK 0x00000200L 4899 #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN_MASK 0x00000400L 4900 #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN_MASK 0x00001000L 4901 #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN_MASK 0x00002000L 4902 #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN_MASK 0x00004000L 4903 #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN_MASK 0x00008000L 4904 //UVD_CGC_MEM_SD_CTRL 4905 #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN__SHIFT 0x0 4906 #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN__SHIFT 0x1 4907 #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN__SHIFT 0x2 4908 #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN__SHIFT 0x3 4909 #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN__SHIFT 0x4 4910 #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5 4911 #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN__SHIFT 0x6 4912 #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN__SHIFT 0x7 4913 #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN__SHIFT 0x8 4914 #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN__SHIFT 0x9 4915 #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa 4916 #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN__SHIFT 0xc 4917 #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN__SHIFT 0xd 4918 #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN__SHIFT 0xe 4919 #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN__SHIFT 0xf 4920 #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN_MASK 0x00000001L 4921 #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN_MASK 0x00000002L 4922 #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN_MASK 0x00000004L 4923 #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN_MASK 0x00000008L 4924 #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN_MASK 0x00000010L 4925 #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN_MASK 0x00000020L 4926 #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN_MASK 0x00000040L 4927 #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN_MASK 0x00000080L 4928 #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN_MASK 0x00000100L 4929 #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN_MASK 0x00000200L 4930 #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN_MASK 0x00000400L 4931 #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN_MASK 0x00001000L 4932 #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN_MASK 0x00002000L 4933 #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN_MASK 0x00004000L 4934 #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN_MASK 0x00008000L 4935 //UVD_SW_SCRATCH_00 4936 #define UVD_SW_SCRATCH_00__DATA__SHIFT 0x0 4937 #define UVD_SW_SCRATCH_00__DATA_MASK 0xFFFFFFFFL 4938 //UVD_SW_SCRATCH_01 4939 #define UVD_SW_SCRATCH_01__DATA__SHIFT 0x0 4940 #define UVD_SW_SCRATCH_01__DATA_MASK 0xFFFFFFFFL 4941 //UVD_SW_SCRATCH_02 4942 #define UVD_SW_SCRATCH_02__DATA__SHIFT 0x0 4943 #define UVD_SW_SCRATCH_02__DATA_MASK 0xFFFFFFFFL 4944 //UVD_SW_SCRATCH_03 4945 #define UVD_SW_SCRATCH_03__DATA__SHIFT 0x0 4946 #define UVD_SW_SCRATCH_03__DATA_MASK 0xFFFFFFFFL 4947 //UVD_SW_SCRATCH_04 4948 #define UVD_SW_SCRATCH_04__DATA__SHIFT 0x0 4949 #define UVD_SW_SCRATCH_04__DATA_MASK 0xFFFFFFFFL 4950 //UVD_SW_SCRATCH_05 4951 #define UVD_SW_SCRATCH_05__DATA__SHIFT 0x0 4952 #define UVD_SW_SCRATCH_05__DATA_MASK 0xFFFFFFFFL 4953 //UVD_SW_SCRATCH_06 4954 #define UVD_SW_SCRATCH_06__DATA__SHIFT 0x0 4955 #define UVD_SW_SCRATCH_06__DATA_MASK 0xFFFFFFFFL 4956 //UVD_SW_SCRATCH_07 4957 #define UVD_SW_SCRATCH_07__DATA__SHIFT 0x0 4958 #define UVD_SW_SCRATCH_07__DATA_MASK 0xFFFFFFFFL 4959 //UVD_SW_SCRATCH_08 4960 #define UVD_SW_SCRATCH_08__DATA__SHIFT 0x0 4961 #define UVD_SW_SCRATCH_08__DATA_MASK 0xFFFFFFFFL 4962 //UVD_SW_SCRATCH_09 4963 #define UVD_SW_SCRATCH_09__DATA__SHIFT 0x0 4964 #define UVD_SW_SCRATCH_09__DATA_MASK 0xFFFFFFFFL 4965 //UVD_SW_SCRATCH_10 4966 #define UVD_SW_SCRATCH_10__DATA__SHIFT 0x0 4967 #define UVD_SW_SCRATCH_10__DATA_MASK 0xFFFFFFFFL 4968 //UVD_SW_SCRATCH_11 4969 #define UVD_SW_SCRATCH_11__DATA__SHIFT 0x0 4970 #define UVD_SW_SCRATCH_11__DATA_MASK 0xFFFFFFFFL 4971 //UVD_SW_SCRATCH_12 4972 #define UVD_SW_SCRATCH_12__DATA__SHIFT 0x0 4973 #define UVD_SW_SCRATCH_12__DATA_MASK 0xFFFFFFFFL 4974 //UVD_SW_SCRATCH_13 4975 #define UVD_SW_SCRATCH_13__DATA__SHIFT 0x0 4976 #define UVD_SW_SCRATCH_13__DATA_MASK 0xFFFFFFFFL 4977 //UVD_SW_SCRATCH_14 4978 #define UVD_SW_SCRATCH_14__DATA__SHIFT 0x0 4979 #define UVD_SW_SCRATCH_14__DATA_MASK 0xFFFFFFFFL 4980 //UVD_SW_SCRATCH_15 4981 #define UVD_SW_SCRATCH_15__DATA__SHIFT 0x0 4982 #define UVD_SW_SCRATCH_15__DATA_MASK 0xFFFFFFFFL 4983 //UVD_MEMCHECK_SYS_INT_EN 4984 #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN__SHIFT 0x0 4985 #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN__SHIFT 0x1 4986 #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN__SHIFT 0x2 4987 #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN__SHIFT 0x3 4988 #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN__SHIFT 0x4 4989 #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN__SHIFT 0x5 4990 #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 4991 #define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN__SHIFT 0x7 4992 #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 4993 #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 4994 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa 4995 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb 4996 #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN__SHIFT 0xc 4997 #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN__SHIFT 0xf 4998 #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 4999 #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 5000 #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 5001 #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 5002 #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 5003 #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 5004 #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 5005 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x1b 5006 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1c 5007 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1d 5008 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1e 5009 #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN__SHIFT 0x1f 5010 #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN_MASK 0x00000001L 5011 #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN_MASK 0x00000002L 5012 #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN_MASK 0x00000004L 5013 #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN_MASK 0x00000008L 5014 #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN_MASK 0x00000010L 5015 #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN_MASK 0x00000020L 5016 #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L 5017 #define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN_MASK 0x00000080L 5018 #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L 5019 #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L 5020 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L 5021 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L 5022 #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN_MASK 0x00001000L 5023 #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L 5024 #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L 5025 #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L 5026 #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L 5027 #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L 5028 #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L 5029 #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L 5030 #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L 5031 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN_MASK 0x08000000L 5032 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN_MASK 0x10000000L 5033 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN_MASK 0x20000000L 5034 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x40000000L 5035 #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN_MASK 0x80000000L 5036 //UVD_MEMCHECK_SYS_INT_STAT 5037 #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR__SHIFT 0x0 5038 #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR__SHIFT 0x1 5039 #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR__SHIFT 0x2 5040 #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR__SHIFT 0x3 5041 #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR__SHIFT 0x4 5042 #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR__SHIFT 0x5 5043 #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR__SHIFT 0x6 5044 #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR__SHIFT 0x7 5045 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR__SHIFT 0x8 5046 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR__SHIFT 0x9 5047 #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR__SHIFT 0xa 5048 #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR__SHIFT 0xb 5049 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc 5050 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd 5051 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR__SHIFT 0xe 5052 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR__SHIFT 0xf 5053 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 5054 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 5055 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 5056 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 5057 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 5058 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 5059 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 5060 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 5061 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR__SHIFT 0x18 5062 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR__SHIFT 0x19 5063 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e 5064 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f 5065 #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR_MASK 0x00000001L 5066 #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR_MASK 0x00000002L 5067 #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR_MASK 0x00000004L 5068 #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR_MASK 0x00000008L 5069 #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR_MASK 0x00000010L 5070 #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR_MASK 0x00000020L 5071 #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR_MASK 0x00000040L 5072 #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR_MASK 0x00000080L 5073 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR_MASK 0x00000100L 5074 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR_MASK 0x00000200L 5075 #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR_MASK 0x00000400L 5076 #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR_MASK 0x00000800L 5077 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L 5078 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L 5079 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L 5080 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L 5081 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L 5082 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L 5083 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L 5084 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L 5085 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L 5086 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L 5087 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L 5088 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L 5089 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR_MASK 0x01000000L 5090 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR_MASK 0x02000000L 5091 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L 5092 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L 5093 //UVD_MEMCHECK_SYS_INT_ACK 5094 #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK__SHIFT 0x0 5095 #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK__SHIFT 0x1 5096 #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK__SHIFT 0x2 5097 #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK__SHIFT 0x3 5098 #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK__SHIFT 0x4 5099 #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK__SHIFT 0x5 5100 #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK__SHIFT 0x6 5101 #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK__SHIFT 0x7 5102 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK__SHIFT 0x8 5103 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK__SHIFT 0x9 5104 #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK__SHIFT 0xa 5105 #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK__SHIFT 0xb 5106 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc 5107 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd 5108 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK__SHIFT 0xe 5109 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK__SHIFT 0xf 5110 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 5111 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 5112 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 5113 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 5114 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 5115 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 5116 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 5117 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 5118 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK__SHIFT 0x18 5119 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK__SHIFT 0x19 5120 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e 5121 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f 5122 #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK_MASK 0x00000001L 5123 #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK_MASK 0x00000002L 5124 #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK_MASK 0x00000004L 5125 #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK_MASK 0x00000008L 5126 #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK_MASK 0x00000010L 5127 #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK_MASK 0x00000020L 5128 #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK_MASK 0x00000040L 5129 #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK_MASK 0x00000080L 5130 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK_MASK 0x00000100L 5131 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK_MASK 0x00000200L 5132 #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK_MASK 0x00000400L 5133 #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK_MASK 0x00000800L 5134 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L 5135 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L 5136 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L 5137 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L 5138 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L 5139 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L 5140 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L 5141 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L 5142 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L 5143 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L 5144 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L 5145 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L 5146 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK_MASK 0x01000000L 5147 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK_MASK 0x02000000L 5148 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L 5149 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L 5150 //UVD_MEMCHECK_VCPU_INT_EN 5151 #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN__SHIFT 0x0 5152 #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN__SHIFT 0x1 5153 #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN__SHIFT 0x2 5154 #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN__SHIFT 0x3 5155 #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN__SHIFT 0x4 5156 #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN__SHIFT 0x5 5157 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 5158 #define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN__SHIFT 0x7 5159 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 5160 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 5161 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa 5162 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb 5163 #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN__SHIFT 0xc 5164 #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN__SHIFT 0xf 5165 #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 5166 #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 5167 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 5168 #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 5169 #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 5170 #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 5171 #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 5172 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x19 5173 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1a 5174 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1b 5175 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1c 5176 #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN__SHIFT 0x1d 5177 #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN_MASK 0x00000001L 5178 #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN_MASK 0x00000002L 5179 #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN_MASK 0x00000004L 5180 #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN_MASK 0x00000008L 5181 #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN_MASK 0x00000010L 5182 #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN_MASK 0x00000020L 5183 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L 5184 #define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN_MASK 0x00000080L 5185 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L 5186 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L 5187 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L 5188 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L 5189 #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN_MASK 0x00001000L 5190 #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L 5191 #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L 5192 #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L 5193 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L 5194 #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L 5195 #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L 5196 #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L 5197 #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L 5198 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN_MASK 0x02000000L 5199 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN_MASK 0x04000000L 5200 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN_MASK 0x08000000L 5201 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x10000000L 5202 #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN_MASK 0x20000000L 5203 //UVD_MEMCHECK_VCPU_INT_STAT 5204 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR__SHIFT 0x0 5205 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR__SHIFT 0x1 5206 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR__SHIFT 0x2 5207 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR__SHIFT 0x3 5208 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR__SHIFT 0x4 5209 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR__SHIFT 0x5 5210 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR__SHIFT 0x6 5211 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR__SHIFT 0x7 5212 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR__SHIFT 0x8 5213 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR__SHIFT 0x9 5214 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR__SHIFT 0xa 5215 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR__SHIFT 0xb 5216 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc 5217 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd 5218 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR__SHIFT 0xe 5219 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR__SHIFT 0xf 5220 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 5221 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 5222 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 5223 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 5224 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 5225 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 5226 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 5227 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 5228 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR__SHIFT 0x18 5229 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR__SHIFT 0x19 5230 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e 5231 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f 5232 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR_MASK 0x00000001L 5233 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR_MASK 0x00000002L 5234 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR_MASK 0x00000004L 5235 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR_MASK 0x00000008L 5236 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR_MASK 0x00000010L 5237 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR_MASK 0x00000020L 5238 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR_MASK 0x00000040L 5239 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR_MASK 0x00000080L 5240 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR_MASK 0x00000100L 5241 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR_MASK 0x00000200L 5242 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR_MASK 0x00000400L 5243 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR_MASK 0x00000800L 5244 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L 5245 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L 5246 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L 5247 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L 5248 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L 5249 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L 5250 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L 5251 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L 5252 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L 5253 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L 5254 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L 5255 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L 5256 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR_MASK 0x01000000L 5257 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR_MASK 0x02000000L 5258 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L 5259 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L 5260 //UVD_MEMCHECK_VCPU_INT_ACK 5261 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK__SHIFT 0x0 5262 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK__SHIFT 0x1 5263 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK__SHIFT 0x2 5264 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK__SHIFT 0x3 5265 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK__SHIFT 0x4 5266 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK__SHIFT 0x5 5267 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK__SHIFT 0x6 5268 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK__SHIFT 0x7 5269 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK__SHIFT 0x8 5270 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK__SHIFT 0x9 5271 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK__SHIFT 0xa 5272 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK__SHIFT 0xb 5273 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc 5274 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd 5275 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK__SHIFT 0xe 5276 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK__SHIFT 0xf 5277 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 5278 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 5279 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 5280 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 5281 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 5282 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 5283 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 5284 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 5285 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK__SHIFT 0x18 5286 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK__SHIFT 0x19 5287 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e 5288 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f 5289 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK_MASK 0x00000001L 5290 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK_MASK 0x00000002L 5291 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK_MASK 0x00000004L 5292 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK_MASK 0x00000008L 5293 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK_MASK 0x00000010L 5294 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK_MASK 0x00000020L 5295 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK_MASK 0x00000040L 5296 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK_MASK 0x00000080L 5297 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK_MASK 0x00000100L 5298 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK_MASK 0x00000200L 5299 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK_MASK 0x00000400L 5300 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK_MASK 0x00000800L 5301 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L 5302 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L 5303 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L 5304 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L 5305 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L 5306 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L 5307 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L 5308 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L 5309 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L 5310 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L 5311 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L 5312 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L 5313 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK_MASK 0x01000000L 5314 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK_MASK 0x02000000L 5315 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L 5316 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L 5317 //UVD_MEMCHECK2_SYS_INT_STAT 5318 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 5319 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 5320 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 5321 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 5322 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 5323 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 5324 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 5325 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 5326 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 5327 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 5328 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 5329 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 5330 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 5331 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 5332 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x16 5333 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x17 5334 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x18 5335 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x19 5336 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x1a 5337 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x1b 5338 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x1c 5339 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x1d 5340 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR__SHIFT 0x1e 5341 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR__SHIFT 0x1f 5342 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 5343 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 5344 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 5345 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 5346 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 5347 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 5348 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 5349 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 5350 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 5351 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 5352 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 5353 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 5354 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 5355 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 5356 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00400000L 5357 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00800000L 5358 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x01000000L 5359 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x02000000L 5360 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x04000000L 5361 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x08000000L 5362 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x10000000L 5363 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x20000000L 5364 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR_MASK 0x40000000L 5365 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR_MASK 0x80000000L 5366 //UVD_MEMCHECK2_SYS_INT_ACK 5367 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 5368 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 5369 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 5370 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 5371 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 5372 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 5373 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 5374 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 5375 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 5376 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 5377 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 5378 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 5379 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 5380 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 5381 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x16 5382 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x17 5383 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x18 5384 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x19 5385 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x1a 5386 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x1b 5387 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x1c 5388 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x1d 5389 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK__SHIFT 0x1e 5390 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK__SHIFT 0x1f 5391 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 5392 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 5393 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 5394 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 5395 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 5396 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 5397 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 5398 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 5399 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 5400 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 5401 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 5402 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 5403 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 5404 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 5405 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00400000L 5406 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00800000L 5407 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x01000000L 5408 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x02000000L 5409 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x04000000L 5410 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x08000000L 5411 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x10000000L 5412 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x20000000L 5413 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK_MASK 0x40000000L 5414 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK_MASK 0x80000000L 5415 //UVD_MEMCHECK2_VCPU_INT_STAT 5416 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 5417 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 5418 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 5419 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 5420 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 5421 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 5422 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 5423 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 5424 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 5425 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 5426 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 5427 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 5428 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 5429 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 5430 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x12 5431 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x13 5432 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x14 5433 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x15 5434 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x16 5435 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x17 5436 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x18 5437 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x19 5438 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR__SHIFT 0x1a 5439 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR__SHIFT 0x1b 5440 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 5441 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 5442 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 5443 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 5444 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 5445 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 5446 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 5447 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 5448 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 5449 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 5450 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 5451 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 5452 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 5453 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 5454 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00040000L 5455 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00080000L 5456 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x00100000L 5457 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x00200000L 5458 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x00400000L 5459 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x00800000L 5460 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x01000000L 5461 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x02000000L 5462 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR_MASK 0x04000000L 5463 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR_MASK 0x08000000L 5464 //UVD_MEMCHECK2_VCPU_INT_ACK 5465 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 5466 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 5467 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 5468 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 5469 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 5470 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 5471 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 5472 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 5473 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 5474 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 5475 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 5476 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 5477 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 5478 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 5479 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x12 5480 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x13 5481 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x14 5482 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x15 5483 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x16 5484 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x17 5485 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x18 5486 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x19 5487 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK__SHIFT 0x1a 5488 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK__SHIFT 0x1b 5489 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 5490 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 5491 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 5492 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 5493 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 5494 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 5495 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 5496 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 5497 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 5498 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 5499 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 5500 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 5501 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 5502 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 5503 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00040000L 5504 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00080000L 5505 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x00100000L 5506 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x00200000L 5507 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x00400000L 5508 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x00800000L 5509 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x01000000L 5510 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x02000000L 5511 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L 5512 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L 5513 //UVD_IH_SEM_CTRL 5514 #define UVD_IH_SEM_CTRL__IH_STALL_EN__SHIFT 0x0 5515 #define UVD_IH_SEM_CTRL__SEM_STALL_EN__SHIFT 0x1 5516 #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 5517 #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN__SHIFT 0x3 5518 #define UVD_IH_SEM_CTRL__IH_VMID__SHIFT 0x4 5519 #define UVD_IH_SEM_CTRL__IH_USER_DATA__SHIFT 0x8 5520 #define UVD_IH_SEM_CTRL__IH_RINGID__SHIFT 0x14 5521 #define UVD_IH_SEM_CTRL__IH_STALL_EN_MASK 0x00000001L 5522 #define UVD_IH_SEM_CTRL__SEM_STALL_EN_MASK 0x00000002L 5523 #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 5524 #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN_MASK 0x00000008L 5525 #define UVD_IH_SEM_CTRL__IH_VMID_MASK 0x000000F0L 5526 #define UVD_IH_SEM_CTRL__IH_USER_DATA_MASK 0x000FFF00L 5527 #define UVD_IH_SEM_CTRL__IH_RINGID_MASK 0x0FF00000L 5528 5529 5530 #endif 5531