1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/slab.h>
18
19 #include <linux/regulator/consumer.h>
20
21 #define USB_PHY_UTMI_CTRL0 (0x3c)
22 #define SLEEPM BIT(0)
23
24 #define USB_PHY_UTMI_CTRL5 (0x50)
25 #define POR BIT(1)
26
27 #define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
28 #define PHY_ENABLE BIT(0)
29 #define SIDDQ_SEL BIT(1)
30 #define SIDDQ BIT(2)
31 #define FSEL GENMASK(6, 4)
32 #define FSEL_38_4_MHZ_VAL (0x6)
33
34 #define USB_PHY_HS_PHY_CTRL2 (0x64)
35 #define USB2_SUSPEND_N BIT(2)
36 #define USB2_SUSPEND_N_SEL BIT(3)
37
38 #define USB_PHY_CFG0 (0x94)
39 #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
40
41 #define USB_PHY_CFG1 (0x154)
42 #define PLL_EN BIT(0)
43
44 #define USB_PHY_FSEL_SEL (0xb8)
45 #define FSEL_SEL BIT(0)
46
47 #define USB_PHY_XCFGI_39_32 (0x16c)
48 #define HSTX_PE GENMASK(3, 2)
49
50 #define USB_PHY_XCFGI_71_64 (0x17c)
51 #define HSTX_SWING GENMASK(3, 0)
52
53 #define USB_PHY_XCFGI_31_24 (0x168)
54 #define HSTX_SLEW GENMASK(2, 0)
55
56 #define USB_PHY_XCFGI_7_0 (0x15c)
57 #define PLL_LOCK_TIME GENMASK(1, 0)
58
59 #define M31_EUSB_PHY_INIT_CFG(o, b, v) \
60 { \
61 .off = o, \
62 .mask = b, \
63 .val = v, \
64 }
65
66 struct m31_phy_tbl_entry {
67 u32 off;
68 u32 mask;
69 u32 val;
70 };
71
72 struct m31_eusb2_priv_data {
73 const struct m31_phy_tbl_entry *setup_seq;
74 unsigned int setup_seq_nregs;
75 const struct m31_phy_tbl_entry *override_seq;
76 unsigned int override_seq_nregs;
77 const struct m31_phy_tbl_entry *reset_seq;
78 unsigned int reset_seq_nregs;
79 unsigned int fsel;
80 };
81
82 static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = {
83 M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1),
84 M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1),
85 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, PHY_ENABLE, 1),
86 M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1),
87 M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1),
88 };
89
90 static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = {
91 M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, HSTX_PE, 0),
92 M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, HSTX_SWING, 7),
93 M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, HSTX_SLEW, 0),
94 M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_7_0, PLL_LOCK_TIME, 0),
95 };
96
97 static const struct m31_phy_tbl_entry m31_eusb_phy_reset_tbl[] = {
98 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 1),
99 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N, 1),
100 M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL0, SLEEPM, 1),
101 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ_SEL, 1),
102 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0),
103 M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 0),
104 M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0),
105 M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0),
106 };
107
108 static const struct regulator_bulk_data m31_eusb_phy_vregs[] = {
109 { .supply = "vdd" },
110 { .supply = "vdda12" },
111 };
112
113 #define M31_EUSB_NUM_VREGS ARRAY_SIZE(m31_eusb_phy_vregs)
114
115 struct m31eusb2_phy {
116 struct phy *phy;
117 void __iomem *base;
118 const struct m31_eusb2_priv_data *data;
119 enum phy_mode mode;
120
121 struct regulator_bulk_data *vregs;
122 struct clk *clk;
123 struct reset_control *reset;
124
125 struct phy *repeater;
126 };
127
m31eusb2_phy_write_readback(void __iomem * base,u32 offset,const u32 mask,u32 val)128 static int m31eusb2_phy_write_readback(void __iomem *base, u32 offset,
129 const u32 mask, u32 val)
130 {
131 u32 write_val;
132 u32 tmp;
133
134 tmp = readl(base + offset);
135 tmp &= ~mask;
136 write_val = tmp | val;
137
138 writel(write_val, base + offset);
139
140 tmp = readl(base + offset);
141 tmp &= mask;
142
143 if (tmp != val) {
144 pr_err("write: %x to offset: %x FAILED\n", val, offset);
145 return -EINVAL;
146 }
147
148 return 0;
149 }
150
m31eusb2_phy_write_sequence(struct m31eusb2_phy * phy,const struct m31_phy_tbl_entry * tbl,int num)151 static int m31eusb2_phy_write_sequence(struct m31eusb2_phy *phy,
152 const struct m31_phy_tbl_entry *tbl,
153 int num)
154 {
155 int i;
156 int ret;
157
158 for (i = 0 ; i < num; i++, tbl++) {
159 dev_dbg(&phy->phy->dev, "Offset:%x BitMask:%x Value:%x",
160 tbl->off, tbl->mask, tbl->val);
161
162 ret = m31eusb2_phy_write_readback(phy->base,
163 tbl->off, tbl->mask,
164 tbl->val << __ffs(tbl->mask));
165 if (ret < 0)
166 return ret;
167 }
168
169 return 0;
170 }
171
m31eusb2_phy_set_mode(struct phy * uphy,enum phy_mode mode,int submode)172 static int m31eusb2_phy_set_mode(struct phy *uphy, enum phy_mode mode, int submode)
173 {
174 struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
175
176 phy->mode = mode;
177
178 return phy_set_mode_ext(phy->repeater, mode, submode);
179 }
180
m31eusb2_phy_init(struct phy * uphy)181 static int m31eusb2_phy_init(struct phy *uphy)
182 {
183 struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
184 const struct m31_eusb2_priv_data *data = phy->data;
185 int ret;
186
187 ret = regulator_bulk_enable(M31_EUSB_NUM_VREGS, phy->vregs);
188 if (ret) {
189 dev_err(&uphy->dev, "failed to enable regulator, %d\n", ret);
190 return ret;
191 }
192
193 ret = phy_init(phy->repeater);
194 if (ret) {
195 dev_err(&uphy->dev, "repeater init failed. %d\n", ret);
196 goto disable_vreg;
197 }
198
199 ret = clk_prepare_enable(phy->clk);
200 if (ret) {
201 dev_err(&uphy->dev, "failed to enable ref clock, %d\n", ret);
202 goto disable_repeater;
203 }
204
205 /* Perform phy reset */
206 reset_control_assert(phy->reset);
207 udelay(5);
208 reset_control_deassert(phy->reset);
209
210 m31eusb2_phy_write_sequence(phy, data->setup_seq, data->setup_seq_nregs);
211 m31eusb2_phy_write_readback(phy->base,
212 USB_PHY_HS_PHY_CTRL_COMMON0, FSEL,
213 FIELD_PREP(FSEL, data->fsel));
214 m31eusb2_phy_write_sequence(phy, data->override_seq, data->override_seq_nregs);
215 m31eusb2_phy_write_sequence(phy, data->reset_seq, data->reset_seq_nregs);
216
217 return 0;
218
219 disable_repeater:
220 phy_exit(phy->repeater);
221 disable_vreg:
222 regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs);
223
224 return 0;
225 }
226
m31eusb2_phy_exit(struct phy * uphy)227 static int m31eusb2_phy_exit(struct phy *uphy)
228 {
229 struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
230
231 clk_disable_unprepare(phy->clk);
232 regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs);
233 phy_exit(phy->repeater);
234
235 return 0;
236 }
237
238 static const struct phy_ops m31eusb2_phy_gen_ops = {
239 .init = m31eusb2_phy_init,
240 .exit = m31eusb2_phy_exit,
241 .set_mode = m31eusb2_phy_set_mode,
242 .owner = THIS_MODULE,
243 };
244
m31eusb2_phy_probe(struct platform_device * pdev)245 static int m31eusb2_phy_probe(struct platform_device *pdev)
246 {
247 struct phy_provider *phy_provider;
248 const struct m31_eusb2_priv_data *data;
249 struct device *dev = &pdev->dev;
250 struct m31eusb2_phy *phy;
251 int ret;
252
253 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
254 if (!phy)
255 return -ENOMEM;
256
257 data = device_get_match_data(dev);
258 if (!data)
259 return -EINVAL;
260 phy->data = data;
261
262 phy->base = devm_platform_ioremap_resource(pdev, 0);
263 if (IS_ERR(phy->base))
264 return PTR_ERR(phy->base);
265
266 phy->reset = devm_reset_control_get_exclusive(dev, NULL);
267 if (IS_ERR(phy->reset))
268 return PTR_ERR(phy->reset);
269
270 phy->clk = devm_clk_get(dev, NULL);
271 if (IS_ERR(phy->clk))
272 return dev_err_probe(dev, PTR_ERR(phy->clk),
273 "failed to get clk\n");
274
275 phy->phy = devm_phy_create(dev, NULL, &m31eusb2_phy_gen_ops);
276 if (IS_ERR(phy->phy))
277 return dev_err_probe(dev, PTR_ERR(phy->phy),
278 "failed to create phy\n");
279
280 ret = devm_regulator_bulk_get_const(dev, M31_EUSB_NUM_VREGS,
281 m31_eusb_phy_vregs, &phy->vregs);
282 if (ret)
283 return dev_err_probe(dev, ret,
284 "failed to get regulator supplies\n");
285
286 phy_set_drvdata(phy->phy, phy);
287
288 phy->repeater = devm_of_phy_get_by_index(dev, dev->of_node, 0);
289 if (IS_ERR(phy->repeater))
290 return dev_err_probe(dev, PTR_ERR(phy->repeater),
291 "failed to get repeater\n");
292
293 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
294
295 return PTR_ERR_OR_ZERO(phy_provider);
296 }
297
298 static const struct m31_eusb2_priv_data m31_eusb_v1_data = {
299 .setup_seq = m31_eusb2_setup_tbl,
300 .setup_seq_nregs = ARRAY_SIZE(m31_eusb2_setup_tbl),
301 .override_seq = m31_eusb_phy_override_tbl,
302 .override_seq_nregs = ARRAY_SIZE(m31_eusb_phy_override_tbl),
303 .reset_seq = m31_eusb_phy_reset_tbl,
304 .reset_seq_nregs = ARRAY_SIZE(m31_eusb_phy_reset_tbl),
305 .fsel = FSEL_38_4_MHZ_VAL,
306 };
307
308 static const struct of_device_id m31eusb2_phy_id_table[] = {
309 { .compatible = "qcom,sm8750-m31-eusb2-phy", .data = &m31_eusb_v1_data },
310 { },
311 };
312 MODULE_DEVICE_TABLE(of, m31eusb2_phy_id_table);
313
314 static struct platform_driver m31eusb2_phy_driver = {
315 .probe = m31eusb2_phy_probe,
316 .driver = {
317 .name = "qcom-m31eusb2-phy",
318 .of_match_table = m31eusb2_phy_id_table,
319 },
320 };
321
322 module_platform_driver(m31eusb2_phy_driver);
323
324 MODULE_AUTHOR("Wesley Cheng <quic_wcheng@quicinc.com>");
325 MODULE_DESCRIPTION("eUSB2 Qualcomm M31 HSPHY driver");
326 MODULE_LICENSE("GPL");
327