1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12 #ifndef _UFSHCD_H
13 #define _UFSHCD_H
14
15 #include <linux/bitfield.h>
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
18 #include <linux/devfreq.h>
19 #include <linux/fault-inject.h>
20 #include <linux/debugfs.h>
21 #include <linux/msi.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/dma-direction.h>
24 #include <scsi/scsi_device.h>
25 #include <scsi/scsi_host.h>
26 #include <ufs/unipro.h>
27 #include <ufs/ufs.h>
28 #include <ufs/ufs_quirks.h>
29 #include <ufs/ufshci.h>
30
31 #define UFSHCD "ufshcd"
32
33 struct scsi_device;
34 struct ufs_hba;
35
36 enum dev_cmd_type {
37 DEV_CMD_TYPE_NOP = 0x0,
38 DEV_CMD_TYPE_QUERY = 0x1,
39 DEV_CMD_TYPE_RPMB = 0x2,
40 };
41
42 enum ufs_event_type {
43 /* uic specific errors */
44 UFS_EVT_PA_ERR = 0,
45 UFS_EVT_DL_ERR,
46 UFS_EVT_NL_ERR,
47 UFS_EVT_TL_ERR,
48 UFS_EVT_DME_ERR,
49
50 /* fatal errors */
51 UFS_EVT_AUTO_HIBERN8_ERR,
52 UFS_EVT_FATAL_ERR,
53 UFS_EVT_LINK_STARTUP_FAIL,
54 UFS_EVT_RESUME_ERR,
55 UFS_EVT_SUSPEND_ERR,
56 UFS_EVT_WL_SUSP_ERR,
57 UFS_EVT_WL_RES_ERR,
58
59 /* abnormal events */
60 UFS_EVT_DEV_RESET,
61 UFS_EVT_HOST_RESET,
62 UFS_EVT_ABORT,
63
64 UFS_EVT_CNT,
65 };
66
67 /**
68 * struct uic_command - UIC command structure
69 * @command: UIC command
70 * @argument1: UIC command argument 1
71 * @argument2: UIC command argument 2
72 * @argument3: UIC command argument 3
73 * @cmd_active: Indicate if UIC command is outstanding
74 * @done: UIC command completion
75 */
76 struct uic_command {
77 const u32 command;
78 const u32 argument1;
79 u32 argument2;
80 u32 argument3;
81 int cmd_active;
82 struct completion done;
83 };
84
85 /* Used to differentiate the power management options */
86 enum ufs_pm_op {
87 UFS_RUNTIME_PM,
88 UFS_SYSTEM_PM,
89 UFS_SHUTDOWN_PM,
90 };
91
92 /* Host <-> Device UniPro Link state */
93 enum uic_link_state {
94 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
95 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
96 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
97 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */
98 };
99
100 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
101 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
102 UIC_LINK_ACTIVE_STATE)
103 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
104 UIC_LINK_HIBERN8_STATE)
105 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
106 UIC_LINK_BROKEN_STATE)
107 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
108 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
109 UIC_LINK_ACTIVE_STATE)
110 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
111 UIC_LINK_HIBERN8_STATE)
112 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
113 UIC_LINK_BROKEN_STATE)
114
115 #define ufshcd_set_ufs_dev_active(h) \
116 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
117 #define ufshcd_set_ufs_dev_sleep(h) \
118 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
119 #define ufshcd_set_ufs_dev_poweroff(h) \
120 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
121 #define ufshcd_set_ufs_dev_deepsleep(h) \
122 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
123 #define ufshcd_is_ufs_dev_active(h) \
124 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
125 #define ufshcd_is_ufs_dev_sleep(h) \
126 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
127 #define ufshcd_is_ufs_dev_poweroff(h) \
128 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
129 #define ufshcd_is_ufs_dev_deepsleep(h) \
130 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
131
132 /*
133 * UFS Power management levels.
134 * Each level is in increasing order of power savings, except DeepSleep
135 * which is lower than PowerDown with power on but not PowerDown with
136 * power off.
137 */
138 enum ufs_pm_level {
139 UFS_PM_LVL_0,
140 UFS_PM_LVL_1,
141 UFS_PM_LVL_2,
142 UFS_PM_LVL_3,
143 UFS_PM_LVL_4,
144 UFS_PM_LVL_5,
145 UFS_PM_LVL_6,
146 UFS_PM_LVL_MAX
147 };
148
149 struct ufs_pm_lvl_states {
150 enum ufs_dev_pwr_mode dev_state;
151 enum uic_link_state link_state;
152 };
153
154 /**
155 * struct ufshcd_lrb - local reference block
156 * @utr_descriptor_ptr: UTRD address of the command
157 * @ucd_req_ptr: UCD address of the command
158 * @ucd_rsp_ptr: Response UPIU address for this command
159 * @ucd_prdt_ptr: PRDT address of the command
160 * @utrd_dma_addr: UTRD dma address for debug
161 * @ucd_prdt_dma_addr: PRDT dma address for debug
162 * @ucd_rsp_dma_addr: UPIU response dma address for debug
163 * @ucd_req_dma_addr: UPIU request dma address for debug
164 * @cmd: pointer to SCSI command
165 * @scsi_status: SCSI status of the command
166 * @command_type: SCSI, UFS, Query.
167 * @task_tag: Task tag of the command
168 * @lun: LUN of the command
169 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
170 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
171 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
172 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
173 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
174 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
175 * @data_unit_num: the data unit number for the first block for inline crypto
176 * @req_abort_skip: skip request abort task flag
177 */
178 struct ufshcd_lrb {
179 struct utp_transfer_req_desc *utr_descriptor_ptr;
180 struct utp_upiu_req *ucd_req_ptr;
181 struct utp_upiu_rsp *ucd_rsp_ptr;
182 struct ufshcd_sg_entry *ucd_prdt_ptr;
183
184 dma_addr_t utrd_dma_addr;
185 dma_addr_t ucd_req_dma_addr;
186 dma_addr_t ucd_rsp_dma_addr;
187 dma_addr_t ucd_prdt_dma_addr;
188
189 struct scsi_cmnd *cmd;
190 int scsi_status;
191
192 int command_type;
193 int task_tag;
194 u8 lun; /* UPIU LUN id field is only 8-bit wide */
195 bool intr_cmd;
196 ktime_t issue_time_stamp;
197 u64 issue_time_stamp_local_clock;
198 ktime_t compl_time_stamp;
199 u64 compl_time_stamp_local_clock;
200 #ifdef CONFIG_SCSI_UFS_CRYPTO
201 int crypto_key_slot;
202 u64 data_unit_num;
203 #endif
204
205 bool req_abort_skip;
206 };
207
208 /**
209 * struct ufs_query_req - parameters for building a query request
210 * @query_func: UPIU header query function
211 * @upiu_req: the query request data
212 */
213 struct ufs_query_req {
214 u8 query_func;
215 struct utp_upiu_query upiu_req;
216 };
217
218 /**
219 * struct ufs_query_resp - UPIU QUERY
220 * @response: device response code
221 * @upiu_res: query response data
222 */
223 struct ufs_query_res {
224 struct utp_upiu_query upiu_res;
225 };
226
227 /**
228 * struct ufs_query - holds relevant data structures for query request
229 * @request: request upiu and function
230 * @descriptor: buffer for sending/receiving descriptor
231 * @response: response upiu and response
232 */
233 struct ufs_query {
234 struct ufs_query_req request;
235 u8 *descriptor;
236 struct ufs_query_res response;
237 };
238
239 /**
240 * struct ufs_dev_cmd - all assosiated fields with device management commands
241 * @type: device management command type - Query, NOP OUT
242 * @lock: lock to allow one command at a time
243 * @complete: internal commands completion
244 * @query: Device management query information
245 */
246 struct ufs_dev_cmd {
247 enum dev_cmd_type type;
248 struct mutex lock;
249 struct completion *complete;
250 struct ufs_query query;
251 };
252
253 /**
254 * struct ufs_clk_info - UFS clock related info
255 * @list: list headed by hba->clk_list_head
256 * @clk: clock node
257 * @name: clock name
258 * @max_freq: maximum frequency supported by the clock
259 * @min_freq: min frequency that can be used for clock scaling
260 * @curr_freq: indicates the current frequency that it is set to
261 * @keep_link_active: indicates that the clk should not be disabled if
262 * link is active
263 * @enabled: variable to check against multiple enable/disable
264 */
265 struct ufs_clk_info {
266 struct list_head list;
267 struct clk *clk;
268 const char *name;
269 u32 max_freq;
270 u32 min_freq;
271 u32 curr_freq;
272 bool keep_link_active;
273 bool enabled;
274 };
275
276 enum ufs_notify_change_status {
277 PRE_CHANGE,
278 POST_CHANGE,
279 };
280
281 struct ufs_pa_layer_attr {
282 u32 gear_rx;
283 u32 gear_tx;
284 u32 lane_rx;
285 u32 lane_tx;
286 u32 pwr_rx;
287 u32 pwr_tx;
288 u32 hs_rate;
289 };
290
291 struct ufs_pwr_mode_info {
292 bool is_valid;
293 struct ufs_pa_layer_attr info;
294 };
295
296 /**
297 * struct ufs_hba_variant_ops - variant specific callbacks
298 * @name: variant name
299 * @max_num_rtt: maximum RTT supported by the host
300 * @init: called when the driver is initialized
301 * @exit: called to cleanup everything done in init
302 * @set_dma_mask: For setting another DMA mask than indicated by the 64AS
303 * capability bit.
304 * @get_ufs_hci_version: called to get UFS HCI version
305 * @clk_scale_notify: notifies that clks are scaled up/down
306 * @setup_clocks: called before touching any of the controller registers
307 * @hce_enable_notify: called before and after HCE enable bit is set to allow
308 * variant specific Uni-Pro initialization.
309 * @link_startup_notify: called before and after Link startup is carried out
310 * to allow variant specific Uni-Pro initialization.
311 * @pwr_change_notify: called before and after a power mode change
312 * is carried out to allow vendor spesific capabilities
313 * to be set. PRE_CHANGE can modify final_params based
314 * on desired_pwr_mode, but POST_CHANGE must not alter
315 * the final_params parameter
316 * @setup_xfer_req: called before any transfer request is issued
317 * to set some things
318 * @setup_task_mgmt: called before any task management request is issued
319 * to set some things
320 * @hibern8_notify: called around hibern8 enter/exit
321 * @apply_dev_quirks: called to apply device specific quirks
322 * @fixup_dev_quirks: called to modify device specific quirks
323 * @suspend: called during host controller PM callback
324 * @resume: called during host controller PM callback
325 * @dbg_register_dump: used to dump controller debug information
326 * @phy_initialization: used to initialize phys
327 * @device_reset: called to issue a reset pulse on the UFS device
328 * @config_scaling_param: called to configure clock scaling parameters
329 * @program_key: program or evict an inline encryption key
330 * @fill_crypto_prdt: initialize crypto-related fields in the PRDT
331 * @event_notify: called to notify important events
332 * @mcq_config_resource: called to configure MCQ platform resources
333 * @get_hba_mac: reports maximum number of outstanding commands supported by
334 * the controller. Should be implemented for UFSHCI 4.0 or later
335 * controllers that are not compliant with the UFSHCI 4.0 specification.
336 * @op_runtime_config: called to config Operation and runtime regs Pointers
337 * @get_outstanding_cqs: called to get outstanding completion queues
338 * @config_esi: called to config Event Specific Interrupt
339 * @config_scsi_dev: called to configure SCSI device parameters
340 */
341 struct ufs_hba_variant_ops {
342 const char *name;
343 int max_num_rtt;
344 int (*init)(struct ufs_hba *);
345 void (*exit)(struct ufs_hba *);
346 u32 (*get_ufs_hci_version)(struct ufs_hba *);
347 int (*set_dma_mask)(struct ufs_hba *);
348 int (*clk_scale_notify)(struct ufs_hba *, bool,
349 enum ufs_notify_change_status);
350 int (*setup_clocks)(struct ufs_hba *, bool,
351 enum ufs_notify_change_status);
352 int (*hce_enable_notify)(struct ufs_hba *,
353 enum ufs_notify_change_status);
354 int (*link_startup_notify)(struct ufs_hba *,
355 enum ufs_notify_change_status);
356 int (*pwr_change_notify)(struct ufs_hba *,
357 enum ufs_notify_change_status status,
358 struct ufs_pa_layer_attr *desired_pwr_mode,
359 struct ufs_pa_layer_attr *final_params);
360 void (*setup_xfer_req)(struct ufs_hba *hba, int tag,
361 bool is_scsi_cmd);
362 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
363 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
364 enum ufs_notify_change_status);
365 int (*apply_dev_quirks)(struct ufs_hba *hba);
366 void (*fixup_dev_quirks)(struct ufs_hba *hba);
367 int (*suspend)(struct ufs_hba *, enum ufs_pm_op,
368 enum ufs_notify_change_status);
369 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
370 void (*dbg_register_dump)(struct ufs_hba *hba);
371 int (*phy_initialization)(struct ufs_hba *);
372 int (*device_reset)(struct ufs_hba *hba);
373 void (*config_scaling_param)(struct ufs_hba *hba,
374 struct devfreq_dev_profile *profile,
375 struct devfreq_simple_ondemand_data *data);
376 int (*program_key)(struct ufs_hba *hba,
377 const union ufs_crypto_cfg_entry *cfg, int slot);
378 int (*fill_crypto_prdt)(struct ufs_hba *hba,
379 const struct bio_crypt_ctx *crypt_ctx,
380 void *prdt, unsigned int num_segments);
381 void (*event_notify)(struct ufs_hba *hba,
382 enum ufs_event_type evt, void *data);
383 int (*mcq_config_resource)(struct ufs_hba *hba);
384 int (*get_hba_mac)(struct ufs_hba *hba);
385 int (*op_runtime_config)(struct ufs_hba *hba);
386 int (*get_outstanding_cqs)(struct ufs_hba *hba,
387 unsigned long *ocqs);
388 int (*config_esi)(struct ufs_hba *hba);
389 void (*config_scsi_dev)(struct scsi_device *sdev);
390 };
391
392 /* clock gating state */
393 enum clk_gating_state {
394 CLKS_OFF,
395 CLKS_ON,
396 REQ_CLKS_OFF,
397 REQ_CLKS_ON,
398 };
399
400 /**
401 * struct ufs_clk_gating - UFS clock gating related info
402 * @gate_work: worker to turn off clocks after some delay as specified in
403 * delay_ms
404 * @ungate_work: worker to turn on clocks that will be used in case of
405 * interrupt context
406 * @state: the current clocks state
407 * @delay_ms: gating delay in ms
408 * @is_suspended: clk gating is suspended when set to 1 which can be used
409 * during suspend/resume
410 * @delay_attr: sysfs attribute to control delay_attr
411 * @enable_attr: sysfs attribute to enable/disable clock gating
412 * @is_enabled: Indicates the current status of clock gating
413 * @is_initialized: Indicates whether clock gating is initialized or not
414 * @active_reqs: number of requests that are pending and should be waited for
415 * completion before gating clocks.
416 * @clk_gating_workq: workqueue for clock gating work.
417 */
418 struct ufs_clk_gating {
419 struct delayed_work gate_work;
420 struct work_struct ungate_work;
421 enum clk_gating_state state;
422 unsigned long delay_ms;
423 bool is_suspended;
424 struct device_attribute delay_attr;
425 struct device_attribute enable_attr;
426 bool is_enabled;
427 bool is_initialized;
428 int active_reqs;
429 struct workqueue_struct *clk_gating_workq;
430 };
431
432 /**
433 * struct ufs_clk_scaling - UFS clock scaling related data
434 * @active_reqs: number of requests that are pending. If this is zero when
435 * devfreq ->target() function is called then schedule "suspend_work" to
436 * suspend devfreq.
437 * @tot_busy_t: Total busy time in current polling window
438 * @window_start_t: Start time (in jiffies) of the current polling window
439 * @busy_start_t: Start time of current busy period
440 * @enable_attr: sysfs attribute to enable/disable clock scaling
441 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
442 * one keeps track of previous power mode.
443 * @workq: workqueue to schedule devfreq suspend/resume work
444 * @suspend_work: worker to suspend devfreq
445 * @resume_work: worker to resume devfreq
446 * @target_freq: frequency requested by devfreq framework
447 * @min_gear: lowest HS gear to scale down to
448 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
449 * clkscale_enable sysfs node
450 * @is_allowed: tracks if scaling is currently allowed or not, used to block
451 * clock scaling which is not invoked from devfreq governor
452 * @is_initialized: Indicates whether clock scaling is initialized or not
453 * @is_busy_started: tracks if busy period has started or not
454 * @is_suspended: tracks if devfreq is suspended or not
455 */
456 struct ufs_clk_scaling {
457 int active_reqs;
458 unsigned long tot_busy_t;
459 ktime_t window_start_t;
460 ktime_t busy_start_t;
461 struct device_attribute enable_attr;
462 struct ufs_pa_layer_attr saved_pwr_info;
463 struct workqueue_struct *workq;
464 struct work_struct suspend_work;
465 struct work_struct resume_work;
466 unsigned long target_freq;
467 u32 min_gear;
468 bool is_enabled;
469 bool is_allowed;
470 bool is_initialized;
471 bool is_busy_started;
472 bool is_suspended;
473 bool suspend_on_no_request;
474 };
475
476 #define UFS_EVENT_HIST_LENGTH 8
477 /**
478 * struct ufs_event_hist - keeps history of errors
479 * @pos: index to indicate cyclic buffer position
480 * @val: cyclic buffer for registers value
481 * @tstamp: cyclic buffer for time stamp
482 * @cnt: error counter
483 */
484 struct ufs_event_hist {
485 int pos;
486 u32 val[UFS_EVENT_HIST_LENGTH];
487 u64 tstamp[UFS_EVENT_HIST_LENGTH];
488 unsigned long long cnt;
489 };
490
491 /**
492 * struct ufs_stats - keeps usage/err statistics
493 * @last_intr_status: record the last interrupt status.
494 * @last_intr_ts: record the last interrupt timestamp.
495 * @hibern8_exit_cnt: Counter to keep track of number of exits,
496 * reset this after link-startup.
497 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
498 * Clear after the first successful command completion.
499 * @event: array with event history.
500 */
501 struct ufs_stats {
502 u32 last_intr_status;
503 u64 last_intr_ts;
504
505 u32 hibern8_exit_cnt;
506 u64 last_hibern8_exit_tstamp;
507 struct ufs_event_hist event[UFS_EVT_CNT];
508 };
509
510 /**
511 * enum ufshcd_state - UFS host controller state
512 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
513 * processing.
514 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
515 * SCSI commands.
516 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
517 * SCSI commands may be submitted to the controller.
518 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
519 * newly submitted SCSI commands with error code DID_BAD_TARGET.
520 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
521 * failed. Fail all SCSI commands with error code DID_ERROR.
522 */
523 enum ufshcd_state {
524 UFSHCD_STATE_RESET,
525 UFSHCD_STATE_OPERATIONAL,
526 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
527 UFSHCD_STATE_EH_SCHEDULED_FATAL,
528 UFSHCD_STATE_ERROR,
529 };
530
531 enum ufshcd_quirks {
532 /* Interrupt aggregation support is broken */
533 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
534
535 /*
536 * delay before each dme command is required as the unipro
537 * layer has shown instabilities
538 */
539 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
540
541 /*
542 * If UFS host controller is having issue in processing LCC (Line
543 * Control Command) coming from device then enable this quirk.
544 * When this quirk is enabled, host controller driver should disable
545 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
546 * attribute of device to 0).
547 */
548 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
549
550 /*
551 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
552 * inbound Link supports unterminated line in HS mode. Setting this
553 * attribute to 1 fixes moving to HS gear.
554 */
555 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
556
557 /*
558 * This quirk needs to be enabled if the host controller only allows
559 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
560 * SLOW AUTO).
561 */
562 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
563
564 /*
565 * This quirk needs to be enabled if the host controller doesn't
566 * advertise the correct version in UFS_VER register. If this quirk
567 * is enabled, standard UFS host driver will call the vendor specific
568 * ops (get_ufs_hci_version) to get the correct version.
569 */
570 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
571
572 /*
573 * Clear handling for transfer/task request list is just opposite.
574 */
575 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
576
577 /*
578 * This quirk needs to be enabled if host controller doesn't allow
579 * that the interrupt aggregation timer and counter are reset by s/w.
580 */
581 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
582
583 /*
584 * This quirks needs to be enabled if host controller cannot be
585 * enabled via HCE register.
586 */
587 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
588
589 /*
590 * This quirk needs to be enabled if the host controller regards
591 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
592 */
593 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
594
595 /*
596 * This quirk needs to be enabled if the host controller reports
597 * OCS FATAL ERROR with device error through sense data
598 */
599 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
600
601 /*
602 * This quirk needs to be enabled if the host controller has
603 * auto-hibernate capability but it doesn't work.
604 */
605 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
606
607 /*
608 * This quirk needs to disable manual flush for write booster
609 */
610 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
611
612 /*
613 * This quirk needs to disable unipro timeout values
614 * before power mode change
615 */
616 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
617
618 /*
619 * This quirk needs to be enabled if the host controller does not
620 * support UIC command
621 */
622 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,
623
624 /*
625 * This quirk needs to be enabled if the host controller cannot
626 * support physical host configuration.
627 */
628 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,
629
630 /*
631 * This quirk needs to be enabled if the host controller has
632 * auto-hibernate capability but it's FASTAUTO only.
633 */
634 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
635
636 /*
637 * This quirk needs to be enabled if the host controller needs
638 * to reinit the device after switching to maximum gear.
639 */
640 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
641
642 /*
643 * Some host raises interrupt (per queue) in addition to
644 * CQES (traditional) when ESI is disabled.
645 * Enable this quirk will disable CQES and use per queue interrupt.
646 */
647 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,
648
649 /*
650 * Some host does not implement SQ Run Time Command (SQRTC) register
651 * thus need this quirk to skip related flow.
652 */
653 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
654
655 /*
656 * This quirk needs to be enabled if the host controller supports inline
657 * encryption but it needs to initialize the crypto capabilities in a
658 * nonstandard way and/or needs to override blk_crypto_ll_ops. If
659 * enabled, the standard code won't initialize the blk_crypto_profile;
660 * ufs_hba_variant_ops::init() must do it instead.
661 */
662 UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22,
663
664 /*
665 * This quirk needs to be enabled if the host controller supports inline
666 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
667 * host controller initialization fails if that bit is set.
668 */
669 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23,
670
671 /*
672 * This quirk needs to be enabled if the host controller driver copies
673 * cryptographic keys into the PRDT in order to send them to hardware,
674 * and therefore the PRDT should be zeroized after each request (as per
675 * the standard best practice for managing keys).
676 */
677 UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24,
678
679 /*
680 * This quirk indicates that the controller reports the value 1 (not
681 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
682 * Controller Capabilities register although it supports the legacy
683 * single doorbell mode.
684 */
685 UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25,
686 };
687
688 enum ufshcd_caps {
689 /* Allow dynamic clk gating */
690 UFSHCD_CAP_CLK_GATING = 1 << 0,
691
692 /* Allow hiberb8 with clk gating */
693 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
694
695 /* Allow dynamic clk scaling */
696 UFSHCD_CAP_CLK_SCALING = 1 << 2,
697
698 /* Allow auto bkops to enabled during runtime suspend */
699 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
700
701 /*
702 * This capability allows host controller driver to use the UFS HCI's
703 * interrupt aggregation capability.
704 * CAUTION: Enabling this might reduce overall UFS throughput.
705 */
706 UFSHCD_CAP_INTR_AGGR = 1 << 4,
707
708 /*
709 * This capability allows the device auto-bkops to be always enabled
710 * except during suspend (both runtime and suspend).
711 * Enabling this capability means that device will always be allowed
712 * to do background operation when it's active but it might degrade
713 * the performance of ongoing read/write operations.
714 */
715 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
716
717 /*
718 * This capability allows host controller driver to automatically
719 * enable runtime power management by itself instead of waiting
720 * for userspace to control the power management.
721 */
722 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
723
724 /*
725 * This capability allows the host controller driver to turn-on
726 * WriteBooster, if the underlying device supports it and is
727 * provisioned to be used. This would increase the write performance.
728 */
729 UFSHCD_CAP_WB_EN = 1 << 7,
730
731 /*
732 * This capability allows the host controller driver to use the
733 * inline crypto engine, if it is present
734 */
735 UFSHCD_CAP_CRYPTO = 1 << 8,
736
737 /*
738 * This capability allows the controller regulators to be put into
739 * lpm mode aggressively during clock gating.
740 * This would increase power savings.
741 */
742 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,
743
744 /*
745 * This capability allows the host controller driver to use DeepSleep,
746 * if it is supported by the UFS device. The host controller driver must
747 * support device hardware reset via the hba->device_reset() callback,
748 * in order to exit DeepSleep state.
749 */
750 UFSHCD_CAP_DEEPSLEEP = 1 << 10,
751
752 /*
753 * This capability allows the host controller driver to use temperature
754 * notification if it is supported by the UFS device.
755 */
756 UFSHCD_CAP_TEMP_NOTIF = 1 << 11,
757
758 /*
759 * Enable WriteBooster when scaling up the clock and disable
760 * WriteBooster when scaling the clock down.
761 */
762 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,
763 };
764
765 struct ufs_hba_variant_params {
766 struct devfreq_dev_profile devfreq_profile;
767 struct devfreq_simple_ondemand_data ondemand_data;
768 u16 hba_enable_delay_us;
769 u32 wb_flush_threshold;
770 };
771
772 struct ufs_hba_monitor {
773 unsigned long chunk_size;
774
775 unsigned long nr_sec_rw[2];
776 ktime_t total_busy[2];
777
778 unsigned long nr_req[2];
779 /* latencies*/
780 ktime_t lat_sum[2];
781 ktime_t lat_max[2];
782 ktime_t lat_min[2];
783
784 u32 nr_queued[2];
785 ktime_t busy_start_ts[2];
786
787 ktime_t enabled_ts;
788 bool enabled;
789 };
790
791 /**
792 * struct ufshcd_res_info_t - MCQ related resource regions
793 *
794 * @name: resource name
795 * @resource: pointer to resource region
796 * @base: register base address
797 */
798 struct ufshcd_res_info {
799 const char *name;
800 struct resource *resource;
801 void __iomem *base;
802 };
803
804 enum ufshcd_res {
805 RES_UFS,
806 RES_MCQ,
807 RES_MCQ_SQD,
808 RES_MCQ_SQIS,
809 RES_MCQ_CQD,
810 RES_MCQ_CQIS,
811 RES_MCQ_VS,
812 RES_MAX,
813 };
814
815 /**
816 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
817 *
818 * @offset: Doorbell Address Offset
819 * @stride: Steps proportional to queue [0...31]
820 * @base: base address
821 */
822 struct ufshcd_mcq_opr_info_t {
823 unsigned long offset;
824 unsigned long stride;
825 void __iomem *base;
826 };
827
828 enum ufshcd_mcq_opr {
829 OPR_SQD,
830 OPR_SQIS,
831 OPR_CQD,
832 OPR_CQIS,
833 OPR_MAX,
834 };
835
836 /**
837 * struct ufs_hba - per adapter private structure
838 * @mmio_base: UFSHCI base register address
839 * @ucdl_base_addr: UFS Command Descriptor base address
840 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
841 * @utmrdl_base_addr: UTP Task Management Descriptor base address
842 * @ucdl_dma_addr: UFS Command Descriptor DMA address
843 * @utrdl_dma_addr: UTRDL DMA address
844 * @utmrdl_dma_addr: UTMRDL DMA address
845 * @host: Scsi_Host instance of the driver
846 * @dev: device handle
847 * @ufs_device_wlun: WLUN that controls the entire UFS device.
848 * @hwmon_device: device instance registered with the hwmon core.
849 * @curr_dev_pwr_mode: active UFS device power mode.
850 * @uic_link_state: active state of the link to the UFS device.
851 * @rpm_lvl: desired UFS power management level during runtime PM.
852 * @spm_lvl: desired UFS power management level during system PM.
853 * @pm_op_in_progress: whether or not a PM operation is in progress.
854 * @ahit: value of Auto-Hibernate Idle Timer register.
855 * @lrb: local reference block
856 * @outstanding_tasks: Bits representing outstanding task requests
857 * @outstanding_lock: Protects @outstanding_reqs.
858 * @outstanding_reqs: Bits representing outstanding transfer requests
859 * @capabilities: UFS Controller Capabilities
860 * @mcq_capabilities: UFS Multi Circular Queue capabilities
861 * @nutrs: Transfer Request Queue depth supported by controller
862 * @nortt - Max outstanding RTTs supported by controller
863 * @nutmrs: Task Management Queue depth supported by controller
864 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
865 * @ufs_version: UFS Version to which controller complies
866 * @vops: pointer to variant specific operations
867 * @vps: pointer to variant specific parameters
868 * @priv: pointer to variant specific private data
869 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
870 * @irq: Irq number of the controller
871 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
872 * @dev_ref_clk_freq: reference clock frequency
873 * @quirks: bitmask with information about deviations from the UFSHCI standard.
874 * @dev_quirks: bitmask with information about deviations from the UFS standard.
875 * @tmf_tag_set: TMF tag set.
876 * @tmf_queue: Used to allocate TMF tags.
877 * @tmf_rqs: array with pointers to TMF requests while these are in progress.
878 * @active_uic_cmd: pointer to active UIC command.
879 * @uic_cmd_mutex: mutex used for serializing UIC command processing.
880 * @uic_async_done: completion used to wait for power mode or hibernation state
881 * changes.
882 * @ufshcd_state: UFSHCD state
883 * @eh_flags: Error handling flags
884 * @intr_mask: Interrupt Mask Bits
885 * @ee_ctrl_mask: Exception event control mask
886 * @ee_drv_mask: Exception event mask for driver
887 * @ee_usr_mask: Exception event mask for user (set via debugfs)
888 * @ee_ctrl_mutex: Used to serialize exception event information.
889 * @is_powered: flag to check if HBA is powered
890 * @shutting_down: flag to check if shutdown has been invoked
891 * @host_sem: semaphore used to serialize concurrent contexts
892 * @eh_wq: Workqueue that eh_work works on
893 * @eh_work: Worker to handle UFS errors that require s/w attention
894 * @eeh_work: Worker to handle exception events
895 * @errors: HBA errors
896 * @uic_error: UFS interconnect layer error status
897 * @saved_err: sticky error mask
898 * @saved_uic_err: sticky UIC error mask
899 * @ufs_stats: various error counters
900 * @force_reset: flag to force eh_work perform a full reset
901 * @force_pmc: flag to force a power mode change
902 * @silence_err_logs: flag to silence error logs
903 * @dev_cmd: ufs device management command information
904 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
905 * @nop_out_timeout: NOP OUT timeout value
906 * @dev_info: information about the UFS device
907 * @auto_bkops_enabled: to track whether bkops is enabled in device
908 * @vreg_info: UFS device voltage regulator information
909 * @clk_list_head: UFS host controller clocks list node head
910 * @use_pm_opp: Indicates whether OPP based scaling is used or not
911 * @req_abort_count: number of times ufshcd_abort() has been called
912 * @lanes_per_direction: number of lanes per data direction between the UFS
913 * controller and the UFS device.
914 * @pwr_info: holds current power mode
915 * @max_pwr_info: keeps the device max valid pwm
916 * @clk_gating: information related to clock gating
917 * @caps: bitmask with information about UFS controller capabilities
918 * @devfreq: frequency scaling information owned by the devfreq core
919 * @clk_scaling: frequency scaling information owned by the UFS driver
920 * @system_suspending: system suspend has been started and system resume has
921 * not yet finished.
922 * @is_sys_suspended: UFS device has been suspended because of system suspend
923 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
924 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
925 * device is known or not.
926 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
927 * @clk_scaling_lock: used to serialize device commands and clock scaling
928 * @desc_size: descriptor sizes reported by device
929 * @bsg_dev: struct device associated with the BSG queue
930 * @bsg_queue: BSG queue associated with the UFS controller
931 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
932 * management) after the UFS device has finished a WriteBooster buffer
933 * flush or auto BKOP.
934 * @monitor: statistics about UFS commands
935 * @crypto_capabilities: Content of crypto capabilities register (0x100)
936 * @crypto_cap_array: Array of crypto capabilities
937 * @crypto_cfg_register: Start of the crypto cfg array
938 * @crypto_profile: the crypto profile of this hba (if applicable)
939 * @debugfs_root: UFS controller debugfs root directory
940 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
941 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
942 * ee_ctrl_mask
943 * @luns_avail: number of regular and well known LUNs supported by the UFS
944 * device
945 * @nr_hw_queues: number of hardware queues configured
946 * @nr_queues: number of Queues of different queue types
947 * @complete_put: whether or not to call ufshcd_rpm_put() from inside
948 * ufshcd_resume_complete()
949 * @ext_iid_sup: is EXT_IID is supported by UFSHC
950 * @mcq_sup: is mcq supported by UFSHC
951 * @mcq_enabled: is mcq ready to accept requests
952 * @res: array of resource info of MCQ registers
953 * @mcq_base: Multi circular queue registers base address
954 * @uhq: array of supported hardware queues
955 * @dev_cmd_queue: Queue for issuing device management commands
956 * @mcq_opr: MCQ operation and runtime registers
957 * @ufs_rtc_update_work: A work for UFS RTC periodic update
958 * @pm_qos_req: PM QoS request handle
959 * @pm_qos_enabled: flag to check if pm qos is enabled
960 */
961 struct ufs_hba {
962 void __iomem *mmio_base;
963
964 /* Virtual memory reference */
965 struct utp_transfer_cmd_desc *ucdl_base_addr;
966 struct utp_transfer_req_desc *utrdl_base_addr;
967 struct utp_task_req_desc *utmrdl_base_addr;
968
969 /* DMA memory reference */
970 dma_addr_t ucdl_dma_addr;
971 dma_addr_t utrdl_dma_addr;
972 dma_addr_t utmrdl_dma_addr;
973
974 struct Scsi_Host *host;
975 struct device *dev;
976 struct scsi_device *ufs_device_wlun;
977
978 #ifdef CONFIG_SCSI_UFS_HWMON
979 struct device *hwmon_device;
980 #endif
981
982 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
983 enum uic_link_state uic_link_state;
984 /* Desired UFS power management level during runtime PM */
985 enum ufs_pm_level rpm_lvl;
986 /* Desired UFS power management level during system PM */
987 enum ufs_pm_level spm_lvl;
988 int pm_op_in_progress;
989
990 /* Auto-Hibernate Idle Timer register value */
991 u32 ahit;
992
993 struct ufshcd_lrb *lrb;
994
995 unsigned long outstanding_tasks;
996 spinlock_t outstanding_lock;
997 unsigned long outstanding_reqs;
998
999 u32 capabilities;
1000 int nutrs;
1001 int nortt;
1002 u32 mcq_capabilities;
1003 int nutmrs;
1004 u32 reserved_slot;
1005 u32 ufs_version;
1006 const struct ufs_hba_variant_ops *vops;
1007 struct ufs_hba_variant_params *vps;
1008 void *priv;
1009 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1010 size_t sg_entry_size;
1011 #endif
1012 unsigned int irq;
1013 bool is_irq_enabled;
1014 enum ufs_ref_clk_freq dev_ref_clk_freq;
1015
1016 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
1017
1018 /* Device deviations from standard UFS device spec. */
1019 unsigned int dev_quirks;
1020
1021 struct blk_mq_tag_set tmf_tag_set;
1022 struct request_queue *tmf_queue;
1023 struct request **tmf_rqs;
1024
1025 struct uic_command *active_uic_cmd;
1026 struct mutex uic_cmd_mutex;
1027 struct completion *uic_async_done;
1028
1029 enum ufshcd_state ufshcd_state;
1030 u32 eh_flags;
1031 u32 intr_mask;
1032 u16 ee_ctrl_mask;
1033 u16 ee_drv_mask;
1034 u16 ee_usr_mask;
1035 struct mutex ee_ctrl_mutex;
1036 bool is_powered;
1037 bool shutting_down;
1038 struct semaphore host_sem;
1039
1040 /* Work Queues */
1041 struct workqueue_struct *eh_wq;
1042 struct work_struct eh_work;
1043 struct work_struct eeh_work;
1044
1045 /* HBA Errors */
1046 u32 errors;
1047 u32 uic_error;
1048 u32 saved_err;
1049 u32 saved_uic_err;
1050 struct ufs_stats ufs_stats;
1051 bool force_reset;
1052 bool force_pmc;
1053 bool silence_err_logs;
1054
1055 /* Device management request data */
1056 struct ufs_dev_cmd dev_cmd;
1057 ktime_t last_dme_cmd_tstamp;
1058 int nop_out_timeout;
1059
1060 /* Keeps information of the UFS device connected to this host */
1061 struct ufs_dev_info dev_info;
1062 bool auto_bkops_enabled;
1063 struct ufs_vreg_info vreg_info;
1064 struct list_head clk_list_head;
1065 bool use_pm_opp;
1066
1067 /* Number of requests aborts */
1068 int req_abort_count;
1069
1070 /* Number of lanes available (1 or 2) for Rx/Tx */
1071 u32 lanes_per_direction;
1072 struct ufs_pa_layer_attr pwr_info;
1073 struct ufs_pwr_mode_info max_pwr_info;
1074
1075 struct ufs_clk_gating clk_gating;
1076 /* Control to enable/disable host capabilities */
1077 u32 caps;
1078
1079 struct devfreq *devfreq;
1080 struct ufs_clk_scaling clk_scaling;
1081 bool system_suspending;
1082 bool is_sys_suspended;
1083
1084 enum bkops_status urgent_bkops_lvl;
1085 bool is_urgent_bkops_lvl_checked;
1086
1087 struct mutex wb_mutex;
1088 struct rw_semaphore clk_scaling_lock;
1089
1090 struct device bsg_dev;
1091 struct request_queue *bsg_queue;
1092 struct delayed_work rpm_dev_flush_recheck_work;
1093
1094 struct ufs_hba_monitor monitor;
1095
1096 #ifdef CONFIG_SCSI_UFS_CRYPTO
1097 union ufs_crypto_capabilities crypto_capabilities;
1098 union ufs_crypto_cap_entry *crypto_cap_array;
1099 u32 crypto_cfg_register;
1100 struct blk_crypto_profile crypto_profile;
1101 #endif
1102 #ifdef CONFIG_DEBUG_FS
1103 struct dentry *debugfs_root;
1104 struct delayed_work debugfs_ee_work;
1105 u32 debugfs_ee_rate_limit_ms;
1106 #endif
1107 #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION
1108 struct fault_attr trigger_eh_attr;
1109 struct fault_attr timeout_attr;
1110 #endif
1111 u32 luns_avail;
1112 unsigned int nr_hw_queues;
1113 unsigned int nr_queues[HCTX_MAX_TYPES];
1114 bool complete_put;
1115 bool ext_iid_sup;
1116 bool scsi_host_added;
1117 bool mcq_sup;
1118 bool lsdb_sup;
1119 bool mcq_enabled;
1120 struct ufshcd_res_info res[RES_MAX];
1121 void __iomem *mcq_base;
1122 struct ufs_hw_queue *uhq;
1123 struct ufs_hw_queue *dev_cmd_queue;
1124 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1125
1126 struct delayed_work ufs_rtc_update_work;
1127 struct pm_qos_request pm_qos_req;
1128 bool pm_qos_enabled;
1129 };
1130
1131 /**
1132 * struct ufs_hw_queue - per hardware queue structure
1133 * @mcq_sq_head: base address of submission queue head pointer
1134 * @mcq_sq_tail: base address of submission queue tail pointer
1135 * @mcq_cq_head: base address of completion queue head pointer
1136 * @mcq_cq_tail: base address of completion queue tail pointer
1137 * @sqe_base_addr: submission queue entry base address
1138 * @sqe_dma_addr: submission queue dma address
1139 * @cqe_base_addr: completion queue base address
1140 * @cqe_dma_addr: completion queue dma address
1141 * @max_entries: max number of slots in this hardware queue
1142 * @id: hardware queue ID
1143 * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1144 * @sq_lock: serialize submission queue access
1145 * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1146 * @cq_head_slot: current slot to which CQ head pointer is pointing
1147 * @cq_lock: Synchronize between multiple polling instances
1148 * @sq_mutex: prevent submission queue concurrent access
1149 */
1150 struct ufs_hw_queue {
1151 void __iomem *mcq_sq_head;
1152 void __iomem *mcq_sq_tail;
1153 void __iomem *mcq_cq_head;
1154 void __iomem *mcq_cq_tail;
1155
1156 struct utp_transfer_req_desc *sqe_base_addr;
1157 dma_addr_t sqe_dma_addr;
1158 struct cq_entry *cqe_base_addr;
1159 dma_addr_t cqe_dma_addr;
1160 u32 max_entries;
1161 u32 id;
1162 u32 sq_tail_slot;
1163 spinlock_t sq_lock;
1164 u32 cq_tail_slot;
1165 u32 cq_head_slot;
1166 spinlock_t cq_lock;
1167 /* prevent concurrent access to submission queue */
1168 struct mutex sq_mutex;
1169 };
1170
1171 #define MCQ_QCFG_SIZE 0x40
1172
ufshcd_mcq_opr_offset(struct ufs_hba * hba,enum ufshcd_mcq_opr opr,int idx)1173 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,
1174 enum ufshcd_mcq_opr opr, int idx)
1175 {
1176 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1177 }
1178
ufshcd_mcq_cfg_offset(unsigned int reg,int idx)1179 static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx)
1180 {
1181 return reg + MCQ_QCFG_SIZE * idx;
1182 }
1183
1184 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
ufshcd_sg_entry_size(const struct ufs_hba * hba)1185 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1186 {
1187 return hba->sg_entry_size;
1188 }
1189
ufshcd_set_sg_entry_size(struct ufs_hba * hba,size_t sg_entry_size)1190 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1191 {
1192 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1193 hba->sg_entry_size = sg_entry_size;
1194 }
1195 #else
ufshcd_sg_entry_size(const struct ufs_hba * hba)1196 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1197 {
1198 return sizeof(struct ufshcd_sg_entry);
1199 }
1200
1201 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \
1202 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1203 #endif
1204
ufshcd_get_ucd_size(const struct ufs_hba * hba)1205 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1206 {
1207 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1208 }
1209
1210 /* Returns true if clocks can be gated. Otherwise false */
ufshcd_is_clkgating_allowed(struct ufs_hba * hba)1211 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1212 {
1213 return hba->caps & UFSHCD_CAP_CLK_GATING;
1214 }
ufshcd_can_hibern8_during_gating(struct ufs_hba * hba)1215 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1216 {
1217 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1218 }
ufshcd_is_clkscaling_supported(struct ufs_hba * hba)1219 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1220 {
1221 return hba->caps & UFSHCD_CAP_CLK_SCALING;
1222 }
ufshcd_can_autobkops_during_suspend(struct ufs_hba * hba)1223 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1224 {
1225 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1226 }
ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba * hba)1227 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1228 {
1229 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1230 }
1231
ufshcd_is_intr_aggr_allowed(struct ufs_hba * hba)1232 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1233 {
1234 return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1235 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1236 }
1237
ufshcd_can_aggressive_pc(struct ufs_hba * hba)1238 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1239 {
1240 return !!(ufshcd_is_link_hibern8(hba) &&
1241 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1242 }
1243
ufshcd_is_auto_hibern8_supported(struct ufs_hba * hba)1244 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1245 {
1246 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1247 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1248 }
1249
ufshcd_is_auto_hibern8_enabled(struct ufs_hba * hba)1250 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1251 {
1252 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1253 }
1254
ufshcd_is_wb_allowed(struct ufs_hba * hba)1255 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1256 {
1257 return hba->caps & UFSHCD_CAP_WB_EN;
1258 }
1259
ufshcd_enable_wb_if_scaling_up(struct ufs_hba * hba)1260 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1261 {
1262 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1263 }
1264
1265 #define ufsmcq_writel(hba, val, reg) \
1266 writel((val), (hba)->mcq_base + (reg))
1267 #define ufsmcq_readl(hba, reg) \
1268 readl((hba)->mcq_base + (reg))
1269
1270 #define ufsmcq_writelx(hba, val, reg) \
1271 writel_relaxed((val), (hba)->mcq_base + (reg))
1272 #define ufsmcq_readlx(hba, reg) \
1273 readl_relaxed((hba)->mcq_base + (reg))
1274
1275 #define ufshcd_writel(hba, val, reg) \
1276 writel((val), (hba)->mmio_base + (reg))
1277 #define ufshcd_readl(hba, reg) \
1278 readl((hba)->mmio_base + (reg))
1279
1280 /**
1281 * ufshcd_rmwl - perform read/modify/write for a controller register
1282 * @hba: per adapter instance
1283 * @mask: mask to apply on read value
1284 * @val: actual value to write
1285 * @reg: register address
1286 */
ufshcd_rmwl(struct ufs_hba * hba,u32 mask,u32 val,u32 reg)1287 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1288 {
1289 u32 tmp;
1290
1291 tmp = ufshcd_readl(hba, reg);
1292 tmp &= ~mask;
1293 tmp |= (val & mask);
1294 ufshcd_writel(hba, tmp, reg);
1295 }
1296
1297 void ufshcd_enable_irq(struct ufs_hba *hba);
1298 void ufshcd_disable_irq(struct ufs_hba *hba);
1299 int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1300 void ufshcd_dealloc_host(struct ufs_hba *);
1301 int ufshcd_hba_enable(struct ufs_hba *hba);
1302 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1303 int ufshcd_link_recovery(struct ufs_hba *hba);
1304 int ufshcd_make_hba_operational(struct ufs_hba *hba);
1305 void ufshcd_remove(struct ufs_hba *);
1306 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1307 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1308 void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1309 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1310 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1311 void ufshcd_hba_stop(struct ufs_hba *hba);
1312 void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1313 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);
1314 unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba);
1315 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);
1316 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1317 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1318 struct ufs_hw_queue *hwq);
1319 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
1320 void ufshcd_mcq_enable(struct ufs_hba *hba);
1321 void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1322 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1323
1324 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1325 struct dev_pm_opp *opp, void *data,
1326 bool scaling_down);
1327 /**
1328 * ufshcd_set_variant - set variant specific data to the hba
1329 * @hba: per adapter instance
1330 * @variant: pointer to variant specific data
1331 */
ufshcd_set_variant(struct ufs_hba * hba,void * variant)1332 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1333 {
1334 BUG_ON(!hba);
1335 hba->priv = variant;
1336 }
1337
1338 /**
1339 * ufshcd_get_variant - get variant specific data from the hba
1340 * @hba: per adapter instance
1341 */
ufshcd_get_variant(struct ufs_hba * hba)1342 static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1343 {
1344 BUG_ON(!hba);
1345 return hba->priv;
1346 }
1347
1348 #ifdef CONFIG_PM
1349 extern int ufshcd_runtime_suspend(struct device *dev);
1350 extern int ufshcd_runtime_resume(struct device *dev);
1351 #endif
1352 #ifdef CONFIG_PM_SLEEP
1353 extern int ufshcd_system_suspend(struct device *dev);
1354 extern int ufshcd_system_resume(struct device *dev);
1355 extern int ufshcd_system_freeze(struct device *dev);
1356 extern int ufshcd_system_thaw(struct device *dev);
1357 extern int ufshcd_system_restore(struct device *dev);
1358 #endif
1359
1360 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1361 int agreed_gear,
1362 int adapt_val);
1363 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1364 u8 attr_set, u32 mib_val, u8 peer);
1365 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1366 u32 *mib_val, u8 peer);
1367 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1368 struct ufs_pa_layer_attr *desired_pwr_mode);
1369 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1370
1371 /* UIC command interfaces for DME primitives */
1372 #define DME_LOCAL 0
1373 #define DME_PEER 1
1374 #define ATTR_SET_NOR 0 /* NORMAL */
1375 #define ATTR_SET_ST 1 /* STATIC */
1376
ufshcd_dme_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1377 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1378 u32 mib_val)
1379 {
1380 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1381 mib_val, DME_LOCAL);
1382 }
1383
ufshcd_dme_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1384 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1385 u32 mib_val)
1386 {
1387 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1388 mib_val, DME_LOCAL);
1389 }
1390
ufshcd_dme_peer_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1391 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1392 u32 mib_val)
1393 {
1394 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1395 mib_val, DME_PEER);
1396 }
1397
ufshcd_dme_peer_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1398 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1399 u32 mib_val)
1400 {
1401 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1402 mib_val, DME_PEER);
1403 }
1404
ufshcd_dme_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1405 static inline int ufshcd_dme_get(struct ufs_hba *hba,
1406 u32 attr_sel, u32 *mib_val)
1407 {
1408 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1409 }
1410
ufshcd_dme_peer_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1411 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1412 u32 attr_sel, u32 *mib_val)
1413 {
1414 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1415 }
1416
ufshcd_is_hs_mode(struct ufs_pa_layer_attr * pwr_info)1417 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
1418 {
1419 return (pwr_info->pwr_rx == FAST_MODE ||
1420 pwr_info->pwr_rx == FASTAUTO_MODE) &&
1421 (pwr_info->pwr_tx == FAST_MODE ||
1422 pwr_info->pwr_tx == FASTAUTO_MODE);
1423 }
1424
ufshcd_disable_host_tx_lcc(struct ufs_hba * hba)1425 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1426 {
1427 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1428 }
1429
1430 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1431 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1432 const struct ufs_dev_quirk *fixups);
1433 #define SD_ASCII_STD true
1434 #define SD_RAW false
1435 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1436 u8 **buf, bool ascii);
1437
1438 void ufshcd_hold(struct ufs_hba *hba);
1439 void ufshcd_release(struct ufs_hba *hba);
1440
1441 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1442
1443 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1444
1445 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1446
1447 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1448 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1449 struct ufs_ehs *ehs_rsp, int sg_cnt,
1450 struct scatterlist *sg_list, enum dma_data_direction dir);
1451 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1452 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1453 int ufshcd_suspend_prepare(struct device *dev);
1454 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1455 void ufshcd_resume_complete(struct device *dev);
1456 bool ufshcd_is_hba_active(struct ufs_hba *hba);
1457 void ufshcd_pm_qos_init(struct ufs_hba *hba);
1458 void ufshcd_pm_qos_exit(struct ufs_hba *hba);
1459
1460 /* Wrapper functions for safely calling variant operations */
ufshcd_vops_init(struct ufs_hba * hba)1461 static inline int ufshcd_vops_init(struct ufs_hba *hba)
1462 {
1463 if (hba->vops && hba->vops->init)
1464 return hba->vops->init(hba);
1465
1466 return 0;
1467 }
1468
ufshcd_vops_phy_initialization(struct ufs_hba * hba)1469 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1470 {
1471 if (hba->vops && hba->vops->phy_initialization)
1472 return hba->vops->phy_initialization(hba);
1473
1474 return 0;
1475 }
1476
1477 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1478
1479 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1480 const char *prefix);
1481
1482 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1483 int ufshcd_write_ee_control(struct ufs_hba *hba);
1484 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1485 const u16 *other_mask, u16 set, u16 clr);
1486
1487 #endif /* End of Header */
1488