1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers 4 * 5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) 6 * Copyright (C) 2003 Robert Schwebel, Pengutronix 7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix 8 * Copyright (C) 2003 David Brownell 9 * Copyright (C) 2003 Joshua Wise 10 */ 11 12 /* #define VERBOSE_DEBUG */ 13 14 #include <linux/device.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/ioport.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/slab.h> 24 #include <linux/timer.h> 25 #include <linux/list.h> 26 #include <linux/interrupt.h> 27 #include <linux/mm.h> 28 #include <linux/platform_data/pxa2xx_udc.h> 29 #include <linux/platform_device.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/irq.h> 32 #include <linux/clk.h> 33 #include <linux/seq_file.h> 34 #include <linux/debugfs.h> 35 #include <linux/io.h> 36 #include <linux/prefetch.h> 37 38 #include <asm/byteorder.h> 39 #include <asm/dma.h> 40 #include <asm/mach-types.h> 41 #include <linux/unaligned.h> 42 43 #include <linux/usb/ch9.h> 44 #include <linux/usb/gadget.h> 45 #include <linux/usb/otg.h> 46 47 #define UDCCR 0x0000 /* UDC Control Register */ 48 #define UDC_RES1 0x0004 /* UDC Undocumented - Reserved1 */ 49 #define UDC_RES2 0x0008 /* UDC Undocumented - Reserved2 */ 50 #define UDC_RES3 0x000C /* UDC Undocumented - Reserved3 */ 51 #define UDCCS0 0x0010 /* UDC Endpoint 0 Control/Status Register */ 52 #define UDCCS1 0x0014 /* UDC Endpoint 1 (IN) Control/Status Register */ 53 #define UDCCS2 0x0018 /* UDC Endpoint 2 (OUT) Control/Status Register */ 54 #define UDCCS3 0x001C /* UDC Endpoint 3 (IN) Control/Status Register */ 55 #define UDCCS4 0x0020 /* UDC Endpoint 4 (OUT) Control/Status Register */ 56 #define UDCCS5 0x0024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */ 57 #define UDCCS6 0x0028 /* UDC Endpoint 6 (IN) Control/Status Register */ 58 #define UDCCS7 0x002C /* UDC Endpoint 7 (OUT) Control/Status Register */ 59 #define UDCCS8 0x0030 /* UDC Endpoint 8 (IN) Control/Status Register */ 60 #define UDCCS9 0x0034 /* UDC Endpoint 9 (OUT) Control/Status Register */ 61 #define UDCCS10 0x0038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */ 62 #define UDCCS11 0x003C /* UDC Endpoint 11 (IN) Control/Status Register */ 63 #define UDCCS12 0x0040 /* UDC Endpoint 12 (OUT) Control/Status Register */ 64 #define UDCCS13 0x0044 /* UDC Endpoint 13 (IN) Control/Status Register */ 65 #define UDCCS14 0x0048 /* UDC Endpoint 14 (OUT) Control/Status Register */ 66 #define UDCCS15 0x004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */ 67 #define UFNRH 0x0060 /* UDC Frame Number Register High */ 68 #define UFNRL 0x0064 /* UDC Frame Number Register Low */ 69 #define UBCR2 0x0068 /* UDC Byte Count Reg 2 */ 70 #define UBCR4 0x006c /* UDC Byte Count Reg 4 */ 71 #define UBCR7 0x0070 /* UDC Byte Count Reg 7 */ 72 #define UBCR9 0x0074 /* UDC Byte Count Reg 9 */ 73 #define UBCR12 0x0078 /* UDC Byte Count Reg 12 */ 74 #define UBCR14 0x007c /* UDC Byte Count Reg 14 */ 75 #define UDDR0 0x0080 /* UDC Endpoint 0 Data Register */ 76 #define UDDR1 0x0100 /* UDC Endpoint 1 Data Register */ 77 #define UDDR2 0x0180 /* UDC Endpoint 2 Data Register */ 78 #define UDDR3 0x0200 /* UDC Endpoint 3 Data Register */ 79 #define UDDR4 0x0400 /* UDC Endpoint 4 Data Register */ 80 #define UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */ 81 #define UDDR6 0x0600 /* UDC Endpoint 6 Data Register */ 82 #define UDDR7 0x0680 /* UDC Endpoint 7 Data Register */ 83 #define UDDR8 0x0700 /* UDC Endpoint 8 Data Register */ 84 #define UDDR9 0x0900 /* UDC Endpoint 9 Data Register */ 85 #define UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */ 86 #define UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */ 87 #define UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */ 88 #define UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */ 89 #define UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */ 90 #define UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */ 91 92 #define UICR0 0x0050 /* UDC Interrupt Control Register 0 */ 93 #define UICR1 0x0054 /* UDC Interrupt Control Register 1 */ 94 95 #define USIR0 0x0058 /* UDC Status Interrupt Register 0 */ 96 #define USIR1 0x005C /* UDC Status Interrupt Register 1 */ 97 98 #define UDCCR_UDE (1 << 0) /* UDC enable */ 99 #define UDCCR_UDA (1 << 1) /* UDC active */ 100 #define UDCCR_RSM (1 << 2) /* Device resume */ 101 #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ 102 #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ 103 #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ 104 #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ 105 #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ 106 107 #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ 108 #define UDCCS0_IPR (1 << 1) /* IN packet ready */ 109 #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ 110 #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ 111 #define UDCCS0_SST (1 << 4) /* Sent stall */ 112 #define UDCCS0_FST (1 << 5) /* Force stall */ 113 #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ 114 #define UDCCS0_SA (1 << 7) /* Setup active */ 115 116 #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ 117 #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ 118 #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ 119 #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ 120 #define UDCCS_BI_SST (1 << 4) /* Sent stall */ 121 #define UDCCS_BI_FST (1 << 5) /* Force stall */ 122 #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ 123 124 #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ 125 #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ 126 #define UDCCS_BO_DME (1 << 3) /* DMA enable */ 127 #define UDCCS_BO_SST (1 << 4) /* Sent stall */ 128 #define UDCCS_BO_FST (1 << 5) /* Force stall */ 129 #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ 130 #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ 131 132 #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ 133 #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ 134 #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ 135 #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ 136 #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ 137 138 #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ 139 #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ 140 #ifdef CONFIG_ARCH_IXP4XX /* FIXME: is this right?, datasheed says '2' */ 141 #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ 142 #endif 143 #ifdef CONFIG_ARCH_PXA 144 #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ 145 #endif 146 #define UDCCS_IO_DME (1 << 3) /* DMA enable */ 147 #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ 148 #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ 149 150 #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ 151 #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ 152 #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ 153 #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ 154 #define UDCCS_INT_SST (1 << 4) /* Sent stall */ 155 #define UDCCS_INT_FST (1 << 5) /* Force stall */ 156 #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ 157 158 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ 159 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ 160 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ 161 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ 162 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ 163 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ 164 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ 165 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ 166 167 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ 168 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ 169 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ 170 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ 171 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ 172 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ 173 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ 174 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ 175 176 #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ 177 #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ 178 #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ 179 #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ 180 #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ 181 #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ 182 #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ 183 #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ 184 185 #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ 186 #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ 187 #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ 188 #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ 189 #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ 190 #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ 191 #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ 192 #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ 193 194 /* 195 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x 196 * series processors. The UDC for the IXP 4xx series is very similar. 197 * There are fifteen endpoints, in addition to ep0. 198 * 199 * Such controller drivers work with a gadget driver. The gadget driver 200 * returns descriptors, implements configuration and data protocols used 201 * by the host to interact with this device, and allocates endpoints to 202 * the different protocol interfaces. The controller driver virtualizes 203 * usb hardware so that the gadget drivers will be more portable. 204 * 205 * This UDC hardware wants to implement a bit too much USB protocol, so 206 * it constrains the sorts of USB configuration change events that work. 207 * The errata for these chips are misleading; some "fixed" bugs from 208 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. 209 * 210 * Note that the UDC hardware supports DMA (except on IXP) but that's 211 * not used here. IN-DMA (to host) is simple enough, when the data is 212 * suitably aligned (16 bytes) ... the network stack doesn't do that, 213 * other software can. OUT-DMA is buggy in most chip versions, as well 214 * as poorly designed (data toggle not automatic). So this driver won't 215 * bother using DMA. (Mostly-working IN-DMA support was available in 216 * kernels before 2.6.23, but was never enabled or well tested.) 217 */ 218 219 #define DRIVER_VERSION "30-June-2007" 220 #define DRIVER_DESC "PXA 25x USB Device Controller driver" 221 222 223 static const char driver_name [] = "pxa25x_udc"; 224 225 static const char ep0name [] = "ep0"; 226 227 228 #ifdef CONFIG_ARCH_IXP4XX 229 230 /* cpu-specific register addresses are compiled in to this code */ 231 #ifdef CONFIG_ARCH_PXA 232 #error "Can't configure both IXP and PXA" 233 #endif 234 235 /* IXP doesn't yet support <linux/clk.h> */ 236 #define clk_get(dev,name) NULL 237 #define clk_enable(clk) do { } while (0) 238 #define clk_disable(clk) do { } while (0) 239 #define clk_put(clk) do { } while (0) 240 241 #endif 242 243 #include "pxa25x_udc.h" 244 245 246 #ifdef CONFIG_USB_PXA25X_SMALL 247 #define SIZE_STR " (small)" 248 #else 249 #define SIZE_STR "" 250 #endif 251 252 /* --------------------------------------------------------------------------- 253 * endpoint related parts of the api to the usb controller hardware, 254 * used by gadget driver; and the inner talker-to-hardware core. 255 * --------------------------------------------------------------------------- 256 */ 257 258 static void pxa25x_ep_fifo_flush (struct usb_ep *ep); 259 static void nuke (struct pxa25x_ep *, int status); 260 261 /* one GPIO should control a D+ pullup, so host sees this device (or not) */ 262 static void pullup_off(void) 263 { 264 gpiod_set_value(the_controller->pullup_gpio, 0); 265 } 266 267 static void pullup_on(void) 268 { 269 gpiod_set_value(the_controller->pullup_gpio, 1); 270 } 271 272 #if defined(CONFIG_CPU_BIG_ENDIAN) 273 /* 274 * IXP4xx has its buses wired up in a way that relies on never doing any 275 * byte swaps, independent of whether it runs in big-endian or little-endian 276 * mode, as explained by Krzysztof Hałasa. 277 * 278 * We only support pxa25x in little-endian mode, but it is very likely 279 * that it works the same way. 280 */ 281 static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val) 282 { 283 iowrite32be(val, dev->regs + reg); 284 } 285 286 static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg) 287 { 288 return ioread32be(dev->regs + reg); 289 } 290 #else 291 static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val) 292 { 293 writel(val, dev->regs + reg); 294 } 295 296 static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg) 297 { 298 return readl(dev->regs + reg); 299 } 300 #endif 301 302 static void pio_irq_enable(struct pxa25x_ep *ep) 303 { 304 u32 bEndpointAddress = ep->bEndpointAddress & 0xf; 305 306 if (bEndpointAddress < 8) 307 udc_set_reg(ep->dev, UICR0, udc_get_reg(ep->dev, UICR0) & 308 ~(1 << bEndpointAddress)); 309 else { 310 bEndpointAddress -= 8; 311 udc_set_reg(ep->dev, UICR1, udc_get_reg(ep->dev, UICR1) & 312 ~(1 << bEndpointAddress)); 313 } 314 } 315 316 static void pio_irq_disable(struct pxa25x_ep *ep) 317 { 318 u32 bEndpointAddress = ep->bEndpointAddress & 0xf; 319 320 if (bEndpointAddress < 8) 321 udc_set_reg(ep->dev, UICR0, udc_get_reg(ep->dev, UICR0) | 322 (1 << bEndpointAddress)); 323 else { 324 bEndpointAddress -= 8; 325 udc_set_reg(ep->dev, UICR1, udc_get_reg(ep->dev, UICR1) | 326 (1 << bEndpointAddress)); 327 } 328 } 329 330 /* The UDCCR reg contains mask and interrupt status bits, 331 * so using '|=' isn't safe as it may ack an interrupt. 332 */ 333 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE) 334 335 static inline void udc_set_mask_UDCCR(struct pxa25x_udc *dev, int mask) 336 { 337 u32 udccr = udc_get_reg(dev, UDCCR); 338 339 udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR); 340 } 341 342 static inline void udc_clear_mask_UDCCR(struct pxa25x_udc *dev, int mask) 343 { 344 u32 udccr = udc_get_reg(dev, UDCCR); 345 346 udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR); 347 } 348 349 static inline void udc_ack_int_UDCCR(struct pxa25x_udc *dev, int mask) 350 { 351 /* udccr contains the bits we dont want to change */ 352 u32 udccr = udc_get_reg(dev, UDCCR) & UDCCR_MASK_BITS; 353 354 udc_set_reg(dev, udccr | (mask & ~UDCCR_MASK_BITS), UDCCR); 355 } 356 357 static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *ep) 358 { 359 return udc_get_reg(ep->dev, ep->regoff_udccs); 360 } 361 362 static inline void udc_ep_set_UDCCS(struct pxa25x_ep *ep, u32 data) 363 { 364 udc_set_reg(ep->dev, data, ep->regoff_udccs); 365 } 366 367 static inline u32 udc_ep0_get_UDCCS(struct pxa25x_udc *dev) 368 { 369 return udc_get_reg(dev, UDCCS0); 370 } 371 372 static inline void udc_ep0_set_UDCCS(struct pxa25x_udc *dev, u32 data) 373 { 374 udc_set_reg(dev, data, UDCCS0); 375 } 376 377 static inline u32 udc_ep_get_UDDR(struct pxa25x_ep *ep) 378 { 379 return udc_get_reg(ep->dev, ep->regoff_uddr); 380 } 381 382 static inline void udc_ep_set_UDDR(struct pxa25x_ep *ep, u32 data) 383 { 384 udc_set_reg(ep->dev, data, ep->regoff_uddr); 385 } 386 387 static inline u32 udc_ep_get_UBCR(struct pxa25x_ep *ep) 388 { 389 return udc_get_reg(ep->dev, ep->regoff_ubcr); 390 } 391 392 /* 393 * endpoint enable/disable 394 * 395 * we need to verify the descriptors used to enable endpoints. since pxa25x 396 * endpoint configurations are fixed, and are pretty much always enabled, 397 * there's not a lot to manage here. 398 * 399 * because pxa25x can't selectively initialize bulk (or interrupt) endpoints, 400 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except 401 * for a single interface (with only the default altsetting) and for gadget 402 * drivers that don't halt endpoints (not reset by set_interface). that also 403 * means that if you use ISO, you must violate the USB spec rule that all 404 * iso endpoints must be in non-default altsettings. 405 */ 406 static int pxa25x_ep_enable (struct usb_ep *_ep, 407 const struct usb_endpoint_descriptor *desc) 408 { 409 struct pxa25x_ep *ep; 410 struct pxa25x_udc *dev; 411 412 ep = container_of (_ep, struct pxa25x_ep, ep); 413 if (!_ep || !desc || _ep->name == ep0name 414 || desc->bDescriptorType != USB_DT_ENDPOINT 415 || ep->bEndpointAddress != desc->bEndpointAddress 416 || ep->fifo_size < usb_endpoint_maxp (desc)) { 417 DMSG("%s, bad ep or descriptor\n", __func__); 418 return -EINVAL; 419 } 420 421 /* xfer types must match, except that interrupt ~= bulk */ 422 if (ep->bmAttributes != desc->bmAttributes 423 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK 424 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { 425 DMSG("%s, %s type mismatch\n", __func__, _ep->name); 426 return -EINVAL; 427 } 428 429 /* hardware _could_ do smaller, but driver doesn't */ 430 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK 431 && usb_endpoint_maxp (desc) 432 != BULK_FIFO_SIZE) 433 || !desc->wMaxPacketSize) { 434 DMSG("%s, bad %s maxpacket\n", __func__, _ep->name); 435 return -ERANGE; 436 } 437 438 dev = ep->dev; 439 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { 440 DMSG("%s, bogus device state\n", __func__); 441 return -ESHUTDOWN; 442 } 443 444 ep->ep.desc = desc; 445 ep->stopped = 0; 446 ep->pio_irqs = 0; 447 ep->ep.maxpacket = usb_endpoint_maxp (desc); 448 449 /* flush fifo (mostly for OUT buffers) */ 450 pxa25x_ep_fifo_flush (_ep); 451 452 /* ... reset halt state too, if we could ... */ 453 454 DBG(DBG_VERBOSE, "enabled %s\n", _ep->name); 455 return 0; 456 } 457 458 static int pxa25x_ep_disable (struct usb_ep *_ep) 459 { 460 struct pxa25x_ep *ep; 461 unsigned long flags; 462 463 ep = container_of (_ep, struct pxa25x_ep, ep); 464 if (!_ep || !ep->ep.desc) { 465 DMSG("%s, %s not enabled\n", __func__, 466 _ep ? ep->ep.name : NULL); 467 return -EINVAL; 468 } 469 local_irq_save(flags); 470 471 nuke (ep, -ESHUTDOWN); 472 473 /* flush fifo (mostly for IN buffers) */ 474 pxa25x_ep_fifo_flush (_ep); 475 476 ep->ep.desc = NULL; 477 ep->stopped = 1; 478 479 local_irq_restore(flags); 480 DBG(DBG_VERBOSE, "%s disabled\n", _ep->name); 481 return 0; 482 } 483 484 /*-------------------------------------------------------------------------*/ 485 486 /* for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers 487 * must still pass correctly initialized endpoints, since other controller 488 * drivers may care about how it's currently set up (dma issues etc). 489 */ 490 491 /* 492 * pxa25x_ep_alloc_request - allocate a request data structure 493 */ 494 static struct usb_request * 495 pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags) 496 { 497 struct pxa25x_request *req; 498 499 req = kzalloc_obj(*req, gfp_flags); 500 if (!req) 501 return NULL; 502 503 INIT_LIST_HEAD (&req->queue); 504 return &req->req; 505 } 506 507 508 /* 509 * pxa25x_ep_free_request - deallocate a request data structure 510 */ 511 static void 512 pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req) 513 { 514 struct pxa25x_request *req; 515 516 req = container_of (_req, struct pxa25x_request, req); 517 WARN_ON(!list_empty (&req->queue)); 518 kfree(req); 519 } 520 521 /*-------------------------------------------------------------------------*/ 522 523 /* 524 * done - retire a request; caller blocked irqs 525 */ 526 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status) 527 { 528 unsigned stopped = ep->stopped; 529 530 list_del_init(&req->queue); 531 532 if (likely (req->req.status == -EINPROGRESS)) 533 req->req.status = status; 534 else 535 status = req->req.status; 536 537 if (status && status != -ESHUTDOWN) 538 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n", 539 ep->ep.name, &req->req, status, 540 req->req.actual, req->req.length); 541 542 /* don't modify queue heads during completion callback */ 543 ep->stopped = 1; 544 usb_gadget_giveback_request(&ep->ep, &req->req); 545 ep->stopped = stopped; 546 } 547 548 549 static inline void ep0_idle (struct pxa25x_udc *dev) 550 { 551 dev->ep0state = EP0_IDLE; 552 } 553 554 static int 555 write_packet(struct pxa25x_ep *ep, struct pxa25x_request *req, unsigned max) 556 { 557 u8 *buf; 558 unsigned length, count; 559 560 buf = req->req.buf + req->req.actual; 561 prefetch(buf); 562 563 /* how big will this packet be? */ 564 length = min(req->req.length - req->req.actual, max); 565 req->req.actual += length; 566 567 count = length; 568 while (likely(count--)) 569 udc_ep_set_UDDR(ep, *buf++); 570 571 return length; 572 } 573 574 /* 575 * write to an IN endpoint fifo, as many packets as possible. 576 * irqs will use this to write the rest later. 577 * caller guarantees at least one packet buffer is ready (or a zlp). 578 */ 579 static int 580 write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) 581 { 582 unsigned max; 583 584 max = usb_endpoint_maxp(ep->ep.desc); 585 do { 586 unsigned count; 587 int is_last, is_short; 588 589 count = write_packet(ep, req, max); 590 591 /* last packet is usually short (or a zlp) */ 592 if (unlikely (count != max)) 593 is_last = is_short = 1; 594 else { 595 if (likely(req->req.length != req->req.actual) 596 || req->req.zero) 597 is_last = 0; 598 else 599 is_last = 1; 600 /* interrupt/iso maxpacket may not fill the fifo */ 601 is_short = unlikely (max < ep->fifo_size); 602 } 603 604 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n", 605 ep->ep.name, count, 606 is_last ? "/L" : "", is_short ? "/S" : "", 607 req->req.length - req->req.actual, req); 608 609 /* let loose that packet. maybe try writing another one, 610 * double buffering might work. TSP, TPC, and TFS 611 * bit values are the same for all normal IN endpoints. 612 */ 613 udc_ep_set_UDCCS(ep, UDCCS_BI_TPC); 614 if (is_short) 615 udc_ep_set_UDCCS(ep, UDCCS_BI_TSP); 616 617 /* requests complete when all IN data is in the FIFO */ 618 if (is_last) { 619 done (ep, req, 0); 620 if (list_empty(&ep->queue)) 621 pio_irq_disable(ep); 622 return 1; 623 } 624 625 // TODO experiment: how robust can fifo mode tweaking be? 626 // double buffering is off in the default fifo mode, which 627 // prevents TFS from being set here. 628 629 } while (udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS); 630 return 0; 631 } 632 633 /* caller asserts req->pending (ep0 irq status nyet cleared); starts 634 * ep0 data stage. these chips want very simple state transitions. 635 */ 636 static inline 637 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag) 638 { 639 udc_ep0_set_UDCCS(dev, flags|UDCCS0_SA|UDCCS0_OPR); 640 udc_set_reg(dev, USIR0, USIR0_IR0); 641 dev->req_pending = 0; 642 DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n", 643 __func__, tag, udc_ep0_get_UDCCS(dev), flags); 644 } 645 646 static int 647 write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) 648 { 649 struct pxa25x_udc *dev = ep->dev; 650 unsigned count; 651 int is_short; 652 653 count = write_packet(&dev->ep[0], req, EP0_FIFO_SIZE); 654 ep->dev->stats.write.bytes += count; 655 656 /* last packet "must be" short (or a zlp) */ 657 is_short = (count != EP0_FIFO_SIZE); 658 659 DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count, 660 req->req.length - req->req.actual, req); 661 662 if (unlikely (is_short)) { 663 if (ep->dev->req_pending) 664 ep0start(ep->dev, UDCCS0_IPR, "short IN"); 665 else 666 udc_ep0_set_UDCCS(dev, UDCCS0_IPR); 667 668 count = req->req.length; 669 done (ep, req, 0); 670 ep0_idle(ep->dev); 671 #ifndef CONFIG_ARCH_IXP4XX 672 #if 1 673 /* This seems to get rid of lost status irqs in some cases: 674 * host responds quickly, or next request involves config 675 * change automagic, or should have been hidden, or ... 676 * 677 * FIXME get rid of all udelays possible... 678 */ 679 if (count >= EP0_FIFO_SIZE) { 680 count = 100; 681 do { 682 if ((udc_ep0_get_UDCCS(dev) & UDCCS0_OPR) != 0) { 683 /* clear OPR, generate ack */ 684 udc_ep0_set_UDCCS(dev, UDCCS0_OPR); 685 break; 686 } 687 count--; 688 udelay(1); 689 } while (count); 690 } 691 #endif 692 #endif 693 } else if (ep->dev->req_pending) 694 ep0start(ep->dev, 0, "IN"); 695 return is_short; 696 } 697 698 699 /* 700 * read_fifo - unload packet(s) from the fifo we use for usb OUT 701 * transfers and put them into the request. caller should have made 702 * sure there's at least one packet ready. 703 * 704 * returns true if the request completed because of short packet or the 705 * request buffer having filled (and maybe overran till end-of-packet). 706 */ 707 static int 708 read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) 709 { 710 for (;;) { 711 u32 udccs; 712 u8 *buf; 713 unsigned bufferspace, count, is_short; 714 715 /* make sure there's a packet in the FIFO. 716 * UDCCS_{BO,IO}_RPC are all the same bit value. 717 * UDCCS_{BO,IO}_RNE are all the same bit value. 718 */ 719 udccs = udc_ep_get_UDCCS(ep); 720 if (unlikely ((udccs & UDCCS_BO_RPC) == 0)) 721 break; 722 buf = req->req.buf + req->req.actual; 723 prefetchw(buf); 724 bufferspace = req->req.length - req->req.actual; 725 726 /* read all bytes from this packet */ 727 if (likely (udccs & UDCCS_BO_RNE)) { 728 count = 1 + (0x0ff & udc_ep_get_UBCR(ep)); 729 req->req.actual += min (count, bufferspace); 730 } else /* zlp */ 731 count = 0; 732 is_short = (count < ep->ep.maxpacket); 733 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n", 734 ep->ep.name, udccs, count, 735 is_short ? "/S" : "", 736 req, req->req.actual, req->req.length); 737 while (likely (count-- != 0)) { 738 u8 byte = (u8) udc_ep_get_UDDR(ep); 739 740 if (unlikely (bufferspace == 0)) { 741 /* this happens when the driver's buffer 742 * is smaller than what the host sent. 743 * discard the extra data. 744 */ 745 if (req->req.status != -EOVERFLOW) 746 DMSG("%s overflow %d\n", 747 ep->ep.name, count); 748 req->req.status = -EOVERFLOW; 749 } else { 750 *buf++ = byte; 751 bufferspace--; 752 } 753 } 754 udc_ep_set_UDCCS(ep, UDCCS_BO_RPC); 755 /* RPC/RSP/RNE could now reflect the other packet buffer */ 756 757 /* iso is one request per packet */ 758 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 759 if (udccs & UDCCS_IO_ROF) 760 req->req.status = -EHOSTUNREACH; 761 /* more like "is_done" */ 762 is_short = 1; 763 } 764 765 /* completion */ 766 if (is_short || req->req.actual == req->req.length) { 767 done (ep, req, 0); 768 if (list_empty(&ep->queue)) 769 pio_irq_disable(ep); 770 return 1; 771 } 772 773 /* finished that packet. the next one may be waiting... */ 774 } 775 return 0; 776 } 777 778 /* 779 * special ep0 version of the above. no UBCR0 or double buffering; status 780 * handshaking is magic. most device protocols don't need control-OUT. 781 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other 782 * protocols do use them. 783 */ 784 static int 785 read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) 786 { 787 u8 *buf, byte; 788 unsigned bufferspace; 789 790 buf = req->req.buf + req->req.actual; 791 bufferspace = req->req.length - req->req.actual; 792 793 while (udc_ep_get_UDCCS(ep) & UDCCS0_RNE) { 794 byte = (u8) UDDR0; 795 796 if (unlikely (bufferspace == 0)) { 797 /* this happens when the driver's buffer 798 * is smaller than what the host sent. 799 * discard the extra data. 800 */ 801 if (req->req.status != -EOVERFLOW) 802 DMSG("%s overflow\n", ep->ep.name); 803 req->req.status = -EOVERFLOW; 804 } else { 805 *buf++ = byte; 806 req->req.actual++; 807 bufferspace--; 808 } 809 } 810 811 udc_ep_set_UDCCS(ep, UDCCS0_OPR | UDCCS0_IPR); 812 813 /* completion */ 814 if (req->req.actual >= req->req.length) 815 return 1; 816 817 /* finished that packet. the next one may be waiting... */ 818 return 0; 819 } 820 821 /*-------------------------------------------------------------------------*/ 822 823 static int 824 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 825 { 826 struct pxa25x_request *req; 827 struct pxa25x_ep *ep; 828 struct pxa25x_udc *dev; 829 unsigned long flags; 830 831 req = container_of(_req, struct pxa25x_request, req); 832 if (unlikely (!_req || !_req->complete || !_req->buf 833 || !list_empty(&req->queue))) { 834 DMSG("%s, bad params\n", __func__); 835 return -EINVAL; 836 } 837 838 ep = container_of(_ep, struct pxa25x_ep, ep); 839 if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) { 840 DMSG("%s, bad ep\n", __func__); 841 return -EINVAL; 842 } 843 844 dev = ep->dev; 845 if (unlikely (!dev->driver 846 || dev->gadget.speed == USB_SPEED_UNKNOWN)) { 847 DMSG("%s, bogus device state\n", __func__); 848 return -ESHUTDOWN; 849 } 850 851 /* iso is always one packet per request, that's the only way 852 * we can report per-packet status. that also helps with dma. 853 */ 854 if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 855 && req->req.length > usb_endpoint_maxp(ep->ep.desc))) 856 return -EMSGSIZE; 857 858 DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n", 859 _ep->name, _req, _req->length, _req->buf); 860 861 local_irq_save(flags); 862 863 _req->status = -EINPROGRESS; 864 _req->actual = 0; 865 866 /* kickstart this i/o queue? */ 867 if (list_empty(&ep->queue) && !ep->stopped) { 868 if (ep->ep.desc == NULL/* ep0 */) { 869 unsigned length = _req->length; 870 871 switch (dev->ep0state) { 872 case EP0_IN_DATA_PHASE: 873 dev->stats.write.ops++; 874 if (write_ep0_fifo(ep, req)) 875 req = NULL; 876 break; 877 878 case EP0_OUT_DATA_PHASE: 879 dev->stats.read.ops++; 880 /* messy ... */ 881 if (dev->req_config) { 882 DBG(DBG_VERBOSE, "ep0 config ack%s\n", 883 dev->has_cfr ? "" : " raced"); 884 if (dev->has_cfr) 885 udc_set_reg(dev, UDCCFR, UDCCFR_AREN | 886 UDCCFR_ACM | UDCCFR_MB1); 887 done(ep, req, 0); 888 dev->ep0state = EP0_END_XFER; 889 local_irq_restore (flags); 890 return 0; 891 } 892 if (dev->req_pending) 893 ep0start(dev, UDCCS0_IPR, "OUT"); 894 if (length == 0 || ((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0 895 && read_ep0_fifo(ep, req))) { 896 ep0_idle(dev); 897 done(ep, req, 0); 898 req = NULL; 899 } 900 break; 901 902 default: 903 DMSG("ep0 i/o, odd state %d\n", dev->ep0state); 904 local_irq_restore (flags); 905 return -EL2HLT; 906 } 907 /* can the FIFO can satisfy the request immediately? */ 908 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { 909 if ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) != 0 910 && write_fifo(ep, req)) 911 req = NULL; 912 } else if ((udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) != 0 913 && read_fifo(ep, req)) { 914 req = NULL; 915 } 916 917 if (likely(req && ep->ep.desc)) 918 pio_irq_enable(ep); 919 } 920 921 /* pio or dma irq handler advances the queue. */ 922 if (likely(req != NULL)) 923 list_add_tail(&req->queue, &ep->queue); 924 local_irq_restore(flags); 925 926 return 0; 927 } 928 929 930 /* 931 * nuke - dequeue ALL requests 932 */ 933 static void nuke(struct pxa25x_ep *ep, int status) 934 { 935 struct pxa25x_request *req; 936 937 /* called with irqs blocked */ 938 while (!list_empty(&ep->queue)) { 939 req = list_entry(ep->queue.next, 940 struct pxa25x_request, 941 queue); 942 done(ep, req, status); 943 } 944 if (ep->ep.desc) 945 pio_irq_disable(ep); 946 } 947 948 949 /* dequeue JUST ONE request */ 950 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 951 { 952 struct pxa25x_ep *ep; 953 struct pxa25x_request *req = NULL; 954 struct pxa25x_request *iter; 955 unsigned long flags; 956 957 ep = container_of(_ep, struct pxa25x_ep, ep); 958 if (!_ep || ep->ep.name == ep0name) 959 return -EINVAL; 960 961 local_irq_save(flags); 962 963 /* make sure it's actually queued on this endpoint */ 964 list_for_each_entry(iter, &ep->queue, queue) { 965 if (&iter->req != _req) 966 continue; 967 req = iter; 968 break; 969 } 970 if (!req) { 971 local_irq_restore(flags); 972 return -EINVAL; 973 } 974 975 done(ep, req, -ECONNRESET); 976 977 local_irq_restore(flags); 978 return 0; 979 } 980 981 /*-------------------------------------------------------------------------*/ 982 983 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value) 984 { 985 struct pxa25x_ep *ep; 986 unsigned long flags; 987 988 ep = container_of(_ep, struct pxa25x_ep, ep); 989 if (unlikely (!_ep 990 || (!ep->ep.desc && ep->ep.name != ep0name)) 991 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 992 DMSG("%s, bad ep\n", __func__); 993 return -EINVAL; 994 } 995 if (value == 0) { 996 /* this path (reset toggle+halt) is needed to implement 997 * SET_INTERFACE on normal hardware. but it can't be 998 * done from software on the PXA UDC, and the hardware 999 * forgets to do it as part of SET_INTERFACE automagic. 1000 */ 1001 DMSG("only host can clear %s halt\n", _ep->name); 1002 return -EROFS; 1003 } 1004 1005 local_irq_save(flags); 1006 1007 if ((ep->bEndpointAddress & USB_DIR_IN) != 0 1008 && ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) == 0 1009 || !list_empty(&ep->queue))) { 1010 local_irq_restore(flags); 1011 return -EAGAIN; 1012 } 1013 1014 /* FST bit is the same for control, bulk in, bulk out, interrupt in */ 1015 udc_ep_set_UDCCS(ep, UDCCS_BI_FST|UDCCS_BI_FTF); 1016 1017 /* ep0 needs special care */ 1018 if (!ep->ep.desc) { 1019 start_watchdog(ep->dev); 1020 ep->dev->req_pending = 0; 1021 ep->dev->ep0state = EP0_STALL; 1022 1023 /* and bulk/intr endpoints like dropping stalls too */ 1024 } else { 1025 unsigned i; 1026 for (i = 0; i < 1000; i += 20) { 1027 if (udc_ep_get_UDCCS(ep) & UDCCS_BI_SST) 1028 break; 1029 udelay(20); 1030 } 1031 } 1032 local_irq_restore(flags); 1033 1034 DBG(DBG_VERBOSE, "%s halt\n", _ep->name); 1035 return 0; 1036 } 1037 1038 static int pxa25x_ep_fifo_status(struct usb_ep *_ep) 1039 { 1040 struct pxa25x_ep *ep; 1041 1042 ep = container_of(_ep, struct pxa25x_ep, ep); 1043 if (!_ep) { 1044 DMSG("%s, bad ep\n", __func__); 1045 return -ENODEV; 1046 } 1047 /* pxa can't report unclaimed bytes from IN fifos */ 1048 if ((ep->bEndpointAddress & USB_DIR_IN) != 0) 1049 return -EOPNOTSUPP; 1050 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN 1051 || (udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) == 0) 1052 return 0; 1053 else 1054 return (udc_ep_get_UBCR(ep) & 0xfff) + 1; 1055 } 1056 1057 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep) 1058 { 1059 struct pxa25x_ep *ep; 1060 1061 ep = container_of(_ep, struct pxa25x_ep, ep); 1062 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { 1063 DMSG("%s, bad ep\n", __func__); 1064 return; 1065 } 1066 1067 /* toggle and halt bits stay unchanged */ 1068 1069 /* for OUT, just read and discard the FIFO contents. */ 1070 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) { 1071 while (((udc_ep_get_UDCCS(ep)) & UDCCS_BO_RNE) != 0) 1072 (void)udc_ep_get_UDDR(ep); 1073 return; 1074 } 1075 1076 /* most IN status is the same, but ISO can't stall */ 1077 udc_ep_set_UDCCS(ep, UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR 1078 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1079 ? 0 : UDCCS_BI_SST)); 1080 } 1081 1082 1083 static const struct usb_ep_ops pxa25x_ep_ops = { 1084 .enable = pxa25x_ep_enable, 1085 .disable = pxa25x_ep_disable, 1086 1087 .alloc_request = pxa25x_ep_alloc_request, 1088 .free_request = pxa25x_ep_free_request, 1089 1090 .queue = pxa25x_ep_queue, 1091 .dequeue = pxa25x_ep_dequeue, 1092 1093 .set_halt = pxa25x_ep_set_halt, 1094 .fifo_status = pxa25x_ep_fifo_status, 1095 .fifo_flush = pxa25x_ep_fifo_flush, 1096 }; 1097 1098 1099 /* --------------------------------------------------------------------------- 1100 * device-scoped parts of the api to the usb controller hardware 1101 * --------------------------------------------------------------------------- 1102 */ 1103 1104 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget) 1105 { 1106 struct pxa25x_udc *dev; 1107 1108 dev = container_of(_gadget, struct pxa25x_udc, gadget); 1109 return ((udc_get_reg(dev, UFNRH) & 0x07) << 8) | 1110 (udc_get_reg(dev, UFNRL) & 0xff); 1111 } 1112 1113 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget) 1114 { 1115 struct pxa25x_udc *udc; 1116 1117 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1118 1119 /* host may not have enabled remote wakeup */ 1120 if ((udc_ep0_get_UDCCS(udc) & UDCCS0_DRWF) == 0) 1121 return -EHOSTUNREACH; 1122 udc_set_mask_UDCCR(udc, UDCCR_RSM); 1123 return 0; 1124 } 1125 1126 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *); 1127 static void udc_enable (struct pxa25x_udc *); 1128 static void udc_disable(struct pxa25x_udc *); 1129 1130 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not 1131 * in active use. 1132 */ 1133 static int pullup(struct pxa25x_udc *udc) 1134 { 1135 int is_active = udc->vbus && udc->pullup && !udc->suspended; 1136 DMSG("%s\n", is_active ? "active" : "inactive"); 1137 if (is_active) { 1138 if (!udc->active) { 1139 udc->active = 1; 1140 /* Enable clock for USB device */ 1141 clk_enable(udc->clk); 1142 udc_enable(udc); 1143 } 1144 } else { 1145 if (udc->active) { 1146 if (udc->gadget.speed != USB_SPEED_UNKNOWN) { 1147 DMSG("disconnect %s\n", udc->driver 1148 ? udc->driver->driver.name 1149 : "(no driver)"); 1150 stop_activity(udc, udc->driver); 1151 } 1152 udc_disable(udc); 1153 /* Disable clock for USB device */ 1154 clk_disable(udc->clk); 1155 udc->active = 0; 1156 } 1157 1158 } 1159 return 0; 1160 } 1161 1162 /* VBUS reporting logically comes from a transceiver */ 1163 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) 1164 { 1165 struct pxa25x_udc *udc; 1166 1167 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1168 udc->vbus = is_active; 1169 DMSG("vbus %s\n", is_active ? "supplied" : "inactive"); 1170 pullup(udc); 1171 return 0; 1172 } 1173 1174 /* drivers may have software control over D+ pullup */ 1175 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active) 1176 { 1177 struct pxa25x_udc *udc; 1178 1179 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1180 1181 if (!udc->pullup_gpio) 1182 return -EOPNOTSUPP; 1183 1184 udc->pullup = (is_active != 0); 1185 pullup(udc); 1186 return 0; 1187 } 1188 1189 /* boards may consume current from VBUS, up to 100-500mA based on config. 1190 * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs 1191 * violate USB specs. 1192 */ 1193 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) 1194 { 1195 struct pxa25x_udc *udc; 1196 1197 udc = container_of(_gadget, struct pxa25x_udc, gadget); 1198 1199 if (!IS_ERR_OR_NULL(udc->transceiver)) 1200 return usb_phy_set_power(udc->transceiver, mA); 1201 return -EOPNOTSUPP; 1202 } 1203 1204 static int pxa25x_udc_start(struct usb_gadget *g, 1205 struct usb_gadget_driver *driver); 1206 static int pxa25x_udc_stop(struct usb_gadget *g); 1207 1208 static const struct usb_gadget_ops pxa25x_udc_ops = { 1209 .get_frame = pxa25x_udc_get_frame, 1210 .wakeup = pxa25x_udc_wakeup, 1211 .vbus_session = pxa25x_udc_vbus_session, 1212 .pullup = pxa25x_udc_pullup, 1213 .vbus_draw = pxa25x_udc_vbus_draw, 1214 .udc_start = pxa25x_udc_start, 1215 .udc_stop = pxa25x_udc_stop, 1216 }; 1217 1218 /*-------------------------------------------------------------------------*/ 1219 1220 #ifdef CONFIG_USB_GADGET_DEBUG_FS 1221 1222 static int udc_debug_show(struct seq_file *m, void *_d) 1223 { 1224 struct pxa25x_udc *dev = m->private; 1225 unsigned long flags; 1226 int i; 1227 u32 tmp; 1228 1229 local_irq_save(flags); 1230 1231 /* basic device status */ 1232 seq_printf(m, DRIVER_DESC "\n" 1233 "%s version: %s\nGadget driver: %s\nHost %s\n\n", 1234 driver_name, DRIVER_VERSION SIZE_STR "(pio)", 1235 dev->driver ? dev->driver->driver.name : "(none)", 1236 dev->gadget.speed == USB_SPEED_FULL ? "full speed" : "disconnected"); 1237 1238 /* registers for device and ep0 */ 1239 seq_printf(m, 1240 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", 1241 udc_get_reg(dev, UICR1), udc_get_reg(dev, UICR0), 1242 udc_get_reg(dev, USIR1), udc_get_reg(dev, USIR0), 1243 udc_get_reg(dev, UFNRH), udc_get_reg(dev, UFNRL)); 1244 1245 tmp = udc_get_reg(dev, UDCCR); 1246 seq_printf(m, 1247 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp, 1248 (tmp & UDCCR_REM) ? " rem" : "", 1249 (tmp & UDCCR_RSTIR) ? " rstir" : "", 1250 (tmp & UDCCR_SRM) ? " srm" : "", 1251 (tmp & UDCCR_SUSIR) ? " susir" : "", 1252 (tmp & UDCCR_RESIR) ? " resir" : "", 1253 (tmp & UDCCR_RSM) ? " rsm" : "", 1254 (tmp & UDCCR_UDA) ? " uda" : "", 1255 (tmp & UDCCR_UDE) ? " ude" : ""); 1256 1257 tmp = udc_ep0_get_UDCCS(dev); 1258 seq_printf(m, 1259 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp, 1260 (tmp & UDCCS0_SA) ? " sa" : "", 1261 (tmp & UDCCS0_RNE) ? " rne" : "", 1262 (tmp & UDCCS0_FST) ? " fst" : "", 1263 (tmp & UDCCS0_SST) ? " sst" : "", 1264 (tmp & UDCCS0_DRWF) ? " dwrf" : "", 1265 (tmp & UDCCS0_FTF) ? " ftf" : "", 1266 (tmp & UDCCS0_IPR) ? " ipr" : "", 1267 (tmp & UDCCS0_OPR) ? " opr" : ""); 1268 1269 if (dev->has_cfr) { 1270 tmp = udc_get_reg(dev, UDCCFR); 1271 seq_printf(m, 1272 "udccfr %02X =%s%s\n", tmp, 1273 (tmp & UDCCFR_AREN) ? " aren" : "", 1274 (tmp & UDCCFR_ACM) ? " acm" : ""); 1275 } 1276 1277 if (dev->gadget.speed != USB_SPEED_FULL || !dev->driver) 1278 goto done; 1279 1280 seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n", 1281 dev->stats.write.bytes, dev->stats.write.ops, 1282 dev->stats.read.bytes, dev->stats.read.ops, 1283 dev->stats.irqs); 1284 1285 /* dump endpoint queues */ 1286 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 1287 struct pxa25x_ep *ep = &dev->ep [i]; 1288 struct pxa25x_request *req; 1289 1290 if (i != 0) { 1291 const struct usb_endpoint_descriptor *desc; 1292 1293 desc = ep->ep.desc; 1294 if (!desc) 1295 continue; 1296 tmp = udc_ep_get_UDCCS(&dev->ep[i]); 1297 seq_printf(m, 1298 "%s max %d %s udccs %02x irqs %lu\n", 1299 ep->ep.name, usb_endpoint_maxp(desc), 1300 "pio", tmp, ep->pio_irqs); 1301 /* TODO translate all five groups of udccs bits! */ 1302 1303 } else /* ep0 should only have one transfer queued */ 1304 seq_printf(m, "ep0 max 16 pio irqs %lu\n", 1305 ep->pio_irqs); 1306 1307 if (list_empty(&ep->queue)) { 1308 seq_printf(m, "\t(nothing queued)\n"); 1309 continue; 1310 } 1311 list_for_each_entry(req, &ep->queue, queue) { 1312 seq_printf(m, 1313 "\treq %p len %d/%d buf %p\n", 1314 &req->req, req->req.actual, 1315 req->req.length, req->req.buf); 1316 } 1317 } 1318 1319 done: 1320 local_irq_restore(flags); 1321 return 0; 1322 } 1323 DEFINE_SHOW_ATTRIBUTE(udc_debug); 1324 1325 #define create_debug_files(dev) \ 1326 do { \ 1327 debugfs_create_file(dev->gadget.name, \ 1328 S_IRUGO, NULL, dev, &udc_debug_fops); \ 1329 } while (0) 1330 #define remove_debug_files(dev) debugfs_lookup_and_remove(dev->gadget.name, NULL) 1331 1332 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */ 1333 1334 #define create_debug_files(dev) do {} while (0) 1335 #define remove_debug_files(dev) do {} while (0) 1336 1337 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */ 1338 1339 /*-------------------------------------------------------------------------*/ 1340 1341 /* 1342 * udc_disable - disable USB device controller 1343 */ 1344 static void udc_disable(struct pxa25x_udc *dev) 1345 { 1346 /* block all irqs */ 1347 udc_set_mask_UDCCR(dev, UDCCR_SRM|UDCCR_REM); 1348 udc_set_reg(dev, UICR0, 0xff); 1349 udc_set_reg(dev, UICR1, 0xff); 1350 udc_set_reg(dev, UFNRH, UFNRH_SIM); 1351 1352 /* if hardware supports it, disconnect from usb */ 1353 pullup_off(); 1354 1355 udc_clear_mask_UDCCR(dev, UDCCR_UDE); 1356 1357 ep0_idle (dev); 1358 dev->gadget.speed = USB_SPEED_UNKNOWN; 1359 } 1360 1361 1362 /* 1363 * udc_reinit - initialize software state 1364 */ 1365 static void udc_reinit(struct pxa25x_udc *dev) 1366 { 1367 u32 i; 1368 1369 /* device/ep0 records init */ 1370 INIT_LIST_HEAD (&dev->gadget.ep_list); 1371 INIT_LIST_HEAD (&dev->gadget.ep0->ep_list); 1372 dev->ep0state = EP0_IDLE; 1373 dev->gadget.quirk_altset_not_supp = 1; 1374 1375 /* basic endpoint records init */ 1376 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 1377 struct pxa25x_ep *ep = &dev->ep[i]; 1378 1379 if (i != 0) 1380 list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list); 1381 1382 ep->ep.desc = NULL; 1383 ep->stopped = 0; 1384 INIT_LIST_HEAD (&ep->queue); 1385 ep->pio_irqs = 0; 1386 usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket); 1387 } 1388 1389 /* the rest was statically initialized, and is read-only */ 1390 } 1391 1392 /* until it's enabled, this UDC should be completely invisible 1393 * to any USB host. 1394 */ 1395 static void udc_enable (struct pxa25x_udc *dev) 1396 { 1397 udc_clear_mask_UDCCR(dev, UDCCR_UDE); 1398 1399 /* try to clear these bits before we enable the udc */ 1400 udc_ack_int_UDCCR(dev, UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR); 1401 1402 ep0_idle(dev); 1403 dev->gadget.speed = USB_SPEED_UNKNOWN; 1404 dev->stats.irqs = 0; 1405 1406 /* 1407 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual: 1408 * - enable UDC 1409 * - if RESET is already in progress, ack interrupt 1410 * - unmask reset interrupt 1411 */ 1412 udc_set_mask_UDCCR(dev, UDCCR_UDE); 1413 if (!(udc_get_reg(dev, UDCCR) & UDCCR_UDA)) 1414 udc_ack_int_UDCCR(dev, UDCCR_RSTIR); 1415 1416 if (dev->has_cfr /* UDC_RES2 is defined */) { 1417 /* pxa255 (a0+) can avoid a set_config race that could 1418 * prevent gadget drivers from configuring correctly 1419 */ 1420 udc_set_reg(dev, UDCCFR, UDCCFR_ACM | UDCCFR_MB1); 1421 } else { 1422 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1) 1423 * which could result in missing packets and interrupts. 1424 * supposedly one bit per endpoint, controlling whether it 1425 * double buffers or not; ACM/AREN bits fit into the holes. 1426 * zero bits (like USIR0_IRx) disable double buffering. 1427 */ 1428 udc_set_reg(dev, UDC_RES1, 0x00); 1429 udc_set_reg(dev, UDC_RES2, 0x00); 1430 } 1431 1432 /* enable suspend/resume and reset irqs */ 1433 udc_clear_mask_UDCCR(dev, UDCCR_SRM | UDCCR_REM); 1434 1435 /* enable ep0 irqs */ 1436 udc_set_reg(dev, UICR0, udc_get_reg(dev, UICR0) & ~UICR0_IM0); 1437 1438 /* if hardware supports it, pullup D+ and wait for reset */ 1439 pullup_on(); 1440 } 1441 1442 1443 /* when a driver is successfully registered, it will receive 1444 * control requests including set_configuration(), which enables 1445 * non-control requests. then usb traffic follows until a 1446 * disconnect is reported. then a host may connect again, or 1447 * the driver might get unbound. 1448 */ 1449 static int pxa25x_udc_start(struct usb_gadget *g, 1450 struct usb_gadget_driver *driver) 1451 { 1452 struct pxa25x_udc *dev = to_pxa25x(g); 1453 int retval; 1454 1455 /* first hook up the driver ... */ 1456 dev->driver = driver; 1457 dev->pullup = 1; 1458 1459 /* ... then enable host detection and ep0; and we're ready 1460 * for set_configuration as well as eventual disconnect. 1461 */ 1462 /* connect to bus through transceiver */ 1463 if (!IS_ERR_OR_NULL(dev->transceiver)) { 1464 retval = otg_set_peripheral(dev->transceiver->otg, 1465 &dev->gadget); 1466 if (retval) 1467 goto bind_fail; 1468 } 1469 1470 dump_state(dev); 1471 return 0; 1472 bind_fail: 1473 return retval; 1474 } 1475 1476 static void 1477 reset_gadget(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) 1478 { 1479 int i; 1480 1481 /* don't disconnect drivers more than once */ 1482 if (dev->gadget.speed == USB_SPEED_UNKNOWN) 1483 driver = NULL; 1484 dev->gadget.speed = USB_SPEED_UNKNOWN; 1485 1486 /* prevent new request submissions, kill any outstanding requests */ 1487 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 1488 struct pxa25x_ep *ep = &dev->ep[i]; 1489 1490 ep->stopped = 1; 1491 nuke(ep, -ESHUTDOWN); 1492 } 1493 timer_delete_sync(&dev->timer); 1494 1495 /* report reset; the driver is already quiesced */ 1496 if (driver) 1497 usb_gadget_udc_reset(&dev->gadget, driver); 1498 1499 /* re-init driver-visible data structures */ 1500 udc_reinit(dev); 1501 } 1502 1503 static void 1504 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) 1505 { 1506 int i; 1507 1508 /* don't disconnect drivers more than once */ 1509 if (dev->gadget.speed == USB_SPEED_UNKNOWN) 1510 driver = NULL; 1511 dev->gadget.speed = USB_SPEED_UNKNOWN; 1512 1513 /* prevent new request submissions, kill any outstanding requests */ 1514 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { 1515 struct pxa25x_ep *ep = &dev->ep[i]; 1516 1517 ep->stopped = 1; 1518 nuke(ep, -ESHUTDOWN); 1519 } 1520 timer_delete_sync(&dev->timer); 1521 1522 /* report disconnect; the driver is already quiesced */ 1523 if (driver) 1524 driver->disconnect(&dev->gadget); 1525 1526 /* re-init driver-visible data structures */ 1527 udc_reinit(dev); 1528 } 1529 1530 static int pxa25x_udc_stop(struct usb_gadget*g) 1531 { 1532 struct pxa25x_udc *dev = to_pxa25x(g); 1533 1534 local_irq_disable(); 1535 dev->pullup = 0; 1536 stop_activity(dev, NULL); 1537 local_irq_enable(); 1538 1539 if (!IS_ERR_OR_NULL(dev->transceiver)) 1540 (void) otg_set_peripheral(dev->transceiver->otg, NULL); 1541 1542 dev->driver = NULL; 1543 1544 dump_state(dev); 1545 1546 return 0; 1547 } 1548 1549 /*-------------------------------------------------------------------------*/ 1550 1551 static inline void clear_ep_state (struct pxa25x_udc *dev) 1552 { 1553 unsigned i; 1554 1555 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint 1556 * fifos, and pending transactions mustn't be continued in any case. 1557 */ 1558 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) 1559 nuke(&dev->ep[i], -ECONNABORTED); 1560 } 1561 1562 static void udc_watchdog(struct timer_list *t) 1563 { 1564 struct pxa25x_udc *dev = timer_container_of(dev, t, timer); 1565 1566 local_irq_disable(); 1567 if (dev->ep0state == EP0_STALL 1568 && (udc_ep0_get_UDCCS(dev) & UDCCS0_FST) == 0 1569 && (udc_ep0_get_UDCCS(dev) & UDCCS0_SST) == 0) { 1570 udc_ep0_set_UDCCS(dev, UDCCS0_FST|UDCCS0_FTF); 1571 DBG(DBG_VERBOSE, "ep0 re-stall\n"); 1572 start_watchdog(dev); 1573 } 1574 local_irq_enable(); 1575 } 1576 1577 static void handle_ep0 (struct pxa25x_udc *dev) 1578 { 1579 u32 udccs0 = udc_ep0_get_UDCCS(dev); 1580 struct pxa25x_ep *ep = &dev->ep [0]; 1581 struct pxa25x_request *req; 1582 union { 1583 struct usb_ctrlrequest r; 1584 u8 raw [8]; 1585 u32 word [2]; 1586 } u; 1587 1588 if (list_empty(&ep->queue)) 1589 req = NULL; 1590 else 1591 req = list_entry(ep->queue.next, struct pxa25x_request, queue); 1592 1593 /* clear stall status */ 1594 if (udccs0 & UDCCS0_SST) { 1595 nuke(ep, -EPIPE); 1596 udc_ep0_set_UDCCS(dev, UDCCS0_SST); 1597 timer_delete(&dev->timer); 1598 ep0_idle(dev); 1599 } 1600 1601 /* previous request unfinished? non-error iff back-to-back ... */ 1602 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { 1603 nuke(ep, 0); 1604 timer_delete(&dev->timer); 1605 ep0_idle(dev); 1606 } 1607 1608 switch (dev->ep0state) { 1609 case EP0_IDLE: 1610 /* late-breaking status? */ 1611 udccs0 = udc_ep0_get_UDCCS(dev); 1612 1613 /* start control request? */ 1614 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE)) 1615 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) { 1616 int i; 1617 1618 nuke (ep, -EPROTO); 1619 1620 /* read SETUP packet */ 1621 for (i = 0; i < 8; i++) { 1622 if (unlikely(!(udc_ep0_get_UDCCS(dev) & UDCCS0_RNE))) { 1623 bad_setup: 1624 DMSG("SETUP %d!\n", i); 1625 goto stall; 1626 } 1627 u.raw [i] = (u8) UDDR0; 1628 } 1629 if (unlikely((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0)) 1630 goto bad_setup; 1631 1632 got_setup: 1633 DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n", 1634 u.r.bRequestType, u.r.bRequest, 1635 le16_to_cpu(u.r.wValue), 1636 le16_to_cpu(u.r.wIndex), 1637 le16_to_cpu(u.r.wLength)); 1638 1639 /* cope with automagic for some standard requests. */ 1640 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) 1641 == USB_TYPE_STANDARD; 1642 dev->req_config = 0; 1643 dev->req_pending = 1; 1644 switch (u.r.bRequest) { 1645 /* hardware restricts gadget drivers here! */ 1646 case USB_REQ_SET_CONFIGURATION: 1647 if (u.r.bRequestType == USB_RECIP_DEVICE) { 1648 /* reflect hardware's automagic 1649 * up to the gadget driver. 1650 */ 1651 config_change: 1652 dev->req_config = 1; 1653 clear_ep_state(dev); 1654 /* if !has_cfr, there's no synch 1655 * else use AREN (later) not SA|OPR 1656 * USIR0_IR0 acts edge sensitive 1657 */ 1658 } 1659 break; 1660 /* ... and here, even more ... */ 1661 case USB_REQ_SET_INTERFACE: 1662 if (u.r.bRequestType == USB_RECIP_INTERFACE) { 1663 /* udc hardware is broken by design: 1664 * - altsetting may only be zero; 1665 * - hw resets all interfaces' eps; 1666 * - ep reset doesn't include halt(?). 1667 */ 1668 DMSG("broken set_interface (%d/%d)\n", 1669 le16_to_cpu(u.r.wIndex), 1670 le16_to_cpu(u.r.wValue)); 1671 goto config_change; 1672 } 1673 break; 1674 /* hardware was supposed to hide this */ 1675 case USB_REQ_SET_ADDRESS: 1676 if (u.r.bRequestType == USB_RECIP_DEVICE) { 1677 ep0start(dev, 0, "address"); 1678 return; 1679 } 1680 break; 1681 } 1682 1683 if (u.r.bRequestType & USB_DIR_IN) 1684 dev->ep0state = EP0_IN_DATA_PHASE; 1685 else 1686 dev->ep0state = EP0_OUT_DATA_PHASE; 1687 1688 i = dev->driver->setup(&dev->gadget, &u.r); 1689 if (i < 0) { 1690 /* hardware automagic preventing STALL... */ 1691 if (dev->req_config) { 1692 /* hardware sometimes neglects to tell 1693 * tell us about config change events, 1694 * so later ones may fail... 1695 */ 1696 WARNING("config change %02x fail %d?\n", 1697 u.r.bRequest, i); 1698 return; 1699 /* TODO experiment: if has_cfr, 1700 * hardware didn't ACK; maybe we 1701 * could actually STALL! 1702 */ 1703 } 1704 DBG(DBG_VERBOSE, "protocol STALL, " 1705 "%02x err %d\n", udc_ep0_get_UDCCS(dev), i); 1706 stall: 1707 /* the watchdog timer helps deal with cases 1708 * where udc seems to clear FST wrongly, and 1709 * then NAKs instead of STALLing. 1710 */ 1711 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall"); 1712 start_watchdog(dev); 1713 dev->ep0state = EP0_STALL; 1714 1715 /* deferred i/o == no response yet */ 1716 } else if (dev->req_pending) { 1717 if (likely(dev->ep0state == EP0_IN_DATA_PHASE 1718 || dev->req_std || u.r.wLength)) 1719 ep0start(dev, 0, "defer"); 1720 else 1721 ep0start(dev, UDCCS0_IPR, "defer/IPR"); 1722 } 1723 1724 /* expect at least one data or status stage irq */ 1725 return; 1726 1727 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA)) 1728 == (UDCCS0_OPR|UDCCS0_SA))) { 1729 unsigned i; 1730 1731 /* pxa210/250 erratum 131 for B0/B1 says RNE lies. 1732 * still observed on a pxa255 a0. 1733 */ 1734 DBG(DBG_VERBOSE, "e131\n"); 1735 nuke(ep, -EPROTO); 1736 1737 /* read SETUP data, but don't trust it too much */ 1738 for (i = 0; i < 8; i++) 1739 u.raw [i] = (u8) UDDR0; 1740 if ((u.r.bRequestType & USB_RECIP_MASK) 1741 > USB_RECIP_OTHER) 1742 goto stall; 1743 if (u.word [0] == 0 && u.word [1] == 0) 1744 goto stall; 1745 goto got_setup; 1746 } else { 1747 /* some random early IRQ: 1748 * - we acked FST 1749 * - IPR cleared 1750 * - OPR got set, without SA (likely status stage) 1751 */ 1752 udc_ep0_set_UDCCS(dev, udccs0 & (UDCCS0_SA|UDCCS0_OPR)); 1753 } 1754 break; 1755 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ 1756 if (udccs0 & UDCCS0_OPR) { 1757 udc_ep0_set_UDCCS(dev, UDCCS0_OPR|UDCCS0_FTF); 1758 DBG(DBG_VERBOSE, "ep0in premature status\n"); 1759 if (req) 1760 done(ep, req, 0); 1761 ep0_idle(dev); 1762 } else /* irq was IPR clearing */ { 1763 if (req) { 1764 /* this IN packet might finish the request */ 1765 (void) write_ep0_fifo(ep, req); 1766 } /* else IN token before response was written */ 1767 } 1768 break; 1769 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ 1770 if (udccs0 & UDCCS0_OPR) { 1771 if (req) { 1772 /* this OUT packet might finish the request */ 1773 if (read_ep0_fifo(ep, req)) 1774 done(ep, req, 0); 1775 /* else more OUT packets expected */ 1776 } /* else OUT token before read was issued */ 1777 } else /* irq was IPR clearing */ { 1778 DBG(DBG_VERBOSE, "ep0out premature status\n"); 1779 if (req) 1780 done(ep, req, 0); 1781 ep0_idle(dev); 1782 } 1783 break; 1784 case EP0_END_XFER: 1785 if (req) 1786 done(ep, req, 0); 1787 /* ack control-IN status (maybe in-zlp was skipped) 1788 * also appears after some config change events. 1789 */ 1790 if (udccs0 & UDCCS0_OPR) 1791 udc_ep0_set_UDCCS(dev, UDCCS0_OPR); 1792 ep0_idle(dev); 1793 break; 1794 case EP0_STALL: 1795 udc_ep0_set_UDCCS(dev, UDCCS0_FST); 1796 break; 1797 } 1798 udc_set_reg(dev, USIR0, USIR0_IR0); 1799 } 1800 1801 static void handle_ep(struct pxa25x_ep *ep) 1802 { 1803 struct pxa25x_request *req; 1804 int is_in = ep->bEndpointAddress & USB_DIR_IN; 1805 int completed; 1806 u32 udccs, tmp; 1807 1808 do { 1809 completed = 0; 1810 if (likely (!list_empty(&ep->queue))) 1811 req = list_entry(ep->queue.next, 1812 struct pxa25x_request, queue); 1813 else 1814 req = NULL; 1815 1816 // TODO check FST handling 1817 1818 udccs = udc_ep_get_UDCCS(ep); 1819 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */ 1820 tmp = UDCCS_BI_TUR; 1821 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) 1822 tmp |= UDCCS_BI_SST; 1823 tmp &= udccs; 1824 if (likely (tmp)) 1825 udc_ep_set_UDCCS(ep, tmp); 1826 if (req && likely ((udccs & UDCCS_BI_TFS) != 0)) 1827 completed = write_fifo(ep, req); 1828 1829 } else { /* irq from RPC (or for ISO, ROF) */ 1830 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) 1831 tmp = UDCCS_BO_SST | UDCCS_BO_DME; 1832 else 1833 tmp = UDCCS_IO_ROF | UDCCS_IO_DME; 1834 tmp &= udccs; 1835 if (likely(tmp)) 1836 udc_ep_set_UDCCS(ep, tmp); 1837 1838 /* fifos can hold packets, ready for reading... */ 1839 if (likely(req)) { 1840 completed = read_fifo(ep, req); 1841 } else 1842 pio_irq_disable(ep); 1843 } 1844 ep->pio_irqs++; 1845 } while (completed); 1846 } 1847 1848 /* 1849 * pxa25x_udc_irq - interrupt handler 1850 * 1851 * avoid delays in ep0 processing. the control handshaking isn't always 1852 * under software control (pxa250c0 and the pxa255 are better), and delays 1853 * could cause usb protocol errors. 1854 */ 1855 static irqreturn_t 1856 pxa25x_udc_irq(int irq, void *_dev) 1857 { 1858 struct pxa25x_udc *dev = _dev; 1859 int handled; 1860 1861 dev->stats.irqs++; 1862 do { 1863 u32 udccr = udc_get_reg(dev, UDCCR); 1864 1865 handled = 0; 1866 1867 /* SUSpend Interrupt Request */ 1868 if (unlikely(udccr & UDCCR_SUSIR)) { 1869 udc_ack_int_UDCCR(dev, UDCCR_SUSIR); 1870 handled = 1; 1871 DBG(DBG_VERBOSE, "USB suspend\n"); 1872 1873 if (dev->gadget.speed != USB_SPEED_UNKNOWN 1874 && dev->driver 1875 && dev->driver->suspend) 1876 dev->driver->suspend(&dev->gadget); 1877 ep0_idle (dev); 1878 } 1879 1880 /* RESume Interrupt Request */ 1881 if (unlikely(udccr & UDCCR_RESIR)) { 1882 udc_ack_int_UDCCR(dev, UDCCR_RESIR); 1883 handled = 1; 1884 DBG(DBG_VERBOSE, "USB resume\n"); 1885 1886 if (dev->gadget.speed != USB_SPEED_UNKNOWN 1887 && dev->driver 1888 && dev->driver->resume) 1889 dev->driver->resume(&dev->gadget); 1890 } 1891 1892 /* ReSeT Interrupt Request - USB reset */ 1893 if (unlikely(udccr & UDCCR_RSTIR)) { 1894 udc_ack_int_UDCCR(dev, UDCCR_RSTIR); 1895 handled = 1; 1896 1897 if ((udc_get_reg(dev, UDCCR) & UDCCR_UDA) == 0) { 1898 DBG(DBG_VERBOSE, "USB reset start\n"); 1899 1900 /* reset driver and endpoints, 1901 * in case that's not yet done 1902 */ 1903 reset_gadget(dev, dev->driver); 1904 1905 } else { 1906 DBG(DBG_VERBOSE, "USB reset end\n"); 1907 dev->gadget.speed = USB_SPEED_FULL; 1908 memset(&dev->stats, 0, sizeof dev->stats); 1909 /* driver and endpoints are still reset */ 1910 } 1911 1912 } else { 1913 u32 usir0 = udc_get_reg(dev, USIR0) & 1914 ~udc_get_reg(dev, UICR0); 1915 u32 usir1 = udc_get_reg(dev, USIR1) & 1916 ~udc_get_reg(dev, UICR1); 1917 int i; 1918 1919 if (unlikely (!usir0 && !usir1)) 1920 continue; 1921 1922 DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0); 1923 1924 /* control traffic */ 1925 if (usir0 & USIR0_IR0) { 1926 dev->ep[0].pio_irqs++; 1927 handle_ep0(dev); 1928 handled = 1; 1929 } 1930 1931 /* endpoint data transfers */ 1932 for (i = 0; i < 8; i++) { 1933 u32 tmp = 1 << i; 1934 1935 if (i && (usir0 & tmp)) { 1936 handle_ep(&dev->ep[i]); 1937 udc_set_reg(dev, USIR0, 1938 udc_get_reg(dev, USIR0) | tmp); 1939 handled = 1; 1940 } 1941 #ifndef CONFIG_USB_PXA25X_SMALL 1942 if (usir1 & tmp) { 1943 handle_ep(&dev->ep[i+8]); 1944 udc_set_reg(dev, USIR1, 1945 udc_get_reg(dev, USIR1) | tmp); 1946 handled = 1; 1947 } 1948 #endif 1949 } 1950 } 1951 1952 /* we could also ask for 1 msec SOF (SIR) interrupts */ 1953 1954 } while (handled); 1955 return IRQ_HANDLED; 1956 } 1957 1958 /*-------------------------------------------------------------------------*/ 1959 1960 static void nop_release (struct device *dev) 1961 { 1962 DMSG("%s %s\n", __func__, dev_name(dev)); 1963 } 1964 1965 /* this uses load-time allocation and initialization (instead of 1966 * doing it at run-time) to save code, eliminate fault paths, and 1967 * be more obviously correct. 1968 */ 1969 static struct pxa25x_udc memory = { 1970 .gadget = { 1971 .ops = &pxa25x_udc_ops, 1972 .ep0 = &memory.ep[0].ep, 1973 .name = driver_name, 1974 .dev = { 1975 .init_name = "gadget", 1976 .release = nop_release, 1977 }, 1978 }, 1979 1980 /* control endpoint */ 1981 .ep[0] = { 1982 .ep = { 1983 .name = ep0name, 1984 .ops = &pxa25x_ep_ops, 1985 .maxpacket = EP0_FIFO_SIZE, 1986 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, 1987 USB_EP_CAPS_DIR_ALL), 1988 }, 1989 .dev = &memory, 1990 .regoff_udccs = UDCCS0, 1991 .regoff_uddr = UDDR0, 1992 }, 1993 1994 /* first group of endpoints */ 1995 .ep[1] = { 1996 .ep = { 1997 .name = "ep1in-bulk", 1998 .ops = &pxa25x_ep_ops, 1999 .maxpacket = BULK_FIFO_SIZE, 2000 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2001 USB_EP_CAPS_DIR_IN), 2002 }, 2003 .dev = &memory, 2004 .fifo_size = BULK_FIFO_SIZE, 2005 .bEndpointAddress = USB_DIR_IN | 1, 2006 .bmAttributes = USB_ENDPOINT_XFER_BULK, 2007 .regoff_udccs = UDCCS1, 2008 .regoff_uddr = UDDR1, 2009 }, 2010 .ep[2] = { 2011 .ep = { 2012 .name = "ep2out-bulk", 2013 .ops = &pxa25x_ep_ops, 2014 .maxpacket = BULK_FIFO_SIZE, 2015 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2016 USB_EP_CAPS_DIR_OUT), 2017 }, 2018 .dev = &memory, 2019 .fifo_size = BULK_FIFO_SIZE, 2020 .bEndpointAddress = 2, 2021 .bmAttributes = USB_ENDPOINT_XFER_BULK, 2022 .regoff_udccs = UDCCS2, 2023 .regoff_ubcr = UBCR2, 2024 .regoff_uddr = UDDR2, 2025 }, 2026 #ifndef CONFIG_USB_PXA25X_SMALL 2027 .ep[3] = { 2028 .ep = { 2029 .name = "ep3in-iso", 2030 .ops = &pxa25x_ep_ops, 2031 .maxpacket = ISO_FIFO_SIZE, 2032 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2033 USB_EP_CAPS_DIR_IN), 2034 }, 2035 .dev = &memory, 2036 .fifo_size = ISO_FIFO_SIZE, 2037 .bEndpointAddress = USB_DIR_IN | 3, 2038 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 2039 .regoff_udccs = UDCCS3, 2040 .regoff_uddr = UDDR3, 2041 }, 2042 .ep[4] = { 2043 .ep = { 2044 .name = "ep4out-iso", 2045 .ops = &pxa25x_ep_ops, 2046 .maxpacket = ISO_FIFO_SIZE, 2047 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2048 USB_EP_CAPS_DIR_OUT), 2049 }, 2050 .dev = &memory, 2051 .fifo_size = ISO_FIFO_SIZE, 2052 .bEndpointAddress = 4, 2053 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 2054 .regoff_udccs = UDCCS4, 2055 .regoff_ubcr = UBCR4, 2056 .regoff_uddr = UDDR4, 2057 }, 2058 .ep[5] = { 2059 .ep = { 2060 .name = "ep5in-int", 2061 .ops = &pxa25x_ep_ops, 2062 .maxpacket = INT_FIFO_SIZE, 2063 .caps = USB_EP_CAPS(0, 0), 2064 }, 2065 .dev = &memory, 2066 .fifo_size = INT_FIFO_SIZE, 2067 .bEndpointAddress = USB_DIR_IN | 5, 2068 .bmAttributes = USB_ENDPOINT_XFER_INT, 2069 .regoff_udccs = UDCCS5, 2070 .regoff_uddr = UDDR5, 2071 }, 2072 2073 /* second group of endpoints */ 2074 .ep[6] = { 2075 .ep = { 2076 .name = "ep6in-bulk", 2077 .ops = &pxa25x_ep_ops, 2078 .maxpacket = BULK_FIFO_SIZE, 2079 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2080 USB_EP_CAPS_DIR_IN), 2081 }, 2082 .dev = &memory, 2083 .fifo_size = BULK_FIFO_SIZE, 2084 .bEndpointAddress = USB_DIR_IN | 6, 2085 .bmAttributes = USB_ENDPOINT_XFER_BULK, 2086 .regoff_udccs = UDCCS6, 2087 .regoff_uddr = UDDR6, 2088 }, 2089 .ep[7] = { 2090 .ep = { 2091 .name = "ep7out-bulk", 2092 .ops = &pxa25x_ep_ops, 2093 .maxpacket = BULK_FIFO_SIZE, 2094 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2095 USB_EP_CAPS_DIR_OUT), 2096 }, 2097 .dev = &memory, 2098 .fifo_size = BULK_FIFO_SIZE, 2099 .bEndpointAddress = 7, 2100 .bmAttributes = USB_ENDPOINT_XFER_BULK, 2101 .regoff_udccs = UDCCS7, 2102 .regoff_ubcr = UBCR7, 2103 .regoff_uddr = UDDR7, 2104 }, 2105 .ep[8] = { 2106 .ep = { 2107 .name = "ep8in-iso", 2108 .ops = &pxa25x_ep_ops, 2109 .maxpacket = ISO_FIFO_SIZE, 2110 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2111 USB_EP_CAPS_DIR_IN), 2112 }, 2113 .dev = &memory, 2114 .fifo_size = ISO_FIFO_SIZE, 2115 .bEndpointAddress = USB_DIR_IN | 8, 2116 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 2117 .regoff_udccs = UDCCS8, 2118 .regoff_uddr = UDDR8, 2119 }, 2120 .ep[9] = { 2121 .ep = { 2122 .name = "ep9out-iso", 2123 .ops = &pxa25x_ep_ops, 2124 .maxpacket = ISO_FIFO_SIZE, 2125 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2126 USB_EP_CAPS_DIR_OUT), 2127 }, 2128 .dev = &memory, 2129 .fifo_size = ISO_FIFO_SIZE, 2130 .bEndpointAddress = 9, 2131 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 2132 .regoff_udccs = UDCCS9, 2133 .regoff_ubcr = UBCR9, 2134 .regoff_uddr = UDDR9, 2135 }, 2136 .ep[10] = { 2137 .ep = { 2138 .name = "ep10in-int", 2139 .ops = &pxa25x_ep_ops, 2140 .maxpacket = INT_FIFO_SIZE, 2141 .caps = USB_EP_CAPS(0, 0), 2142 }, 2143 .dev = &memory, 2144 .fifo_size = INT_FIFO_SIZE, 2145 .bEndpointAddress = USB_DIR_IN | 10, 2146 .bmAttributes = USB_ENDPOINT_XFER_INT, 2147 .regoff_udccs = UDCCS10, 2148 .regoff_uddr = UDDR10, 2149 }, 2150 2151 /* third group of endpoints */ 2152 .ep[11] = { 2153 .ep = { 2154 .name = "ep11in-bulk", 2155 .ops = &pxa25x_ep_ops, 2156 .maxpacket = BULK_FIFO_SIZE, 2157 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2158 USB_EP_CAPS_DIR_IN), 2159 }, 2160 .dev = &memory, 2161 .fifo_size = BULK_FIFO_SIZE, 2162 .bEndpointAddress = USB_DIR_IN | 11, 2163 .bmAttributes = USB_ENDPOINT_XFER_BULK, 2164 .regoff_udccs = UDCCS11, 2165 .regoff_uddr = UDDR11, 2166 }, 2167 .ep[12] = { 2168 .ep = { 2169 .name = "ep12out-bulk", 2170 .ops = &pxa25x_ep_ops, 2171 .maxpacket = BULK_FIFO_SIZE, 2172 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2173 USB_EP_CAPS_DIR_OUT), 2174 }, 2175 .dev = &memory, 2176 .fifo_size = BULK_FIFO_SIZE, 2177 .bEndpointAddress = 12, 2178 .bmAttributes = USB_ENDPOINT_XFER_BULK, 2179 .regoff_udccs = UDCCS12, 2180 .regoff_ubcr = UBCR12, 2181 .regoff_uddr = UDDR12, 2182 }, 2183 .ep[13] = { 2184 .ep = { 2185 .name = "ep13in-iso", 2186 .ops = &pxa25x_ep_ops, 2187 .maxpacket = ISO_FIFO_SIZE, 2188 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2189 USB_EP_CAPS_DIR_IN), 2190 }, 2191 .dev = &memory, 2192 .fifo_size = ISO_FIFO_SIZE, 2193 .bEndpointAddress = USB_DIR_IN | 13, 2194 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 2195 .regoff_udccs = UDCCS13, 2196 .regoff_uddr = UDDR13, 2197 }, 2198 .ep[14] = { 2199 .ep = { 2200 .name = "ep14out-iso", 2201 .ops = &pxa25x_ep_ops, 2202 .maxpacket = ISO_FIFO_SIZE, 2203 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2204 USB_EP_CAPS_DIR_OUT), 2205 }, 2206 .dev = &memory, 2207 .fifo_size = ISO_FIFO_SIZE, 2208 .bEndpointAddress = 14, 2209 .bmAttributes = USB_ENDPOINT_XFER_ISOC, 2210 .regoff_udccs = UDCCS14, 2211 .regoff_ubcr = UBCR14, 2212 .regoff_uddr = UDDR14, 2213 }, 2214 .ep[15] = { 2215 .ep = { 2216 .name = "ep15in-int", 2217 .ops = &pxa25x_ep_ops, 2218 .maxpacket = INT_FIFO_SIZE, 2219 .caps = USB_EP_CAPS(0, 0), 2220 }, 2221 .dev = &memory, 2222 .fifo_size = INT_FIFO_SIZE, 2223 .bEndpointAddress = USB_DIR_IN | 15, 2224 .bmAttributes = USB_ENDPOINT_XFER_INT, 2225 .regoff_udccs = UDCCS15, 2226 .regoff_uddr = UDDR15, 2227 }, 2228 #endif /* !CONFIG_USB_PXA25X_SMALL */ 2229 }; 2230 2231 #define CP15R0_VENDOR_MASK 0xffffe000 2232 2233 #if defined(CONFIG_ARCH_PXA) 2234 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */ 2235 2236 #elif defined(CONFIG_ARCH_IXP4XX) 2237 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */ 2238 2239 #endif 2240 2241 #define CP15R0_PROD_MASK 0x000003f0 2242 #define PXA25x 0x00000100 /* and PXA26x */ 2243 #define PXA210 0x00000120 2244 2245 #define CP15R0_REV_MASK 0x0000000f 2246 2247 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK) 2248 2249 #define PXA255_A0 0x00000106 /* or PXA260_B1 */ 2250 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */ 2251 #define PXA250_B2 0x00000104 2252 #define PXA250_B1 0x00000103 /* or PXA260_A0 */ 2253 #define PXA250_B0 0x00000102 2254 #define PXA250_A1 0x00000101 2255 #define PXA250_A0 0x00000100 2256 2257 #define PXA210_C0 0x00000125 2258 #define PXA210_B2 0x00000124 2259 #define PXA210_B1 0x00000123 2260 #define PXA210_B0 0x00000122 2261 #define IXP425_A0 0x000001c1 2262 #define IXP425_B0 0x000001f1 2263 #define IXP465_AD 0x00000200 2264 2265 /* 2266 * probe - binds to the platform device 2267 */ 2268 static int pxa25x_udc_probe(struct platform_device *pdev) 2269 { 2270 struct pxa25x_udc *dev = &memory; 2271 int retval, irq; 2272 u32 chiprev; 2273 2274 pr_info("%s: version %s\n", driver_name, DRIVER_VERSION); 2275 2276 /* insist on Intel/ARM/XScale */ 2277 asm("mrc p15, 0, %0, c0, c0" : "=r" (chiprev)); 2278 if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) { 2279 pr_err("%s: not XScale!\n", driver_name); 2280 return -ENODEV; 2281 } 2282 2283 /* trigger chiprev-specific logic */ 2284 switch (chiprev & CP15R0_PRODREV_MASK) { 2285 #if defined(CONFIG_ARCH_PXA) 2286 case PXA255_A0: 2287 dev->has_cfr = 1; 2288 break; 2289 case PXA250_A0: 2290 case PXA250_A1: 2291 /* A0/A1 "not released"; ep 13, 15 unusable */ 2292 fallthrough; 2293 case PXA250_B2: case PXA210_B2: 2294 case PXA250_B1: case PXA210_B1: 2295 case PXA250_B0: case PXA210_B0: 2296 /* OUT-DMA is broken ... */ 2297 fallthrough; 2298 case PXA250_C0: case PXA210_C0: 2299 break; 2300 #elif defined(CONFIG_ARCH_IXP4XX) 2301 case IXP425_A0: 2302 case IXP425_B0: 2303 case IXP465_AD: 2304 dev->has_cfr = 1; 2305 break; 2306 #endif 2307 default: 2308 pr_err("%s: unrecognized processor: %08x\n", 2309 driver_name, chiprev); 2310 /* iop3xx, ixp4xx, ... */ 2311 return -ENODEV; 2312 } 2313 2314 irq = platform_get_irq(pdev, 0); 2315 if (irq < 0) 2316 return irq; 2317 2318 dev->regs = devm_platform_ioremap_resource(pdev, 0); 2319 if (IS_ERR(dev->regs)) 2320 return PTR_ERR(dev->regs); 2321 2322 dev->clk = devm_clk_get(&pdev->dev, NULL); 2323 if (IS_ERR(dev->clk)) 2324 return PTR_ERR(dev->clk); 2325 2326 pr_debug("%s: IRQ %d%s%s\n", driver_name, irq, 2327 dev->has_cfr ? "" : " (!cfr)", 2328 SIZE_STR "(pio)" 2329 ); 2330 2331 /* other non-static parts of init */ 2332 dev->dev = &pdev->dev; 2333 2334 dev->transceiver = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); 2335 2336 dev->pullup_gpio = devm_gpiod_get_index_optional(&pdev->dev, "pullup", 0, 2337 GPIOD_OUT_HIGH); 2338 if (IS_ERR(dev->pullup_gpio)) { 2339 dev_dbg(&pdev->dev, 2340 "can't get pullup gpio err: %ld\n", 2341 PTR_ERR(dev->pullup_gpio)); 2342 retval = PTR_ERR(dev->pullup_gpio); 2343 goto err; 2344 } 2345 2346 timer_setup(&dev->timer, udc_watchdog, 0); 2347 2348 the_controller = dev; 2349 platform_set_drvdata(pdev, dev); 2350 2351 udc_disable(dev); 2352 udc_reinit(dev); 2353 2354 dev->vbus = 0; 2355 2356 /* irq setup after old hardware state is cleaned up */ 2357 retval = devm_request_irq(&pdev->dev, irq, pxa25x_udc_irq, 0, 2358 driver_name, dev); 2359 if (retval != 0) { 2360 pr_err("%s: can't get irq %d, err %d\n", 2361 driver_name, irq, retval); 2362 goto err; 2363 } 2364 dev->got_irq = 1; 2365 2366 create_debug_files(dev); 2367 2368 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget); 2369 if (!retval) 2370 return retval; 2371 2372 remove_debug_files(dev); 2373 err: 2374 if (!IS_ERR_OR_NULL(dev->transceiver)) 2375 dev->transceiver = NULL; 2376 return retval; 2377 } 2378 2379 static void pxa25x_udc_shutdown(struct platform_device *_dev) 2380 { 2381 pullup_off(); 2382 } 2383 2384 static void pxa25x_udc_remove(struct platform_device *pdev) 2385 { 2386 struct pxa25x_udc *dev = platform_get_drvdata(pdev); 2387 2388 if (dev->driver) { 2389 dev_err(&pdev->dev, 2390 "Driver still in use but removing anyhow\n"); 2391 return; 2392 } 2393 2394 usb_del_gadget_udc(&dev->gadget); 2395 dev->pullup = 0; 2396 pullup(dev); 2397 2398 remove_debug_files(dev); 2399 2400 if (!IS_ERR_OR_NULL(dev->transceiver)) 2401 dev->transceiver = NULL; 2402 2403 the_controller = NULL; 2404 } 2405 2406 /*-------------------------------------------------------------------------*/ 2407 2408 #ifdef CONFIG_PM 2409 2410 /* USB suspend (controlled by the host) and system suspend (controlled 2411 * by the PXA) don't necessarily work well together. If USB is active, 2412 * the 48 MHz clock is required; so the system can't enter 33 MHz idle 2413 * mode, or any deeper PM saving state. 2414 * 2415 * For now, we punt and forcibly disconnect from the USB host when PXA 2416 * enters any suspend state. While we're disconnected, we always disable 2417 * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states. 2418 * Boards without software pullup control shouldn't use those states. 2419 * VBUS IRQs should probably be ignored so that the PXA device just acts 2420 * "dead" to USB hosts until system resume. 2421 */ 2422 static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state) 2423 { 2424 struct pxa25x_udc *udc = platform_get_drvdata(dev); 2425 unsigned long flags; 2426 2427 if (!udc->pullup_gpio) 2428 WARNING("USB host won't detect disconnect!\n"); 2429 udc->suspended = 1; 2430 2431 local_irq_save(flags); 2432 pullup(udc); 2433 local_irq_restore(flags); 2434 2435 return 0; 2436 } 2437 2438 static int pxa25x_udc_resume(struct platform_device *dev) 2439 { 2440 struct pxa25x_udc *udc = platform_get_drvdata(dev); 2441 unsigned long flags; 2442 2443 udc->suspended = 0; 2444 local_irq_save(flags); 2445 pullup(udc); 2446 local_irq_restore(flags); 2447 2448 return 0; 2449 } 2450 2451 #else 2452 #define pxa25x_udc_suspend NULL 2453 #define pxa25x_udc_resume NULL 2454 #endif 2455 2456 /*-------------------------------------------------------------------------*/ 2457 2458 static struct platform_driver udc_driver = { 2459 .shutdown = pxa25x_udc_shutdown, 2460 .probe = pxa25x_udc_probe, 2461 .remove = pxa25x_udc_remove, 2462 .suspend = pxa25x_udc_suspend, 2463 .resume = pxa25x_udc_resume, 2464 .driver = { 2465 .name = "pxa25x-udc", 2466 }, 2467 }; 2468 2469 module_platform_driver(udc_driver); 2470 2471 MODULE_DESCRIPTION(DRIVER_DESC); 2472 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); 2473 MODULE_LICENSE("GPL"); 2474 MODULE_ALIAS("platform:pxa25x-udc"); 2475