1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/circ_buf.h>
12 #include <linux/module.h>
13 #include <linux/ioport.h>
14 #include <linux/init.h>
15 #include <linux/console.h>
16 #include <linux/sysrq.h>
17 #include <linux/platform_device.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/ktime.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/rational.h>
27 #include <linux/slab.h>
28 #include <linux/of.h>
29 #include <linux/io.h>
30 #include <linux/iopoll.h>
31 #include <linux/dma-mapping.h>
32
33 #include <asm/irq.h>
34 #include <linux/dma/imx-dma.h>
35
36 #include "serial_mctrl_gpio.h"
37
38 /* Register definitions */
39 #define URXD0 0x0 /* Receiver Register */
40 #define URTX0 0x40 /* Transmitter Register */
41 #define UCR1 0x80 /* Control Register 1 */
42 #define UCR2 0x84 /* Control Register 2 */
43 #define UCR3 0x88 /* Control Register 3 */
44 #define UCR4 0x8c /* Control Register 4 */
45 #define UFCR 0x90 /* FIFO Control Register */
46 #define USR1 0x94 /* Status Register 1 */
47 #define USR2 0x98 /* Status Register 2 */
48 #define UESC 0x9c /* Escape Character Register */
49 #define UTIM 0xa0 /* Escape Timer Register */
50 #define UBIR 0xa4 /* BRM Incremental Register */
51 #define UBMR 0xa8 /* BRM Modulator Register */
52 #define UBRC 0xac /* Baud Rate Count Register */
53 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
55 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
56
57 /* UART Control Register Bit Fields.*/
58 #define URXD_DUMMY_READ (1<<16)
59 #define URXD_CHARRDY (1<<15)
60 #define URXD_ERR (1<<14)
61 #define URXD_OVRRUN (1<<13)
62 #define URXD_FRMERR (1<<12)
63 #define URXD_BRK (1<<11)
64 #define URXD_PRERR (1<<10)
65 #define URXD_RX_DATA (0xFF<<0)
66 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
67 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
68 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
69 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
70 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
71 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
72 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
73 #define UCR1_IREN (1<<7) /* Infrared interface enable */
74 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
76 #define UCR1_SNDBRK (1<<4) /* Send break */
77 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
79 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
80 #define UCR1_DOZE (1<<1) /* Doze */
81 #define UCR1_UARTEN (1<<0) /* UART enabled */
82 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
84 #define UCR2_CTSC (1<<13) /* CTS pin control */
85 #define UCR2_CTS (1<<12) /* Clear to send */
86 #define UCR2_ESCEN (1<<11) /* Escape enable */
87 #define UCR2_PREN (1<<8) /* Parity enable */
88 #define UCR2_PROE (1<<7) /* Parity odd/even */
89 #define UCR2_STPB (1<<6) /* Stop */
90 #define UCR2_WS (1<<5) /* Word size */
91 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
92 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
93 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
94 #define UCR2_RXEN (1<<1) /* Receiver enabled */
95 #define UCR2_SRST (1<<0) /* SW reset */
96 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
97 #define UCR3_PARERREN (1<<12) /* Parity enable */
98 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
99 #define UCR3_DSR (1<<10) /* Data set ready */
100 #define UCR3_DCD (1<<9) /* Data carrier detect */
101 #define UCR3_RI (1<<8) /* Ring indicator */
102 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
103 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
104 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
105 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
106 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
107 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109 #define UCR3_BPEN (1<<0) /* Preset registers enable */
110 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
112 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
113 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
114 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
115 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
116 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
117 #define UCR4_IRSC (1<<5) /* IR special case */
118 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
119 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
120 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123 #define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
124 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
125 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
127 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
128 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
129 #define USR1_RTSS (1<<14) /* RTS pin status */
130 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
131 #define USR1_RTSD (1<<12) /* RTS delta */
132 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
133 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
134 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
135 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
136 #define USR1_DTRD (1<<7) /* DTR Delta */
137 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
138 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
139 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
140 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
141 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
142 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
143 #define USR2_IDLE (1<<12) /* Idle condition */
144 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
145 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
146 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
147 #define USR2_WAKE (1<<7) /* Wake */
148 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
149 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
150 #define USR2_TXDC (1<<3) /* Transmitter complete */
151 #define USR2_BRCD (1<<2) /* Break condition */
152 #define USR2_ORE (1<<1) /* Overrun error */
153 #define USR2_RDR (1<<0) /* Recv data ready */
154 #define UTS_FRCPERR (1<<13) /* Force parity error */
155 #define UTS_LOOP (1<<12) /* Loop tx and rx */
156 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
157 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
158 #define UTS_TXFULL (1<<4) /* TxFIFO full */
159 #define UTS_RXFULL (1<<3) /* RxFIFO full */
160 #define UTS_SOFTRST (1<<0) /* Software reset */
161
162 /* We've been assigned a range on the "Low-density serial ports" major */
163 #define SERIAL_IMX_MAJOR 207
164 #define MINOR_START 16
165 #define DEV_NAME "ttymxc"
166
167 /*
168 * This determines how often we check the modem status signals
169 * for any change. They generally aren't connected to an IRQ
170 * so we have to poll them. We also check immediately before
171 * filling the TX fifo incase CTS has been dropped.
172 */
173 #define MCTRL_TIMEOUT (250*HZ/1000)
174
175 #define DRIVER_NAME "IMX-uart"
176
177 #define UART_NR 8
178
179 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
180 enum imx_uart_type {
181 IMX1_UART,
182 IMX21_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* counter to stop 0xff flood */
214 int idle_counter;
215
216 /* DMA fields */
217 unsigned int dma_is_enabled:1;
218 unsigned int dma_is_rxing:1;
219 unsigned int dma_is_txing:1;
220 struct dma_chan *dma_chan_rx, *dma_chan_tx;
221 struct scatterlist rx_sgl, tx_sgl[2];
222 void *rx_buf;
223 struct circ_buf rx_ring;
224 unsigned int rx_buf_size;
225 unsigned int rx_period_length;
226 unsigned int rx_periods;
227 dma_cookie_t rx_cookie;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 unsigned int saved_reg[10];
231 bool context_saved;
232
233 enum imx_tx_state tx_state;
234 struct hrtimer trigger_start_tx;
235 struct hrtimer trigger_stop_tx;
236 };
237
238 struct imx_port_ucrs {
239 unsigned int ucr1;
240 unsigned int ucr2;
241 unsigned int ucr3;
242 };
243
244 static const struct imx_uart_data imx_uart_imx1_devdata = {
245 .uts_reg = IMX1_UTS,
246 .devtype = IMX1_UART,
247 };
248
249 static const struct imx_uart_data imx_uart_imx21_devdata = {
250 .uts_reg = IMX21_UTS,
251 .devtype = IMX21_UART,
252 };
253
254 static const struct of_device_id imx_uart_dt_ids[] = {
255 /*
256 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
257 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
258 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
259 * doesn't make any distinction between these two variants.
260 */
261 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
262 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
263 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
264 { /* sentinel */ }
265 };
266 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
267
to_imx_port(struct uart_port * port)268 static inline struct imx_port *to_imx_port(struct uart_port *port)
269 {
270 return container_of(port, struct imx_port, port);
271 }
272
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)273 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
274 {
275 writel(val, sport->port.membase + offset);
276 }
277
imx_uart_readl(struct imx_port * sport,u32 offset)278 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
279 {
280 return readl(sport->port.membase + offset);
281 }
282
imx_uart_uts_reg(struct imx_port * sport)283 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
284 {
285 return sport->devdata->uts_reg;
286 }
287
imx_uart_is_imx1(struct imx_port * sport)288 static inline int imx_uart_is_imx1(struct imx_port *sport)
289 {
290 return sport->devdata->devtype == IMX1_UART;
291 }
292
293 /*
294 * Save and restore functions for UCR1, UCR2 and UCR3 registers
295 */
296 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)297 static void imx_uart_ucrs_save(struct imx_port *sport,
298 struct imx_port_ucrs *ucr)
299 {
300 /* save control registers */
301 ucr->ucr1 = imx_uart_readl(sport, UCR1);
302 ucr->ucr2 = imx_uart_readl(sport, UCR2);
303 ucr->ucr3 = imx_uart_readl(sport, UCR3);
304 }
305
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)306 static void imx_uart_ucrs_restore(struct imx_port *sport,
307 struct imx_port_ucrs *ucr)
308 {
309 /* restore control registers */
310 imx_uart_writel(sport, ucr->ucr1, UCR1);
311 imx_uart_writel(sport, ucr->ucr2, UCR2);
312 imx_uart_writel(sport, ucr->ucr3, UCR3);
313 }
314 #endif
315
316 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)317 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
318 {
319 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
320
321 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
322 }
323
324 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)325 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
326 {
327 *ucr2 &= ~UCR2_CTSC;
328 *ucr2 |= UCR2_CTS;
329
330 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
331 }
332
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)333 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
334 {
335 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
336 }
337
338 /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)339 static void imx_uart_soft_reset(struct imx_port *sport)
340 {
341 int i = 10;
342 u32 ucr2, ubir, ubmr, uts;
343
344 /*
345 * According to the Reference Manual description of the UART SRST bit:
346 *
347 * "Reset the transmit and receive state machines,
348 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
349 * and UTS[6-3]".
350 *
351 * We don't need to restore the old values from USR1, USR2, URXD and
352 * UTXD. UBRC is read only, so only save/restore the other three
353 * registers.
354 */
355 ubir = imx_uart_readl(sport, UBIR);
356 ubmr = imx_uart_readl(sport, UBMR);
357 uts = imx_uart_readl(sport, IMX21_UTS);
358
359 ucr2 = imx_uart_readl(sport, UCR2);
360 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
361
362 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
363 udelay(1);
364
365 /* Restore the registers */
366 imx_uart_writel(sport, ubir, UBIR);
367 imx_uart_writel(sport, ubmr, UBMR);
368 imx_uart_writel(sport, uts, IMX21_UTS);
369
370 sport->idle_counter = 0;
371 }
372
imx_uart_disable_loopback_rs485(struct imx_port * sport)373 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
374 {
375 unsigned int uts;
376
377 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
378 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
379 uts &= ~UTS_LOOP;
380 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
381 }
382
383 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)384 static void imx_uart_start_rx(struct uart_port *port)
385 {
386 struct imx_port *sport = to_imx_port(port);
387 unsigned int ucr1, ucr2;
388
389 ucr1 = imx_uart_readl(sport, UCR1);
390 ucr2 = imx_uart_readl(sport, UCR2);
391
392 ucr2 |= UCR2_RXEN;
393
394 if (sport->dma_is_enabled) {
395 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
396 } else {
397 ucr1 |= UCR1_RRDYEN;
398 ucr2 |= UCR2_ATEN;
399 }
400
401 /* Write UCR2 first as it includes RXEN */
402 imx_uart_writel(sport, ucr2, UCR2);
403 imx_uart_writel(sport, ucr1, UCR1);
404 imx_uart_disable_loopback_rs485(sport);
405 }
406
407 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)408 static void imx_uart_stop_tx(struct uart_port *port)
409 {
410 struct imx_port *sport = to_imx_port(port);
411 u32 ucr1, ucr4, usr2;
412
413 if (sport->tx_state == OFF)
414 return;
415
416 /*
417 * We are maybe in the SMP context, so if the DMA TX thread is running
418 * on other cpu, we have to wait for it to finish.
419 */
420 if (sport->dma_is_txing)
421 return;
422
423 ucr1 = imx_uart_readl(sport, UCR1);
424 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
425
426 ucr4 = imx_uart_readl(sport, UCR4);
427 usr2 = imx_uart_readl(sport, USR2);
428 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
429 /* The shifter is still busy, so retry once TC triggers */
430 return;
431 }
432
433 ucr4 &= ~UCR4_TCEN;
434 imx_uart_writel(sport, ucr4, UCR4);
435
436 /* in rs485 mode disable transmitter */
437 if (port->rs485.flags & SER_RS485_ENABLED) {
438 if (sport->tx_state == SEND) {
439 sport->tx_state = WAIT_AFTER_SEND;
440
441 if (port->rs485.delay_rts_after_send > 0) {
442 start_hrtimer_ms(&sport->trigger_stop_tx,
443 port->rs485.delay_rts_after_send);
444 return;
445 }
446
447 /* continue without any delay */
448 }
449
450 if (sport->tx_state == WAIT_AFTER_RTS ||
451 sport->tx_state == WAIT_AFTER_SEND) {
452 u32 ucr2;
453
454 hrtimer_try_to_cancel(&sport->trigger_start_tx);
455
456 ucr2 = imx_uart_readl(sport, UCR2);
457 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
458 imx_uart_rts_active(sport, &ucr2);
459 else
460 imx_uart_rts_inactive(sport, &ucr2);
461 imx_uart_writel(sport, ucr2, UCR2);
462
463 if (!port->rs485_rx_during_tx_gpio)
464 imx_uart_start_rx(port);
465
466 sport->tx_state = OFF;
467 }
468 } else {
469 sport->tx_state = OFF;
470 }
471 }
472
imx_uart_stop_rx_with_loopback_ctrl(struct uart_port * port,bool loopback)473 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
474 {
475 struct imx_port *sport = to_imx_port(port);
476 u32 ucr1, ucr2, ucr4, uts;
477
478 ucr1 = imx_uart_readl(sport, UCR1);
479 ucr2 = imx_uart_readl(sport, UCR2);
480 ucr4 = imx_uart_readl(sport, UCR4);
481
482 if (sport->dma_is_enabled) {
483 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
484 } else {
485 ucr1 &= ~UCR1_RRDYEN;
486 ucr2 &= ~UCR2_ATEN;
487 ucr4 &= ~UCR4_OREN;
488 }
489 imx_uart_writel(sport, ucr1, UCR1);
490 imx_uart_writel(sport, ucr4, UCR4);
491
492 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
493 if (port->rs485.flags & SER_RS485_ENABLED &&
494 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
495 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
496 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
497 uts |= UTS_LOOP;
498 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
499 ucr2 |= UCR2_RXEN;
500 } else {
501 ucr2 &= ~UCR2_RXEN;
502 }
503
504 imx_uart_writel(sport, ucr2, UCR2);
505 }
506
507 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)508 static void imx_uart_stop_rx(struct uart_port *port)
509 {
510 /*
511 * Stop RX and enable loopback in order to make sure RS485 bus
512 * is not blocked. Se comment in imx_uart_probe().
513 */
514 imx_uart_stop_rx_with_loopback_ctrl(port, true);
515 }
516
517 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)518 static void imx_uart_enable_ms(struct uart_port *port)
519 {
520 struct imx_port *sport = to_imx_port(port);
521
522 mod_timer(&sport->timer, jiffies);
523
524 mctrl_gpio_enable_ms(sport->gpios);
525 }
526
527 static void imx_uart_dma_tx(struct imx_port *sport);
528
529 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)530 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
531 {
532 struct tty_port *tport = &sport->port.state->port;
533 unsigned char c;
534
535 if (sport->port.x_char) {
536 /* Send next char */
537 imx_uart_writel(sport, sport->port.x_char, URTX0);
538 sport->port.icount.tx++;
539 sport->port.x_char = 0;
540 return;
541 }
542
543 if (kfifo_is_empty(&tport->xmit_fifo) ||
544 uart_tx_stopped(&sport->port)) {
545 imx_uart_stop_tx(&sport->port);
546 return;
547 }
548
549 if (sport->dma_is_enabled) {
550 u32 ucr1;
551 /*
552 * We've just sent a X-char Ensure the TX DMA is enabled
553 * and the TX IRQ is disabled.
554 **/
555 ucr1 = imx_uart_readl(sport, UCR1);
556 ucr1 &= ~UCR1_TRDYEN;
557 if (sport->dma_is_txing) {
558 ucr1 |= UCR1_TXDMAEN;
559 imx_uart_writel(sport, ucr1, UCR1);
560 } else {
561 imx_uart_writel(sport, ucr1, UCR1);
562 imx_uart_dma_tx(sport);
563 }
564
565 return;
566 }
567
568 while (!(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) &&
569 uart_fifo_get(&sport->port, &c))
570 imx_uart_writel(sport, c, URTX0);
571
572 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
573 uart_write_wakeup(&sport->port);
574
575 if (kfifo_is_empty(&tport->xmit_fifo))
576 imx_uart_stop_tx(&sport->port);
577 }
578
imx_uart_dma_tx_callback(void * data)579 static void imx_uart_dma_tx_callback(void *data)
580 {
581 struct imx_port *sport = data;
582 struct tty_port *tport = &sport->port.state->port;
583 struct scatterlist *sgl = &sport->tx_sgl[0];
584 unsigned long flags;
585 u32 ucr1;
586
587 uart_port_lock_irqsave(&sport->port, &flags);
588
589 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
590
591 ucr1 = imx_uart_readl(sport, UCR1);
592 ucr1 &= ~UCR1_TXDMAEN;
593 imx_uart_writel(sport, ucr1, UCR1);
594
595 uart_xmit_advance(&sport->port, sport->tx_bytes);
596
597 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
598
599 sport->dma_is_txing = 0;
600
601 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
602 uart_write_wakeup(&sport->port);
603
604 if (!kfifo_is_empty(&tport->xmit_fifo) &&
605 !uart_tx_stopped(&sport->port))
606 imx_uart_dma_tx(sport);
607 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
608 u32 ucr4 = imx_uart_readl(sport, UCR4);
609 ucr4 |= UCR4_TCEN;
610 imx_uart_writel(sport, ucr4, UCR4);
611 }
612
613 uart_port_unlock_irqrestore(&sport->port, flags);
614 }
615
616 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)617 static void imx_uart_dma_tx(struct imx_port *sport)
618 {
619 struct tty_port *tport = &sport->port.state->port;
620 struct scatterlist *sgl = sport->tx_sgl;
621 struct dma_async_tx_descriptor *desc;
622 struct dma_chan *chan = sport->dma_chan_tx;
623 struct device *dev = sport->port.dev;
624 u32 ucr1, ucr4;
625 int ret;
626
627 if (sport->dma_is_txing)
628 return;
629
630 ucr4 = imx_uart_readl(sport, UCR4);
631 ucr4 &= ~UCR4_TCEN;
632 imx_uart_writel(sport, ucr4, UCR4);
633
634 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl));
635 sport->tx_bytes = kfifo_len(&tport->xmit_fifo);
636 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl,
637 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes);
638
639 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
640 if (ret == 0) {
641 dev_err(dev, "DMA mapping error for TX.\n");
642 return;
643 }
644 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
645 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
646 if (!desc) {
647 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
648 DMA_TO_DEVICE);
649 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
650 return;
651 }
652 desc->callback = imx_uart_dma_tx_callback;
653 desc->callback_param = sport;
654
655 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes);
656
657 ucr1 = imx_uart_readl(sport, UCR1);
658 ucr1 |= UCR1_TXDMAEN;
659 imx_uart_writel(sport, ucr1, UCR1);
660
661 /* fire it */
662 sport->dma_is_txing = 1;
663 dmaengine_submit(desc);
664 dma_async_issue_pending(chan);
665 return;
666 }
667
668 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)669 static void imx_uart_start_tx(struct uart_port *port)
670 {
671 struct imx_port *sport = to_imx_port(port);
672 struct tty_port *tport = &sport->port.state->port;
673 u32 ucr1;
674
675 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo))
676 return;
677
678 /*
679 * We cannot simply do nothing here if sport->tx_state == SEND already
680 * because UCR1_TXMPTYEN might already have been cleared in
681 * imx_uart_stop_tx(), but tx_state is still SEND.
682 */
683
684 if (port->rs485.flags & SER_RS485_ENABLED) {
685 if (sport->tx_state == OFF) {
686 u32 ucr2 = imx_uart_readl(sport, UCR2);
687 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
688 imx_uart_rts_active(sport, &ucr2);
689 else
690 imx_uart_rts_inactive(sport, &ucr2);
691 imx_uart_writel(sport, ucr2, UCR2);
692
693 /*
694 * Since we are about to transmit we can not stop RX
695 * with loopback enabled because that will make our
696 * transmitted data being just looped to RX.
697 */
698 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
699 !port->rs485_rx_during_tx_gpio)
700 imx_uart_stop_rx_with_loopback_ctrl(port, false);
701
702 sport->tx_state = WAIT_AFTER_RTS;
703
704 if (port->rs485.delay_rts_before_send > 0) {
705 start_hrtimer_ms(&sport->trigger_start_tx,
706 port->rs485.delay_rts_before_send);
707 return;
708 }
709
710 /* continue without any delay */
711 }
712
713 if (sport->tx_state == WAIT_AFTER_SEND
714 || sport->tx_state == WAIT_AFTER_RTS) {
715
716 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
717
718 /*
719 * Enable transmitter and shifter empty irq only if DMA
720 * is off. In the DMA case this is done in the
721 * tx-callback.
722 */
723 if (!sport->dma_is_enabled) {
724 u32 ucr4 = imx_uart_readl(sport, UCR4);
725 ucr4 |= UCR4_TCEN;
726 imx_uart_writel(sport, ucr4, UCR4);
727 }
728
729 sport->tx_state = SEND;
730 }
731 } else {
732 sport->tx_state = SEND;
733 }
734
735 if (!sport->dma_is_enabled) {
736 ucr1 = imx_uart_readl(sport, UCR1);
737 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
738 }
739
740 if (sport->dma_is_enabled) {
741 if (sport->port.x_char) {
742 /* We have X-char to send, so enable TX IRQ and
743 * disable TX DMA to let TX interrupt to send X-char */
744 ucr1 = imx_uart_readl(sport, UCR1);
745 ucr1 &= ~UCR1_TXDMAEN;
746 ucr1 |= UCR1_TRDYEN;
747 imx_uart_writel(sport, ucr1, UCR1);
748 return;
749 }
750
751 if (!kfifo_is_empty(&tport->xmit_fifo) &&
752 !uart_tx_stopped(port))
753 imx_uart_dma_tx(sport);
754 return;
755 }
756 }
757
__imx_uart_rtsint(int irq,void * dev_id)758 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
759 {
760 struct imx_port *sport = dev_id;
761 u32 usr1;
762
763 imx_uart_writel(sport, USR1_RTSD, USR1);
764 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
765 uart_handle_cts_change(&sport->port, usr1);
766 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
767
768 return IRQ_HANDLED;
769 }
770
imx_uart_rtsint(int irq,void * dev_id)771 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
772 {
773 struct imx_port *sport = dev_id;
774 irqreturn_t ret;
775
776 uart_port_lock(&sport->port);
777
778 ret = __imx_uart_rtsint(irq, dev_id);
779
780 uart_port_unlock(&sport->port);
781
782 return ret;
783 }
784
imx_uart_txint(int irq,void * dev_id)785 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
786 {
787 struct imx_port *sport = dev_id;
788
789 uart_port_lock(&sport->port);
790 imx_uart_transmit_buffer(sport);
791 uart_port_unlock(&sport->port);
792 return IRQ_HANDLED;
793 }
794
795 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
796 * This is to be called from Rx ISRs only when some bytes were actually
797 * received.
798 *
799 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
800 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
801 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
802 * that is terminated by any activity on RxD line, or could be stopped by
803 * issuing soft reset to the UART (just stop/start of RX does not help). Note
804 * that what we do here is sending isolated start bit about 2.4 times shorter
805 * than it is to be on UART configured baud rate.
806 */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)807 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
808 {
809 /* To detect hardware 0xff flood we monitor RxD line between RX
810 * interrupts to isolate "receiving" of char(s) with no activity
811 * on RxD line, that'd never happen on actual data transfers.
812 *
813 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
814 * race here if we clear USR2_WAKE when receiving of a char is in
815 * progress, so we might get RX interrupt later with USR2_WAKE bit
816 * cleared. Note though that as we don't try to clear USR2_WAKE when we
817 * detected no activity, this race may hide actual activity only once.
818 *
819 * Yet another case where receive interrupt may occur without RxD
820 * activity is expiration of aging timer, so we consider this as well.
821 *
822 * We use 'idle_counter' to ensure that we got at least so many RX
823 * interrupts without any detected activity on RxD line. 2 cases
824 * described plus 1 to be on the safe side gives us a margin of 3,
825 * below. In practice I was not able to produce a false positive to
826 * induce soft reset at regular data transfers even using 1 as the
827 * margin, so 3 is actually very strong.
828 *
829 * We count interrupts, not chars in 'idle-counter' for simplicity.
830 */
831
832 if (usr2 & USR2_WAKE) {
833 imx_uart_writel(sport, USR2_WAKE, USR2);
834 sport->idle_counter = 0;
835 } else if (++sport->idle_counter > 3) {
836 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
837 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
838 }
839 }
840
__imx_uart_rxint(int irq,void * dev_id)841 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
842 {
843 struct imx_port *sport = dev_id;
844 struct tty_port *port = &sport->port.state->port;
845 u32 usr2, rx;
846
847 /* If we received something, check for 0xff flood */
848 usr2 = imx_uart_readl(sport, USR2);
849 if (usr2 & USR2_RDR)
850 imx_uart_check_flood(sport, usr2);
851
852 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
853 unsigned int flg = TTY_NORMAL;
854 sport->port.icount.rx++;
855
856 if (unlikely(rx & URXD_ERR)) {
857 if (rx & URXD_BRK) {
858 sport->port.icount.brk++;
859 if (uart_handle_break(&sport->port))
860 continue;
861 }
862 else if (rx & URXD_PRERR)
863 sport->port.icount.parity++;
864 else if (rx & URXD_FRMERR)
865 sport->port.icount.frame++;
866 if (rx & URXD_OVRRUN)
867 sport->port.icount.overrun++;
868
869 if (rx & sport->port.ignore_status_mask)
870 continue;
871
872 rx &= (sport->port.read_status_mask | 0xFF);
873
874 if (rx & URXD_BRK)
875 flg = TTY_BREAK;
876 else if (rx & URXD_PRERR)
877 flg = TTY_PARITY;
878 else if (rx & URXD_FRMERR)
879 flg = TTY_FRAME;
880 if (rx & URXD_OVRRUN)
881 flg = TTY_OVERRUN;
882
883 sport->port.sysrq = 0;
884 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
885 continue;
886 }
887
888 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
889 continue;
890
891 if (tty_insert_flip_char(port, rx, flg) == 0)
892 sport->port.icount.buf_overrun++;
893 }
894
895 tty_flip_buffer_push(port);
896
897 return IRQ_HANDLED;
898 }
899
imx_uart_rxint(int irq,void * dev_id)900 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
901 {
902 struct imx_port *sport = dev_id;
903 irqreturn_t ret;
904
905 uart_port_lock(&sport->port);
906
907 ret = __imx_uart_rxint(irq, dev_id);
908
909 uart_port_unlock(&sport->port);
910
911 return ret;
912 }
913
914 static void imx_uart_clear_rx_errors(struct imx_port *sport);
915
916 /*
917 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
918 */
imx_uart_get_hwmctrl(struct imx_port * sport)919 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
920 {
921 unsigned int tmp = TIOCM_DSR;
922 unsigned usr1 = imx_uart_readl(sport, USR1);
923 unsigned usr2 = imx_uart_readl(sport, USR2);
924
925 if (usr1 & USR1_RTSS)
926 tmp |= TIOCM_CTS;
927
928 /* in DCE mode DCDIN is always 0 */
929 if (!(usr2 & USR2_DCDIN))
930 tmp |= TIOCM_CAR;
931
932 if (sport->dte_mode)
933 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
934 tmp |= TIOCM_RI;
935
936 return tmp;
937 }
938
939 /*
940 * Handle any change of modem status signal since we were last called.
941 */
imx_uart_mctrl_check(struct imx_port * sport)942 static void imx_uart_mctrl_check(struct imx_port *sport)
943 {
944 unsigned int status, changed;
945
946 status = imx_uart_get_hwmctrl(sport);
947 changed = status ^ sport->old_status;
948
949 if (changed == 0)
950 return;
951
952 sport->old_status = status;
953
954 if (changed & TIOCM_RI && status & TIOCM_RI)
955 sport->port.icount.rng++;
956 if (changed & TIOCM_DSR)
957 sport->port.icount.dsr++;
958 if (changed & TIOCM_CAR)
959 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
960 if (changed & TIOCM_CTS)
961 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
962
963 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
964 }
965
imx_uart_int(int irq,void * dev_id)966 static irqreturn_t imx_uart_int(int irq, void *dev_id)
967 {
968 struct imx_port *sport = dev_id;
969 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
970 irqreturn_t ret = IRQ_NONE;
971
972 uart_port_lock(&sport->port);
973
974 usr1 = imx_uart_readl(sport, USR1);
975 usr2 = imx_uart_readl(sport, USR2);
976 ucr1 = imx_uart_readl(sport, UCR1);
977 ucr2 = imx_uart_readl(sport, UCR2);
978 ucr3 = imx_uart_readl(sport, UCR3);
979 ucr4 = imx_uart_readl(sport, UCR4);
980
981 /*
982 * Even if a condition is true that can trigger an irq only handle it if
983 * the respective irq source is enabled. This prevents some undesired
984 * actions, for example if a character that sits in the RX FIFO and that
985 * should be fetched via DMA is tried to be fetched using PIO. Or the
986 * receiver is currently off and so reading from URXD0 results in an
987 * exception. So just mask the (raw) status bits for disabled irqs.
988 */
989 if ((ucr1 & UCR1_RRDYEN) == 0)
990 usr1 &= ~USR1_RRDY;
991 if ((ucr2 & UCR2_ATEN) == 0)
992 usr1 &= ~USR1_AGTIM;
993 if ((ucr1 & UCR1_TRDYEN) == 0)
994 usr1 &= ~USR1_TRDY;
995 if ((ucr4 & UCR4_TCEN) == 0)
996 usr2 &= ~USR2_TXDC;
997 if ((ucr3 & UCR3_DTRDEN) == 0)
998 usr1 &= ~USR1_DTRD;
999 if ((ucr1 & UCR1_RTSDEN) == 0)
1000 usr1 &= ~USR1_RTSD;
1001 if ((ucr3 & UCR3_AWAKEN) == 0)
1002 usr1 &= ~USR1_AWAKE;
1003 if ((ucr4 & UCR4_OREN) == 0)
1004 usr2 &= ~USR2_ORE;
1005
1006 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1007 imx_uart_writel(sport, USR1_AGTIM, USR1);
1008
1009 __imx_uart_rxint(irq, dev_id);
1010 ret = IRQ_HANDLED;
1011 }
1012
1013 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1014 imx_uart_transmit_buffer(sport);
1015 ret = IRQ_HANDLED;
1016 }
1017
1018 if (usr1 & USR1_DTRD) {
1019 imx_uart_writel(sport, USR1_DTRD, USR1);
1020
1021 imx_uart_mctrl_check(sport);
1022
1023 ret = IRQ_HANDLED;
1024 }
1025
1026 if (usr1 & USR1_RTSD) {
1027 __imx_uart_rtsint(irq, dev_id);
1028 ret = IRQ_HANDLED;
1029 }
1030
1031 if (usr1 & USR1_AWAKE) {
1032 imx_uart_writel(sport, USR1_AWAKE, USR1);
1033 ret = IRQ_HANDLED;
1034 }
1035
1036 if (usr2 & USR2_ORE) {
1037 sport->port.icount.overrun++;
1038 imx_uart_writel(sport, USR2_ORE, USR2);
1039 ret = IRQ_HANDLED;
1040 }
1041
1042 uart_port_unlock(&sport->port);
1043
1044 return ret;
1045 }
1046
1047 /*
1048 * Return TIOCSER_TEMT when transmitter is not busy.
1049 */
imx_uart_tx_empty(struct uart_port * port)1050 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1051 {
1052 struct imx_port *sport = to_imx_port(port);
1053 unsigned int ret;
1054
1055 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1056
1057 /* If the TX DMA is working, return 0. */
1058 if (sport->dma_is_txing)
1059 ret = 0;
1060
1061 return ret;
1062 }
1063
1064 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1065 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1066 {
1067 struct imx_port *sport = to_imx_port(port);
1068 unsigned int ret = imx_uart_get_hwmctrl(sport);
1069
1070 mctrl_gpio_get(sport->gpios, &ret);
1071
1072 return ret;
1073 }
1074
1075 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1076 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1077 {
1078 struct imx_port *sport = to_imx_port(port);
1079 u32 ucr3, uts;
1080
1081 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1082 u32 ucr2;
1083
1084 /*
1085 * Turn off autoRTS if RTS is lowered and restore autoRTS
1086 * setting if RTS is raised.
1087 */
1088 ucr2 = imx_uart_readl(sport, UCR2);
1089 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1090 if (mctrl & TIOCM_RTS) {
1091 ucr2 |= UCR2_CTS;
1092 /*
1093 * UCR2_IRTS is unset if and only if the port is
1094 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1095 * to get the state to restore to.
1096 */
1097 if (!(ucr2 & UCR2_IRTS))
1098 ucr2 |= UCR2_CTSC;
1099 }
1100 imx_uart_writel(sport, ucr2, UCR2);
1101 }
1102
1103 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1104 if (!(mctrl & TIOCM_DTR))
1105 ucr3 |= UCR3_DSR;
1106 imx_uart_writel(sport, ucr3, UCR3);
1107
1108 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1109 if (mctrl & TIOCM_LOOP)
1110 uts |= UTS_LOOP;
1111 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1112
1113 mctrl_gpio_set(sport->gpios, mctrl);
1114 }
1115
1116 /*
1117 * Interrupts always disabled.
1118 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1119 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1120 {
1121 struct imx_port *sport = to_imx_port(port);
1122 unsigned long flags;
1123 u32 ucr1;
1124
1125 uart_port_lock_irqsave(&sport->port, &flags);
1126
1127 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1128
1129 if (break_state != 0)
1130 ucr1 |= UCR1_SNDBRK;
1131
1132 imx_uart_writel(sport, ucr1, UCR1);
1133
1134 uart_port_unlock_irqrestore(&sport->port, flags);
1135 }
1136
1137 /*
1138 * This is our per-port timeout handler, for checking the
1139 * modem status signals.
1140 */
imx_uart_timeout(struct timer_list * t)1141 static void imx_uart_timeout(struct timer_list *t)
1142 {
1143 struct imx_port *sport = from_timer(sport, t, timer);
1144 unsigned long flags;
1145
1146 if (sport->port.state) {
1147 uart_port_lock_irqsave(&sport->port, &flags);
1148 imx_uart_mctrl_check(sport);
1149 uart_port_unlock_irqrestore(&sport->port, flags);
1150
1151 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1152 }
1153 }
1154
1155 /*
1156 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1157 * [1] the RX DMA buffer is full.
1158 * [2] the aging timer expires
1159 *
1160 * Condition [2] is triggered when a character has been sitting in the FIFO
1161 * for at least 8 byte durations.
1162 */
imx_uart_dma_rx_callback(void * data)1163 static void imx_uart_dma_rx_callback(void *data)
1164 {
1165 struct imx_port *sport = data;
1166 struct dma_chan *chan = sport->dma_chan_rx;
1167 struct scatterlist *sgl = &sport->rx_sgl;
1168 struct tty_port *port = &sport->port.state->port;
1169 struct dma_tx_state state;
1170 struct circ_buf *rx_ring = &sport->rx_ring;
1171 enum dma_status status;
1172 unsigned int w_bytes = 0;
1173 unsigned int r_bytes;
1174 unsigned int bd_size;
1175
1176 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1177
1178 if (status == DMA_ERROR) {
1179 uart_port_lock(&sport->port);
1180 imx_uart_clear_rx_errors(sport);
1181 uart_port_unlock(&sport->port);
1182 return;
1183 }
1184
1185 /*
1186 * The state-residue variable represents the empty space
1187 * relative to the entire buffer. Taking this in consideration
1188 * the head is always calculated base on the buffer total
1189 * length - DMA transaction residue. The UART script from the
1190 * SDMA firmware will jump to the next buffer descriptor,
1191 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1192 * Taking this in consideration the tail is always at the
1193 * beginning of the buffer descriptor that contains the head.
1194 */
1195
1196 /* Calculate the head */
1197 rx_ring->head = sg_dma_len(sgl) - state.residue;
1198
1199 /* Calculate the tail. */
1200 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1201 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1202
1203 if (rx_ring->head <= sg_dma_len(sgl) &&
1204 rx_ring->head > rx_ring->tail) {
1205
1206 /* Move data from tail to head */
1207 r_bytes = rx_ring->head - rx_ring->tail;
1208
1209 /* If we received something, check for 0xff flood */
1210 uart_port_lock(&sport->port);
1211 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1212 uart_port_unlock(&sport->port);
1213
1214 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1215
1216 /* CPU claims ownership of RX DMA buffer */
1217 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1218 DMA_FROM_DEVICE);
1219
1220 w_bytes = tty_insert_flip_string(port,
1221 sport->rx_buf + rx_ring->tail, r_bytes);
1222
1223 /* UART retrieves ownership of RX DMA buffer */
1224 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1225 DMA_FROM_DEVICE);
1226
1227 if (w_bytes != r_bytes)
1228 sport->port.icount.buf_overrun++;
1229
1230 sport->port.icount.rx += w_bytes;
1231 }
1232 } else {
1233 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1234 WARN_ON(rx_ring->head <= rx_ring->tail);
1235 }
1236
1237 if (w_bytes) {
1238 tty_flip_buffer_push(port);
1239 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1240 }
1241 }
1242
imx_uart_start_rx_dma(struct imx_port * sport)1243 static int imx_uart_start_rx_dma(struct imx_port *sport)
1244 {
1245 struct scatterlist *sgl = &sport->rx_sgl;
1246 struct dma_chan *chan = sport->dma_chan_rx;
1247 struct device *dev = sport->port.dev;
1248 struct dma_async_tx_descriptor *desc;
1249 int ret;
1250
1251 sport->rx_ring.head = 0;
1252 sport->rx_ring.tail = 0;
1253
1254 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1255 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1256 if (ret == 0) {
1257 dev_err(dev, "DMA mapping error for RX.\n");
1258 return -EINVAL;
1259 }
1260
1261 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1262 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1263 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1264
1265 if (!desc) {
1266 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1267 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1268 return -EINVAL;
1269 }
1270 desc->callback = imx_uart_dma_rx_callback;
1271 desc->callback_param = sport;
1272
1273 dev_dbg(dev, "RX: prepare for the DMA.\n");
1274 sport->dma_is_rxing = 1;
1275 sport->rx_cookie = dmaengine_submit(desc);
1276 dma_async_issue_pending(chan);
1277 return 0;
1278 }
1279
imx_uart_clear_rx_errors(struct imx_port * sport)1280 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1281 {
1282 struct tty_port *port = &sport->port.state->port;
1283 u32 usr1, usr2;
1284
1285 usr1 = imx_uart_readl(sport, USR1);
1286 usr2 = imx_uart_readl(sport, USR2);
1287
1288 if (usr2 & USR2_BRCD) {
1289 sport->port.icount.brk++;
1290 imx_uart_writel(sport, USR2_BRCD, USR2);
1291 uart_handle_break(&sport->port);
1292 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1293 sport->port.icount.buf_overrun++;
1294 tty_flip_buffer_push(port);
1295 } else {
1296 if (usr1 & USR1_FRAMERR) {
1297 sport->port.icount.frame++;
1298 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1299 } else if (usr1 & USR1_PARITYERR) {
1300 sport->port.icount.parity++;
1301 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1302 }
1303 }
1304
1305 if (usr2 & USR2_ORE) {
1306 sport->port.icount.overrun++;
1307 imx_uart_writel(sport, USR2_ORE, USR2);
1308 }
1309
1310 sport->idle_counter = 0;
1311
1312 }
1313
1314 #define TXTL_DEFAULT 8
1315 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1316 #define TXTL_DMA 8 /* DMA burst setting */
1317 #define RXTL_DMA 9 /* DMA burst setting */
1318
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1319 static void imx_uart_setup_ufcr(struct imx_port *sport,
1320 unsigned char txwl, unsigned char rxwl)
1321 {
1322 unsigned int val;
1323
1324 /* set receiver / transmitter trigger level */
1325 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1326 val |= txwl << UFCR_TXTL_SHF | rxwl;
1327 imx_uart_writel(sport, val, UFCR);
1328 }
1329
imx_uart_dma_exit(struct imx_port * sport)1330 static void imx_uart_dma_exit(struct imx_port *sport)
1331 {
1332 if (sport->dma_chan_rx) {
1333 dmaengine_terminate_sync(sport->dma_chan_rx);
1334 dma_release_channel(sport->dma_chan_rx);
1335 sport->dma_chan_rx = NULL;
1336 sport->rx_cookie = -EINVAL;
1337 kfree(sport->rx_buf);
1338 sport->rx_buf = NULL;
1339 }
1340
1341 if (sport->dma_chan_tx) {
1342 dmaengine_terminate_sync(sport->dma_chan_tx);
1343 dma_release_channel(sport->dma_chan_tx);
1344 sport->dma_chan_tx = NULL;
1345 }
1346 }
1347
imx_uart_dma_init(struct imx_port * sport)1348 static int imx_uart_dma_init(struct imx_port *sport)
1349 {
1350 struct dma_slave_config slave_config = {};
1351 struct device *dev = sport->port.dev;
1352 struct dma_chan *chan;
1353 int ret;
1354
1355 /* Prepare for RX : */
1356 chan = dma_request_chan(dev, "rx");
1357 if (IS_ERR(chan)) {
1358 dev_dbg(dev, "cannot get the DMA channel.\n");
1359 sport->dma_chan_rx = NULL;
1360 ret = PTR_ERR(chan);
1361 goto err;
1362 }
1363 sport->dma_chan_rx = chan;
1364
1365 slave_config.direction = DMA_DEV_TO_MEM;
1366 slave_config.src_addr = sport->port.mapbase + URXD0;
1367 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1368 /* one byte less than the watermark level to enable the aging timer */
1369 slave_config.src_maxburst = RXTL_DMA - 1;
1370 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1371 if (ret) {
1372 dev_err(dev, "error in RX dma configuration.\n");
1373 goto err;
1374 }
1375
1376 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1377 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1378 if (!sport->rx_buf) {
1379 ret = -ENOMEM;
1380 goto err;
1381 }
1382 sport->rx_ring.buf = sport->rx_buf;
1383
1384 /* Prepare for TX : */
1385 chan = dma_request_chan(dev, "tx");
1386 if (IS_ERR(chan)) {
1387 dev_err(dev, "cannot get the TX DMA channel!\n");
1388 sport->dma_chan_tx = NULL;
1389 ret = PTR_ERR(chan);
1390 goto err;
1391 }
1392 sport->dma_chan_tx = chan;
1393
1394 slave_config.direction = DMA_MEM_TO_DEV;
1395 slave_config.dst_addr = sport->port.mapbase + URTX0;
1396 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1397 slave_config.dst_maxburst = TXTL_DMA;
1398 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1399 if (ret) {
1400 dev_err(dev, "error in TX dma configuration.");
1401 goto err;
1402 }
1403
1404 return 0;
1405 err:
1406 imx_uart_dma_exit(sport);
1407 return ret;
1408 }
1409
imx_uart_enable_dma(struct imx_port * sport)1410 static void imx_uart_enable_dma(struct imx_port *sport)
1411 {
1412 u32 ucr1;
1413
1414 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1415
1416 /* set UCR1 */
1417 ucr1 = imx_uart_readl(sport, UCR1);
1418 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1419 imx_uart_writel(sport, ucr1, UCR1);
1420
1421 sport->dma_is_enabled = 1;
1422 }
1423
imx_uart_disable_dma(struct imx_port * sport)1424 static void imx_uart_disable_dma(struct imx_port *sport)
1425 {
1426 u32 ucr1;
1427
1428 /* clear UCR1 */
1429 ucr1 = imx_uart_readl(sport, UCR1);
1430 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1431 imx_uart_writel(sport, ucr1, UCR1);
1432
1433 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1434
1435 sport->dma_is_enabled = 0;
1436 }
1437
1438 /* half the RX buffer size */
1439 #define CTSTL 16
1440
imx_uart_startup(struct uart_port * port)1441 static int imx_uart_startup(struct uart_port *port)
1442 {
1443 struct imx_port *sport = to_imx_port(port);
1444 int retval;
1445 unsigned long flags;
1446 int dma_is_inited = 0;
1447 u32 ucr1, ucr2, ucr3, ucr4;
1448
1449 retval = clk_prepare_enable(sport->clk_per);
1450 if (retval)
1451 return retval;
1452 retval = clk_prepare_enable(sport->clk_ipg);
1453 if (retval) {
1454 clk_disable_unprepare(sport->clk_per);
1455 return retval;
1456 }
1457
1458 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1459
1460 /* disable the DREN bit (Data Ready interrupt enable) before
1461 * requesting IRQs
1462 */
1463 ucr4 = imx_uart_readl(sport, UCR4);
1464
1465 /* set the trigger level for CTS */
1466 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1467 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1468
1469 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1470
1471 /* Can we enable the DMA support? */
1472 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1473 lockdep_set_subclass(&port->lock, 1);
1474 dma_is_inited = 1;
1475 }
1476
1477 uart_port_lock_irqsave(&sport->port, &flags);
1478
1479 /* Reset fifo's and state machines */
1480 imx_uart_soft_reset(sport);
1481
1482 /*
1483 * Finally, clear and enable interrupts
1484 */
1485 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1486 imx_uart_writel(sport, USR2_ORE, USR2);
1487
1488 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1489 ucr1 |= UCR1_UARTEN;
1490 if (sport->have_rtscts)
1491 ucr1 |= UCR1_RTSDEN;
1492
1493 imx_uart_writel(sport, ucr1, UCR1);
1494
1495 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1496 if (!dma_is_inited)
1497 ucr4 |= UCR4_OREN;
1498 if (sport->inverted_rx)
1499 ucr4 |= UCR4_INVR;
1500 imx_uart_writel(sport, ucr4, UCR4);
1501
1502 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1503 /*
1504 * configure tx polarity before enabling tx
1505 */
1506 if (sport->inverted_tx)
1507 ucr3 |= UCR3_INVT;
1508
1509 if (!imx_uart_is_imx1(sport)) {
1510 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1511
1512 if (sport->dte_mode)
1513 /* disable broken interrupts */
1514 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1515 }
1516 imx_uart_writel(sport, ucr3, UCR3);
1517
1518 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1519 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1520 if (!sport->have_rtscts)
1521 ucr2 |= UCR2_IRTS;
1522 /*
1523 * make sure the edge sensitive RTS-irq is disabled,
1524 * we're using RTSD instead.
1525 */
1526 if (!imx_uart_is_imx1(sport))
1527 ucr2 &= ~UCR2_RTSEN;
1528 imx_uart_writel(sport, ucr2, UCR2);
1529
1530 /*
1531 * Enable modem status interrupts
1532 */
1533 imx_uart_enable_ms(&sport->port);
1534
1535 if (dma_is_inited) {
1536 imx_uart_enable_dma(sport);
1537 imx_uart_start_rx_dma(sport);
1538 } else {
1539 ucr1 = imx_uart_readl(sport, UCR1);
1540 ucr1 |= UCR1_RRDYEN;
1541 imx_uart_writel(sport, ucr1, UCR1);
1542
1543 ucr2 = imx_uart_readl(sport, UCR2);
1544 ucr2 |= UCR2_ATEN;
1545 imx_uart_writel(sport, ucr2, UCR2);
1546 }
1547
1548 imx_uart_disable_loopback_rs485(sport);
1549
1550 uart_port_unlock_irqrestore(&sport->port, flags);
1551
1552 return 0;
1553 }
1554
imx_uart_shutdown(struct uart_port * port)1555 static void imx_uart_shutdown(struct uart_port *port)
1556 {
1557 struct imx_port *sport = to_imx_port(port);
1558 unsigned long flags;
1559 u32 ucr1, ucr2, ucr4, uts;
1560 int loops;
1561
1562 if (sport->dma_is_enabled) {
1563 dmaengine_terminate_sync(sport->dma_chan_tx);
1564 if (sport->dma_is_txing) {
1565 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1566 sport->dma_tx_nents, DMA_TO_DEVICE);
1567 sport->dma_is_txing = 0;
1568 }
1569 dmaengine_terminate_sync(sport->dma_chan_rx);
1570 if (sport->dma_is_rxing) {
1571 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1572 1, DMA_FROM_DEVICE);
1573 sport->dma_is_rxing = 0;
1574 }
1575
1576 uart_port_lock_irqsave(&sport->port, &flags);
1577 imx_uart_stop_tx(port);
1578 imx_uart_stop_rx(port);
1579 imx_uart_disable_dma(sport);
1580 uart_port_unlock_irqrestore(&sport->port, flags);
1581 imx_uart_dma_exit(sport);
1582 }
1583
1584 mctrl_gpio_disable_ms(sport->gpios);
1585
1586 uart_port_lock_irqsave(&sport->port, &flags);
1587 ucr2 = imx_uart_readl(sport, UCR2);
1588 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1589 imx_uart_writel(sport, ucr2, UCR2);
1590 uart_port_unlock_irqrestore(&sport->port, flags);
1591
1592 /*
1593 * Stop our timer.
1594 */
1595 del_timer_sync(&sport->timer);
1596
1597 /*
1598 * Disable all interrupts, port and break condition.
1599 */
1600
1601 uart_port_lock_irqsave(&sport->port, &flags);
1602
1603 ucr1 = imx_uart_readl(sport, UCR1);
1604 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1605 UCR1_ATDMAEN | UCR1_SNDBRK);
1606 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1607 if (port->rs485.flags & SER_RS485_ENABLED &&
1608 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1609 sport->have_rtscts && !sport->have_rtsgpio) {
1610 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1611 uts |= UTS_LOOP;
1612 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1613 ucr1 |= UCR1_UARTEN;
1614 } else {
1615 ucr1 &= ~UCR1_UARTEN;
1616 }
1617 imx_uart_writel(sport, ucr1, UCR1);
1618
1619 ucr4 = imx_uart_readl(sport, UCR4);
1620 ucr4 &= ~UCR4_TCEN;
1621 imx_uart_writel(sport, ucr4, UCR4);
1622
1623 /*
1624 * We have to ensure the tx state machine ends up in OFF. This
1625 * is especially important for rs485 where we must not leave
1626 * the RTS signal high, blocking the bus indefinitely.
1627 *
1628 * All interrupts are now disabled, so imx_uart_stop_tx() will
1629 * no longer be called from imx_uart_transmit_buffer(). It may
1630 * still be called via the hrtimers, and if those are in play,
1631 * we have to honour the delays.
1632 */
1633 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND)
1634 imx_uart_stop_tx(port);
1635
1636 /*
1637 * In many cases (rs232 mode, or if tx_state was
1638 * WAIT_AFTER_RTS, or if tx_state was SEND and there is no
1639 * delay_rts_after_send), this will have moved directly to
1640 * OFF. In rs485 mode, tx_state might already have been
1641 * WAIT_AFTER_SEND and the hrtimer thus already started, or
1642 * the above imx_uart_stop_tx() call could have started it. In
1643 * those cases, we have to wait for the hrtimer to fire and
1644 * complete the transition to OFF.
1645 */
1646 loops = port->rs485.flags & SER_RS485_ENABLED ?
1647 port->rs485.delay_rts_after_send : 0;
1648 while (sport->tx_state != OFF && loops--) {
1649 uart_port_unlock_irqrestore(&sport->port, flags);
1650 msleep(1);
1651 uart_port_lock_irqsave(&sport->port, &flags);
1652 }
1653
1654 if (sport->tx_state != OFF) {
1655 dev_warn(sport->port.dev, "unexpected tx_state %d\n",
1656 sport->tx_state);
1657 /*
1658 * This machine may be busted, but ensure the RTS
1659 * signal is inactive in order not to block other
1660 * devices.
1661 */
1662 if (port->rs485.flags & SER_RS485_ENABLED) {
1663 ucr2 = imx_uart_readl(sport, UCR2);
1664 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1665 imx_uart_rts_active(sport, &ucr2);
1666 else
1667 imx_uart_rts_inactive(sport, &ucr2);
1668 imx_uart_writel(sport, ucr2, UCR2);
1669 }
1670 sport->tx_state = OFF;
1671 }
1672
1673 uart_port_unlock_irqrestore(&sport->port, flags);
1674
1675 clk_disable_unprepare(sport->clk_per);
1676 clk_disable_unprepare(sport->clk_ipg);
1677 }
1678
1679 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1680 static void imx_uart_flush_buffer(struct uart_port *port)
1681 {
1682 struct imx_port *sport = to_imx_port(port);
1683 struct scatterlist *sgl = &sport->tx_sgl[0];
1684
1685 if (!sport->dma_chan_tx)
1686 return;
1687
1688 sport->tx_bytes = 0;
1689 dmaengine_terminate_all(sport->dma_chan_tx);
1690 if (sport->dma_is_txing) {
1691 u32 ucr1;
1692
1693 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1694 DMA_TO_DEVICE);
1695 ucr1 = imx_uart_readl(sport, UCR1);
1696 ucr1 &= ~UCR1_TXDMAEN;
1697 imx_uart_writel(sport, ucr1, UCR1);
1698 sport->dma_is_txing = 0;
1699 }
1700
1701 imx_uart_soft_reset(sport);
1702
1703 }
1704
1705 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1706 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1707 const struct ktermios *old)
1708 {
1709 struct imx_port *sport = to_imx_port(port);
1710 unsigned long flags;
1711 u32 ucr2, old_ucr2, ufcr;
1712 unsigned int baud, quot;
1713 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1714 unsigned long div;
1715 unsigned long num, denom, old_ubir, old_ubmr;
1716 uint64_t tdiv64;
1717
1718 /*
1719 * We only support CS7 and CS8.
1720 */
1721 while ((termios->c_cflag & CSIZE) != CS7 &&
1722 (termios->c_cflag & CSIZE) != CS8) {
1723 termios->c_cflag &= ~CSIZE;
1724 termios->c_cflag |= old_csize;
1725 old_csize = CS8;
1726 }
1727
1728 del_timer_sync(&sport->timer);
1729
1730 /*
1731 * Ask the core to calculate the divisor for us.
1732 */
1733 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1734 quot = uart_get_divisor(port, baud);
1735
1736 uart_port_lock_irqsave(&sport->port, &flags);
1737
1738 /*
1739 * Read current UCR2 and save it for future use, then clear all the bits
1740 * except those we will or may need to preserve.
1741 */
1742 old_ucr2 = imx_uart_readl(sport, UCR2);
1743 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1744
1745 ucr2 |= UCR2_SRST | UCR2_IRTS;
1746 if ((termios->c_cflag & CSIZE) == CS8)
1747 ucr2 |= UCR2_WS;
1748
1749 if (!sport->have_rtscts)
1750 termios->c_cflag &= ~CRTSCTS;
1751
1752 if (port->rs485.flags & SER_RS485_ENABLED) {
1753 /*
1754 * RTS is mandatory for rs485 operation, so keep
1755 * it under manual control and keep transmitter
1756 * disabled.
1757 */
1758 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1759 imx_uart_rts_active(sport, &ucr2);
1760 else
1761 imx_uart_rts_inactive(sport, &ucr2);
1762
1763 } else if (termios->c_cflag & CRTSCTS) {
1764 /*
1765 * Only let receiver control RTS output if we were not requested
1766 * to have RTS inactive (which then should take precedence).
1767 */
1768 if (ucr2 & UCR2_CTS)
1769 ucr2 |= UCR2_CTSC;
1770 }
1771
1772 if (termios->c_cflag & CRTSCTS)
1773 ucr2 &= ~UCR2_IRTS;
1774 if (termios->c_cflag & CSTOPB)
1775 ucr2 |= UCR2_STPB;
1776 if (termios->c_cflag & PARENB) {
1777 ucr2 |= UCR2_PREN;
1778 if (termios->c_cflag & PARODD)
1779 ucr2 |= UCR2_PROE;
1780 }
1781
1782 sport->port.read_status_mask = 0;
1783 if (termios->c_iflag & INPCK)
1784 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1785 if (termios->c_iflag & (BRKINT | PARMRK))
1786 sport->port.read_status_mask |= URXD_BRK;
1787
1788 /*
1789 * Characters to ignore
1790 */
1791 sport->port.ignore_status_mask = 0;
1792 if (termios->c_iflag & IGNPAR)
1793 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1794 if (termios->c_iflag & IGNBRK) {
1795 sport->port.ignore_status_mask |= URXD_BRK;
1796 /*
1797 * If we're ignoring parity and break indicators,
1798 * ignore overruns too (for real raw support).
1799 */
1800 if (termios->c_iflag & IGNPAR)
1801 sport->port.ignore_status_mask |= URXD_OVRRUN;
1802 }
1803
1804 if ((termios->c_cflag & CREAD) == 0)
1805 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1806
1807 /*
1808 * Update the per-port timeout.
1809 */
1810 uart_update_timeout(port, termios->c_cflag, baud);
1811
1812 /* custom-baudrate handling */
1813 div = sport->port.uartclk / (baud * 16);
1814 if (baud == 38400 && quot != div)
1815 baud = sport->port.uartclk / (quot * 16);
1816
1817 div = sport->port.uartclk / (baud * 16);
1818 if (div > 7)
1819 div = 7;
1820 if (!div)
1821 div = 1;
1822
1823 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1824 1 << 16, 1 << 16, &num, &denom);
1825
1826 tdiv64 = sport->port.uartclk;
1827 tdiv64 *= num;
1828 do_div(tdiv64, denom * 16 * div);
1829 tty_termios_encode_baud_rate(termios,
1830 (speed_t)tdiv64, (speed_t)tdiv64);
1831
1832 num -= 1;
1833 denom -= 1;
1834
1835 ufcr = imx_uart_readl(sport, UFCR);
1836 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1837 imx_uart_writel(sport, ufcr, UFCR);
1838
1839 /*
1840 * Two registers below should always be written both and in this
1841 * particular order. One consequence is that we need to check if any of
1842 * them changes and then update both. We do need the check for change
1843 * as even writing the same values seem to "restart"
1844 * transmission/receiving logic in the hardware, that leads to data
1845 * breakage even when rate doesn't in fact change. E.g., user switches
1846 * RTS/CTS handshake and suddenly gets broken bytes.
1847 */
1848 old_ubir = imx_uart_readl(sport, UBIR);
1849 old_ubmr = imx_uart_readl(sport, UBMR);
1850 if (old_ubir != num || old_ubmr != denom) {
1851 imx_uart_writel(sport, num, UBIR);
1852 imx_uart_writel(sport, denom, UBMR);
1853 }
1854
1855 if (!imx_uart_is_imx1(sport))
1856 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1857 IMX21_ONEMS);
1858
1859 imx_uart_writel(sport, ucr2, UCR2);
1860
1861 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1862 imx_uart_enable_ms(&sport->port);
1863
1864 uart_port_unlock_irqrestore(&sport->port, flags);
1865 }
1866
imx_uart_type(struct uart_port * port)1867 static const char *imx_uart_type(struct uart_port *port)
1868 {
1869 return port->type == PORT_IMX ? "IMX" : NULL;
1870 }
1871
1872 /*
1873 * Configure/autoconfigure the port.
1874 */
imx_uart_config_port(struct uart_port * port,int flags)1875 static void imx_uart_config_port(struct uart_port *port, int flags)
1876 {
1877 if (flags & UART_CONFIG_TYPE)
1878 port->type = PORT_IMX;
1879 }
1880
1881 /*
1882 * Verify the new serial_struct (for TIOCSSERIAL).
1883 * The only change we allow are to the flags and type, and
1884 * even then only between PORT_IMX and PORT_UNKNOWN
1885 */
1886 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1887 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1888 {
1889 int ret = 0;
1890
1891 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1892 ret = -EINVAL;
1893 if (port->irq != ser->irq)
1894 ret = -EINVAL;
1895 if (ser->io_type != UPIO_MEM)
1896 ret = -EINVAL;
1897 if (port->uartclk / 16 != ser->baud_base)
1898 ret = -EINVAL;
1899 if (port->mapbase != (unsigned long)ser->iomem_base)
1900 ret = -EINVAL;
1901 if (port->iobase != ser->port)
1902 ret = -EINVAL;
1903 if (ser->hub6 != 0)
1904 ret = -EINVAL;
1905 return ret;
1906 }
1907
1908 #if defined(CONFIG_CONSOLE_POLL)
1909
imx_uart_poll_init(struct uart_port * port)1910 static int imx_uart_poll_init(struct uart_port *port)
1911 {
1912 struct imx_port *sport = to_imx_port(port);
1913 unsigned long flags;
1914 u32 ucr1, ucr2;
1915 int retval;
1916
1917 retval = clk_prepare_enable(sport->clk_ipg);
1918 if (retval)
1919 return retval;
1920 retval = clk_prepare_enable(sport->clk_per);
1921 if (retval)
1922 clk_disable_unprepare(sport->clk_ipg);
1923
1924 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1925
1926 uart_port_lock_irqsave(&sport->port, &flags);
1927
1928 /*
1929 * Be careful about the order of enabling bits here. First enable the
1930 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1931 * This prevents that a character that already sits in the RX fifo is
1932 * triggering an irq but the try to fetch it from there results in an
1933 * exception because UARTEN or RXEN is still off.
1934 */
1935 ucr1 = imx_uart_readl(sport, UCR1);
1936 ucr2 = imx_uart_readl(sport, UCR2);
1937
1938 if (imx_uart_is_imx1(sport))
1939 ucr1 |= IMX1_UCR1_UARTCLKEN;
1940
1941 ucr1 |= UCR1_UARTEN;
1942 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1943
1944 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1945 ucr2 &= ~UCR2_ATEN;
1946
1947 imx_uart_writel(sport, ucr1, UCR1);
1948 imx_uart_writel(sport, ucr2, UCR2);
1949
1950 /* now enable irqs */
1951 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1952 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1953
1954 uart_port_unlock_irqrestore(&sport->port, flags);
1955
1956 return 0;
1957 }
1958
imx_uart_poll_get_char(struct uart_port * port)1959 static int imx_uart_poll_get_char(struct uart_port *port)
1960 {
1961 struct imx_port *sport = to_imx_port(port);
1962 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1963 return NO_POLL_CHAR;
1964
1965 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1966 }
1967
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1968 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1969 {
1970 struct imx_port *sport = to_imx_port(port);
1971 unsigned int status;
1972
1973 /* drain */
1974 do {
1975 status = imx_uart_readl(sport, USR1);
1976 } while (~status & USR1_TRDY);
1977
1978 /* write */
1979 imx_uart_writel(sport, c, URTX0);
1980
1981 /* flush */
1982 do {
1983 status = imx_uart_readl(sport, USR2);
1984 } while (~status & USR2_TXDC);
1985 }
1986 #endif
1987
1988 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)1989 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1990 struct serial_rs485 *rs485conf)
1991 {
1992 struct imx_port *sport = to_imx_port(port);
1993 u32 ucr2, ufcr;
1994
1995 if (rs485conf->flags & SER_RS485_ENABLED) {
1996 /* Enable receiver if low-active RTS signal is requested */
1997 if (sport->have_rtscts && !sport->have_rtsgpio &&
1998 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1999 rs485conf->flags |= SER_RS485_RX_DURING_TX;
2000
2001 /* disable transmitter */
2002 ucr2 = imx_uart_readl(sport, UCR2);
2003 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
2004 imx_uart_rts_active(sport, &ucr2);
2005 else
2006 imx_uart_rts_inactive(sport, &ucr2);
2007 imx_uart_writel(sport, ucr2, UCR2);
2008 }
2009
2010 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
2011 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
2012 rs485conf->flags & SER_RS485_RX_DURING_TX) {
2013 /* If the receiver trigger is 0, set it to a default value */
2014 ufcr = imx_uart_readl(sport, UFCR);
2015 if ((ufcr & UFCR_RXTL_MASK) == 0)
2016 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2017 imx_uart_start_rx(port);
2018 }
2019
2020 return 0;
2021 }
2022
2023 static const struct uart_ops imx_uart_pops = {
2024 .tx_empty = imx_uart_tx_empty,
2025 .set_mctrl = imx_uart_set_mctrl,
2026 .get_mctrl = imx_uart_get_mctrl,
2027 .stop_tx = imx_uart_stop_tx,
2028 .start_tx = imx_uart_start_tx,
2029 .stop_rx = imx_uart_stop_rx,
2030 .enable_ms = imx_uart_enable_ms,
2031 .break_ctl = imx_uart_break_ctl,
2032 .startup = imx_uart_startup,
2033 .shutdown = imx_uart_shutdown,
2034 .flush_buffer = imx_uart_flush_buffer,
2035 .set_termios = imx_uart_set_termios,
2036 .type = imx_uart_type,
2037 .config_port = imx_uart_config_port,
2038 .verify_port = imx_uart_verify_port,
2039 #if defined(CONFIG_CONSOLE_POLL)
2040 .poll_init = imx_uart_poll_init,
2041 .poll_get_char = imx_uart_poll_get_char,
2042 .poll_put_char = imx_uart_poll_put_char,
2043 #endif
2044 };
2045
2046 static struct imx_port *imx_uart_ports[UART_NR];
2047
2048 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)2049 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2050 {
2051 struct imx_port *sport = to_imx_port(port);
2052
2053 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2054 barrier();
2055
2056 imx_uart_writel(sport, ch, URTX0);
2057 }
2058
2059 /*
2060 * Interrupts are disabled on entering
2061 */
2062 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)2063 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2064 {
2065 struct imx_port *sport = imx_uart_ports[co->index];
2066 struct imx_port_ucrs old_ucr;
2067 unsigned long flags;
2068 unsigned int ucr1, usr2;
2069 int locked = 1;
2070
2071 if (sport->port.sysrq)
2072 locked = 0;
2073 else if (oops_in_progress)
2074 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2075 else
2076 uart_port_lock_irqsave(&sport->port, &flags);
2077
2078 /*
2079 * First, save UCR1/2/3 and then disable interrupts
2080 */
2081 imx_uart_ucrs_save(sport, &old_ucr);
2082 ucr1 = old_ucr.ucr1;
2083
2084 if (imx_uart_is_imx1(sport))
2085 ucr1 |= IMX1_UCR1_UARTCLKEN;
2086 ucr1 |= UCR1_UARTEN;
2087 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2088
2089 imx_uart_writel(sport, ucr1, UCR1);
2090
2091 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2092
2093 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2094
2095 /*
2096 * Finally, wait for transmitter to become empty
2097 * and restore UCR1/2/3
2098 */
2099 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2100 0, USEC_PER_SEC, false, sport, USR2);
2101 imx_uart_ucrs_restore(sport, &old_ucr);
2102
2103 if (locked)
2104 uart_port_unlock_irqrestore(&sport->port, flags);
2105 }
2106
2107 /*
2108 * If the port was already initialised (eg, by a boot loader),
2109 * try to determine the current setup.
2110 */
2111 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2112 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2113 int *parity, int *bits)
2114 {
2115
2116 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2117 /* ok, the port was enabled */
2118 unsigned int ucr2, ubir, ubmr, uartclk;
2119 unsigned int baud_raw;
2120 unsigned int ucfr_rfdiv;
2121
2122 ucr2 = imx_uart_readl(sport, UCR2);
2123
2124 *parity = 'n';
2125 if (ucr2 & UCR2_PREN) {
2126 if (ucr2 & UCR2_PROE)
2127 *parity = 'o';
2128 else
2129 *parity = 'e';
2130 }
2131
2132 if (ucr2 & UCR2_WS)
2133 *bits = 8;
2134 else
2135 *bits = 7;
2136
2137 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2138 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2139
2140 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2141 if (ucfr_rfdiv == 6)
2142 ucfr_rfdiv = 7;
2143 else
2144 ucfr_rfdiv = 6 - ucfr_rfdiv;
2145
2146 uartclk = clk_get_rate(sport->clk_per);
2147 uartclk /= ucfr_rfdiv;
2148
2149 { /*
2150 * The next code provides exact computation of
2151 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2152 * without need of float support or long long division,
2153 * which would be required to prevent 32bit arithmetic overflow
2154 */
2155 unsigned int mul = ubir + 1;
2156 unsigned int div = 16 * (ubmr + 1);
2157 unsigned int rem = uartclk % div;
2158
2159 baud_raw = (uartclk / div) * mul;
2160 baud_raw += (rem * mul + div / 2) / div;
2161 *baud = (baud_raw + 50) / 100 * 100;
2162 }
2163
2164 if (*baud != baud_raw)
2165 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2166 baud_raw, *baud);
2167 }
2168 }
2169
2170 static int
imx_uart_console_setup(struct console * co,char * options)2171 imx_uart_console_setup(struct console *co, char *options)
2172 {
2173 struct imx_port *sport;
2174 int baud = 9600;
2175 int bits = 8;
2176 int parity = 'n';
2177 int flow = 'n';
2178 int retval;
2179
2180 /*
2181 * Check whether an invalid uart number has been specified, and
2182 * if so, search for the first available port that does have
2183 * console support.
2184 */
2185 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2186 co->index = 0;
2187 sport = imx_uart_ports[co->index];
2188 if (sport == NULL)
2189 return -ENODEV;
2190
2191 /* For setting the registers, we only need to enable the ipg clock. */
2192 retval = clk_prepare_enable(sport->clk_ipg);
2193 if (retval)
2194 goto error_console;
2195
2196 if (options)
2197 uart_parse_options(options, &baud, &parity, &bits, &flow);
2198 else
2199 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2200
2201 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2202
2203 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2204
2205 if (retval) {
2206 clk_disable_unprepare(sport->clk_ipg);
2207 goto error_console;
2208 }
2209
2210 retval = clk_prepare_enable(sport->clk_per);
2211 if (retval)
2212 clk_disable_unprepare(sport->clk_ipg);
2213
2214 error_console:
2215 return retval;
2216 }
2217
2218 static int
imx_uart_console_exit(struct console * co)2219 imx_uart_console_exit(struct console *co)
2220 {
2221 struct imx_port *sport = imx_uart_ports[co->index];
2222
2223 clk_disable_unprepare(sport->clk_per);
2224 clk_disable_unprepare(sport->clk_ipg);
2225
2226 return 0;
2227 }
2228
2229 static struct uart_driver imx_uart_uart_driver;
2230 static struct console imx_uart_console = {
2231 .name = DEV_NAME,
2232 .write = imx_uart_console_write,
2233 .device = uart_console_device,
2234 .setup = imx_uart_console_setup,
2235 .exit = imx_uart_console_exit,
2236 .flags = CON_PRINTBUFFER,
2237 .index = -1,
2238 .data = &imx_uart_uart_driver,
2239 };
2240
2241 #define IMX_CONSOLE &imx_uart_console
2242
2243 #else
2244 #define IMX_CONSOLE NULL
2245 #endif
2246
2247 static struct uart_driver imx_uart_uart_driver = {
2248 .owner = THIS_MODULE,
2249 .driver_name = DRIVER_NAME,
2250 .dev_name = DEV_NAME,
2251 .major = SERIAL_IMX_MAJOR,
2252 .minor = MINOR_START,
2253 .nr = ARRAY_SIZE(imx_uart_ports),
2254 .cons = IMX_CONSOLE,
2255 };
2256
imx_trigger_start_tx(struct hrtimer * t)2257 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2258 {
2259 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2260 unsigned long flags;
2261
2262 uart_port_lock_irqsave(&sport->port, &flags);
2263 if (sport->tx_state == WAIT_AFTER_RTS)
2264 imx_uart_start_tx(&sport->port);
2265 uart_port_unlock_irqrestore(&sport->port, flags);
2266
2267 return HRTIMER_NORESTART;
2268 }
2269
imx_trigger_stop_tx(struct hrtimer * t)2270 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2271 {
2272 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2273 unsigned long flags;
2274
2275 uart_port_lock_irqsave(&sport->port, &flags);
2276 if (sport->tx_state == WAIT_AFTER_SEND)
2277 imx_uart_stop_tx(&sport->port);
2278 uart_port_unlock_irqrestore(&sport->port, flags);
2279
2280 return HRTIMER_NORESTART;
2281 }
2282
2283 static const struct serial_rs485 imx_rs485_supported = {
2284 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2285 SER_RS485_RX_DURING_TX,
2286 .delay_rts_before_send = 1,
2287 .delay_rts_after_send = 1,
2288 };
2289
2290 /* Default RX DMA buffer configuration */
2291 #define RX_DMA_PERIODS 16
2292 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2293
imx_uart_probe(struct platform_device * pdev)2294 static int imx_uart_probe(struct platform_device *pdev)
2295 {
2296 struct device_node *np = pdev->dev.of_node;
2297 struct imx_port *sport;
2298 void __iomem *base;
2299 u32 dma_buf_conf[2];
2300 int ret = 0;
2301 u32 ucr1, ucr2, uts;
2302 struct resource *res;
2303 int txirq, rxirq, rtsirq;
2304
2305 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2306 if (!sport)
2307 return -ENOMEM;
2308
2309 sport->devdata = of_device_get_match_data(&pdev->dev);
2310
2311 ret = of_alias_get_id(np, "serial");
2312 if (ret < 0) {
2313 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2314 return ret;
2315 }
2316 sport->port.line = ret;
2317
2318 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2319 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2320
2321 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2322
2323 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2324
2325 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2326
2327 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2328
2329 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2330 sport->rx_period_length = dma_buf_conf[0];
2331 sport->rx_periods = dma_buf_conf[1];
2332 } else {
2333 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2334 sport->rx_periods = RX_DMA_PERIODS;
2335 }
2336
2337 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2338 dev_err(&pdev->dev, "serial%d out of range\n",
2339 sport->port.line);
2340 return -EINVAL;
2341 }
2342
2343 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2344 if (IS_ERR(base))
2345 return PTR_ERR(base);
2346
2347 rxirq = platform_get_irq(pdev, 0);
2348 if (rxirq < 0)
2349 return rxirq;
2350 txirq = platform_get_irq_optional(pdev, 1);
2351 rtsirq = platform_get_irq_optional(pdev, 2);
2352
2353 sport->port.dev = &pdev->dev;
2354 sport->port.mapbase = res->start;
2355 sport->port.membase = base;
2356 sport->port.type = PORT_IMX;
2357 sport->port.iotype = UPIO_MEM;
2358 sport->port.irq = rxirq;
2359 sport->port.fifosize = 32;
2360 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2361 sport->port.ops = &imx_uart_pops;
2362 sport->port.rs485_config = imx_uart_rs485_config;
2363 /* RTS is required to control the RS485 transmitter */
2364 if (sport->have_rtscts || sport->have_rtsgpio)
2365 sport->port.rs485_supported = imx_rs485_supported;
2366 sport->port.flags = UPF_BOOT_AUTOCONF;
2367 timer_setup(&sport->timer, imx_uart_timeout, 0);
2368
2369 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2370 if (IS_ERR(sport->gpios))
2371 return PTR_ERR(sport->gpios);
2372
2373 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2374 if (IS_ERR(sport->clk_ipg)) {
2375 ret = PTR_ERR(sport->clk_ipg);
2376 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2377 return ret;
2378 }
2379
2380 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2381 if (IS_ERR(sport->clk_per)) {
2382 ret = PTR_ERR(sport->clk_per);
2383 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2384 return ret;
2385 }
2386
2387 sport->port.uartclk = clk_get_rate(sport->clk_per);
2388
2389 /* For register access, we only need to enable the ipg clock. */
2390 ret = clk_prepare_enable(sport->clk_ipg);
2391 if (ret) {
2392 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2393 return ret;
2394 }
2395
2396 ret = uart_get_rs485_mode(&sport->port);
2397 if (ret)
2398 goto err_clk;
2399
2400 /*
2401 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2402 * signal cannot be set low during transmission in case the
2403 * receiver is off (limitation of the i.MX UART IP).
2404 */
2405 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2406 sport->have_rtscts && !sport->have_rtsgpio &&
2407 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2408 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2409 dev_err(&pdev->dev,
2410 "low-active RTS not possible when receiver is off, enabling receiver\n");
2411
2412 /* Disable interrupts before requesting them */
2413 ucr1 = imx_uart_readl(sport, UCR1);
2414 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2415 imx_uart_writel(sport, ucr1, UCR1);
2416
2417 /* Disable Ageing Timer interrupt */
2418 ucr2 = imx_uart_readl(sport, UCR2);
2419 ucr2 &= ~UCR2_ATEN;
2420 imx_uart_writel(sport, ucr2, UCR2);
2421
2422 /*
2423 * In case RS485 is enabled without GPIO RTS control, the UART IP
2424 * is used to control CTS signal. Keep both the UART and Receiver
2425 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2426 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2427 * data from being fed into the RX FIFO, enable loopback mode in
2428 * UTS register, which disconnects the RX path from external RXD
2429 * pin and connects it to the Transceiver, which is disabled, so
2430 * no data can be fed to the RX FIFO that way.
2431 */
2432 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2433 sport->have_rtscts && !sport->have_rtsgpio) {
2434 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2435 uts |= UTS_LOOP;
2436 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2437
2438 ucr1 = imx_uart_readl(sport, UCR1);
2439 ucr1 |= UCR1_UARTEN;
2440 imx_uart_writel(sport, ucr1, UCR1);
2441
2442 ucr2 = imx_uart_readl(sport, UCR2);
2443 ucr2 |= UCR2_RXEN;
2444 imx_uart_writel(sport, ucr2, UCR2);
2445 }
2446
2447 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2448 /*
2449 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2450 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2451 * and DCD (when they are outputs) or enables the respective
2452 * irqs. So set this bit early, i.e. before requesting irqs.
2453 */
2454 u32 ufcr = imx_uart_readl(sport, UFCR);
2455 if (!(ufcr & UFCR_DCEDTE))
2456 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2457
2458 /*
2459 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2460 * enabled later because they cannot be cleared
2461 * (confirmed on i.MX25) which makes them unusable.
2462 */
2463 imx_uart_writel(sport,
2464 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2465 UCR3);
2466
2467 } else {
2468 u32 ucr3 = UCR3_DSR;
2469 u32 ufcr = imx_uart_readl(sport, UFCR);
2470 if (ufcr & UFCR_DCEDTE)
2471 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2472
2473 if (!imx_uart_is_imx1(sport))
2474 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2475 imx_uart_writel(sport, ucr3, UCR3);
2476 }
2477
2478 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2479 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2480 sport->trigger_start_tx.function = imx_trigger_start_tx;
2481 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2482
2483 /*
2484 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2485 * chips only have one interrupt.
2486 */
2487 if (txirq > 0) {
2488 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2489 dev_name(&pdev->dev), sport);
2490 if (ret) {
2491 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2492 ret);
2493 goto err_clk;
2494 }
2495
2496 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2497 dev_name(&pdev->dev), sport);
2498 if (ret) {
2499 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2500 ret);
2501 goto err_clk;
2502 }
2503
2504 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2505 dev_name(&pdev->dev), sport);
2506 if (ret) {
2507 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2508 ret);
2509 goto err_clk;
2510 }
2511 } else {
2512 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2513 dev_name(&pdev->dev), sport);
2514 if (ret) {
2515 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2516 goto err_clk;
2517 }
2518 }
2519
2520 imx_uart_ports[sport->port.line] = sport;
2521
2522 platform_set_drvdata(pdev, sport);
2523
2524 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2525
2526 err_clk:
2527 clk_disable_unprepare(sport->clk_ipg);
2528
2529 return ret;
2530 }
2531
imx_uart_remove(struct platform_device * pdev)2532 static void imx_uart_remove(struct platform_device *pdev)
2533 {
2534 struct imx_port *sport = platform_get_drvdata(pdev);
2535
2536 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2537 }
2538
imx_uart_restore_context(struct imx_port * sport)2539 static void imx_uart_restore_context(struct imx_port *sport)
2540 {
2541 unsigned long flags;
2542
2543 uart_port_lock_irqsave(&sport->port, &flags);
2544 if (!sport->context_saved) {
2545 uart_port_unlock_irqrestore(&sport->port, flags);
2546 return;
2547 }
2548
2549 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2550 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2551 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2552 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2553 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2554 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2555 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2556 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2557 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2558 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2559 sport->context_saved = false;
2560 uart_port_unlock_irqrestore(&sport->port, flags);
2561 }
2562
imx_uart_save_context(struct imx_port * sport)2563 static void imx_uart_save_context(struct imx_port *sport)
2564 {
2565 unsigned long flags;
2566
2567 /* Save necessary regs */
2568 uart_port_lock_irqsave(&sport->port, &flags);
2569 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2570 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2571 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2572 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2573 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2574 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2575 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2576 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2577 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2578 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2579 sport->context_saved = true;
2580 uart_port_unlock_irqrestore(&sport->port, flags);
2581 }
2582
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2583 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2584 {
2585 u32 ucr3;
2586
2587 ucr3 = imx_uart_readl(sport, UCR3);
2588 if (on) {
2589 imx_uart_writel(sport, USR1_AWAKE, USR1);
2590 ucr3 |= UCR3_AWAKEN;
2591 } else {
2592 ucr3 &= ~UCR3_AWAKEN;
2593 }
2594 imx_uart_writel(sport, ucr3, UCR3);
2595
2596 if (sport->have_rtscts) {
2597 u32 ucr1 = imx_uart_readl(sport, UCR1);
2598 if (on) {
2599 imx_uart_writel(sport, USR1_RTSD, USR1);
2600 ucr1 |= UCR1_RTSDEN;
2601 } else {
2602 ucr1 &= ~UCR1_RTSDEN;
2603 }
2604 imx_uart_writel(sport, ucr1, UCR1);
2605 }
2606 }
2607
imx_uart_suspend_noirq(struct device * dev)2608 static int imx_uart_suspend_noirq(struct device *dev)
2609 {
2610 struct imx_port *sport = dev_get_drvdata(dev);
2611
2612 imx_uart_save_context(sport);
2613
2614 clk_disable(sport->clk_ipg);
2615
2616 pinctrl_pm_select_sleep_state(dev);
2617
2618 return 0;
2619 }
2620
imx_uart_resume_noirq(struct device * dev)2621 static int imx_uart_resume_noirq(struct device *dev)
2622 {
2623 struct imx_port *sport = dev_get_drvdata(dev);
2624 int ret;
2625
2626 pinctrl_pm_select_default_state(dev);
2627
2628 ret = clk_enable(sport->clk_ipg);
2629 if (ret)
2630 return ret;
2631
2632 imx_uart_restore_context(sport);
2633
2634 return 0;
2635 }
2636
imx_uart_suspend(struct device * dev)2637 static int imx_uart_suspend(struct device *dev)
2638 {
2639 struct imx_port *sport = dev_get_drvdata(dev);
2640 int ret;
2641
2642 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2643 disable_irq(sport->port.irq);
2644
2645 ret = clk_prepare_enable(sport->clk_ipg);
2646 if (ret)
2647 return ret;
2648
2649 /* enable wakeup from i.MX UART */
2650 imx_uart_enable_wakeup(sport, true);
2651
2652 return 0;
2653 }
2654
imx_uart_resume(struct device * dev)2655 static int imx_uart_resume(struct device *dev)
2656 {
2657 struct imx_port *sport = dev_get_drvdata(dev);
2658
2659 /* disable wakeup from i.MX UART */
2660 imx_uart_enable_wakeup(sport, false);
2661
2662 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2663 enable_irq(sport->port.irq);
2664
2665 clk_disable_unprepare(sport->clk_ipg);
2666
2667 return 0;
2668 }
2669
imx_uart_freeze(struct device * dev)2670 static int imx_uart_freeze(struct device *dev)
2671 {
2672 struct imx_port *sport = dev_get_drvdata(dev);
2673
2674 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2675
2676 return clk_prepare_enable(sport->clk_ipg);
2677 }
2678
imx_uart_thaw(struct device * dev)2679 static int imx_uart_thaw(struct device *dev)
2680 {
2681 struct imx_port *sport = dev_get_drvdata(dev);
2682
2683 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2684
2685 clk_disable_unprepare(sport->clk_ipg);
2686
2687 return 0;
2688 }
2689
2690 static const struct dev_pm_ops imx_uart_pm_ops = {
2691 .suspend_noirq = imx_uart_suspend_noirq,
2692 .resume_noirq = imx_uart_resume_noirq,
2693 .freeze_noirq = imx_uart_suspend_noirq,
2694 .thaw_noirq = imx_uart_resume_noirq,
2695 .restore_noirq = imx_uart_resume_noirq,
2696 .suspend = imx_uart_suspend,
2697 .resume = imx_uart_resume,
2698 .freeze = imx_uart_freeze,
2699 .thaw = imx_uart_thaw,
2700 .restore = imx_uart_thaw,
2701 };
2702
2703 static struct platform_driver imx_uart_platform_driver = {
2704 .probe = imx_uart_probe,
2705 .remove_new = imx_uart_remove,
2706
2707 .driver = {
2708 .name = "imx-uart",
2709 .of_match_table = imx_uart_dt_ids,
2710 .pm = &imx_uart_pm_ops,
2711 },
2712 };
2713
imx_uart_init(void)2714 static int __init imx_uart_init(void)
2715 {
2716 int ret = uart_register_driver(&imx_uart_uart_driver);
2717
2718 if (ret)
2719 return ret;
2720
2721 ret = platform_driver_register(&imx_uart_platform_driver);
2722 if (ret != 0)
2723 uart_unregister_driver(&imx_uart_uart_driver);
2724
2725 return ret;
2726 }
2727
imx_uart_exit(void)2728 static void __exit imx_uart_exit(void)
2729 {
2730 platform_driver_unregister(&imx_uart_platform_driver);
2731 uart_unregister_driver(&imx_uart_uart_driver);
2732 }
2733
2734 module_init(imx_uart_init);
2735 module_exit(imx_uart_exit);
2736
2737 MODULE_AUTHOR("Sascha Hauer");
2738 MODULE_DESCRIPTION("IMX generic serial port driver");
2739 MODULE_LICENSE("GPL");
2740 MODULE_ALIAS("platform:imx-uart");
2741