1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/circ_buf.h> 11 #include <linux/clk.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_dma.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/serial_core.h> 27 #include <linux/slab.h> 28 #include <linux/tty_flip.h> 29 30 /* All registers are 8-bit width */ 31 #define UARTBDH 0x00 32 #define UARTBDL 0x01 33 #define UARTCR1 0x02 34 #define UARTCR2 0x03 35 #define UARTSR1 0x04 36 #define UARTCR3 0x06 37 #define UARTDR 0x07 38 #define UARTCR4 0x0a 39 #define UARTCR5 0x0b 40 #define UARTMODEM 0x0d 41 #define UARTPFIFO 0x10 42 #define UARTCFIFO 0x11 43 #define UARTSFIFO 0x12 44 #define UARTTWFIFO 0x13 45 #define UARTTCFIFO 0x14 46 #define UARTRWFIFO 0x15 47 48 #define UARTBDH_LBKDIE 0x80 49 #define UARTBDH_RXEDGIE 0x40 50 #define UARTBDH_SBR_MASK 0x1f 51 52 #define UARTCR1_LOOPS 0x80 53 #define UARTCR1_RSRC 0x20 54 #define UARTCR1_M 0x10 55 #define UARTCR1_WAKE 0x08 56 #define UARTCR1_ILT 0x04 57 #define UARTCR1_PE 0x02 58 #define UARTCR1_PT 0x01 59 60 #define UARTCR2_TIE 0x80 61 #define UARTCR2_TCIE 0x40 62 #define UARTCR2_RIE 0x20 63 #define UARTCR2_ILIE 0x10 64 #define UARTCR2_TE 0x08 65 #define UARTCR2_RE 0x04 66 #define UARTCR2_RWU 0x02 67 #define UARTCR2_SBK 0x01 68 69 #define UARTSR1_TDRE 0x80 70 #define UARTSR1_TC 0x40 71 #define UARTSR1_RDRF 0x20 72 #define UARTSR1_IDLE 0x10 73 #define UARTSR1_OR 0x08 74 #define UARTSR1_NF 0x04 75 #define UARTSR1_FE 0x02 76 #define UARTSR1_PE 0x01 77 78 #define UARTCR3_R8 0x80 79 #define UARTCR3_T8 0x40 80 #define UARTCR3_TXDIR 0x20 81 #define UARTCR3_TXINV 0x10 82 #define UARTCR3_ORIE 0x08 83 #define UARTCR3_NEIE 0x04 84 #define UARTCR3_FEIE 0x02 85 #define UARTCR3_PEIE 0x01 86 87 #define UARTCR4_MAEN1 0x80 88 #define UARTCR4_MAEN2 0x40 89 #define UARTCR4_M10 0x20 90 #define UARTCR4_BRFA_MASK 0x1f 91 #define UARTCR4_BRFA_OFF 0 92 93 #define UARTCR5_TDMAS 0x80 94 #define UARTCR5_RDMAS 0x20 95 96 #define UARTMODEM_RXRTSE 0x08 97 #define UARTMODEM_TXRTSPOL 0x04 98 #define UARTMODEM_TXRTSE 0x02 99 #define UARTMODEM_TXCTSE 0x01 100 101 #define UARTPFIFO_TXFE 0x80 102 #define UARTPFIFO_FIFOSIZE_MASK 0x7 103 #define UARTPFIFO_TXSIZE_OFF 4 104 #define UARTPFIFO_RXFE 0x08 105 #define UARTPFIFO_RXSIZE_OFF 0 106 107 #define UARTCFIFO_TXFLUSH 0x80 108 #define UARTCFIFO_RXFLUSH 0x40 109 #define UARTCFIFO_RXOFE 0x04 110 #define UARTCFIFO_TXOFE 0x02 111 #define UARTCFIFO_RXUFE 0x01 112 113 #define UARTSFIFO_TXEMPT 0x80 114 #define UARTSFIFO_RXEMPT 0x40 115 #define UARTSFIFO_RXOF 0x04 116 #define UARTSFIFO_TXOF 0x02 117 #define UARTSFIFO_RXUF 0x01 118 119 /* 32-bit global registers only for i.MX7ULP/i.MX8x 120 * Used to reset all internal logic and registers, except the Global Register. 121 */ 122 #define UART_GLOBAL 0x8 123 124 /* 32-bit register definition */ 125 #define UARTBAUD 0x00 126 #define UARTSTAT 0x04 127 #define UARTCTRL 0x08 128 #define UARTDATA 0x0C 129 #define UARTMATCH 0x10 130 #define UARTMODIR 0x14 131 #define UARTFIFO 0x18 132 #define UARTWATER 0x1c 133 134 #define UARTBAUD_MAEN1 0x80000000 135 #define UARTBAUD_MAEN2 0x40000000 136 #define UARTBAUD_M10 0x20000000 137 #define UARTBAUD_TDMAE 0x00800000 138 #define UARTBAUD_RDMAE 0x00200000 139 #define UARTBAUD_MATCFG 0x00400000 140 #define UARTBAUD_BOTHEDGE 0x00020000 141 #define UARTBAUD_RESYNCDIS 0x00010000 142 #define UARTBAUD_LBKDIE 0x00008000 143 #define UARTBAUD_RXEDGIE 0x00004000 144 #define UARTBAUD_SBNS 0x00002000 145 #define UARTBAUD_SBR 0x00000000 146 #define UARTBAUD_SBR_MASK 0x1fff 147 #define UARTBAUD_OSR_MASK 0x1f 148 #define UARTBAUD_OSR_SHIFT 24 149 150 #define UARTSTAT_LBKDIF 0x80000000 151 #define UARTSTAT_RXEDGIF 0x40000000 152 #define UARTSTAT_MSBF 0x20000000 153 #define UARTSTAT_RXINV 0x10000000 154 #define UARTSTAT_RWUID 0x08000000 155 #define UARTSTAT_BRK13 0x04000000 156 #define UARTSTAT_LBKDE 0x02000000 157 #define UARTSTAT_RAF 0x01000000 158 #define UARTSTAT_TDRE 0x00800000 159 #define UARTSTAT_TC 0x00400000 160 #define UARTSTAT_RDRF 0x00200000 161 #define UARTSTAT_IDLE 0x00100000 162 #define UARTSTAT_OR 0x00080000 163 #define UARTSTAT_NF 0x00040000 164 #define UARTSTAT_FE 0x00020000 165 #define UARTSTAT_PE 0x00010000 166 #define UARTSTAT_MA1F 0x00008000 167 #define UARTSTAT_M21F 0x00004000 168 169 #define UARTCTRL_R8T9 0x80000000 170 #define UARTCTRL_R9T8 0x40000000 171 #define UARTCTRL_TXDIR 0x20000000 172 #define UARTCTRL_TXINV 0x10000000 173 #define UARTCTRL_ORIE 0x08000000 174 #define UARTCTRL_NEIE 0x04000000 175 #define UARTCTRL_FEIE 0x02000000 176 #define UARTCTRL_PEIE 0x01000000 177 #define UARTCTRL_TIE 0x00800000 178 #define UARTCTRL_TCIE 0x00400000 179 #define UARTCTRL_RIE 0x00200000 180 #define UARTCTRL_ILIE 0x00100000 181 #define UARTCTRL_TE 0x00080000 182 #define UARTCTRL_RE 0x00040000 183 #define UARTCTRL_RWU 0x00020000 184 #define UARTCTRL_SBK 0x00010000 185 #define UARTCTRL_MA1IE 0x00008000 186 #define UARTCTRL_MA2IE 0x00004000 187 #define UARTCTRL_M7 0x00000800 188 #define UARTCTRL_IDLECFG GENMASK(10, 8) 189 #define UARTCTRL_LOOPS 0x00000080 190 #define UARTCTRL_DOZEEN 0x00000040 191 #define UARTCTRL_RSRC 0x00000020 192 #define UARTCTRL_M 0x00000010 193 #define UARTCTRL_WAKE 0x00000008 194 #define UARTCTRL_ILT 0x00000004 195 #define UARTCTRL_PE 0x00000002 196 #define UARTCTRL_PT 0x00000001 197 198 #define UARTDATA_NOISY 0x00008000 199 #define UARTDATA_PARITYE 0x00004000 200 #define UARTDATA_FRETSC 0x00002000 201 #define UARTDATA_RXEMPT 0x00001000 202 #define UARTDATA_IDLINE 0x00000800 203 #define UARTDATA_MASK 0x3ff 204 205 #define UARTMODIR_IREN 0x00020000 206 #define UARTMODIR_RTSWATER GENMASK(10, 8) 207 #define UARTMODIR_TXCTSSRC 0x00000020 208 #define UARTMODIR_TXCTSC 0x00000010 209 #define UARTMODIR_RXRTSE 0x00000008 210 #define UARTMODIR_TXRTSPOL 0x00000004 211 #define UARTMODIR_TXRTSE 0x00000002 212 #define UARTMODIR_TXCTSE 0x00000001 213 214 #define UARTFIFO_TXEMPT 0x00800000 215 #define UARTFIFO_RXEMPT 0x00400000 216 #define UARTFIFO_TXOF 0x00020000 217 #define UARTFIFO_RXUF 0x00010000 218 #define UARTFIFO_TXFLUSH 0x00008000 219 #define UARTFIFO_RXFLUSH 0x00004000 220 #define UARTFIFO_RXIDEN GENMASK(12, 10) 221 #define UARTFIFO_TXOFE 0x00000200 222 #define UARTFIFO_RXUFE 0x00000100 223 #define UARTFIFO_TXFE 0x00000080 224 #define UARTFIFO_FIFOSIZE_MASK 0x7 225 #define UARTFIFO_TXSIZE_OFF 4 226 #define UARTFIFO_RXFE 0x00000008 227 #define UARTFIFO_RXSIZE_OFF 0 228 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 229 230 #define UARTWATER_COUNT_MASK 0xff 231 #define UARTWATER_TXCNT_OFF 8 232 #define UARTWATER_RXCNT_OFF 24 233 #define UARTWATER_WATER_MASK 0xff 234 #define UARTWATER_TXWATER_OFF 0 235 #define UARTWATER_RXWATER_OFF 16 236 237 #define UART_GLOBAL_RST 0x2 238 #define GLOBAL_RST_MIN_US 20 239 #define GLOBAL_RST_MAX_US 40 240 241 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 242 #define DMA_RX_TIMEOUT (10) 243 #define DMA_RX_IDLE_CHARS 8 244 #define UART_AUTOSUSPEND_TIMEOUT 3000 245 246 #define DRIVER_NAME "fsl-lpuart" 247 #define DEV_NAME "ttyLP" 248 #define UART_NR 12 249 250 /* IMX lpuart has four extra unused regs located at the beginning */ 251 #define IMX_REG_OFF 0x10 252 253 enum lpuart_type { 254 VF610_LPUART, 255 LS1021A_LPUART, 256 LS1028A_LPUART, 257 IMX7ULP_LPUART, 258 IMX8ULP_LPUART, 259 IMX8QXP_LPUART, 260 IMXRT1050_LPUART, 261 }; 262 263 struct lpuart_port { 264 struct uart_port port; 265 enum lpuart_type devtype; 266 struct clk *ipg_clk; 267 struct clk *baud_clk; 268 unsigned int txfifo_size; 269 unsigned int rxfifo_size; 270 271 u8 rx_watermark; 272 bool lpuart_dma_tx_use; 273 bool lpuart_dma_rx_use; 274 struct dma_chan *dma_tx_chan; 275 struct dma_chan *dma_rx_chan; 276 struct dma_async_tx_descriptor *dma_tx_desc; 277 struct dma_async_tx_descriptor *dma_rx_desc; 278 dma_cookie_t dma_tx_cookie; 279 dma_cookie_t dma_rx_cookie; 280 unsigned int dma_tx_bytes; 281 unsigned int dma_rx_bytes; 282 bool dma_tx_in_progress; 283 unsigned int dma_rx_timeout; 284 struct timer_list lpuart_timer; 285 struct scatterlist rx_sgl, tx_sgl[2]; 286 struct circ_buf rx_ring; 287 int rx_dma_rng_buf_len; 288 int last_residue; 289 unsigned int dma_tx_nents; 290 wait_queue_head_t dma_wait; 291 bool is_cs7; /* Set to true when character size is 7 */ 292 /* and the parity is enabled */ 293 bool dma_idle_int; 294 }; 295 296 struct lpuart_soc_data { 297 enum lpuart_type devtype; 298 char iotype; 299 u8 reg_off; 300 u8 rx_watermark; 301 }; 302 303 static const struct lpuart_soc_data vf_data = { 304 .devtype = VF610_LPUART, 305 .iotype = UPIO_MEM, 306 .rx_watermark = 1, 307 }; 308 309 static const struct lpuart_soc_data ls1021a_data = { 310 .devtype = LS1021A_LPUART, 311 .iotype = UPIO_MEM32BE, 312 .rx_watermark = 1, 313 }; 314 315 static const struct lpuart_soc_data ls1028a_data = { 316 .devtype = LS1028A_LPUART, 317 .iotype = UPIO_MEM32, 318 .rx_watermark = 0, 319 }; 320 321 static const struct lpuart_soc_data imx7ulp_data = { 322 .devtype = IMX7ULP_LPUART, 323 .iotype = UPIO_MEM32, 324 .reg_off = IMX_REG_OFF, 325 .rx_watermark = 1, 326 }; 327 328 static const struct lpuart_soc_data imx8ulp_data = { 329 .devtype = IMX8ULP_LPUART, 330 .iotype = UPIO_MEM32, 331 .reg_off = IMX_REG_OFF, 332 .rx_watermark = 3, 333 }; 334 335 static const struct lpuart_soc_data imx8qxp_data = { 336 .devtype = IMX8QXP_LPUART, 337 .iotype = UPIO_MEM32, 338 .reg_off = IMX_REG_OFF, 339 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */ 340 }; 341 static const struct lpuart_soc_data imxrt1050_data = { 342 .devtype = IMXRT1050_LPUART, 343 .iotype = UPIO_MEM32, 344 .reg_off = IMX_REG_OFF, 345 .rx_watermark = 1, 346 }; 347 348 static const struct of_device_id lpuart_dt_ids[] = { 349 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 350 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 351 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 352 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 353 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, }, 354 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 355 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, 356 { /* sentinel */ } 357 }; 358 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 359 360 /* Forward declare this for the dma callbacks*/ 361 static void lpuart_dma_tx_complete(void *arg); 362 363 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) 364 { 365 return (sport->devtype == LS1021A_LPUART || 366 sport->devtype == LS1028A_LPUART); 367 } 368 369 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) 370 { 371 return sport->devtype == IMX7ULP_LPUART; 372 } 373 374 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport) 375 { 376 return sport->devtype == IMX8ULP_LPUART; 377 } 378 379 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 380 { 381 return sport->devtype == IMX8QXP_LPUART; 382 } 383 384 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 385 { 386 switch (port->iotype) { 387 case UPIO_MEM32: 388 return readl(port->membase + off); 389 case UPIO_MEM32BE: 390 return ioread32be(port->membase + off); 391 default: 392 return 0; 393 } 394 } 395 396 static inline void lpuart32_write(struct uart_port *port, u32 val, 397 u32 off) 398 { 399 switch (port->iotype) { 400 case UPIO_MEM32: 401 writel(val, port->membase + off); 402 break; 403 case UPIO_MEM32BE: 404 iowrite32be(val, port->membase + off); 405 break; 406 default: 407 break; 408 } 409 } 410 411 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 412 { 413 int ret = 0; 414 415 if (is_en) { 416 ret = clk_prepare_enable(sport->ipg_clk); 417 if (ret) 418 return ret; 419 420 ret = clk_prepare_enable(sport->baud_clk); 421 if (ret) { 422 clk_disable_unprepare(sport->ipg_clk); 423 return ret; 424 } 425 } else { 426 clk_disable_unprepare(sport->baud_clk); 427 clk_disable_unprepare(sport->ipg_clk); 428 } 429 430 return 0; 431 } 432 433 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 434 { 435 if (is_imx8qxp_lpuart(sport)) 436 return clk_get_rate(sport->baud_clk); 437 438 return clk_get_rate(sport->ipg_clk); 439 } 440 441 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 442 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 443 444 static void lpuart_stop_tx(struct uart_port *port) 445 { 446 u8 cr2; 447 448 cr2 = readb(port->membase + UARTCR2); 449 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE); 450 writeb(cr2, port->membase + UARTCR2); 451 } 452 453 static void lpuart32_stop_tx(struct uart_port *port) 454 { 455 u32 ctrl; 456 457 ctrl = lpuart32_read(port, UARTCTRL); 458 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 459 lpuart32_write(port, ctrl, UARTCTRL); 460 } 461 462 static void lpuart_stop_rx(struct uart_port *port) 463 { 464 u8 cr2; 465 466 cr2 = readb(port->membase + UARTCR2); 467 writeb(cr2 & ~UARTCR2_RE, port->membase + UARTCR2); 468 } 469 470 static void lpuart32_stop_rx(struct uart_port *port) 471 { 472 u32 ctrl; 473 474 ctrl = lpuart32_read(port, UARTCTRL); 475 lpuart32_write(port, ctrl & ~UARTCTRL_RE, UARTCTRL); 476 } 477 478 static void lpuart_dma_tx(struct lpuart_port *sport) 479 { 480 struct tty_port *tport = &sport->port.state->port; 481 struct scatterlist *sgl = sport->tx_sgl; 482 struct device *dev = sport->port.dev; 483 struct dma_chan *chan = sport->dma_tx_chan; 484 int ret; 485 486 if (sport->dma_tx_in_progress) 487 return; 488 489 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); 490 sport->dma_tx_bytes = kfifo_len(&tport->xmit_fifo); 491 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, 492 ARRAY_SIZE(sport->tx_sgl), sport->dma_tx_bytes); 493 494 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 495 DMA_TO_DEVICE); 496 if (!ret) { 497 dev_err(dev, "DMA mapping error for TX.\n"); 498 return; 499 } 500 501 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 502 ret, DMA_MEM_TO_DEV, 503 DMA_PREP_INTERRUPT); 504 if (!sport->dma_tx_desc) { 505 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 506 DMA_TO_DEVICE); 507 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 508 return; 509 } 510 511 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 512 sport->dma_tx_desc->callback_param = sport; 513 sport->dma_tx_in_progress = true; 514 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 515 dma_async_issue_pending(chan); 516 } 517 518 static bool lpuart_stopped_or_empty(struct uart_port *port) 519 { 520 return kfifo_is_empty(&port->state->port.xmit_fifo) || 521 uart_tx_stopped(port); 522 } 523 524 static void lpuart_dma_tx_complete(void *arg) 525 { 526 struct lpuart_port *sport = arg; 527 struct scatterlist *sgl = &sport->tx_sgl[0]; 528 struct tty_port *tport = &sport->port.state->port; 529 struct dma_chan *chan = sport->dma_tx_chan; 530 unsigned long flags; 531 532 uart_port_lock_irqsave(&sport->port, &flags); 533 if (!sport->dma_tx_in_progress) { 534 uart_port_unlock_irqrestore(&sport->port, flags); 535 return; 536 } 537 538 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 539 DMA_TO_DEVICE); 540 541 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); 542 sport->dma_tx_in_progress = false; 543 uart_port_unlock_irqrestore(&sport->port, flags); 544 545 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 546 uart_write_wakeup(&sport->port); 547 548 if (waitqueue_active(&sport->dma_wait)) { 549 wake_up(&sport->dma_wait); 550 return; 551 } 552 553 uart_port_lock_irqsave(&sport->port, &flags); 554 555 if (!lpuart_stopped_or_empty(&sport->port)) 556 lpuart_dma_tx(sport); 557 558 uart_port_unlock_irqrestore(&sport->port, flags); 559 } 560 561 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 562 { 563 switch (sport->port.iotype) { 564 case UPIO_MEM32: 565 return sport->port.mapbase + UARTDATA; 566 case UPIO_MEM32BE: 567 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 568 default: 569 return sport->port.mapbase + UARTDR; 570 } 571 } 572 573 static int lpuart_dma_tx_request(struct uart_port *port) 574 { 575 struct lpuart_port *sport = container_of(port, 576 struct lpuart_port, port); 577 struct dma_slave_config dma_tx_sconfig = {}; 578 int ret; 579 580 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 581 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 582 dma_tx_sconfig.dst_maxburst = 1; 583 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 584 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 585 586 if (ret) { 587 dev_err(port->dev, 588 "DMA slave config failed, err = %d\n", ret); 589 return ret; 590 } 591 592 return 0; 593 } 594 595 static bool lpuart_is_32(struct lpuart_port *sport) 596 { 597 return sport->port.iotype == UPIO_MEM32 || 598 sport->port.iotype == UPIO_MEM32BE; 599 } 600 601 static void lpuart_flush_buffer(struct uart_port *port) 602 { 603 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 604 struct dma_chan *chan = sport->dma_tx_chan; 605 u32 fifo; 606 607 if (sport->lpuart_dma_tx_use) { 608 if (sport->dma_tx_in_progress) { 609 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 610 sport->dma_tx_nents, DMA_TO_DEVICE); 611 sport->dma_tx_in_progress = false; 612 } 613 dmaengine_terminate_async(chan); 614 } 615 616 if (lpuart_is_32(sport)) { 617 fifo = lpuart32_read(port, UARTFIFO); 618 fifo |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 619 lpuart32_write(port, fifo, UARTFIFO); 620 } else { 621 fifo = readb(port->membase + UARTCFIFO); 622 fifo |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 623 writeb(fifo, port->membase + UARTCFIFO); 624 } 625 } 626 627 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 628 u8 bit) 629 { 630 while (!(readb(port->membase + offset) & bit)) 631 cpu_relax(); 632 } 633 634 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 635 u32 bit) 636 { 637 while (!(lpuart32_read(port, offset) & bit)) 638 cpu_relax(); 639 } 640 641 #if defined(CONFIG_CONSOLE_POLL) 642 643 static int lpuart_poll_init(struct uart_port *port) 644 { 645 unsigned long flags; 646 u8 fifo; 647 648 port->fifosize = 0; 649 650 uart_port_lock_irqsave(port, &flags); 651 /* Disable Rx & Tx */ 652 writeb(0, port->membase + UARTCR2); 653 654 fifo = readb(port->membase + UARTPFIFO); 655 /* Enable Rx and Tx FIFO */ 656 writeb(fifo | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 657 port->membase + UARTPFIFO); 658 659 /* flush Tx and Rx FIFO */ 660 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 661 port->membase + UARTCFIFO); 662 663 /* explicitly clear RDRF */ 664 if (readb(port->membase + UARTSR1) & UARTSR1_RDRF) { 665 readb(port->membase + UARTDR); 666 writeb(UARTSFIFO_RXUF, port->membase + UARTSFIFO); 667 } 668 669 writeb(0, port->membase + UARTTWFIFO); 670 writeb(1, port->membase + UARTRWFIFO); 671 672 /* Enable Rx and Tx */ 673 writeb(UARTCR2_RE | UARTCR2_TE, port->membase + UARTCR2); 674 uart_port_unlock_irqrestore(port, flags); 675 676 return 0; 677 } 678 679 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 680 { 681 /* drain */ 682 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 683 writeb(c, port->membase + UARTDR); 684 } 685 686 static int lpuart_poll_get_char(struct uart_port *port) 687 { 688 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 689 return NO_POLL_CHAR; 690 691 return readb(port->membase + UARTDR); 692 } 693 694 static int lpuart32_poll_init(struct uart_port *port) 695 { 696 unsigned long flags; 697 u32 fifo; 698 699 port->fifosize = 0; 700 701 uart_port_lock_irqsave(port, &flags); 702 703 /* Disable Rx & Tx */ 704 lpuart32_write(port, 0, UARTCTRL); 705 706 fifo = lpuart32_read(port, UARTFIFO); 707 708 /* Enable Rx and Tx FIFO */ 709 lpuart32_write(port, fifo | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 710 711 /* flush Tx and Rx FIFO */ 712 lpuart32_write(port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 713 714 /* explicitly clear RDRF */ 715 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF) { 716 lpuart32_read(port, UARTDATA); 717 lpuart32_write(port, UARTFIFO_RXUF, UARTFIFO); 718 } 719 720 /* Enable Rx and Tx */ 721 lpuart32_write(port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 722 uart_port_unlock_irqrestore(port, flags); 723 724 return 0; 725 } 726 727 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 728 { 729 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 730 lpuart32_write(port, c, UARTDATA); 731 } 732 733 static int lpuart32_poll_get_char(struct uart_port *port) 734 { 735 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 736 return NO_POLL_CHAR; 737 738 return lpuart32_read(port, UARTDATA); 739 } 740 #endif 741 742 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 743 { 744 struct uart_port *port = &sport->port; 745 u8 ch; 746 747 uart_port_tx(port, ch, 748 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, 749 writeb(ch, port->membase + UARTDR)); 750 } 751 752 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 753 { 754 struct tty_port *tport = &sport->port.state->port; 755 u32 txcnt; 756 unsigned char c; 757 758 if (sport->port.x_char) { 759 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 760 sport->port.icount.tx++; 761 sport->port.x_char = 0; 762 return; 763 } 764 765 if (lpuart_stopped_or_empty(&sport->port)) { 766 lpuart32_stop_tx(&sport->port); 767 return; 768 } 769 770 txcnt = lpuart32_read(&sport->port, UARTWATER); 771 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 772 txcnt &= UARTWATER_COUNT_MASK; 773 while (txcnt < sport->txfifo_size && 774 uart_fifo_get(&sport->port, &c)) { 775 lpuart32_write(&sport->port, c, UARTDATA); 776 txcnt = lpuart32_read(&sport->port, UARTWATER); 777 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 778 txcnt &= UARTWATER_COUNT_MASK; 779 } 780 781 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 782 uart_write_wakeup(&sport->port); 783 784 if (kfifo_is_empty(&tport->xmit_fifo)) 785 lpuart32_stop_tx(&sport->port); 786 } 787 788 static void lpuart_start_tx(struct uart_port *port) 789 { 790 struct lpuart_port *sport = container_of(port, 791 struct lpuart_port, port); 792 u8 cr2; 793 794 cr2 = readb(port->membase + UARTCR2); 795 writeb(cr2 | UARTCR2_TIE, port->membase + UARTCR2); 796 797 if (sport->lpuart_dma_tx_use) { 798 if (!lpuart_stopped_or_empty(port)) 799 lpuart_dma_tx(sport); 800 } else { 801 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 802 lpuart_transmit_buffer(sport); 803 } 804 } 805 806 static void lpuart32_start_tx(struct uart_port *port) 807 { 808 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 809 u32 ctrl; 810 811 if (sport->lpuart_dma_tx_use) { 812 if (!lpuart_stopped_or_empty(port)) 813 lpuart_dma_tx(sport); 814 } else { 815 ctrl = lpuart32_read(port, UARTCTRL); 816 lpuart32_write(port, ctrl | UARTCTRL_TIE, UARTCTRL); 817 818 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 819 lpuart32_transmit_buffer(sport); 820 } 821 } 822 823 static void 824 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) 825 { 826 switch (state) { 827 case UART_PM_STATE_OFF: 828 pm_runtime_mark_last_busy(port->dev); 829 pm_runtime_put_autosuspend(port->dev); 830 break; 831 default: 832 pm_runtime_get_sync(port->dev); 833 break; 834 } 835 } 836 837 /* return TIOCSER_TEMT when transmitter is not busy */ 838 static unsigned int lpuart_tx_empty(struct uart_port *port) 839 { 840 struct lpuart_port *sport = container_of(port, 841 struct lpuart_port, port); 842 u8 sr1 = readb(port->membase + UARTSR1); 843 u8 sfifo = readb(port->membase + UARTSFIFO); 844 845 if (sport->dma_tx_in_progress) 846 return 0; 847 848 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 849 return TIOCSER_TEMT; 850 851 return 0; 852 } 853 854 static unsigned int lpuart32_tx_empty(struct uart_port *port) 855 { 856 struct lpuart_port *sport = container_of(port, 857 struct lpuart_port, port); 858 u32 stat = lpuart32_read(port, UARTSTAT); 859 u32 sfifo = lpuart32_read(port, UARTFIFO); 860 u32 ctrl = lpuart32_read(port, UARTCTRL); 861 862 if (sport->dma_tx_in_progress) 863 return 0; 864 865 /* 866 * LPUART Transmission Complete Flag may never be set while queuing a break 867 * character, so avoid checking for transmission complete when UARTCTRL_SBK 868 * is asserted. 869 */ 870 if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK) 871 return TIOCSER_TEMT; 872 873 return 0; 874 } 875 876 static void lpuart_txint(struct lpuart_port *sport) 877 { 878 uart_port_lock(&sport->port); 879 lpuart_transmit_buffer(sport); 880 uart_port_unlock(&sport->port); 881 } 882 883 static void lpuart_rxint(struct lpuart_port *sport) 884 { 885 unsigned int flg, ignored = 0, overrun = 0; 886 struct tty_port *port = &sport->port.state->port; 887 u8 rx, sr; 888 889 uart_port_lock(&sport->port); 890 891 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 892 flg = TTY_NORMAL; 893 sport->port.icount.rx++; 894 /* 895 * to clear the FE, OR, NF, FE, PE flags, 896 * read SR1 then read DR 897 */ 898 sr = readb(sport->port.membase + UARTSR1); 899 rx = readb(sport->port.membase + UARTDR); 900 901 if (uart_prepare_sysrq_char(&sport->port, rx)) 902 continue; 903 904 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 905 if (sr & UARTSR1_PE) 906 sport->port.icount.parity++; 907 else if (sr & UARTSR1_FE) 908 sport->port.icount.frame++; 909 910 if (sr & UARTSR1_OR) 911 overrun++; 912 913 if (sr & sport->port.ignore_status_mask) { 914 if (++ignored > 100) 915 goto out; 916 continue; 917 } 918 919 sr &= sport->port.read_status_mask; 920 921 if (sr & UARTSR1_PE) 922 flg = TTY_PARITY; 923 else if (sr & UARTSR1_FE) 924 flg = TTY_FRAME; 925 926 if (sr & UARTSR1_OR) 927 flg = TTY_OVERRUN; 928 929 sport->port.sysrq = 0; 930 } 931 932 if (tty_insert_flip_char(port, rx, flg) == 0) 933 sport->port.icount.buf_overrun++; 934 } 935 936 out: 937 if (overrun) { 938 sport->port.icount.overrun += overrun; 939 940 /* 941 * Overruns cause FIFO pointers to become missaligned. 942 * Flushing the receive FIFO reinitializes the pointers. 943 */ 944 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 945 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 946 } 947 948 uart_unlock_and_check_sysrq(&sport->port); 949 950 tty_flip_buffer_push(port); 951 } 952 953 static void lpuart32_txint(struct lpuart_port *sport) 954 { 955 uart_port_lock(&sport->port); 956 lpuart32_transmit_buffer(sport); 957 uart_port_unlock(&sport->port); 958 } 959 960 static void lpuart32_rxint(struct lpuart_port *sport) 961 { 962 unsigned int flg, ignored = 0; 963 struct tty_port *port = &sport->port.state->port; 964 u32 rx, sr; 965 bool is_break; 966 967 uart_port_lock(&sport->port); 968 969 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 970 flg = TTY_NORMAL; 971 sport->port.icount.rx++; 972 /* 973 * to clear the FE, OR, NF, FE, PE flags, 974 * read STAT then read DATA reg 975 */ 976 sr = lpuart32_read(&sport->port, UARTSTAT); 977 rx = lpuart32_read(&sport->port, UARTDATA); 978 rx &= UARTDATA_MASK; 979 980 /* 981 * The LPUART can't distinguish between a break and a framing error, 982 * thus we assume it is a break if the received data is zero. 983 */ 984 is_break = (sr & UARTSTAT_FE) && !rx; 985 986 if (is_break && uart_handle_break(&sport->port)) 987 continue; 988 989 if (uart_prepare_sysrq_char(&sport->port, rx)) 990 continue; 991 992 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 993 if (sr & UARTSTAT_PE) { 994 sport->port.icount.parity++; 995 } else if (sr & UARTSTAT_FE) { 996 if (is_break) 997 sport->port.icount.brk++; 998 else 999 sport->port.icount.frame++; 1000 } 1001 1002 if (sr & UARTSTAT_OR) 1003 sport->port.icount.overrun++; 1004 1005 if (sr & sport->port.ignore_status_mask) { 1006 if (++ignored > 100) 1007 goto out; 1008 continue; 1009 } 1010 1011 sr &= sport->port.read_status_mask; 1012 1013 if (sr & UARTSTAT_PE) { 1014 flg = TTY_PARITY; 1015 } else if (sr & UARTSTAT_FE) { 1016 if (is_break) 1017 flg = TTY_BREAK; 1018 else 1019 flg = TTY_FRAME; 1020 } 1021 1022 if (sr & UARTSTAT_OR) 1023 flg = TTY_OVERRUN; 1024 } 1025 1026 if (sport->is_cs7) 1027 rx &= 0x7F; 1028 1029 if (tty_insert_flip_char(port, rx, flg) == 0) 1030 sport->port.icount.buf_overrun++; 1031 } 1032 1033 out: 1034 uart_unlock_and_check_sysrq(&sport->port); 1035 1036 tty_flip_buffer_push(port); 1037 } 1038 1039 static irqreturn_t lpuart_int(int irq, void *dev_id) 1040 { 1041 struct lpuart_port *sport = dev_id; 1042 u8 sts; 1043 1044 sts = readb(sport->port.membase + UARTSR1); 1045 1046 /* SysRq, using dma, check for linebreak by framing err. */ 1047 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 1048 readb(sport->port.membase + UARTDR); 1049 uart_handle_break(&sport->port); 1050 /* linebreak produces some garbage, removing it */ 1051 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 1052 return IRQ_HANDLED; 1053 } 1054 1055 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 1056 lpuart_rxint(sport); 1057 1058 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 1059 lpuart_txint(sport); 1060 1061 return IRQ_HANDLED; 1062 } 1063 1064 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1065 unsigned char *p, int count) 1066 { 1067 while (count--) { 1068 if (*p && uart_handle_sysrq_char(port, *p)) 1069 return; 1070 p++; 1071 } 1072 } 1073 1074 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1075 { 1076 struct circ_buf *ring = &sport->rx_ring; 1077 int count; 1078 1079 if (ring->head < ring->tail) { 1080 count = sport->rx_sgl.length - ring->tail; 1081 lpuart_handle_sysrq_chars(&sport->port, 1082 ring->buf + ring->tail, count); 1083 ring->tail = 0; 1084 } 1085 1086 if (ring->head > ring->tail) { 1087 count = ring->head - ring->tail; 1088 lpuart_handle_sysrq_chars(&sport->port, 1089 ring->buf + ring->tail, count); 1090 ring->tail = ring->head; 1091 } 1092 } 1093 1094 static int lpuart_tty_insert_flip_string(struct tty_port *port, 1095 unsigned char *chars, size_t size, bool is_cs7) 1096 { 1097 int i; 1098 1099 if (is_cs7) 1100 for (i = 0; i < size; i++) 1101 chars[i] &= 0x7F; 1102 return tty_insert_flip_string(port, chars, size); 1103 } 1104 1105 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1106 { 1107 struct tty_port *port = &sport->port.state->port; 1108 struct dma_tx_state state; 1109 enum dma_status dmastat; 1110 struct dma_chan *chan = sport->dma_rx_chan; 1111 struct circ_buf *ring = &sport->rx_ring; 1112 unsigned long flags; 1113 int count, copied; 1114 1115 if (lpuart_is_32(sport)) { 1116 u32 sr = lpuart32_read(&sport->port, UARTSTAT); 1117 1118 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1119 /* Clear the error flags */ 1120 lpuart32_write(&sport->port, sr, UARTSTAT); 1121 1122 if (sr & UARTSTAT_PE) 1123 sport->port.icount.parity++; 1124 else if (sr & UARTSTAT_FE) 1125 sport->port.icount.frame++; 1126 } 1127 } else { 1128 u8 sr = readb(sport->port.membase + UARTSR1); 1129 1130 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1131 u8 cr2; 1132 1133 /* Disable receiver during this operation... */ 1134 cr2 = readb(sport->port.membase + UARTCR2); 1135 cr2 &= ~UARTCR2_RE; 1136 writeb(cr2, sport->port.membase + UARTCR2); 1137 1138 /* Read DR to clear the error flags */ 1139 readb(sport->port.membase + UARTDR); 1140 1141 if (sr & UARTSR1_PE) 1142 sport->port.icount.parity++; 1143 else if (sr & UARTSR1_FE) 1144 sport->port.icount.frame++; 1145 /* 1146 * At this point parity/framing error is 1147 * cleared However, since the DMA already read 1148 * the data register and we had to read it 1149 * again after reading the status register to 1150 * properly clear the flags, the FIFO actually 1151 * underflowed... This requires a clearing of 1152 * the FIFO... 1153 */ 1154 if (readb(sport->port.membase + UARTSFIFO) & 1155 UARTSFIFO_RXUF) { 1156 writeb(UARTSFIFO_RXUF, 1157 sport->port.membase + UARTSFIFO); 1158 writeb(UARTCFIFO_RXFLUSH, 1159 sport->port.membase + UARTCFIFO); 1160 } 1161 1162 cr2 |= UARTCR2_RE; 1163 writeb(cr2, sport->port.membase + UARTCR2); 1164 } 1165 } 1166 1167 async_tx_ack(sport->dma_rx_desc); 1168 1169 uart_port_lock_irqsave(&sport->port, &flags); 1170 1171 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1172 if (dmastat == DMA_ERROR) { 1173 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1174 uart_port_unlock_irqrestore(&sport->port, flags); 1175 return; 1176 } 1177 1178 /* CPU claims ownership of RX DMA buffer */ 1179 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1180 DMA_FROM_DEVICE); 1181 1182 /* 1183 * ring->head points to the end of data already written by the DMA. 1184 * ring->tail points to the beginning of data to be read by the 1185 * framework. 1186 * The current transfer size should not be larger than the dma buffer 1187 * length. 1188 */ 1189 ring->head = sport->rx_sgl.length - state.residue; 1190 BUG_ON(ring->head > sport->rx_sgl.length); 1191 1192 /* 1193 * Silent handling of keys pressed in the sysrq timeframe 1194 */ 1195 if (sport->port.sysrq) { 1196 lpuart_handle_sysrq(sport); 1197 goto exit; 1198 } 1199 1200 /* 1201 * At this point ring->head may point to the first byte right after the 1202 * last byte of the dma buffer: 1203 * 0 <= ring->head <= sport->rx_sgl.length 1204 * 1205 * However ring->tail must always points inside the dma buffer: 1206 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1207 * 1208 * Since we use a ring buffer, we have to handle the case 1209 * where head is lower than tail. In such a case, we first read from 1210 * tail to the end of the buffer then reset tail. 1211 */ 1212 if (ring->head < ring->tail) { 1213 count = sport->rx_sgl.length - ring->tail; 1214 1215 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1216 count, sport->is_cs7); 1217 if (copied != count) 1218 sport->port.icount.buf_overrun++; 1219 ring->tail = 0; 1220 sport->port.icount.rx += copied; 1221 } 1222 1223 /* Finally we read data from tail to head */ 1224 if (ring->tail < ring->head) { 1225 count = ring->head - ring->tail; 1226 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1227 count, sport->is_cs7); 1228 if (copied != count) 1229 sport->port.icount.buf_overrun++; 1230 /* Wrap ring->head if needed */ 1231 if (ring->head >= sport->rx_sgl.length) 1232 ring->head = 0; 1233 ring->tail = ring->head; 1234 sport->port.icount.rx += copied; 1235 } 1236 1237 sport->last_residue = state.residue; 1238 1239 exit: 1240 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1241 DMA_FROM_DEVICE); 1242 1243 uart_port_unlock_irqrestore(&sport->port, flags); 1244 1245 tty_flip_buffer_push(port); 1246 if (!sport->dma_idle_int) 1247 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1248 } 1249 1250 static void lpuart_dma_rx_complete(void *arg) 1251 { 1252 struct lpuart_port *sport = arg; 1253 1254 lpuart_copy_rx_to_tty(sport); 1255 } 1256 1257 static void lpuart32_dma_idleint(struct lpuart_port *sport) 1258 { 1259 enum dma_status dmastat; 1260 struct dma_chan *chan = sport->dma_rx_chan; 1261 struct circ_buf *ring = &sport->rx_ring; 1262 struct dma_tx_state state; 1263 int count = 0; 1264 1265 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1266 if (dmastat == DMA_ERROR) { 1267 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1268 return; 1269 } 1270 1271 ring->head = sport->rx_sgl.length - state.residue; 1272 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); 1273 1274 /* Check if new data received before copying */ 1275 if (count) 1276 lpuart_copy_rx_to_tty(sport); 1277 } 1278 1279 static irqreturn_t lpuart32_int(int irq, void *dev_id) 1280 { 1281 struct lpuart_port *sport = dev_id; 1282 u32 sts, rxcount; 1283 1284 sts = lpuart32_read(&sport->port, UARTSTAT); 1285 rxcount = lpuart32_read(&sport->port, UARTWATER); 1286 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1287 1288 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1289 lpuart32_rxint(sport); 1290 1291 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1292 lpuart32_txint(sport); 1293 1294 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) 1295 lpuart32_dma_idleint(sport); 1296 1297 lpuart32_write(&sport->port, sts, UARTSTAT); 1298 return IRQ_HANDLED; 1299 } 1300 1301 /* 1302 * Timer function to simulate the hardware EOP (End Of Package) event. 1303 * The timer callback is to check for new RX data and copy to TTY buffer. 1304 * If no new data are received since last interval, the EOP condition is 1305 * met, complete the DMA transfer by copying the data. Otherwise, just 1306 * restart timer. 1307 */ 1308 static void lpuart_timer_func(struct timer_list *t) 1309 { 1310 struct lpuart_port *sport = timer_container_of(sport, t, lpuart_timer); 1311 enum dma_status dmastat; 1312 struct dma_chan *chan = sport->dma_rx_chan; 1313 struct circ_buf *ring = &sport->rx_ring; 1314 struct dma_tx_state state; 1315 unsigned long flags; 1316 int count; 1317 1318 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1319 if (dmastat == DMA_ERROR) { 1320 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1321 return; 1322 } 1323 1324 ring->head = sport->rx_sgl.length - state.residue; 1325 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); 1326 1327 /* Check if new data received before copying */ 1328 if ((count != 0) && (sport->last_residue == state.residue)) 1329 lpuart_copy_rx_to_tty(sport); 1330 else 1331 mod_timer(&sport->lpuart_timer, 1332 jiffies + sport->dma_rx_timeout); 1333 1334 if (uart_port_trylock_irqsave(&sport->port, &flags)) { 1335 sport->last_residue = state.residue; 1336 uart_port_unlock_irqrestore(&sport->port, flags); 1337 } 1338 } 1339 1340 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1341 { 1342 struct dma_slave_config dma_rx_sconfig = {}; 1343 struct circ_buf *ring = &sport->rx_ring; 1344 int ret, nent; 1345 struct tty_port *port = &sport->port.state->port; 1346 struct tty_struct *tty = port->tty; 1347 struct ktermios *termios = &tty->termios; 1348 struct dma_chan *chan = sport->dma_rx_chan; 1349 unsigned int bits = tty_get_frame_size(termios->c_cflag); 1350 unsigned int baud = tty_get_baud_rate(tty); 1351 1352 /* 1353 * Calculate length of one DMA buffer size to keep latency below 1354 * 10ms at any baud rate. 1355 */ 1356 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1357 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); 1358 sport->rx_dma_rng_buf_len = max_t(int, 1359 sport->rxfifo_size * 2, 1360 sport->rx_dma_rng_buf_len); 1361 /* 1362 * Keep this condition check in case rxfifo_size is unavailable 1363 * for some SoCs. 1364 */ 1365 if (sport->rx_dma_rng_buf_len < 16) 1366 sport->rx_dma_rng_buf_len = 16; 1367 1368 sport->last_residue = 0; 1369 sport->dma_rx_timeout = max(nsecs_to_jiffies( 1370 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); 1371 1372 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1373 if (!ring->buf) 1374 return -ENOMEM; 1375 1376 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1377 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1378 DMA_FROM_DEVICE); 1379 1380 if (!nent) { 1381 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1382 ret = -EINVAL; 1383 goto err_free_buf; 1384 } 1385 1386 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1387 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1388 dma_rx_sconfig.src_maxburst = 1; 1389 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1390 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1391 1392 if (ret < 0) { 1393 dev_err(sport->port.dev, 1394 "DMA Rx slave config failed, err = %d\n", ret); 1395 goto err_unmap_sg; 1396 } 1397 1398 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1399 sg_dma_address(&sport->rx_sgl), 1400 sport->rx_sgl.length, 1401 sport->rx_sgl.length / 2, 1402 DMA_DEV_TO_MEM, 1403 DMA_PREP_INTERRUPT); 1404 if (!sport->dma_rx_desc) { 1405 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1406 ret = -ENOMEM; 1407 goto err_unmap_sg; 1408 } 1409 1410 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1411 sport->dma_rx_desc->callback_param = sport; 1412 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1413 dma_async_issue_pending(chan); 1414 1415 if (lpuart_is_32(sport)) { 1416 u32 baud = lpuart32_read(&sport->port, UARTBAUD); 1417 1418 lpuart32_write(&sport->port, baud | UARTBAUD_RDMAE, UARTBAUD); 1419 1420 if (sport->dma_idle_int) { 1421 u32 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1422 1423 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); 1424 } 1425 } else { 1426 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1427 sport->port.membase + UARTCR5); 1428 } 1429 1430 return 0; 1431 1432 err_unmap_sg: 1433 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1434 err_free_buf: 1435 kfree(ring->buf); 1436 ring->buf = NULL; 1437 return ret; 1438 } 1439 1440 static void lpuart_dma_rx_free(struct uart_port *port) 1441 { 1442 struct lpuart_port *sport = container_of(port, 1443 struct lpuart_port, port); 1444 struct dma_chan *chan = sport->dma_rx_chan; 1445 1446 dmaengine_terminate_sync(chan); 1447 if (!sport->dma_idle_int) 1448 timer_delete_sync(&sport->lpuart_timer); 1449 1450 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1451 kfree(sport->rx_ring.buf); 1452 sport->rx_ring.tail = 0; 1453 sport->rx_ring.head = 0; 1454 sport->dma_rx_desc = NULL; 1455 sport->dma_rx_cookie = -EINVAL; 1456 } 1457 1458 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios, 1459 struct serial_rs485 *rs485) 1460 { 1461 u8 modem = readb(port->membase + UARTMODEM) & 1462 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1463 writeb(modem, port->membase + UARTMODEM); 1464 1465 if (rs485->flags & SER_RS485_ENABLED) { 1466 /* Enable auto RS-485 RTS mode */ 1467 modem |= UARTMODEM_TXRTSE; 1468 1469 /* 1470 * The hardware defaults to RTS logic HIGH while transfer. 1471 * Switch polarity in case RTS shall be logic HIGH 1472 * after transfer. 1473 * Note: UART is assumed to be active high. 1474 */ 1475 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1476 modem |= UARTMODEM_TXRTSPOL; 1477 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1478 modem &= ~UARTMODEM_TXRTSPOL; 1479 } 1480 1481 writeb(modem, port->membase + UARTMODEM); 1482 return 0; 1483 } 1484 1485 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios, 1486 struct serial_rs485 *rs485) 1487 { 1488 u32 modem = lpuart32_read(port, UARTMODIR) 1489 & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE); 1490 u32 ctrl; 1491 1492 /* TXRTSE and TXRTSPOL only can be changed when transmitter is disabled. */ 1493 ctrl = lpuart32_read(port, UARTCTRL); 1494 if (ctrl & UARTCTRL_TE) { 1495 /* wait for the transmit engine to complete */ 1496 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC); 1497 lpuart32_write(port, ctrl & ~UARTCTRL_TE, UARTCTRL); 1498 1499 while (lpuart32_read(port, UARTCTRL) & UARTCTRL_TE) 1500 cpu_relax(); 1501 } 1502 1503 lpuart32_write(port, modem, UARTMODIR); 1504 1505 if (rs485->flags & SER_RS485_ENABLED) { 1506 /* Enable auto RS-485 RTS mode */ 1507 modem |= UARTMODIR_TXRTSE; 1508 1509 /* 1510 * The hardware defaults to RTS logic HIGH while transfer. 1511 * Switch polarity in case RTS shall be logic HIGH 1512 * after transfer. 1513 * Note: UART is assumed to be active high. 1514 */ 1515 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1516 modem |= UARTMODIR_TXRTSPOL; 1517 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1518 modem &= ~UARTMODIR_TXRTSPOL; 1519 } 1520 1521 lpuart32_write(port, modem, UARTMODIR); 1522 1523 if (ctrl & UARTCTRL_TE) 1524 lpuart32_write(port, ctrl, UARTCTRL); 1525 1526 return 0; 1527 } 1528 1529 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1530 { 1531 unsigned int mctrl = 0; 1532 u8 cr1; 1533 1534 cr1 = readb(port->membase + UARTCR1); 1535 if (cr1 & UARTCR1_LOOPS) 1536 mctrl |= TIOCM_LOOP; 1537 1538 return mctrl; 1539 } 1540 1541 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1542 { 1543 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1544 u32 ctrl; 1545 1546 ctrl = lpuart32_read(port, UARTCTRL); 1547 if (ctrl & UARTCTRL_LOOPS) 1548 mctrl |= TIOCM_LOOP; 1549 1550 return mctrl; 1551 } 1552 1553 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1554 { 1555 u8 cr1; 1556 1557 cr1 = readb(port->membase + UARTCR1); 1558 1559 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1560 cr1 &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); 1561 if (mctrl & TIOCM_LOOP) 1562 cr1 |= UARTCR1_LOOPS; 1563 1564 writeb(cr1, port->membase + UARTCR1); 1565 } 1566 1567 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1568 { 1569 u32 ctrl; 1570 1571 ctrl = lpuart32_read(port, UARTCTRL); 1572 1573 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1574 ctrl &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); 1575 if (mctrl & TIOCM_LOOP) 1576 ctrl |= UARTCTRL_LOOPS; 1577 1578 lpuart32_write(port, ctrl, UARTCTRL); 1579 } 1580 1581 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1582 { 1583 u8 cr2; 1584 1585 cr2 = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1586 1587 if (break_state != 0) 1588 cr2 |= UARTCR2_SBK; 1589 1590 writeb(cr2, port->membase + UARTCR2); 1591 } 1592 1593 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1594 { 1595 u32 ctrl; 1596 1597 ctrl = lpuart32_read(port, UARTCTRL); 1598 1599 /* 1600 * LPUART IP now has two known bugs, one is CTS has higher priority than the 1601 * break signal, which causes the break signal sending through UARTCTRL_SBK 1602 * may impacted by the CTS input if the HW flow control is enabled. It 1603 * exists on all platforms we support in this driver. 1604 * Another bug is i.MX8QM LPUART may have an additional break character 1605 * being sent after SBK was cleared. 1606 * To avoid above two bugs, we use Transmit Data Inversion function to send 1607 * the break signal instead of UARTCTRL_SBK. 1608 */ 1609 if (break_state != 0) { 1610 /* 1611 * Disable the transmitter to prevent any data from being sent out 1612 * during break, then invert the TX line to send break. 1613 */ 1614 ctrl &= ~UARTCTRL_TE; 1615 lpuart32_write(port, ctrl, UARTCTRL); 1616 ctrl |= UARTCTRL_TXINV; 1617 lpuart32_write(port, ctrl, UARTCTRL); 1618 } else { 1619 /* Disable the TXINV to turn off break and re-enable transmitter. */ 1620 ctrl &= ~UARTCTRL_TXINV; 1621 lpuart32_write(port, ctrl, UARTCTRL); 1622 ctrl |= UARTCTRL_TE; 1623 lpuart32_write(port, ctrl, UARTCTRL); 1624 } 1625 } 1626 1627 static void lpuart_setup_watermark(struct lpuart_port *sport) 1628 { 1629 u8 fifo, cr2, cr2_saved; 1630 1631 cr2 = readb(sport->port.membase + UARTCR2); 1632 cr2_saved = cr2; 1633 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1634 UARTCR2_RIE | UARTCR2_RE); 1635 writeb(cr2, sport->port.membase + UARTCR2); 1636 1637 fifo = readb(sport->port.membase + UARTPFIFO); 1638 writeb(fifo | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1639 sport->port.membase + UARTPFIFO); 1640 1641 /* flush Tx and Rx FIFO */ 1642 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1643 sport->port.membase + UARTCFIFO); 1644 1645 /* explicitly clear RDRF */ 1646 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1647 readb(sport->port.membase + UARTDR); 1648 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1649 } 1650 1651 if (uart_console(&sport->port)) 1652 sport->rx_watermark = 1; 1653 writeb(0, sport->port.membase + UARTTWFIFO); 1654 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); 1655 1656 /* Restore cr2 */ 1657 writeb(cr2_saved, sport->port.membase + UARTCR2); 1658 } 1659 1660 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1661 { 1662 u8 cr2; 1663 1664 lpuart_setup_watermark(sport); 1665 1666 cr2 = readb(sport->port.membase + UARTCR2); 1667 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1668 writeb(cr2, sport->port.membase + UARTCR2); 1669 } 1670 1671 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1672 { 1673 u32 val, ctrl, ctrl_saved; 1674 1675 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1676 ctrl_saved = ctrl; 1677 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1678 UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE); 1679 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1680 1681 /* enable FIFO mode */ 1682 val = lpuart32_read(&sport->port, UARTFIFO); 1683 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1684 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1685 val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3); 1686 lpuart32_write(&sport->port, val, UARTFIFO); 1687 1688 /* set the watermark */ 1689 if (uart_console(&sport->port)) 1690 sport->rx_watermark = 1; 1691 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | 1692 (0x0 << UARTWATER_TXWATER_OFF); 1693 lpuart32_write(&sport->port, val, UARTWATER); 1694 1695 /* set RTS watermark */ 1696 if (!uart_console(&sport->port)) { 1697 val = lpuart32_read(&sport->port, UARTMODIR); 1698 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); 1699 lpuart32_write(&sport->port, val, UARTMODIR); 1700 } 1701 1702 /* Restore cr2 */ 1703 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1704 } 1705 1706 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1707 { 1708 u32 ctrl; 1709 1710 lpuart32_setup_watermark(sport); 1711 1712 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1713 ctrl |= UARTCTRL_RE | UARTCTRL_TE; 1714 ctrl |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7); 1715 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1716 } 1717 1718 static void rx_dma_timer_init(struct lpuart_port *sport) 1719 { 1720 if (sport->dma_idle_int) 1721 return; 1722 1723 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1724 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1725 add_timer(&sport->lpuart_timer); 1726 } 1727 1728 static void lpuart_request_dma(struct lpuart_port *sport) 1729 { 1730 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1731 if (IS_ERR(sport->dma_tx_chan)) { 1732 dev_dbg_once(sport->port.dev, 1733 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1734 PTR_ERR(sport->dma_tx_chan)); 1735 sport->dma_tx_chan = NULL; 1736 } 1737 1738 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1739 if (IS_ERR(sport->dma_rx_chan)) { 1740 dev_dbg_once(sport->port.dev, 1741 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1742 PTR_ERR(sport->dma_rx_chan)); 1743 sport->dma_rx_chan = NULL; 1744 } 1745 } 1746 1747 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1748 { 1749 u32 uartbaud; 1750 int ret; 1751 1752 if (uart_console(&sport->port)) 1753 goto err; 1754 1755 if (!sport->dma_tx_chan) 1756 goto err; 1757 1758 ret = lpuart_dma_tx_request(&sport->port); 1759 if (ret) 1760 goto err; 1761 1762 init_waitqueue_head(&sport->dma_wait); 1763 sport->lpuart_dma_tx_use = true; 1764 if (lpuart_is_32(sport)) { 1765 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1766 lpuart32_write(&sport->port, 1767 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1768 } else { 1769 writeb(readb(sport->port.membase + UARTCR5) | 1770 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1771 } 1772 1773 return; 1774 1775 err: 1776 sport->lpuart_dma_tx_use = false; 1777 } 1778 1779 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1780 { 1781 int ret; 1782 u8 cr3; 1783 1784 if (uart_console(&sport->port)) 1785 goto err; 1786 1787 if (!sport->dma_rx_chan) 1788 goto err; 1789 1790 /* set default Rx DMA timeout */ 1791 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1792 1793 ret = lpuart_start_rx_dma(sport); 1794 if (ret) 1795 goto err; 1796 1797 if (!sport->dma_rx_timeout) 1798 sport->dma_rx_timeout = 1; 1799 1800 sport->lpuart_dma_rx_use = true; 1801 rx_dma_timer_init(sport); 1802 1803 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { 1804 cr3 = readb(sport->port.membase + UARTCR3); 1805 cr3 |= UARTCR3_FEIE; 1806 writeb(cr3, sport->port.membase + UARTCR3); 1807 } 1808 1809 return; 1810 1811 err: 1812 sport->lpuart_dma_rx_use = false; 1813 } 1814 1815 static void lpuart_hw_setup(struct lpuart_port *sport) 1816 { 1817 unsigned long flags; 1818 1819 uart_port_lock_irqsave(&sport->port, &flags); 1820 1821 lpuart_setup_watermark_enable(sport); 1822 1823 lpuart_rx_dma_startup(sport); 1824 lpuart_tx_dma_startup(sport); 1825 1826 uart_port_unlock_irqrestore(&sport->port, flags); 1827 } 1828 1829 static int lpuart_startup(struct uart_port *port) 1830 { 1831 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1832 u8 fifo; 1833 1834 /* determine FIFO size and enable FIFO mode */ 1835 fifo = readb(port->membase + UARTPFIFO); 1836 1837 sport->txfifo_size = UARTFIFO_DEPTH((fifo >> UARTPFIFO_TXSIZE_OFF) & 1838 UARTPFIFO_FIFOSIZE_MASK); 1839 port->fifosize = sport->txfifo_size; 1840 1841 sport->rxfifo_size = UARTFIFO_DEPTH((fifo >> UARTPFIFO_RXSIZE_OFF) & 1842 UARTPFIFO_FIFOSIZE_MASK); 1843 1844 lpuart_request_dma(sport); 1845 lpuart_hw_setup(sport); 1846 1847 return 0; 1848 } 1849 1850 static void lpuart32_hw_disable(struct lpuart_port *sport) 1851 { 1852 u32 ctrl; 1853 1854 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1855 ctrl &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | 1856 UARTCTRL_TIE | UARTCTRL_TE); 1857 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1858 } 1859 1860 static void lpuart32_configure(struct lpuart_port *sport) 1861 { 1862 u32 ctrl; 1863 1864 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1865 if (!sport->lpuart_dma_rx_use) 1866 ctrl |= UARTCTRL_RIE | UARTCTRL_ILIE; 1867 if (!sport->lpuart_dma_tx_use) 1868 ctrl |= UARTCTRL_TIE; 1869 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1870 } 1871 1872 static void lpuart32_hw_setup(struct lpuart_port *sport) 1873 { 1874 unsigned long flags; 1875 1876 uart_port_lock_irqsave(&sport->port, &flags); 1877 1878 lpuart32_hw_disable(sport); 1879 1880 lpuart_rx_dma_startup(sport); 1881 lpuart_tx_dma_startup(sport); 1882 1883 lpuart32_setup_watermark_enable(sport); 1884 lpuart32_configure(sport); 1885 1886 uart_port_unlock_irqrestore(&sport->port, flags); 1887 } 1888 1889 static int lpuart32_startup(struct uart_port *port) 1890 { 1891 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1892 u32 fifo; 1893 1894 /* determine FIFO size */ 1895 fifo = lpuart32_read(port, UARTFIFO); 1896 1897 sport->txfifo_size = UARTFIFO_DEPTH((fifo >> UARTFIFO_TXSIZE_OFF) & 1898 UARTFIFO_FIFOSIZE_MASK); 1899 port->fifosize = sport->txfifo_size; 1900 1901 sport->rxfifo_size = UARTFIFO_DEPTH((fifo >> UARTFIFO_RXSIZE_OFF) & 1902 UARTFIFO_FIFOSIZE_MASK); 1903 1904 /* 1905 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. 1906 * Although they support the RX/TXSIZE fields, their encoding is 1907 * different. Eg the reference manual states 0b101 is 16 words. 1908 */ 1909 if (is_layerscape_lpuart(sport)) { 1910 sport->rxfifo_size = 16; 1911 sport->txfifo_size = 16; 1912 port->fifosize = sport->txfifo_size; 1913 } 1914 1915 lpuart_request_dma(sport); 1916 lpuart32_hw_setup(sport); 1917 1918 return 0; 1919 } 1920 1921 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1922 { 1923 if (sport->lpuart_dma_rx_use) { 1924 lpuart_dma_rx_free(&sport->port); 1925 sport->lpuart_dma_rx_use = false; 1926 } 1927 1928 if (sport->lpuart_dma_tx_use) { 1929 if (wait_event_interruptible_timeout(sport->dma_wait, 1930 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1931 sport->dma_tx_in_progress = false; 1932 dmaengine_terminate_sync(sport->dma_tx_chan); 1933 } 1934 sport->lpuart_dma_tx_use = false; 1935 } 1936 1937 if (sport->dma_tx_chan) 1938 dma_release_channel(sport->dma_tx_chan); 1939 if (sport->dma_rx_chan) 1940 dma_release_channel(sport->dma_rx_chan); 1941 } 1942 1943 static void lpuart_shutdown(struct uart_port *port) 1944 { 1945 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1946 u8 cr2; 1947 unsigned long flags; 1948 1949 uart_port_lock_irqsave(port, &flags); 1950 1951 /* disable Rx/Tx and interrupts */ 1952 cr2 = readb(port->membase + UARTCR2); 1953 cr2 &= ~(UARTCR2_TE | UARTCR2_RE | 1954 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1955 writeb(cr2, port->membase + UARTCR2); 1956 1957 uart_port_unlock_irqrestore(port, flags); 1958 1959 lpuart_dma_shutdown(sport); 1960 } 1961 1962 static void lpuart32_shutdown(struct uart_port *port) 1963 { 1964 struct lpuart_port *sport = 1965 container_of(port, struct lpuart_port, port); 1966 u32 temp; 1967 unsigned long flags; 1968 1969 uart_port_lock_irqsave(port, &flags); 1970 1971 /* clear status */ 1972 temp = lpuart32_read(port, UARTSTAT); 1973 lpuart32_write(port, temp, UARTSTAT); 1974 1975 /* disable Rx/Tx DMA */ 1976 temp = lpuart32_read(port, UARTBAUD); 1977 temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1978 lpuart32_write(port, temp, UARTBAUD); 1979 1980 /* disable Rx/Tx and interrupts and break condition */ 1981 temp = lpuart32_read(port, UARTCTRL); 1982 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE | 1983 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK); 1984 lpuart32_write(port, temp, UARTCTRL); 1985 1986 /* flush Rx/Tx FIFO */ 1987 temp = lpuart32_read(port, UARTFIFO); 1988 temp |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1989 lpuart32_write(port, temp, UARTFIFO); 1990 1991 uart_port_unlock_irqrestore(port, flags); 1992 1993 lpuart_dma_shutdown(sport); 1994 } 1995 1996 static void 1997 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1998 const struct ktermios *old) 1999 { 2000 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2001 unsigned long flags; 2002 u8 cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 2003 unsigned int baud; 2004 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2005 unsigned int sbr, brfa; 2006 2007 cr1 = old_cr1 = readb(port->membase + UARTCR1); 2008 old_cr2 = readb(port->membase + UARTCR2); 2009 cr3 = readb(port->membase + UARTCR3); 2010 cr4 = readb(port->membase + UARTCR4); 2011 bdh = readb(port->membase + UARTBDH); 2012 modem = readb(port->membase + UARTMODEM); 2013 /* 2014 * only support CS8 and CS7, and for CS7 must enable PE. 2015 * supported mode: 2016 * - (7,e/o,1) 2017 * - (8,n,1) 2018 * - (8,m/s,1) 2019 * - (8,e/o,1) 2020 */ 2021 while ((termios->c_cflag & CSIZE) != CS8 && 2022 (termios->c_cflag & CSIZE) != CS7) { 2023 termios->c_cflag &= ~CSIZE; 2024 termios->c_cflag |= old_csize; 2025 old_csize = CS8; 2026 } 2027 2028 if ((termios->c_cflag & CSIZE) == CS8 || 2029 (termios->c_cflag & CSIZE) == CS7) 2030 cr1 = old_cr1 & ~UARTCR1_M; 2031 2032 if (termios->c_cflag & CMSPAR) { 2033 if ((termios->c_cflag & CSIZE) != CS8) { 2034 termios->c_cflag &= ~CSIZE; 2035 termios->c_cflag |= CS8; 2036 } 2037 cr1 |= UARTCR1_M; 2038 } 2039 2040 /* 2041 * When auto RS-485 RTS mode is enabled, 2042 * hardware flow control need to be disabled. 2043 */ 2044 if (port->rs485.flags & SER_RS485_ENABLED) 2045 termios->c_cflag &= ~CRTSCTS; 2046 2047 if (termios->c_cflag & CRTSCTS) 2048 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 2049 else 2050 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 2051 2052 termios->c_cflag &= ~CSTOPB; 2053 2054 /* parity must be enabled when CS7 to match 8-bits format */ 2055 if ((termios->c_cflag & CSIZE) == CS7) 2056 termios->c_cflag |= PARENB; 2057 2058 if (termios->c_cflag & PARENB) { 2059 if (termios->c_cflag & CMSPAR) { 2060 cr1 &= ~UARTCR1_PE; 2061 if (termios->c_cflag & PARODD) 2062 cr3 |= UARTCR3_T8; 2063 else 2064 cr3 &= ~UARTCR3_T8; 2065 } else { 2066 cr1 |= UARTCR1_PE; 2067 if ((termios->c_cflag & CSIZE) == CS8) 2068 cr1 |= UARTCR1_M; 2069 if (termios->c_cflag & PARODD) 2070 cr1 |= UARTCR1_PT; 2071 else 2072 cr1 &= ~UARTCR1_PT; 2073 } 2074 } else { 2075 cr1 &= ~UARTCR1_PE; 2076 } 2077 2078 /* ask the core to calculate the divisor */ 2079 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 2080 2081 /* 2082 * Need to update the Ring buffer length according to the selected 2083 * baud rate and restart Rx DMA path. 2084 * 2085 * Since timer function acqures port->lock, need to stop before 2086 * acquring same lock because otherwise timer_delete_sync() can deadlock. 2087 */ 2088 if (old && sport->lpuart_dma_rx_use) 2089 lpuart_dma_rx_free(port); 2090 2091 uart_port_lock_irqsave(port, &flags); 2092 2093 port->read_status_mask = 0; 2094 if (termios->c_iflag & INPCK) 2095 port->read_status_mask |= UARTSR1_FE | UARTSR1_PE; 2096 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2097 port->read_status_mask |= UARTSR1_FE; 2098 2099 /* characters to ignore */ 2100 port->ignore_status_mask = 0; 2101 if (termios->c_iflag & IGNPAR) 2102 port->ignore_status_mask |= UARTSR1_PE; 2103 if (termios->c_iflag & IGNBRK) { 2104 port->ignore_status_mask |= UARTSR1_FE; 2105 /* 2106 * if we're ignoring parity and break indicators, 2107 * ignore overruns too (for real raw support). 2108 */ 2109 if (termios->c_iflag & IGNPAR) 2110 port->ignore_status_mask |= UARTSR1_OR; 2111 } 2112 2113 /* update the per-port timeout */ 2114 uart_update_timeout(port, termios->c_cflag, baud); 2115 2116 /* wait transmit engin complete */ 2117 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TC); 2118 2119 /* disable transmit and receive */ 2120 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 2121 port->membase + UARTCR2); 2122 2123 sbr = port->uartclk / (16 * baud); 2124 brfa = ((port->uartclk - (16 * sbr * baud)) * 2) / baud; 2125 bdh &= ~UARTBDH_SBR_MASK; 2126 bdh |= (sbr >> 8) & 0x1F; 2127 cr4 &= ~UARTCR4_BRFA_MASK; 2128 brfa &= UARTCR4_BRFA_MASK; 2129 writeb(cr4 | brfa, port->membase + UARTCR4); 2130 writeb(bdh, port->membase + UARTBDH); 2131 writeb(sbr & 0xFF, port->membase + UARTBDL); 2132 writeb(cr3, port->membase + UARTCR3); 2133 writeb(cr1, port->membase + UARTCR1); 2134 writeb(modem, port->membase + UARTMODEM); 2135 2136 /* restore control register */ 2137 writeb(old_cr2, port->membase + UARTCR2); 2138 2139 if (old && sport->lpuart_dma_rx_use) { 2140 if (!lpuart_start_rx_dma(sport)) 2141 rx_dma_timer_init(sport); 2142 else 2143 sport->lpuart_dma_rx_use = false; 2144 } 2145 2146 uart_port_unlock_irqrestore(port, flags); 2147 } 2148 2149 static void __lpuart32_serial_setbrg(struct uart_port *port, 2150 unsigned int baudrate, bool use_rx_dma, 2151 bool use_tx_dma) 2152 { 2153 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, baud; 2154 u32 clk = port->uartclk; 2155 2156 /* 2157 * The idea is to use the best OSR (over-sampling rate) possible. 2158 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 2159 * Loop to find the best OSR value possible, one that generates minimum 2160 * baud_diff iterate through the rest of the supported values of OSR. 2161 * 2162 * Calculation Formula: 2163 * Baud Rate = baud clock / ((OSR+1) × SBR) 2164 */ 2165 baud_diff = baudrate; 2166 osr = 0; 2167 sbr = 0; 2168 2169 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 2170 /* calculate the temporary sbr value */ 2171 tmp_sbr = (clk / (baudrate * tmp_osr)); 2172 if (tmp_sbr == 0) 2173 tmp_sbr = 1; 2174 2175 /* 2176 * calculate the baud rate difference based on the temporary 2177 * osr and sbr values 2178 */ 2179 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 2180 2181 /* select best values between sbr and sbr+1 */ 2182 baud = clk / (tmp_osr * (tmp_sbr + 1)); 2183 if (tmp_diff > (baudrate - baud)) { 2184 tmp_diff = baudrate - baud; 2185 tmp_sbr++; 2186 } 2187 2188 if (tmp_sbr > UARTBAUD_SBR_MASK) 2189 continue; 2190 2191 if (tmp_diff <= baud_diff) { 2192 baud_diff = tmp_diff; 2193 osr = tmp_osr; 2194 sbr = tmp_sbr; 2195 2196 if (!baud_diff) 2197 break; 2198 } 2199 } 2200 2201 /* handle buadrate outside acceptable rate */ 2202 if (baud_diff > ((baudrate / 100) * 3)) 2203 dev_warn(port->dev, 2204 "unacceptable baud rate difference of more than 3%%\n"); 2205 2206 baud = lpuart32_read(port, UARTBAUD); 2207 2208 if ((osr > 3) && (osr < 8)) 2209 baud |= UARTBAUD_BOTHEDGE; 2210 2211 baud &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2212 baud |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2213 2214 baud &= ~UARTBAUD_SBR_MASK; 2215 baud |= sbr & UARTBAUD_SBR_MASK; 2216 2217 if (!use_rx_dma) 2218 baud &= ~UARTBAUD_RDMAE; 2219 if (!use_tx_dma) 2220 baud &= ~UARTBAUD_TDMAE; 2221 2222 lpuart32_write(port, baud, UARTBAUD); 2223 } 2224 2225 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2226 unsigned int baudrate) 2227 { 2228 __lpuart32_serial_setbrg(&sport->port, baudrate, 2229 sport->lpuart_dma_rx_use, 2230 sport->lpuart_dma_tx_use); 2231 } 2232 2233 2234 static void 2235 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2236 const struct ktermios *old) 2237 { 2238 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2239 unsigned long flags; 2240 u32 ctrl, old_ctrl, bd, modem; 2241 unsigned int baud; 2242 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2243 2244 ctrl = old_ctrl = lpuart32_read(port, UARTCTRL); 2245 bd = lpuart32_read(port, UARTBAUD); 2246 modem = lpuart32_read(port, UARTMODIR); 2247 sport->is_cs7 = false; 2248 /* 2249 * only support CS8 and CS7 2250 * supported mode: 2251 * - (7,n,1) (imx only) 2252 * - (7,e/o,1) 2253 * - (8,n,1) 2254 * - (8,m/s,1) 2255 * - (8,e/o,1) 2256 */ 2257 while ((termios->c_cflag & CSIZE) != CS8 && 2258 (termios->c_cflag & CSIZE) != CS7) { 2259 termios->c_cflag &= ~CSIZE; 2260 termios->c_cflag |= old_csize; 2261 old_csize = CS8; 2262 } 2263 2264 if ((termios->c_cflag & CSIZE) == CS8 || 2265 (termios->c_cflag & CSIZE) == CS7) 2266 ctrl = old_ctrl & ~(UARTCTRL_M | UARTCTRL_M7); 2267 2268 if (termios->c_cflag & CMSPAR) { 2269 if ((termios->c_cflag & CSIZE) != CS8) { 2270 termios->c_cflag &= ~CSIZE; 2271 termios->c_cflag |= CS8; 2272 } 2273 ctrl |= UARTCTRL_M; 2274 } 2275 2276 /* 2277 * When auto RS-485 RTS mode is enabled, 2278 * hardware flow control need to be disabled. 2279 */ 2280 if (port->rs485.flags & SER_RS485_ENABLED) 2281 termios->c_cflag &= ~CRTSCTS; 2282 2283 if (termios->c_cflag & CRTSCTS) 2284 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE; 2285 else 2286 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2287 2288 if (termios->c_cflag & CSTOPB) 2289 bd |= UARTBAUD_SBNS; 2290 else 2291 bd &= ~UARTBAUD_SBNS; 2292 2293 /* 2294 * imx support 7-bits format, no limitation on parity when CS7 2295 * for layerscape, parity must be enabled when CS7 to match 8-bits format 2296 */ 2297 if ((termios->c_cflag & CSIZE) == CS7 && !(termios->c_cflag & PARENB)) { 2298 if (is_imx7ulp_lpuart(sport) || 2299 is_imx8ulp_lpuart(sport) || 2300 is_imx8qxp_lpuart(sport)) 2301 ctrl |= UARTCTRL_M7; 2302 else 2303 termios->c_cflag |= PARENB; 2304 } 2305 2306 if ((termios->c_cflag & PARENB)) { 2307 if (termios->c_cflag & CMSPAR) { 2308 ctrl &= ~UARTCTRL_PE; 2309 ctrl |= UARTCTRL_M; 2310 } else { 2311 ctrl |= UARTCTRL_PE; 2312 if ((termios->c_cflag & CSIZE) == CS8) 2313 ctrl |= UARTCTRL_M; 2314 if (termios->c_cflag & PARODD) 2315 ctrl |= UARTCTRL_PT; 2316 else 2317 ctrl &= ~UARTCTRL_PT; 2318 } 2319 } else { 2320 ctrl &= ~UARTCTRL_PE; 2321 } 2322 2323 /* ask the core to calculate the divisor */ 2324 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2325 2326 /* 2327 * Need to update the Ring buffer length according to the selected 2328 * baud rate and restart Rx DMA path. 2329 * 2330 * Since timer function acqures port->lock, need to stop before 2331 * acquring same lock because otherwise timer_delete_sync() can deadlock. 2332 */ 2333 if (old && sport->lpuart_dma_rx_use) 2334 lpuart_dma_rx_free(port); 2335 2336 uart_port_lock_irqsave(port, &flags); 2337 2338 port->read_status_mask = 0; 2339 if (termios->c_iflag & INPCK) 2340 port->read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2341 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2342 port->read_status_mask |= UARTSTAT_FE; 2343 2344 /* characters to ignore */ 2345 port->ignore_status_mask = 0; 2346 if (termios->c_iflag & IGNPAR) 2347 port->ignore_status_mask |= UARTSTAT_PE; 2348 if (termios->c_iflag & IGNBRK) { 2349 port->ignore_status_mask |= UARTSTAT_FE; 2350 /* 2351 * if we're ignoring parity and break indicators, 2352 * ignore overruns too (for real raw support). 2353 */ 2354 if (termios->c_iflag & IGNPAR) 2355 port->ignore_status_mask |= UARTSTAT_OR; 2356 } 2357 2358 /* update the per-port timeout */ 2359 uart_update_timeout(port, termios->c_cflag, baud); 2360 2361 /* 2362 * disable CTS to ensure the transmit engine is not blocked by the flow 2363 * control when there is dirty data in TX FIFO 2364 */ 2365 lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); 2366 2367 /* 2368 * LPUART Transmission Complete Flag may never be set while queuing a break 2369 * character, so skip waiting for transmission complete when UARTCTRL_SBK is 2370 * asserted. 2371 */ 2372 if (!(old_ctrl & UARTCTRL_SBK)) 2373 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC); 2374 2375 /* disable transmit and receive */ 2376 lpuart32_write(port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2377 UARTCTRL); 2378 2379 lpuart32_write(port, bd, UARTBAUD); 2380 lpuart32_serial_setbrg(sport, baud); 2381 /* restore control register */ 2382 lpuart32_write(port, ctrl, UARTCTRL); 2383 /* re-enable the CTS if needed */ 2384 lpuart32_write(port, modem, UARTMODIR); 2385 2386 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE) 2387 sport->is_cs7 = true; 2388 2389 if (old && sport->lpuart_dma_rx_use) { 2390 if (!lpuart_start_rx_dma(sport)) 2391 rx_dma_timer_init(sport); 2392 else 2393 sport->lpuart_dma_rx_use = false; 2394 } 2395 2396 uart_port_unlock_irqrestore(port, flags); 2397 } 2398 2399 static const char *lpuart_type(struct uart_port *port) 2400 { 2401 return "FSL_LPUART"; 2402 } 2403 2404 static void lpuart_release_port(struct uart_port *port) 2405 { 2406 /* nothing to do */ 2407 } 2408 2409 static int lpuart_request_port(struct uart_port *port) 2410 { 2411 return 0; 2412 } 2413 2414 /* configure/autoconfigure the port */ 2415 static void lpuart_config_port(struct uart_port *port, int flags) 2416 { 2417 if (flags & UART_CONFIG_TYPE) 2418 port->type = PORT_LPUART; 2419 } 2420 2421 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2422 { 2423 int ret = 0; 2424 2425 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2426 ret = -EINVAL; 2427 if (port->irq != ser->irq) 2428 ret = -EINVAL; 2429 if (ser->io_type != UPIO_MEM) 2430 ret = -EINVAL; 2431 if (port->uartclk / 16 != ser->baud_base) 2432 ret = -EINVAL; 2433 if (port->iobase != ser->port) 2434 ret = -EINVAL; 2435 if (ser->hub6 != 0) 2436 ret = -EINVAL; 2437 return ret; 2438 } 2439 2440 static const struct uart_ops lpuart_pops = { 2441 .tx_empty = lpuart_tx_empty, 2442 .set_mctrl = lpuart_set_mctrl, 2443 .get_mctrl = lpuart_get_mctrl, 2444 .stop_tx = lpuart_stop_tx, 2445 .start_tx = lpuart_start_tx, 2446 .stop_rx = lpuart_stop_rx, 2447 .break_ctl = lpuart_break_ctl, 2448 .startup = lpuart_startup, 2449 .shutdown = lpuart_shutdown, 2450 .set_termios = lpuart_set_termios, 2451 .pm = lpuart_uart_pm, 2452 .type = lpuart_type, 2453 .request_port = lpuart_request_port, 2454 .release_port = lpuart_release_port, 2455 .config_port = lpuart_config_port, 2456 .verify_port = lpuart_verify_port, 2457 .flush_buffer = lpuart_flush_buffer, 2458 #if defined(CONFIG_CONSOLE_POLL) 2459 .poll_init = lpuart_poll_init, 2460 .poll_get_char = lpuart_poll_get_char, 2461 .poll_put_char = lpuart_poll_put_char, 2462 #endif 2463 }; 2464 2465 static const struct uart_ops lpuart32_pops = { 2466 .tx_empty = lpuart32_tx_empty, 2467 .set_mctrl = lpuart32_set_mctrl, 2468 .get_mctrl = lpuart32_get_mctrl, 2469 .stop_tx = lpuart32_stop_tx, 2470 .start_tx = lpuart32_start_tx, 2471 .stop_rx = lpuart32_stop_rx, 2472 .break_ctl = lpuart32_break_ctl, 2473 .startup = lpuart32_startup, 2474 .shutdown = lpuart32_shutdown, 2475 .set_termios = lpuart32_set_termios, 2476 .pm = lpuart_uart_pm, 2477 .type = lpuart_type, 2478 .request_port = lpuart_request_port, 2479 .release_port = lpuart_release_port, 2480 .config_port = lpuart_config_port, 2481 .verify_port = lpuart_verify_port, 2482 .flush_buffer = lpuart_flush_buffer, 2483 #if defined(CONFIG_CONSOLE_POLL) 2484 .poll_init = lpuart32_poll_init, 2485 .poll_get_char = lpuart32_poll_get_char, 2486 .poll_put_char = lpuart32_poll_put_char, 2487 #endif 2488 }; 2489 2490 static struct lpuart_port *lpuart_ports[UART_NR]; 2491 2492 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2493 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) 2494 { 2495 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2496 writeb(ch, port->membase + UARTDR); 2497 } 2498 2499 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) 2500 { 2501 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2502 lpuart32_write(port, ch, UARTDATA); 2503 } 2504 2505 static void 2506 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2507 { 2508 struct lpuart_port *sport = lpuart_ports[co->index]; 2509 u8 old_cr2, cr2; 2510 unsigned long flags; 2511 int locked = 1; 2512 2513 if (oops_in_progress) 2514 locked = uart_port_trylock_irqsave(&sport->port, &flags); 2515 else 2516 uart_port_lock_irqsave(&sport->port, &flags); 2517 2518 /* first save CR2 and then disable interrupts */ 2519 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2520 cr2 |= UARTCR2_TE | UARTCR2_RE; 2521 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2522 writeb(cr2, sport->port.membase + UARTCR2); 2523 2524 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2525 2526 /* wait for transmitter finish complete and restore CR2 */ 2527 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2528 2529 writeb(old_cr2, sport->port.membase + UARTCR2); 2530 2531 if (locked) 2532 uart_port_unlock_irqrestore(&sport->port, flags); 2533 } 2534 2535 static void 2536 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2537 { 2538 struct lpuart_port *sport = lpuart_ports[co->index]; 2539 u32 old_cr, cr; 2540 unsigned long flags; 2541 int locked = 1; 2542 2543 if (oops_in_progress) 2544 locked = uart_port_trylock_irqsave(&sport->port, &flags); 2545 else 2546 uart_port_lock_irqsave(&sport->port, &flags); 2547 2548 /* first save CR2 and then disable interrupts */ 2549 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2550 cr |= UARTCTRL_TE | UARTCTRL_RE; 2551 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2552 lpuart32_write(&sport->port, cr, UARTCTRL); 2553 2554 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2555 2556 /* wait for transmitter finish complete and restore CR2 */ 2557 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2558 2559 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2560 2561 if (locked) 2562 uart_port_unlock_irqrestore(&sport->port, flags); 2563 } 2564 2565 /* 2566 * if the port was already initialised (eg, by a boot loader), 2567 * try to determine the current setup. 2568 */ 2569 static void __init 2570 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2571 int *parity, int *bits) 2572 { 2573 u8 cr, bdh, bdl, brfa; 2574 unsigned int sbr, uartclk, baud_raw; 2575 2576 cr = readb(sport->port.membase + UARTCR2); 2577 cr &= UARTCR2_TE | UARTCR2_RE; 2578 if (!cr) 2579 return; 2580 2581 /* ok, the port was enabled */ 2582 2583 cr = readb(sport->port.membase + UARTCR1); 2584 2585 *parity = 'n'; 2586 if (cr & UARTCR1_PE) { 2587 if (cr & UARTCR1_PT) 2588 *parity = 'o'; 2589 else 2590 *parity = 'e'; 2591 } 2592 2593 if (cr & UARTCR1_M) 2594 *bits = 9; 2595 else 2596 *bits = 8; 2597 2598 bdh = readb(sport->port.membase + UARTBDH); 2599 bdh &= UARTBDH_SBR_MASK; 2600 bdl = readb(sport->port.membase + UARTBDL); 2601 sbr = bdh; 2602 sbr <<= 8; 2603 sbr |= bdl; 2604 brfa = readb(sport->port.membase + UARTCR4); 2605 brfa &= UARTCR4_BRFA_MASK; 2606 2607 uartclk = lpuart_get_baud_clk_rate(sport); 2608 /* 2609 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2610 */ 2611 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2612 2613 if (*baud != baud_raw) 2614 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2615 "from %d to %d\n", baud_raw, *baud); 2616 } 2617 2618 static void __init 2619 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2620 int *parity, int *bits) 2621 { 2622 u32 cr, bd; 2623 unsigned int sbr, uartclk, baud_raw; 2624 2625 cr = lpuart32_read(&sport->port, UARTCTRL); 2626 cr &= UARTCTRL_TE | UARTCTRL_RE; 2627 if (!cr) 2628 return; 2629 2630 /* ok, the port was enabled */ 2631 2632 cr = lpuart32_read(&sport->port, UARTCTRL); 2633 2634 *parity = 'n'; 2635 if (cr & UARTCTRL_PE) { 2636 if (cr & UARTCTRL_PT) 2637 *parity = 'o'; 2638 else 2639 *parity = 'e'; 2640 } 2641 2642 if (cr & UARTCTRL_M) 2643 *bits = 9; 2644 else 2645 *bits = 8; 2646 2647 bd = lpuart32_read(&sport->port, UARTBAUD); 2648 bd &= UARTBAUD_SBR_MASK; 2649 if (!bd) 2650 return; 2651 2652 sbr = bd; 2653 uartclk = lpuart_get_baud_clk_rate(sport); 2654 /* 2655 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2656 */ 2657 baud_raw = uartclk / (16 * sbr); 2658 2659 if (*baud != baud_raw) 2660 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2661 "from %d to %d\n", baud_raw, *baud); 2662 } 2663 2664 static int __init lpuart_console_setup(struct console *co, char *options) 2665 { 2666 struct lpuart_port *sport; 2667 int baud = 115200; 2668 int bits = 8; 2669 int parity = 'n'; 2670 int flow = 'n'; 2671 2672 /* 2673 * check whether an invalid uart number has been specified, and 2674 * if so, search for the first available port that does have 2675 * console support. 2676 */ 2677 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2678 co->index = 0; 2679 2680 sport = lpuart_ports[co->index]; 2681 if (sport == NULL) 2682 return -ENODEV; 2683 2684 if (options) 2685 uart_parse_options(options, &baud, &parity, &bits, &flow); 2686 else 2687 if (lpuart_is_32(sport)) 2688 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2689 else 2690 lpuart_console_get_options(sport, &baud, &parity, &bits); 2691 2692 if (lpuart_is_32(sport)) 2693 lpuart32_setup_watermark(sport); 2694 else 2695 lpuart_setup_watermark(sport); 2696 2697 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2698 } 2699 2700 static struct uart_driver lpuart_reg; 2701 static struct console lpuart_console = { 2702 .name = DEV_NAME, 2703 .write = lpuart_console_write, 2704 .device = uart_console_device, 2705 .setup = lpuart_console_setup, 2706 .flags = CON_PRINTBUFFER, 2707 .index = -1, 2708 .data = &lpuart_reg, 2709 }; 2710 2711 static struct console lpuart32_console = { 2712 .name = DEV_NAME, 2713 .write = lpuart32_console_write, 2714 .device = uart_console_device, 2715 .setup = lpuart_console_setup, 2716 .flags = CON_PRINTBUFFER, 2717 .index = -1, 2718 .data = &lpuart_reg, 2719 }; 2720 2721 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2722 { 2723 struct earlycon_device *dev = con->data; 2724 2725 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2726 } 2727 2728 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2729 { 2730 struct earlycon_device *dev = con->data; 2731 2732 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2733 } 2734 2735 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2736 const char *opt) 2737 { 2738 if (!device->port.membase) 2739 return -ENODEV; 2740 2741 device->con->write = lpuart_early_write; 2742 return 0; 2743 } 2744 2745 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2746 const char *opt) 2747 { 2748 if (!device->port.membase) 2749 return -ENODEV; 2750 2751 if (device->port.iotype != UPIO_MEM32) 2752 device->port.iotype = UPIO_MEM32BE; 2753 2754 device->con->write = lpuart32_early_write; 2755 return 0; 2756 } 2757 2758 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2759 const char *opt) 2760 { 2761 u32 cr; 2762 2763 if (!device->port.membase) 2764 return -ENODEV; 2765 2766 device->port.iotype = UPIO_MEM32; 2767 device->con->write = lpuart32_early_write; 2768 2769 /* set the baudrate */ 2770 if (device->port.uartclk && device->baud) 2771 __lpuart32_serial_setbrg(&device->port, device->baud, 2772 false, false); 2773 2774 /* enable transmitter */ 2775 cr = lpuart32_read(&device->port, UARTCTRL); 2776 cr |= UARTCTRL_TE; 2777 lpuart32_write(&device->port, cr, UARTCTRL); 2778 2779 return 0; 2780 } 2781 2782 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2783 const char *opt) 2784 { 2785 if (!device->port.membase) 2786 return -ENODEV; 2787 2788 device->port.iotype = UPIO_MEM32; 2789 device->port.membase += IMX_REG_OFF; 2790 device->con->write = lpuart32_early_write; 2791 2792 return 0; 2793 } 2794 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2795 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2796 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2797 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2798 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup); 2799 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2800 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2801 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2802 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2803 2804 #define LPUART_CONSOLE (&lpuart_console) 2805 #define LPUART32_CONSOLE (&lpuart32_console) 2806 #else 2807 #define LPUART_CONSOLE NULL 2808 #define LPUART32_CONSOLE NULL 2809 #endif 2810 2811 static struct uart_driver lpuart_reg = { 2812 .owner = THIS_MODULE, 2813 .driver_name = DRIVER_NAME, 2814 .dev_name = DEV_NAME, 2815 .nr = ARRAY_SIZE(lpuart_ports), 2816 .cons = LPUART_CONSOLE, 2817 }; 2818 2819 static const struct serial_rs485 lpuart_rs485_supported = { 2820 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 2821 /* delay_rts_* and RX_DURING_TX are not supported */ 2822 }; 2823 2824 static int lpuart_global_reset(struct lpuart_port *sport) 2825 { 2826 struct uart_port *port = &sport->port; 2827 void __iomem *global_addr; 2828 u32 ctrl, bd; 2829 unsigned int val = 0; 2830 int ret; 2831 2832 ret = clk_prepare_enable(sport->ipg_clk); 2833 if (ret) { 2834 dev_err(port->dev, "failed to enable uart ipg clk: %d\n", ret); 2835 return ret; 2836 } 2837 2838 if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { 2839 /* 2840 * If the transmitter is used by earlycon, wait for transmit engine to 2841 * complete and then reset. 2842 */ 2843 ctrl = lpuart32_read(port, UARTCTRL); 2844 if (ctrl & UARTCTRL_TE) { 2845 bd = lpuart32_read(port, UARTBAUD); 2846 if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false, 2847 port)) { 2848 dev_warn(port->dev, 2849 "timeout waiting for transmit engine to complete\n"); 2850 clk_disable_unprepare(sport->ipg_clk); 2851 return 0; 2852 } 2853 } 2854 2855 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; 2856 writel(UART_GLOBAL_RST, global_addr); 2857 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2858 writel(0, global_addr); 2859 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2860 2861 /* Recover the transmitter for earlycon. */ 2862 if (ctrl & UARTCTRL_TE) { 2863 lpuart32_write(port, bd, UARTBAUD); 2864 lpuart32_write(port, ctrl, UARTCTRL); 2865 } 2866 } 2867 2868 clk_disable_unprepare(sport->ipg_clk); 2869 return 0; 2870 } 2871 2872 static int lpuart_probe(struct platform_device *pdev) 2873 { 2874 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); 2875 struct device_node *np = pdev->dev.of_node; 2876 struct lpuart_port *sport; 2877 struct resource *res; 2878 irq_handler_t handler; 2879 int ret; 2880 2881 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2882 if (!sport) 2883 return -ENOMEM; 2884 2885 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2886 if (IS_ERR(sport->port.membase)) 2887 return PTR_ERR(sport->port.membase); 2888 2889 sport->port.membase += sdata->reg_off; 2890 sport->port.mapbase = res->start + sdata->reg_off; 2891 sport->port.dev = &pdev->dev; 2892 sport->port.type = PORT_LPUART; 2893 sport->devtype = sdata->devtype; 2894 sport->rx_watermark = sdata->rx_watermark; 2895 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || 2896 is_imx8qxp_lpuart(sport); 2897 ret = platform_get_irq(pdev, 0); 2898 if (ret < 0) 2899 return ret; 2900 sport->port.irq = ret; 2901 sport->port.iotype = sdata->iotype; 2902 if (lpuart_is_32(sport)) 2903 sport->port.ops = &lpuart32_pops; 2904 else 2905 sport->port.ops = &lpuart_pops; 2906 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2907 sport->port.flags = UPF_BOOT_AUTOCONF; 2908 2909 if (lpuart_is_32(sport)) 2910 sport->port.rs485_config = lpuart32_config_rs485; 2911 else 2912 sport->port.rs485_config = lpuart_config_rs485; 2913 sport->port.rs485_supported = lpuart_rs485_supported; 2914 2915 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2916 if (IS_ERR(sport->ipg_clk)) { 2917 ret = PTR_ERR(sport->ipg_clk); 2918 return dev_err_probe(&pdev->dev, ret, "failed to get uart ipg clk\n"); 2919 } 2920 2921 sport->baud_clk = NULL; 2922 if (is_imx8qxp_lpuart(sport)) { 2923 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2924 if (IS_ERR(sport->baud_clk)) { 2925 ret = PTR_ERR(sport->baud_clk); 2926 return dev_err_probe(&pdev->dev, ret, "failed to get uart baud clk\n"); 2927 } 2928 } 2929 2930 ret = of_alias_get_id(np, "serial"); 2931 if (ret < 0) { 2932 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2933 return ret; 2934 } 2935 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2936 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2937 return -EINVAL; 2938 } 2939 sport->port.line = ret; 2940 2941 ret = lpuart_enable_clks(sport); 2942 if (ret) 2943 return ret; 2944 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2945 2946 lpuart_ports[sport->port.line] = sport; 2947 2948 platform_set_drvdata(pdev, &sport->port); 2949 2950 if (lpuart_is_32(sport)) { 2951 lpuart_reg.cons = LPUART32_CONSOLE; 2952 handler = lpuart32_int; 2953 } else { 2954 lpuart_reg.cons = LPUART_CONSOLE; 2955 handler = lpuart_int; 2956 } 2957 2958 pm_runtime_use_autosuspend(&pdev->dev); 2959 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 2960 pm_runtime_set_active(&pdev->dev); 2961 pm_runtime_enable(&pdev->dev); 2962 pm_runtime_mark_last_busy(&pdev->dev); 2963 2964 ret = lpuart_global_reset(sport); 2965 if (ret) 2966 goto failed_reset; 2967 2968 ret = uart_get_rs485_mode(&sport->port); 2969 if (ret) 2970 goto failed_get_rs485; 2971 2972 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2973 if (ret) 2974 goto failed_attach_port; 2975 2976 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, 2977 dev_name(&pdev->dev), sport); 2978 if (ret) 2979 goto failed_irq_request; 2980 2981 return 0; 2982 2983 failed_irq_request: 2984 uart_remove_one_port(&lpuart_reg, &sport->port); 2985 failed_attach_port: 2986 failed_get_rs485: 2987 failed_reset: 2988 pm_runtime_disable(&pdev->dev); 2989 pm_runtime_set_suspended(&pdev->dev); 2990 pm_runtime_dont_use_autosuspend(&pdev->dev); 2991 lpuart_disable_clks(sport); 2992 return ret; 2993 } 2994 2995 static void lpuart_remove(struct platform_device *pdev) 2996 { 2997 struct lpuart_port *sport = platform_get_drvdata(pdev); 2998 2999 uart_remove_one_port(&lpuart_reg, &sport->port); 3000 3001 lpuart_disable_clks(sport); 3002 3003 if (sport->dma_tx_chan) 3004 dma_release_channel(sport->dma_tx_chan); 3005 3006 if (sport->dma_rx_chan) 3007 dma_release_channel(sport->dma_rx_chan); 3008 3009 pm_runtime_disable(&pdev->dev); 3010 pm_runtime_set_suspended(&pdev->dev); 3011 pm_runtime_dont_use_autosuspend(&pdev->dev); 3012 } 3013 3014 static int lpuart_runtime_suspend(struct device *dev) 3015 { 3016 struct platform_device *pdev = to_platform_device(dev); 3017 struct lpuart_port *sport = platform_get_drvdata(pdev); 3018 3019 lpuart_disable_clks(sport); 3020 3021 return 0; 3022 }; 3023 3024 static int lpuart_runtime_resume(struct device *dev) 3025 { 3026 struct platform_device *pdev = to_platform_device(dev); 3027 struct lpuart_port *sport = platform_get_drvdata(pdev); 3028 3029 return lpuart_enable_clks(sport); 3030 }; 3031 3032 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) 3033 { 3034 u32 val, baud; 3035 3036 if (lpuart_is_32(sport)) { 3037 val = lpuart32_read(&sport->port, UARTCTRL); 3038 baud = lpuart32_read(&sport->port, UARTBAUD); 3039 if (on) { 3040 /* set rx_watermark to 0 in wakeup source mode */ 3041 lpuart32_write(&sport->port, 0, UARTWATER); 3042 val |= UARTCTRL_RIE; 3043 /* clear RXEDGIF flag before enable RXEDGIE interrupt */ 3044 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); 3045 baud |= UARTBAUD_RXEDGIE; 3046 } else { 3047 val &= ~UARTCTRL_RIE; 3048 baud &= ~UARTBAUD_RXEDGIE; 3049 } 3050 lpuart32_write(&sport->port, val, UARTCTRL); 3051 lpuart32_write(&sport->port, baud, UARTBAUD); 3052 } else { 3053 val = readb(sport->port.membase + UARTCR2); 3054 if (on) 3055 val |= UARTCR2_RIE; 3056 else 3057 val &= ~UARTCR2_RIE; 3058 writeb(val, sport->port.membase + UARTCR2); 3059 } 3060 } 3061 3062 static bool lpuart_uport_is_active(struct lpuart_port *sport) 3063 { 3064 struct tty_port *port = &sport->port.state->port; 3065 struct tty_struct *tty; 3066 struct device *tty_dev; 3067 int may_wake = 0; 3068 3069 tty = tty_port_tty_get(port); 3070 if (tty) { 3071 tty_dev = tty->dev; 3072 may_wake = tty_dev && device_may_wakeup(tty_dev); 3073 tty_kref_put(tty); 3074 } 3075 3076 if ((tty_port_initialized(port) && may_wake) || 3077 (!console_suspend_enabled && uart_console(&sport->port))) 3078 return true; 3079 3080 return false; 3081 } 3082 3083 static int lpuart_suspend_noirq(struct device *dev) 3084 { 3085 struct lpuart_port *sport = dev_get_drvdata(dev); 3086 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 3087 3088 if (lpuart_uport_is_active(sport)) 3089 serial_lpuart_enable_wakeup(sport, !!irq_wake); 3090 3091 pinctrl_pm_select_sleep_state(dev); 3092 3093 return 0; 3094 } 3095 3096 static int lpuart_resume_noirq(struct device *dev) 3097 { 3098 struct lpuart_port *sport = dev_get_drvdata(dev); 3099 struct tty_port *port = &sport->port.state->port; 3100 bool wake_active; 3101 u32 stat; 3102 3103 pinctrl_pm_select_default_state(dev); 3104 3105 if (lpuart_uport_is_active(sport)) { 3106 serial_lpuart_enable_wakeup(sport, false); 3107 3108 /* clear the wakeup flags */ 3109 if (lpuart_is_32(sport)) { 3110 stat = lpuart32_read(&sport->port, UARTSTAT); 3111 lpuart32_write(&sport->port, stat, UARTSTAT); 3112 3113 /* check whether lpuart wakeup was triggered */ 3114 wake_active = stat & (UARTSTAT_RDRF | UARTSTAT_RXEDGIF); 3115 3116 if (wake_active && irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq))) 3117 pm_wakeup_event(tty_port_tty_get(port)->dev, 0); 3118 } 3119 } 3120 3121 return 0; 3122 } 3123 3124 static int lpuart_suspend(struct device *dev) 3125 { 3126 struct lpuart_port *sport = dev_get_drvdata(dev); 3127 u32 temp; 3128 unsigned long flags; 3129 3130 uart_suspend_port(&lpuart_reg, &sport->port); 3131 3132 if (lpuart_uport_is_active(sport)) { 3133 uart_port_lock_irqsave(&sport->port, &flags); 3134 if (lpuart_is_32(sport)) { 3135 /* disable Rx/Tx and interrupts */ 3136 temp = lpuart32_read(&sport->port, UARTCTRL); 3137 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 3138 lpuart32_write(&sport->port, temp, UARTCTRL); 3139 } else { 3140 /* disable Rx/Tx and interrupts */ 3141 temp = readb(sport->port.membase + UARTCR2); 3142 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 3143 writeb(temp, sport->port.membase + UARTCR2); 3144 } 3145 uart_port_unlock_irqrestore(&sport->port, flags); 3146 3147 if (sport->lpuart_dma_rx_use) { 3148 /* 3149 * EDMA driver during suspend will forcefully release any 3150 * non-idle DMA channels. If port wakeup is enabled or if port 3151 * is console port or 'no_console_suspend' is set the Rx DMA 3152 * cannot resume as expected, hence gracefully release the 3153 * Rx DMA path before suspend and start Rx DMA path on resume. 3154 */ 3155 lpuart_dma_rx_free(&sport->port); 3156 3157 /* Disable Rx DMA to use UART port as wakeup source */ 3158 uart_port_lock_irqsave(&sport->port, &flags); 3159 if (lpuart_is_32(sport)) { 3160 temp = lpuart32_read(&sport->port, UARTBAUD); 3161 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 3162 UARTBAUD); 3163 } else { 3164 writeb(readb(sport->port.membase + UARTCR5) & 3165 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 3166 } 3167 uart_port_unlock_irqrestore(&sport->port, flags); 3168 } 3169 3170 if (sport->lpuart_dma_tx_use) { 3171 uart_port_lock_irqsave(&sport->port, &flags); 3172 if (lpuart_is_32(sport)) { 3173 temp = lpuart32_read(&sport->port, UARTBAUD); 3174 temp &= ~UARTBAUD_TDMAE; 3175 lpuart32_write(&sport->port, temp, UARTBAUD); 3176 } else { 3177 temp = readb(sport->port.membase + UARTCR5); 3178 temp &= ~UARTCR5_TDMAS; 3179 writeb(temp, sport->port.membase + UARTCR5); 3180 } 3181 uart_port_unlock_irqrestore(&sport->port, flags); 3182 sport->dma_tx_in_progress = false; 3183 dmaengine_terminate_sync(sport->dma_tx_chan); 3184 } 3185 } else if (pm_runtime_active(sport->port.dev)) { 3186 lpuart_disable_clks(sport); 3187 pm_runtime_disable(sport->port.dev); 3188 pm_runtime_set_suspended(sport->port.dev); 3189 } 3190 3191 return 0; 3192 } 3193 3194 static void lpuart_console_fixup(struct lpuart_port *sport) 3195 { 3196 struct tty_port *port = &sport->port.state->port; 3197 struct uart_port *uport = &sport->port; 3198 struct ktermios termios; 3199 3200 /* i.MX7ULP enter VLLS mode that lpuart module power off and registers 3201 * all lost no matter the port is wakeup source. 3202 * For console port, console baud rate setting lost and print messy 3203 * log when enable the console port as wakeup source. To avoid the 3204 * issue happen, user should not enable uart port as wakeup source 3205 * in VLLS mode, or restore console setting here. 3206 */ 3207 if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) && 3208 console_suspend_enabled && uart_console(uport)) { 3209 3210 mutex_lock(&port->mutex); 3211 memset(&termios, 0, sizeof(struct ktermios)); 3212 termios.c_cflag = uport->cons->cflag; 3213 if (port->tty && termios.c_cflag == 0) 3214 termios = port->tty->termios; 3215 uport->ops->set_termios(uport, &termios, NULL); 3216 mutex_unlock(&port->mutex); 3217 } 3218 } 3219 3220 static int lpuart_resume(struct device *dev) 3221 { 3222 struct lpuart_port *sport = dev_get_drvdata(dev); 3223 int ret; 3224 3225 if (lpuart_uport_is_active(sport)) { 3226 if (lpuart_is_32(sport)) 3227 lpuart32_hw_setup(sport); 3228 else 3229 lpuart_hw_setup(sport); 3230 } else if (pm_runtime_active(sport->port.dev)) { 3231 ret = lpuart_enable_clks(sport); 3232 if (ret) 3233 return ret; 3234 pm_runtime_set_active(sport->port.dev); 3235 pm_runtime_enable(sport->port.dev); 3236 } 3237 3238 lpuart_console_fixup(sport); 3239 uart_resume_port(&lpuart_reg, &sport->port); 3240 3241 return 0; 3242 } 3243 3244 static const struct dev_pm_ops lpuart_pm_ops = { 3245 RUNTIME_PM_OPS(lpuart_runtime_suspend, 3246 lpuart_runtime_resume, NULL) 3247 NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq, 3248 lpuart_resume_noirq) 3249 SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume) 3250 }; 3251 3252 static struct platform_driver lpuart_driver = { 3253 .probe = lpuart_probe, 3254 .remove = lpuart_remove, 3255 .driver = { 3256 .name = "fsl-lpuart", 3257 .of_match_table = lpuart_dt_ids, 3258 .pm = pm_ptr(&lpuart_pm_ops), 3259 }, 3260 }; 3261 3262 static int __init lpuart_serial_init(void) 3263 { 3264 int ret = uart_register_driver(&lpuart_reg); 3265 3266 if (ret) 3267 return ret; 3268 3269 ret = platform_driver_register(&lpuart_driver); 3270 if (ret) 3271 uart_unregister_driver(&lpuart_reg); 3272 3273 return ret; 3274 } 3275 3276 static void __exit lpuart_serial_exit(void) 3277 { 3278 platform_driver_unregister(&lpuart_driver); 3279 uart_unregister_driver(&lpuart_reg); 3280 } 3281 3282 module_init(lpuart_serial_init); 3283 module_exit(lpuart_serial_exit); 3284 3285 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 3286 MODULE_LICENSE("GPL v2"); 3287