1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_CORE_SHARED_TYPES_H__ 6 #define __DML2_CORE_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_display_cfg_types.h" 10 #include "dml_top_types.h" 11 #include "lib_frl_cap_check.h" 12 13 #define __DML_VBA_DEBUG__ 14 #define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief max vratio for one-to-one prefetch bw scheduling 15 #define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //<brief max vratio for equalized prefetch bw scheduling 16 #define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //<brief max prefetch vratio register limit 17 18 #define __DML2_CALCS_DPP_INVALID__ 0 19 #define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation 20 #define __DML2_CALCS_PIPE_NO_PLANE__ 99 21 22 struct dml2_core_ip_params { 23 unsigned int vblank_nom_default_us; 24 unsigned int remote_iommu_outstanding_translations; 25 unsigned int rob_buffer_size_kbytes; 26 unsigned int config_return_buffer_size_in_kbytes; 27 unsigned int config_return_buffer_segment_size_in_kbytes; 28 unsigned int compressed_buffer_segment_size_in_kbytes; 29 unsigned int meta_fifo_size_in_kentries; 30 unsigned int dpte_buffer_size_in_pte_reqs_luma; 31 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 32 unsigned int pixel_chunk_size_kbytes; 33 unsigned int alpha_pixel_chunk_size_kbytes; 34 unsigned int min_pixel_chunk_size_bytes; 35 unsigned int writeback_chunk_size_kbytes; 36 unsigned int line_buffer_size_bits; 37 unsigned int max_line_buffer_lines; 38 unsigned int writeback_interface_buffer_size_kbytes; 39 unsigned int max_num_dpp; 40 unsigned int max_num_opp; 41 unsigned int max_num_otg; 42 unsigned int TDLUT_33cube_count; 43 unsigned int max_num_wb; 44 unsigned int max_dchub_pscl_bw_pix_per_clk; 45 unsigned int max_pscl_lb_bw_pix_per_clk; 46 unsigned int max_lb_vscl_bw_pix_per_clk; 47 unsigned int max_vscl_hscl_bw_pix_per_clk; 48 double max_hscl_ratio; 49 double max_vscl_ratio; 50 unsigned int max_hscl_taps; 51 unsigned int max_vscl_taps; 52 unsigned int odm_combine_support_mask; 53 unsigned int num_dsc; 54 unsigned int maximum_dsc_bits_per_component; 55 unsigned int maximum_pixels_per_line_per_dsc_unit; 56 bool dsc422_native_support; 57 bool cursor_64bpp_support; 58 double dispclk_ramp_margin_percent; 59 unsigned int dppclk_delay_subtotal; 60 unsigned int dppclk_delay_scl; 61 unsigned int dppclk_delay_scl_lb_only; 62 unsigned int dppclk_delay_cnvc_formatter; 63 unsigned int dppclk_delay_cnvc_cursor; 64 unsigned int cursor_buffer_size; 65 unsigned int cursor_chunk_size; 66 unsigned int dispclk_delay_subtotal; 67 bool dynamic_metadata_vm_enabled; 68 unsigned int max_inter_dcn_tile_repeaters; 69 unsigned int max_num_hdmi_frl_outputs; 70 unsigned int max_num_dp2p0_outputs; 71 unsigned int max_num_dp2p0_streams; 72 bool dcc_supported; 73 bool ptoi_supported; 74 double writeback_max_hscl_ratio; 75 double writeback_max_vscl_ratio; 76 double writeback_min_hscl_ratio; 77 double writeback_min_vscl_ratio; 78 unsigned int writeback_max_hscl_taps; 79 unsigned int writeback_max_vscl_taps; 80 unsigned int writeback_line_buffer_buffer_size; 81 82 unsigned int words_per_channel; 83 bool imall_supported; 84 unsigned int max_flip_time_us; 85 unsigned int max_flip_time_lines; 86 unsigned int subvp_swath_height_margin_lines; 87 unsigned int subvp_fw_processing_delay_us; 88 unsigned int subvp_pstate_allow_width_us; 89 // MRQ 90 bool dcn_mrq_present; 91 unsigned int zero_size_buffer_entries; 92 unsigned int compbuf_reserved_space_zs; 93 unsigned int dcc_meta_buffer_size_bytes; 94 unsigned int meta_chunk_size_kbytes; 95 unsigned int min_meta_chunk_size_bytes; 96 97 unsigned int dchub_arb_to_ret_delay; // num of dcfclk 98 unsigned int hostvm_mode; 99 }; 100 101 struct dml2_core_internal_DmlPipe { 102 double Dppclk; 103 double Dispclk; 104 double PixelClock; 105 double DCFClkDeepSleep; 106 unsigned int DPPPerSurface; 107 bool ScalerEnabled; 108 bool UPSPEnabled; 109 unsigned int UPSPVTaps; 110 enum dml2_sample_positioning UPSPSamplePositioning; 111 enum dml2_rotation_angle RotationAngle; 112 bool mirrored; 113 unsigned int ViewportHeight; 114 unsigned int ViewportHeightC; 115 unsigned int BlockWidth256BytesY; 116 unsigned int BlockHeight256BytesY; 117 unsigned int BlockWidth256BytesC; 118 unsigned int BlockHeight256BytesC; 119 unsigned int BlockWidthY; 120 unsigned int BlockHeightY; 121 unsigned int BlockWidthC; 122 unsigned int BlockHeightC; 123 unsigned int InterlaceEnable; 124 unsigned int NumberOfCursors; 125 unsigned int VBlank; 126 unsigned int HTotal; 127 unsigned int HActive; 128 bool DCCEnable; 129 enum dml2_odm_mode ODMMode; 130 enum dml2_source_format_class SourcePixelFormat; 131 enum dml2_swizzle_mode SurfaceTiling; 132 unsigned int BytePerPixelY; 133 unsigned int BytePerPixelC; 134 bool ProgressiveToInterlaceUnitInOPP; 135 double VRatio; 136 double VRatioChroma; 137 unsigned int VTaps; 138 unsigned int VTapsChroma; 139 unsigned int PitchY; 140 unsigned int PitchC; 141 bool ViewportStationary; 142 unsigned int ViewportXStart; 143 unsigned int ViewportYStart; 144 unsigned int ViewportXStartC; 145 unsigned int ViewportYStartC; 146 bool FORCE_ONE_ROW_FOR_FRAME; 147 unsigned int SwathHeightY; 148 unsigned int SwathHeightC; 149 150 unsigned int DCCMetaPitchY; 151 unsigned int DCCMetaPitchC; 152 }; 153 154 enum dml2_core_internal_request_type { 155 dml2_core_internal_request_type_256_bytes = 0, 156 dml2_core_internal_request_type_128_bytes_non_contiguous = 1, 157 dml2_core_internal_request_type_128_bytes_contiguous = 2, 158 dml2_core_internal_request_type_na = 3 159 }; 160 enum dml2_core_internal_bw_type { 161 dml2_core_internal_bw_sdp = 0, 162 dml2_core_internal_bw_dram = 1, 163 dml2_core_internal_bw_max 164 }; 165 166 enum dml2_core_internal_soc_state_type { 167 dml2_core_internal_soc_state_sys_active = 0, 168 dml2_core_internal_soc_state_svp_prefetch = 1, 169 dml2_core_internal_soc_state_sys_idle = 2, 170 dml2_core_internal_soc_state_max 171 }; 172 173 enum dml2_core_internal_output_type { 174 dml2_core_internal_output_type_unknown = 0, 175 dml2_core_internal_output_type_dp = 1, 176 dml2_core_internal_output_type_edp = 2, 177 dml2_core_internal_output_type_dp2p0 = 3, 178 dml2_core_internal_output_type_hdmi = 4, 179 dml2_core_internal_output_type_hdmifrl = 5 180 }; 181 182 enum dml2_core_internal_output_type_rate { 183 dml2_core_internal_output_rate_unknown = 0, 184 dml2_core_internal_output_rate_dp_rate_hbr = 1, 185 dml2_core_internal_output_rate_dp_rate_hbr2 = 2, 186 dml2_core_internal_output_rate_dp_rate_hbr3 = 3, 187 dml2_core_internal_output_rate_dp_rate_uhbr10 = 4, 188 dml2_core_internal_output_rate_dp_rate_uhbr13p5 = 5, 189 dml2_core_internal_output_rate_dp_rate_uhbr20 = 6, 190 dml2_core_internal_output_rate_hdmi_rate_3x3 = 7, 191 dml2_core_internal_output_rate_hdmi_rate_6x3 = 8, 192 dml2_core_internal_output_rate_hdmi_rate_6x4 = 9, 193 dml2_core_internal_output_rate_hdmi_rate_8x4 = 10, 194 dml2_core_internal_output_rate_hdmi_rate_10x4 = 11, 195 dml2_core_internal_output_rate_hdmi_rate_12x4 = 12, 196 dml2_core_internal_output_rate_hdmi_rate_16x4 = 13, 197 dml2_core_internal_output_rate_hdmi_rate_20x4 = 14 198 }; 199 200 struct dml2_core_internal_watermarks { 201 double UrgentWatermark; 202 double WritebackUrgentWatermark; 203 double DRAMClockChangeWatermark; 204 double FCLKChangeWatermark; 205 double WritebackDRAMClockChangeWatermark; 206 double WritebackFCLKChangeWatermark; 207 double StutterExitWatermark; 208 double StutterEnterPlusExitWatermark; 209 double LowPowerStutterExitWatermark; 210 double LowPowerStutterEnterPlusExitWatermark; 211 double Z8StutterExitWatermark; 212 double Z8StutterEnterPlusExitWatermark; 213 double USRRetrainingWatermark; 214 double temp_read_or_ppt_watermark_us; 215 }; 216 217 struct dml2_core_internal_mode_support_info { 218 //----------------- 219 // Mode Support Information 220 //----------------- 221 bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 222 223 // Mode Support Reason/ 224 bool WritebackLatencySupport; 225 bool ScaleRatioAndTapsSupport; 226 bool SourceFormatPixelAndScanSupport; 227 bool P2IWith420; 228 bool DSCSlicesODMModeSupported; 229 bool DSCOnlyIfNecessaryWithBPP; 230 bool DSC422NativeNotSupported; 231 bool LinkRateDoesNotMatchDPVersion; 232 bool LinkRateForMultistreamNotIndicated; 233 bool BPPForMultistreamNotIndicated; 234 bool MultistreamWithHDMIOreDP; 235 bool MSOOrODMSplitWithNonDPLink; 236 bool NotEnoughLanesForMSO; 237 bool NumberOfOTGSupport; 238 bool NumberOfTDLUT33cubeSupport; 239 bool NumberOfHDMIFRLSupport; 240 bool NumberOfDP2p0Support; 241 bool WritebackScaleRatioAndTapsSupport; 242 bool CursorSupport; 243 bool PitchSupport; 244 bool ViewportExceedsSurface; 245 //bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 246 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 247 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 248 bool InvalidCombinationOfMALLUseForPState; 249 bool ExceededMALLSize; 250 bool EnoughWritebackUnits; 251 252 bool ExceededMultistreamSlots; 253 bool NotEnoughDSCUnits; 254 bool NotEnoughDSCSlices; 255 bool PixelsPerLinePerDSCUnitSupport; 256 bool DSCCLKRequiredMoreThanSupported; 257 bool DTBCLKRequiredMoreThanSupported; 258 bool LinkCapacitySupport; 259 260 bool ROBSupport; 261 bool OutstandingRequestsSupport; 262 bool OutstandingRequestsUrgencyAvoidance; 263 264 bool PTEBufferSizeNotExceeded; 265 bool DCCMetaBufferSizeNotExceeded; 266 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 267 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 268 enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; 269 bool global_dram_clock_change_support_required; 270 bool global_dram_clock_change_supported; 271 bool global_fclk_change_supported; 272 bool global_temp_read_or_ppt_supported; 273 bool fclk_pstate_schedule_admissible; 274 bool temp_read_pstate_schedule_admissible; 275 bool ppt_pstate_schedule_admissible; 276 bool USRRetrainingSupport; 277 bool AvgBandwidthSupport; 278 bool UrgVactiveBandwidthSupport; 279 bool EnoughUrgentLatencyHidingSupport; 280 bool PrefetchScheduleSupported; 281 bool PrefetchSupported; 282 bool PrefetchBandwidthSupported; 283 bool DynamicMetadataSupported; 284 bool VRatioInPrefetchSupported; 285 bool DISPCLK_DPPCLK_Support; 286 bool TotalAvailablePipesSupport; 287 bool ODMSupport; 288 bool ModeSupport; 289 bool ViewportSizeSupport; 290 291 bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 292 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 293 unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 294 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming 295 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required 296 unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode 297 298 double OutputBpp[DML2_MAX_PLANES]; 299 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 300 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 301 302 unsigned int AlignedYPitch[DML2_MAX_PLANES]; 303 unsigned int AlignedCPitch[DML2_MAX_PLANES]; 304 305 unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES]; 306 unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES]; 307 308 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 309 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 310 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 311 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 312 313 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 314 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 315 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 316 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 317 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 318 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 319 320 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 321 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 322 double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP and DRAM, for latency evaluation 323 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 324 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 325 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm etc. 326 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 327 328 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 329 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 330 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 331 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 332 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 333 334 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 335 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 336 bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 337 double max_urgent_latency_us; 338 double max_non_urgent_latency_us; 339 double avg_non_urgent_latency_us; 340 double avg_urgent_latency_us; 341 double df_response_time_us; 342 343 bool incorrect_imall_usage; 344 345 bool g6_temp_read_support; 346 347 struct dml2_core_internal_watermarks watermarks; 348 bool dcfclk_support; 349 bool qos_bandwidth_support; 350 }; 351 352 struct dml2_core_internal_mode_support { 353 // Physical info; only using for programming 354 unsigned int state_idx; // <brief min clk state table index for mode support call 355 unsigned int qos_param_index; // to access the uclk dependent qos_parameters table 356 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 357 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 358 359 // Calculated Clocks 360 double RequiredDISPCLK; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc. 361 double RequiredDPPCLK[DML2_MAX_PLANES]; 362 double RequiredDISPCLKPerSurface[DML2_MAX_PLANES]; 363 double RequiredDTBCLK[DML2_MAX_PLANES]; 364 365 double required_dscclk_freq_mhz[DML2_MAX_PLANES]; 366 367 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 368 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 369 double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 370 double GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes 371 double GlobalDTBCLK; /// <brief the Max DTBCLK freq out of all pipes 372 double uclk_freq_mhz; 373 double dram_bw_mbps; 374 double max_dram_bw_mbps; 375 double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps 376 377 double MaxFabricClock; /// <brief Basically just the clock freq at the min (or given) state 378 double MaxDCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 379 double max_dispclk_freq_mhz; 380 double max_dppclk_freq_mhz; 381 double max_dscclk_freq_mhz; 382 383 bool NoTimeForPrefetch[DML2_MAX_PLANES]; 384 bool NoTimeForDynamicMetadata[DML2_MAX_PLANES]; 385 386 // ---------------------------------- 387 // Mode Support Info and fail reason 388 // ---------------------------------- 389 struct dml2_core_internal_mode_support_info support; 390 391 // These are calculated before the ModeSupport and ModeProgram step 392 // They represent the bound for the return buffer sizing 393 unsigned int MaxTotalDETInKByte; 394 unsigned int NomDETInKByte; 395 unsigned int MinCompressedBufferSizeInKByte; 396 397 // Info obtained at the end of mode support calculations 398 // The reported info is at the "optimal" state and combine setting 399 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 400 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 401 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 402 unsigned int SwathHeightY[DML2_MAX_PLANES]; 403 unsigned int SwathHeightC[DML2_MAX_PLANES]; 404 unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe 405 unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe 406 407 // ---------------------------------- 408 // Intermediates/Informational 409 // ---------------------------------- 410 unsigned int TotImmediateFlipBytes; 411 bool DCCEnabledInAnySurface; 412 double WritebackRequiredDISPCLK; 413 double TimeCalc; 414 double TWait[DML2_MAX_PLANES]; 415 416 bool UnboundedRequestEnabled; 417 unsigned int compbuf_reserved_space_64b; 418 bool hw_debug5; 419 unsigned int CompressedBufferSizeInkByte; 420 double VRatioPreY[DML2_MAX_PLANES]; 421 double VRatioPreC[DML2_MAX_PLANES]; 422 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 423 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 424 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 425 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 426 unsigned int RequiredSlots[DML2_MAX_PLANES]; 427 unsigned int vm_bytes[DML2_MAX_PLANES]; 428 unsigned int DPTEBytesPerRow[DML2_MAX_PLANES]; 429 unsigned int PrefetchLinesY[DML2_MAX_PLANES]; 430 unsigned int PrefetchLinesC[DML2_MAX_PLANES]; 431 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 432 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 433 unsigned int PrefillY[DML2_MAX_PLANES]; 434 unsigned int PrefillC[DML2_MAX_PLANES]; 435 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 436 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 437 438 bool use_one_row_for_frame[DML2_MAX_PLANES]; 439 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 440 441 double dst_y_prefetch[DML2_MAX_PLANES]; 442 double LinesForVM[DML2_MAX_PLANES]; 443 double LinesForDPTERow[DML2_MAX_PLANES]; 444 unsigned int SwathWidthYSingleDPP[DML2_MAX_PLANES]; 445 unsigned int SwathWidthCSingleDPP[DML2_MAX_PLANES]; 446 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 447 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 448 double BytePerPixelInDETY[DML2_MAX_PLANES]; 449 double BytePerPixelInDETC[DML2_MAX_PLANES]; 450 451 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 452 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 453 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 454 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 455 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 456 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 457 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 458 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 459 460 bool surf_linear128_l[DML2_MAX_PLANES]; 461 bool surf_linear128_c[DML2_MAX_PLANES]; 462 463 double PSCL_FACTOR[DML2_MAX_PLANES]; 464 double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES]; 465 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 466 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 467 double Tno_bw[DML2_MAX_PLANES]; 468 double Tno_bw_flip[DML2_MAX_PLANES]; 469 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 470 double dst_y_per_row_flip[DML2_MAX_PLANES]; 471 double WritebackDelayTime[DML2_MAX_PLANES]; 472 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 473 unsigned int dpte_row_height[DML2_MAX_PLANES]; 474 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 475 double UrgLatency; 476 double TripToMemory; 477 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 478 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 479 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 480 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 481 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 482 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 483 double MaximumSwathWidthInLineBufferLuma; 484 double MaximumSwathWidthInLineBufferChroma; 485 double ExtraLatency; 486 double ExtraLatency_sr; 487 double ExtraLatencyPrefetch; 488 489 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 490 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 491 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 492 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 493 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe 494 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 495 496 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 497 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 498 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 499 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 500 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 501 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 502 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 503 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 504 unsigned int meta_req_width[DML2_MAX_PLANES]; 505 unsigned int meta_row_width[DML2_MAX_PLANES]; 506 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 507 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 508 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 509 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 510 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 511 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 512 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 513 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 514 unsigned int meta_req_height[DML2_MAX_PLANES]; 515 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 516 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 517 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 518 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 519 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 520 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 521 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 522 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 523 double TSetup[DML2_MAX_PLANES]; 524 double Tdmdl_vm_raw[DML2_MAX_PLANES]; 525 double Tdmdl_raw[DML2_MAX_PLANES]; 526 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 527 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 528 double MaxActiveFCLKChangeLatencySupported; 529 530 // Backend 531 bool RequiresDSC[DML2_MAX_PLANES]; 532 bool RequiresFEC[DML2_MAX_PLANES]; 533 double OutputBpp[DML2_MAX_PLANES]; 534 double DesiredOutputBpp[DML2_MAX_PLANES]; 535 double PixelClockBackEnd[DML2_MAX_PLANES]; 536 unsigned int DSCDelay[DML2_MAX_PLANES]; 537 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 538 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 539 bool TotalAvailablePipesSupportNoDSC; 540 bool TotalAvailablePipesSupportDSC; 541 unsigned int NumberOfDPPNoDSC; 542 unsigned int NumberOfDPPDSC; 543 enum dml2_odm_mode ODMModeNoDSC; 544 enum dml2_odm_mode ODMModeDSC; 545 double RequiredDISPCLKPerSurfaceNoDSC; 546 double RequiredDISPCLKPerSurfaceDSC; 547 unsigned int EstimatedNumberOfDSCSlices[DML2_MAX_PLANES]; 548 549 // Bandwidth Related Info 550 double BandwidthAvailableForImmediateFlip; 551 double vactive_sw_bw_l[DML2_MAX_PLANES]; // no dcc overhead, for the plane 552 double vactive_sw_bw_c[DML2_MAX_PLANES]; 553 double WriteBandwidth[DML2_MAX_PLANES][DML2_MAX_WRITEBACK]; 554 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 555 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 556 /* Max bandwidth calculated from prefetch schedule should be considered in addition to the pixel data bw to avoid ms/mp mismatches. 557 * 1. oto bw should also be considered when calculating peak urgent bw to avoid situations oto/equ mismatches between ms and mp 558 * 559 * 2. equ bandwidth needs to be considered for calculating peak urgent bw when equ schedule is used in mode support. 560 * Some slight difference in variables may cause the pixel data bandwidth to be higher 561 * even though overall equ prefetch bandwidths can be lower going from ms to mp 562 */ 563 double RequiredPrefetchBWMax[DML2_MAX_PLANES]; 564 double cursor_bw[DML2_MAX_PLANES]; 565 double prefetch_cursor_bw[DML2_MAX_PLANES]; 566 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 567 double final_flip_bw[DML2_MAX_PLANES]; 568 double meta_row_bw[DML2_MAX_PLANES]; 569 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 570 double dpte_row_bw[DML2_MAX_PLANES]; 571 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 572 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 573 double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 574 double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 575 576 // Something that should be feedback to caller 577 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 578 unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES]; 579 unsigned int NoOfDPP[DML2_MAX_PLANES]; 580 unsigned int NoOfOPP[DML2_MAX_PLANES]; 581 bool MPCCombine[DML2_MAX_PLANES]; 582 double dcfclk_deepsleep; 583 double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 584 bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES]; 585 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 586 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 587 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 588 bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES]; 589 bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES]; 590 unsigned int TotalNumberOfActiveDPP; 591 unsigned int TotalNumberOfActiveOPP; 592 unsigned int TotalNumberOfSingleDPPSurfaces; 593 unsigned int TotalNumberOfDCCActiveDPP; 594 unsigned int Total3dlutActive; 595 596 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 597 double VActiveLatencyHidingMargin[DML2_MAX_PLANES]; 598 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 599 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; 600 double pstate_vactive_det_fill_delay_us[dml2_pstate_type_count][DML2_MAX_PLANES]; 601 602 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 603 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 604 unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES]; 605 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 606 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 607 608 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 609 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 610 unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES]; 611 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 612 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 613 614 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 615 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 616 bool lc_comb_mcache[DML2_MAX_PLANES]; 617 618 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 619 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 620 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 621 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 622 623 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 624 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 625 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 626 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 627 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 628 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 629 630 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 631 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 632 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 633 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 634 635 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 636 637 double HostVMInefficiencyFactor; 638 double HostVMInefficiencyFactorPrefetch; 639 640 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 641 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 642 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 643 double tdlut_opt_time[DML2_MAX_PLANES]; 644 double tdlut_drain_time[DML2_MAX_PLANES]; 645 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 646 647 double Tvm_trips_flip[DML2_MAX_PLANES]; 648 double Tr0_trips_flip[DML2_MAX_PLANES]; 649 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 650 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 651 652 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 653 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 654 655 enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; 656 }; 657 658 /// @brief A mega structure that houses various info for model programming step. 659 struct dml2_core_internal_mode_program { 660 unsigned int qos_param_index; // to access the uclk dependent dpm table 661 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 662 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 663 //double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 664 double dram_bw_mbps; 665 double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps 666 double uclk_freq_mhz; 667 unsigned int NoOfDPP[DML2_MAX_PLANES]; 668 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 669 670 //------------- 671 // Intermediate/Informational 672 //------------- 673 double UrgentLatency; 674 double TripToMemory; 675 double MetaTripToMemory; 676 unsigned int VInitPreFillY[DML2_MAX_PLANES]; 677 unsigned int VInitPreFillC[DML2_MAX_PLANES]; 678 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; 679 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; 680 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 681 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 682 683 double BytePerPixelInDETY[DML2_MAX_PLANES]; 684 double BytePerPixelInDETC[DML2_MAX_PLANES]; 685 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 686 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 687 unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe 688 unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe 689 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 690 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 691 unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES]; 692 unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES]; 693 double vactive_sw_bw_l[DML2_MAX_PLANES]; 694 double vactive_sw_bw_c[DML2_MAX_PLANES]; 695 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 696 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 697 698 unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES]; 699 unsigned int vm_bytes[DML2_MAX_PLANES]; 700 unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES]; 701 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 702 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 703 unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES]; 704 double PSCL_THROUGHPUT[DML2_MAX_PLANES]; 705 double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES]; 706 unsigned int DSCDelay[DML2_MAX_PLANES]; 707 double DPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 708 709 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 710 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 711 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 712 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 713 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 714 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 715 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 716 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 717 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 718 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 719 720 bool surf_linear128_l[DML2_MAX_PLANES]; 721 bool surf_linear128_c[DML2_MAX_PLANES]; 722 723 unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES]; 724 double VRatioPrefetchY[DML2_MAX_PLANES]; 725 double VRatioPrefetchC[DML2_MAX_PLANES]; 726 double Tno_bw[DML2_MAX_PLANES]; 727 double Tno_bw_flip[DML2_MAX_PLANES]; 728 double final_flip_bw[DML2_MAX_PLANES]; 729 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 730 double cursor_bw[DML2_MAX_PLANES]; 731 double prefetch_cursor_bw[DML2_MAX_PLANES]; 732 double WritebackDelay[DML2_MAX_PLANES]; 733 unsigned int dpte_row_height[DML2_MAX_PLANES]; 734 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 735 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 736 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 737 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 738 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 739 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 740 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 741 742 double dpte_row_bw[DML2_MAX_PLANES]; 743 double time_per_tdlut_group[DML2_MAX_PLANES]; 744 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 745 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 746 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 747 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 748 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 749 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 750 751 double MaximumSwathWidthInLineBufferLuma; 752 double MaximumSwathWidthInLineBufferChroma; 753 754 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 755 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 756 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 757 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 758 759 double meta_row_bw[DML2_MAX_PLANES]; 760 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 761 unsigned int meta_req_width[DML2_MAX_PLANES]; 762 unsigned int meta_req_height[DML2_MAX_PLANES]; 763 unsigned int meta_row_width[DML2_MAX_PLANES]; 764 unsigned int meta_row_height[DML2_MAX_PLANES]; 765 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 766 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 767 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 768 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 769 770 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 771 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 772 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 773 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 774 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 775 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 776 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 777 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 778 779 double TWait[DML2_MAX_PLANES]; 780 double Tdmdl_vm_raw[DML2_MAX_PLANES]; 781 double Tdmdl_vm[DML2_MAX_PLANES]; 782 double Tdmdl_raw[DML2_MAX_PLANES]; 783 double Tdmdl[DML2_MAX_PLANES]; 784 double TSetup[DML2_MAX_PLANES]; 785 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 786 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 787 788 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 789 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 790 791 bool UnboundedRequestEnabled; 792 unsigned int CompressedBufferSizeInkByte; 793 unsigned int compbuf_reserved_space_64b; 794 bool hw_debug5; 795 unsigned int dcfclk_deep_sleep_hysteresis; 796 unsigned int min_return_latency_in_dcfclk; 797 798 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 799 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 800 double ExtraLatency; 801 double ExtraLatency_sr; 802 double ExtraLatencyPrefetch; 803 bool PrefetchAndImmediateFlipSupported; 804 double TotalDataReadBandwidth; 805 double BandwidthAvailableForImmediateFlip; 806 bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES]; 807 808 bool use_one_row_for_frame[DML2_MAX_PLANES]; 809 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 810 811 double TCalc; 812 unsigned int TotImmediateFlipBytes; 813 814 unsigned int MaxTotalDETInKByte; 815 unsigned int NomDETInKByte; 816 unsigned int MinCompressedBufferSizeInKByte; 817 double PixelClockBackEnd[DML2_MAX_PLANES]; 818 double OutputBpp[DML2_MAX_PLANES]; 819 bool dsc_enable[DML2_MAX_PLANES]; 820 unsigned int num_dsc_slices[DML2_MAX_PLANES]; 821 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 822 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 823 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 824 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 825 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 826 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 827 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 828 double HostVMInefficiencyFactor; 829 double HostVMInefficiencyFactorPrefetch; 830 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 831 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 832 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 833 double tdlut_opt_time[DML2_MAX_PLANES]; 834 double tdlut_drain_time[DML2_MAX_PLANES]; 835 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 836 double Tvm_trips_flip[DML2_MAX_PLANES]; 837 double Tr0_trips_flip[DML2_MAX_PLANES]; 838 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 839 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 840 bool immediate_flip_required; // any pipes need immediate flip 841 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 842 double TotalWRBandwidth; 843 double max_urgent_latency_us; 844 double df_response_time_us; 845 846 enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; 847 // ------------------- 848 // Output 849 // ------------------- 850 unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe 851 unsigned int num_active_pipes; 852 853 bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result 854 855 // Support 856 bool UrgVactiveBandwidthSupport; 857 bool PrefetchScheduleSupported; 858 bool UrgentBandwidthSupport; 859 bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported 860 bool ImmediateFlipSupported; 861 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 862 bool dcfclk_support; 863 864 // Clock 865 double Dcfclk; 866 double Dispclk; // <brief dispclk being used in mode programming 867 double Dppclk[DML2_MAX_PLANES]; // <brief dppclk being used in mode programming 868 double GlobalDPPCLK; 869 870 double DSCCLK[DML2_MAX_PLANES]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now 871 double DCFCLKDeepSleep; 872 873 // ARB reg 874 bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 875 struct dml2_core_internal_watermarks Watermark; 876 877 // DCC compression control 878 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 879 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 880 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 881 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 882 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 883 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 884 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 885 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 886 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 887 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 888 889 // Stutter Efficiency 890 double StutterEfficiency; 891 double StutterEfficiencyNotIncludingVBlank; 892 unsigned int NumberOfStutterBurstsPerFrame; 893 double Z8StutterEfficiency; 894 unsigned int Z8NumberOfStutterBurstsPerFrame; 895 double Z8StutterEfficiencyNotIncludingVBlank; 896 double LowPowerStutterEfficiency; 897 double LowPowerStutterEfficiencyNotIncludingVBlank; 898 unsigned int LowPowerNumberOfStutterBurstsPerFrame; 899 double StutterPeriod; 900 double Z8StutterEfficiencyBestCase; 901 unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; 902 double Z8StutterEfficiencyNotIncludingVBlankBestCase; 903 double StutterPeriodBestCase; 904 905 // DLG TTU reg 906 double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES]; 907 bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES]; 908 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 909 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 910 double dst_y_prefetch[DML2_MAX_PLANES]; 911 double dst_y_per_vm_vblank[DML2_MAX_PLANES]; 912 double dst_y_per_row_vblank[DML2_MAX_PLANES]; 913 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 914 double dst_y_per_row_flip[DML2_MAX_PLANES]; 915 double MinTTUVBlank[DML2_MAX_PLANES]; 916 double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES]; 917 double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES]; 918 double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 919 double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 920 double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES]; 921 double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES]; 922 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 923 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 924 unsigned int CursorDstXOffset[DML2_MAX_PLANES]; 925 unsigned int CursorDstYOffset[DML2_MAX_PLANES]; 926 unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES]; 927 928 double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES]; 929 double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES]; 930 double time_per_pte_group_nom_luma[DML2_MAX_PLANES]; 931 double time_per_pte_group_nom_chroma[DML2_MAX_PLANES]; 932 double time_per_pte_group_vblank_luma[DML2_MAX_PLANES]; 933 double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES]; 934 double time_per_pte_group_flip_luma[DML2_MAX_PLANES]; 935 double time_per_pte_group_flip_chroma[DML2_MAX_PLANES]; 936 double TimePerVMGroupVBlank[DML2_MAX_PLANES]; 937 double TimePerVMGroupFlip[DML2_MAX_PLANES]; 938 double TimePerVMRequestVBlank[DML2_MAX_PLANES]; 939 double TimePerVMRequestFlip[DML2_MAX_PLANES]; 940 941 double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES]; 942 double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES]; 943 double TimePerMetaChunkNominal[DML2_MAX_PLANES]; 944 double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES]; 945 double TimePerMetaChunkVBlank[DML2_MAX_PLANES]; 946 double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES]; 947 double TimePerMetaChunkFlip[DML2_MAX_PLANES]; 948 double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES]; 949 950 double FractionOfUrgentBandwidth; 951 double FractionOfUrgentBandwidthImmediateFlip; 952 double FractionOfUrgentBandwidthMALL; 953 954 // RQ registers 955 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 956 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 957 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 958 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 959 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 960 961 // OTG 962 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 963 unsigned int VStartup[DML2_MAX_PLANES]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank)) 964 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 965 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 966 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 967 unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES]; 968 969 // Latency and Support 970 double MaxActiveFCLKChangeLatencySupported; 971 bool USRRetrainingSupport; 972 bool g6_temp_read_support; 973 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 974 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 975 enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; 976 bool global_dram_clock_change_supported; 977 bool global_fclk_change_supported; 978 bool global_temp_read_or_ppt_supported; 979 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 980 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 981 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; 982 983 // buffer sizing 984 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 985 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 986 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 987 unsigned int SwathHeightY[DML2_MAX_PLANES]; 988 unsigned int SwathHeightC[DML2_MAX_PLANES]; 989 990 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 991 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 992 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 993 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 994 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 995 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 996 997 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 998 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 999 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 1000 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1001 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc. 1002 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 1003 1004 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; 1005 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 1006 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; 1007 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 1008 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; 1009 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 1010 1011 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 1012 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 1013 unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES]; 1014 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 1015 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 1016 1017 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 1018 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 1019 unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES]; 1020 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 1021 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 1022 1023 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 1024 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 1025 bool lc_comb_mcache[DML2_MAX_PLANES]; 1026 1027 double impacted_prefetch_margin_us[DML2_MAX_PLANES]; 1028 }; 1029 1030 struct dml2_core_internal_SOCParametersList { 1031 double UrgentLatency; 1032 double ExtraLatency_sr; 1033 double ExtraLatency; 1034 double WritebackLatency; 1035 double DRAMClockChangeLatency; 1036 double FCLKChangeLatency; 1037 double SRExitTime; 1038 double SREnterPlusExitTime; 1039 double SRExitTimeLowPower; 1040 double SREnterPlusExitTimeLowPower; 1041 double SRExitZ8Time; 1042 double SREnterPlusExitZ8Time; 1043 double USRRetrainingLatency; 1044 double SMNLatency; 1045 double g6_temp_read_blackout_us; 1046 double temp_read_or_ppt_blackout_us; 1047 double max_urgent_latency_us; 1048 double df_response_time_us; 1049 enum dml2_qos_param_type qos_type; 1050 }; 1051 1052 struct dml2_core_calcs_mode_support_locals { 1053 double PixelClockBackEnd[DML2_MAX_PLANES]; 1054 double OutputBpp[DML2_MAX_PLANES]; 1055 1056 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 1057 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 1058 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1059 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1060 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1061 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1062 1063 bool dummy_boolean[3]; 1064 unsigned int dummy_integer[3]; 1065 unsigned int dummy_integer_array[36][DML2_MAX_PLANES]; 1066 enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES]; 1067 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1068 double dummy_single[3]; 1069 double dummy_single_array[DML2_MAX_PLANES]; 1070 double dummy_double_array[3][DML2_MAX_PLANES]; 1071 enum dml2_pstate_method dummy_pstate_method_array[DML2_MAX_PLANES]; 1072 struct dml2_core_internal_watermarks dummy_watermark; 1073 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1074 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1075 1076 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 1077 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 1078 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 1079 struct dml2_core_internal_SOCParametersList mSOCParameters; 1080 struct dml2_core_internal_DmlPipe myPipe; 1081 struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES]; 1082 unsigned int TotalNumberOfActiveWriteback; 1083 unsigned int MaximumSwathWidthSupportLuma; 1084 unsigned int MaximumSwathWidthSupportChroma; 1085 bool MPCCombineMethodAsNeededForPStateChangeAndVoltage; 1086 bool MPCCombineMethodAsPossible; 1087 bool TotalAvailablePipesSupportNoDSC; 1088 unsigned int NumberOfDPPNoDSC; 1089 enum dml2_odm_mode ODMModeNoDSC; 1090 double RequiredDISPCLKPerSurfaceNoDSC; 1091 bool TotalAvailablePipesSupportDSC; 1092 unsigned int NumberOfDPPDSC; 1093 enum dml2_odm_mode ODMModeDSC; 1094 double RequiredDISPCLKPerSurfaceDSC; 1095 double BWOfNonCombinedSurfaceOfMaximumBandwidth; 1096 unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth; 1097 unsigned int TotalNumberOfActiveOTG; 1098 unsigned int TotalNumberOfActiveHDMIFRL; 1099 unsigned int TotalNumberOfActiveDP2p0; 1100 unsigned int TotalNumberOfActiveDP2p0Outputs; 1101 unsigned int TotalSlots; 1102 unsigned int DSCFormatFactor; 1103 unsigned int TotalDSCUnitsRequired; 1104 unsigned int ReorderingBytes; 1105 bool ImmediateFlipRequired; 1106 bool FullFrameMALLPStateMethod; 1107 bool SubViewportMALLPStateMethod; 1108 bool PhantomPipeMALLPStateMethod; 1109 bool SubViewportMALLRefreshGreaterThan120Hz; 1110 1111 double HostVMInefficiencyFactor; 1112 double HostVMInefficiencyFactorPrefetch; 1113 unsigned int MaxVStartup; 1114 double PixelClockBackEndFactor; 1115 unsigned int NumDSCUnitRequired; 1116 1117 double Tvm_trips[DML2_MAX_PLANES]; 1118 double Tr0_trips[DML2_MAX_PLANES]; 1119 double Tvm_trips_flip[DML2_MAX_PLANES]; 1120 double Tr0_trips_flip[DML2_MAX_PLANES]; 1121 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1122 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1123 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1124 1125 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1126 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1127 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1128 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1129 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1130 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1131 1132 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1133 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1134 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1135 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1136 double tdlut_opt_time[DML2_MAX_PLANES]; 1137 double tdlut_drain_time[DML2_MAX_PLANES]; 1138 unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES]; 1139 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1140 1141 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1142 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1143 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1144 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1145 bool stream_visited[DML2_MAX_PLANES]; 1146 1147 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 1148 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 1149 1150 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1151 double Tpre_rounded[DML2_MAX_PLANES]; 1152 double Tpre_oto[DML2_MAX_PLANES]; 1153 bool recalc_prefetch_schedule; 1154 bool recalc_prefetch_done; 1155 double impacted_dst_y_pre[DML2_MAX_PLANES]; 1156 double line_times[DML2_MAX_PLANES]; 1157 enum dml2_source_format_class pixel_format[DML2_MAX_PLANES]; 1158 unsigned int lb_source_lines_l[DML2_MAX_PLANES]; 1159 unsigned int lb_source_lines_c[DML2_MAX_PLANES]; 1160 double prefetch_swath_time_us[DML2_MAX_PLANES]; 1161 }; 1162 1163 struct dml2_core_calcs_mode_programming_locals { 1164 double PixelClockBackEnd[DML2_MAX_PLANES]; 1165 double OutputBpp[DML2_MAX_PLANES]; 1166 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 1167 unsigned int MaxTotalDETInKByte; 1168 unsigned int NomDETInKByte; 1169 unsigned int MinCompressedBufferSizeInKByte; 1170 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 1171 1172 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1173 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1174 double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1175 unsigned int dummy_integer_array[4][DML2_MAX_PLANES]; 1176 enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES]; 1177 double dummy_single_array[2][DML2_MAX_PLANES]; 1178 unsigned int dummy_long_array[8][DML2_MAX_PLANES]; 1179 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1180 bool dummy_boolean[2]; 1181 double dummy_single[2]; 1182 struct dml2_core_internal_watermarks dummy_watermark; 1183 1184 unsigned int DSCFormatFactor; 1185 struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES]; 1186 unsigned int ReorderingBytes; 1187 double HostVMInefficiencyFactor; 1188 double HostVMInefficiencyFactorPrefetch; 1189 unsigned int TotalDCCActiveDPP; 1190 unsigned int TotalActiveDPP; 1191 unsigned int Total3dlutActive; 1192 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 1193 bool immediate_flip_required; // any pipes need immediate flip 1194 bool DestinationLineTimesForPrefetchLessThan2; 1195 bool VRatioPrefetchMoreThanMax; 1196 double MaxTotalRDBandwidthNotIncludingMALLPrefetch; 1197 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1198 double Tvstartup_margin; 1199 double dlg_vblank_start; 1200 double LSetup; 1201 double blank_lines_remaining; 1202 double WRBandwidth; 1203 struct dml2_core_internal_DmlPipe myPipe; 1204 double PixelClockBackEndFactor; 1205 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1206 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1207 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1208 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1209 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1210 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1211 1212 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1213 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1214 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1215 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1216 1217 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1218 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1219 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1220 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1221 double tdlut_opt_time[DML2_MAX_PLANES]; 1222 double tdlut_drain_time[DML2_MAX_PLANES]; 1223 unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES]; 1224 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1225 1226 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1227 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1228 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1229 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1230 1231 double Tvm_trips[DML2_MAX_PLANES]; 1232 double Tr0_trips[DML2_MAX_PLANES]; 1233 double Tvm_trips_flip[DML2_MAX_PLANES]; 1234 double Tr0_trips_flip[DML2_MAX_PLANES]; 1235 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1236 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1237 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1238 1239 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 1240 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 1241 1242 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1243 double Tpre_rounded[DML2_MAX_PLANES]; 1244 double Tpre_oto[DML2_MAX_PLANES]; 1245 bool recalc_prefetch_schedule; 1246 double impacted_dst_y_pre[DML2_MAX_PLANES]; 1247 double line_times[DML2_MAX_PLANES]; 1248 enum dml2_source_format_class pixel_format[DML2_MAX_PLANES]; 1249 unsigned int lb_source_lines_l[DML2_MAX_PLANES]; 1250 unsigned int lb_source_lines_c[DML2_MAX_PLANES]; 1251 unsigned int num_dsc_slices[DML2_MAX_PLANES]; 1252 bool dsc_enable[DML2_MAX_PLANES]; 1253 }; 1254 1255 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals { 1256 double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES]; 1257 double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES]; 1258 double USRRetrainingLatencyMargin[DML2_MAX_PLANES]; 1259 double g6_temp_read_latency_margin[DML2_MAX_PLANES]; 1260 double temp_read_or_ppt_latency_margin[DML2_MAX_PLANES]; 1261 1262 double EffectiveLBLatencyHidingY; 1263 double EffectiveLBLatencyHidingC; 1264 double LinesInDETY[DML2_MAX_PLANES]; 1265 double LinesInDETC[DML2_MAX_PLANES]; 1266 unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES]; 1267 unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES]; 1268 double FullDETBufferingTimeY; 1269 double FullDETBufferingTimeC; 1270 double WritebackDRAMClockChangeLatencyMargin; 1271 double WritebackFCLKChangeLatencyMargin; 1272 double WritebackLatencyHiding; 1273 1274 unsigned int TotalActiveWriteback; 1275 unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES]; 1276 unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES]; 1277 double TotalPixelBW; 1278 double EffectiveDETBufferSizeY; 1279 double ActiveClockChangeLatencyHidingY; 1280 double ActiveClockChangeLatencyHidingC; 1281 double ActiveClockChangeLatencyHiding; 1282 unsigned int dst_y_pstate; 1283 unsigned int src_y_pstate_l; 1284 unsigned int src_y_pstate_c; 1285 unsigned int src_y_ahead_l; 1286 unsigned int src_y_ahead_c; 1287 unsigned int sub_vp_lines_l; 1288 unsigned int sub_vp_lines_c; 1289 1290 }; 1291 1292 struct dml2_core_calcs_CalculateVMRowAndSwath_locals { 1293 unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES]; 1294 unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES]; 1295 unsigned int vm_bytes_l; 1296 unsigned int vm_bytes_c; 1297 unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES]; 1298 unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES]; 1299 unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES]; 1300 unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES]; 1301 unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES]; 1302 unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES]; 1303 unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1304 unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES]; 1305 unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1306 unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES]; 1307 bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES]; 1308 unsigned int HostVMDynamicLevels; 1309 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1310 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1311 }; 1312 1313 struct dml2_core_calcs_CalculateVMRowAndSwath_params { 1314 const struct dml2_display_cfg *display_cfg; 1315 unsigned int NumberOfActiveSurfaces; 1316 struct dml2_core_internal_DmlPipe *myPipe; 1317 unsigned int *SurfaceSizeInMALL; 1318 unsigned int PTEBufferSizeInRequestsLuma; 1319 unsigned int PTEBufferSizeInRequestsChroma; 1320 unsigned int MALLAllocatedForDCN; 1321 unsigned int *SwathWidthY; 1322 unsigned int *SwathWidthC; 1323 unsigned int HostVMMinPageSize; 1324 unsigned int DCCMetaBufferSizeBytes; 1325 bool mrq_present; 1326 enum dml2_pstate_method *uclk_pstate_switch_modes; 1327 1328 // Output 1329 bool *PTEBufferSizeNotExceeded; 1330 bool *DCCMetaBufferSizeNotExceeded; 1331 1332 unsigned int *dpte_row_width_luma_ub; 1333 unsigned int *dpte_row_width_chroma_ub; 1334 unsigned int *dpte_row_height_luma; 1335 unsigned int *dpte_row_height_chroma; 1336 unsigned int *dpte_row_height_linear_luma; // VBA_DELTA 1337 unsigned int *dpte_row_height_linear_chroma; // VBA_DELTA 1338 1339 unsigned int *vm_group_bytes; 1340 unsigned int *dpte_group_bytes; 1341 unsigned int *PixelPTEReqWidthY; 1342 unsigned int *PixelPTEReqHeightY; 1343 unsigned int *PTERequestSizeY; 1344 unsigned int *vmpg_width_y; 1345 unsigned int *vmpg_height_y; 1346 1347 unsigned int *PixelPTEReqWidthC; 1348 unsigned int *PixelPTEReqHeightC; 1349 unsigned int *PTERequestSizeC; 1350 unsigned int *vmpg_width_c; 1351 unsigned int *vmpg_height_c; 1352 1353 unsigned int *dpde0_bytes_per_frame_ub_l; 1354 unsigned int *dpde0_bytes_per_frame_ub_c; 1355 1356 unsigned int *PrefetchSourceLinesY; 1357 unsigned int *PrefetchSourceLinesC; 1358 unsigned int *VInitPreFillY; 1359 unsigned int *VInitPreFillC; 1360 unsigned int *MaxNumSwathY; 1361 unsigned int *MaxNumSwathC; 1362 double *dpte_row_bw; 1363 unsigned int *PixelPTEBytesPerRow; 1364 unsigned int *dpte_row_bytes_per_row_l; 1365 unsigned int *dpte_row_bytes_per_row_c; 1366 unsigned int *vm_bytes; 1367 bool *use_one_row_for_frame; 1368 bool *use_one_row_for_frame_flip; 1369 bool *is_using_mall_for_ss; 1370 bool *PTE_BUFFER_MODE; 1371 unsigned int *BIGK_FRAGMENT_SIZE; 1372 1373 // MRQ 1374 unsigned int *meta_req_width_luma; 1375 unsigned int *meta_req_height_luma; 1376 unsigned int *meta_row_width_luma; 1377 unsigned int *meta_row_height_luma; 1378 unsigned int *meta_pte_bytes_per_frame_ub_l; 1379 1380 unsigned int *meta_req_width_chroma; 1381 unsigned int *meta_req_height_chroma; 1382 unsigned int *meta_row_width_chroma; 1383 unsigned int *meta_row_height_chroma; 1384 unsigned int *meta_pte_bytes_per_frame_ub_c; 1385 double *meta_row_bw; 1386 unsigned int *meta_row_bytes; 1387 unsigned int *meta_row_bytes_per_row_ub_l; 1388 unsigned int *meta_row_bytes_per_row_ub_c; 1389 }; 1390 1391 struct dml2_core_calcs_CalculatePrefetchSchedule_locals { 1392 bool NoTimeToPrefetch; 1393 unsigned int DPPCycles; 1394 unsigned int DISPCLKCycles; 1395 double DSTTotalPixelsAfterScaler; 1396 double LineTime; 1397 double dst_y_prefetch_equ; 1398 double prefetch_bw_oto; 1399 double per_pipe_vactive_sw_bw; 1400 double Tvm_oto; 1401 double Tr0_oto; 1402 double Tvm_oto_lines; 1403 double Tr0_oto_lines; 1404 double dst_y_prefetch_oto; 1405 double TimeForFetchingVM; 1406 double TimeForFetchingRowInVBlank; 1407 double LinesToRequestPrefetchPixelData; 1408 unsigned int HostVMDynamicLevelsTrips; 1409 double trip_to_mem; 1410 double Tvm_trips_rounded; 1411 double Tr0_trips_rounded; 1412 double max_Tsw; 1413 double Lsw_oto; 1414 double prefetch_bw_equ; 1415 double Tvm_equ; 1416 double Tr0_equ; 1417 double Tdmbf; 1418 double Tdmec; 1419 double Tdmsks; 1420 double total_row_bytes; 1421 double prefetch_bw_pr; 1422 double bytes_pp; 1423 double dep_bytes; 1424 double min_Lsw_oto; 1425 double min_Lsw_equ; 1426 double Tsw_est1; 1427 double Tsw_est2; 1428 double Tsw_est3; 1429 double prefetch_bw1; 1430 double prefetch_bw2; 1431 double prefetch_bw3; 1432 double prefetch_bw4; 1433 double dst_y_prefetch_equ_impacted; 1434 1435 double TWait_p; 1436 unsigned int cursor_prefetch_bytes; 1437 }; 1438 1439 struct dml2_core_shared_calculate_det_buffer_size_params { 1440 const struct dml2_display_cfg *display_cfg; 1441 bool ForceSingleDPP; 1442 unsigned int NumberOfActiveSurfaces; 1443 bool UnboundedRequestEnabled; 1444 unsigned int nomDETInKByte; 1445 unsigned int MaxTotalDETInKByte; 1446 unsigned int ConfigReturnBufferSizeInKByte; 1447 unsigned int MinCompressedBufferSizeInKByte; 1448 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1449 unsigned int CompressedBufferSegmentSizeInkByte; 1450 double *ReadBandwidthLuma; 1451 double *ReadBandwidthChroma; 1452 unsigned int *full_swath_bytes_l; 1453 unsigned int *full_swath_bytes_c; 1454 unsigned int *swath_time_value_us; 1455 unsigned int *DPPPerSurface; 1456 bool TryToAllocateForWriteLatency; 1457 unsigned int bestEffortMinActiveLatencyHidingUs; 1458 1459 // Output 1460 unsigned int *DETBufferSizeInKByte; 1461 unsigned int *CompressedBufferSizeInkByte; 1462 }; 1463 1464 struct dml2_core_shared_calculate_vm_and_row_bytes_params { 1465 bool ViewportStationary; 1466 bool DCCEnable; 1467 unsigned int NumberOfDPPs; 1468 unsigned int BlockHeight256Bytes; 1469 unsigned int BlockWidth256Bytes; 1470 enum dml2_source_format_class SourcePixelFormat; 1471 unsigned int SurfaceTiling; 1472 unsigned int BytePerPixel; 1473 enum dml2_rotation_angle RotationAngle; 1474 unsigned int SwathWidth; // per pipe 1475 unsigned int ViewportHeight; 1476 unsigned int ViewportXStart; 1477 unsigned int ViewportYStart; 1478 bool GPUVMEnable; 1479 unsigned int GPUVMMaxPageTableLevels; 1480 unsigned int GPUVMMinPageSizeKBytes; 1481 unsigned int PTEBufferSizeInRequests; 1482 unsigned int Pitch; 1483 unsigned int MacroTileWidth; 1484 unsigned int MacroTileHeight; 1485 bool is_phantom; 1486 unsigned int DCCMetaPitch; 1487 bool mrq_present; 1488 1489 // Output 1490 unsigned int *PixelPTEBytesPerRow; // for bandwidth calculation 1491 unsigned int *PixelPTEBytesPerRowStorage; // for PTE buffer size check 1492 unsigned int *dpte_row_width_ub; 1493 unsigned int *dpte_row_height; 1494 unsigned int *dpte_row_height_linear; 1495 unsigned int *PixelPTEBytesPerRow_one_row_per_frame; 1496 unsigned int *dpte_row_width_ub_one_row_per_frame; 1497 unsigned int *dpte_row_height_one_row_per_frame; 1498 unsigned int *vmpg_width; 1499 unsigned int *vmpg_height; 1500 unsigned int *PixelPTEReqWidth; 1501 unsigned int *PixelPTEReqHeight; 1502 unsigned int *PTERequestSize; 1503 unsigned int *dpde0_bytes_per_frame_ub; 1504 1505 unsigned int *meta_row_bytes; 1506 unsigned int *MetaRequestWidth; 1507 unsigned int *MetaRequestHeight; 1508 unsigned int *meta_row_width; 1509 unsigned int *meta_row_height; 1510 unsigned int *meta_pte_bytes_per_frame_ub; 1511 }; 1512 1513 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals { 1514 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES]; 1515 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES]; 1516 unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES]; 1517 unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES]; 1518 unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES]; 1519 unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES]; 1520 unsigned int SwathTimeValueUs[DML2_MAX_PLANES]; 1521 1522 struct dml2_core_shared_calculate_det_buffer_size_params calculate_det_buffer_size_params; 1523 }; 1524 1525 struct dml2_core_shared_TruncToValidBPP_locals { 1526 struct lib_frl_cap_check_params hdmifrlparams; 1527 struct lib_frl_cap_check_intermediates hdmifrlinter; 1528 }; 1529 1530 struct dml2_core_shared_CalculateDETBufferSize_locals { 1531 unsigned int DETBufferSizePoolInKByte; 1532 unsigned int NextDETBufferPieceInKByte; 1533 unsigned int NextSurfaceToAssignDETPiece; 1534 double TotalBandwidth; 1535 double BandwidthOfSurfacesNotAssignedDETPiece; 1536 unsigned int max_minDET; 1537 unsigned int minDET; 1538 unsigned int minDET_pipe; 1539 unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES]; 1540 unsigned int TotalPixelRate; 1541 unsigned int DETBudgetPerStream[DML2_MAX_PLANES]; 1542 unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES]; 1543 unsigned int IdealDETBudget, DeltaDETBudget; 1544 unsigned int ResidualDETAfterRounding; 1545 }; 1546 1547 struct dml2_core_shared_get_urgent_bandwidth_required_locals { 1548 double required_bandwidth_mbps; 1549 double required_bandwidth_mbps_this_surface; 1550 double adj_factor_p0; 1551 double adj_factor_p1; 1552 double adj_factor_cur; 1553 double adj_factor_p0_pre; 1554 double adj_factor_p1_pre; 1555 double adj_factor_cur_pre; 1556 double per_plane_flip_bw[DML2_MAX_PLANES]; 1557 double mall_svp_prefetch_factor; 1558 double tmp_nom_adj_factor_p0; 1559 double tmp_nom_adj_factor_p1; 1560 double tmp_pref_adj_factor_p0; 1561 double tmp_pref_adj_factor_p1; 1562 double vm_row_bw; 1563 double flip_and_active_bw; 1564 double flip_and_prefetch_bw; 1565 double flip_and_prefetch_bw_max; 1566 double active_and_excess_bw; 1567 }; 1568 1569 struct dml2_core_shared_calculate_peak_bandwidth_required_locals { 1570 double unity_array[DML2_MAX_PLANES]; 1571 double zero_array[DML2_MAX_PLANES]; 1572 double surface_dummy_bw[DML2_MAX_PLANES]; 1573 }; 1574 1575 struct dml2_core_shared_CalculateFlipSchedule_locals { 1576 double min_row_time; 1577 double Tvm_flip; 1578 double Tr0_flip; 1579 double ImmediateFlipBW; 1580 double dpte_row_bytes; 1581 double min_row_height; 1582 double min_row_height_chroma; 1583 double max_flip_time; 1584 double lb_flip_bw; 1585 double hvm_scaled_vm_bytes; 1586 double num_rows; 1587 double hvm_scaled_row_bytes; 1588 double hvm_scaled_vm_row_bytes; 1589 bool dual_plane; 1590 }; 1591 1592 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals { 1593 unsigned int plane_idx; 1594 unsigned int stream_idx; 1595 enum dml2_source_format_class source_format; 1596 const struct dml2_timing_cfg *timing; 1597 bool dual_plane; 1598 enum dml2_odm_mode odm_mode; 1599 1600 unsigned int htotal; 1601 unsigned int hactive; 1602 unsigned int hblank_end; 1603 unsigned int vblank_end; 1604 bool interlaced; 1605 double pclk_freq_in_mhz; 1606 double refclk_freq_in_mhz; 1607 double ref_freq_to_pix_freq; 1608 1609 unsigned int num_active_pipes; 1610 unsigned int first_pipe_idx_in_plane; 1611 unsigned int pipe_idx_in_combine; 1612 unsigned int odm_combine_factor; 1613 1614 double min_ttu_vblank; 1615 unsigned int min_dst_y_next_start; 1616 1617 unsigned int vready_after_vcount0; 1618 1619 unsigned int dst_x_after_scaler; 1620 unsigned int dst_y_after_scaler; 1621 1622 double dst_y_prefetch; 1623 double dst_y_per_vm_vblank; 1624 double dst_y_per_row_vblank; 1625 double dst_y_per_vm_flip; 1626 double dst_y_per_row_flip; 1627 1628 double max_dst_y_per_vm_vblank; 1629 double max_dst_y_per_row_vblank; 1630 1631 double vratio_pre_l; 1632 double vratio_pre_c; 1633 1634 double refcyc_per_line_delivery_pre_l; 1635 double refcyc_per_line_delivery_l; 1636 1637 double refcyc_per_line_delivery_pre_c; 1638 double refcyc_per_line_delivery_c; 1639 1640 double refcyc_per_req_delivery_pre_l; 1641 double refcyc_per_req_delivery_l; 1642 1643 double refcyc_per_req_delivery_pre_c; 1644 double refcyc_per_req_delivery_c; 1645 1646 double dst_y_per_pte_row_nom_l; 1647 double dst_y_per_pte_row_nom_c; 1648 double refcyc_per_pte_group_nom_l; 1649 double refcyc_per_pte_group_nom_c; 1650 double refcyc_per_pte_group_vblank_l; 1651 double refcyc_per_pte_group_vblank_c; 1652 double refcyc_per_pte_group_flip_l; 1653 double refcyc_per_pte_group_flip_c; 1654 double refcyc_per_tdlut_group; 1655 1656 double dst_y_per_meta_row_nom_l; 1657 double dst_y_per_meta_row_nom_c; 1658 double refcyc_per_meta_chunk_nom_l; 1659 double refcyc_per_meta_chunk_nom_c; 1660 double refcyc_per_meta_chunk_vblank_l; 1661 double refcyc_per_meta_chunk_vblank_c; 1662 double refcyc_per_meta_chunk_flip_l; 1663 double refcyc_per_meta_chunk_flip_c; 1664 }; 1665 1666 struct dml2_core_shared_CalculateMetaAndPTETimes_params { 1667 struct dml2_core_internal_scratch *scratch; 1668 const struct dml2_display_cfg *display_cfg; 1669 unsigned int NumberOfActiveSurfaces; 1670 bool *use_one_row_for_frame; 1671 double *dst_y_per_row_vblank; 1672 double *dst_y_per_row_flip; 1673 unsigned int *BytePerPixelY; 1674 unsigned int *BytePerPixelC; 1675 unsigned int *dpte_row_height; 1676 unsigned int *dpte_row_height_chroma; 1677 unsigned int *dpte_group_bytes; 1678 unsigned int *PTERequestSizeY; 1679 unsigned int *PTERequestSizeC; 1680 unsigned int *PixelPTEReqWidthY; 1681 unsigned int *PixelPTEReqHeightY; 1682 unsigned int *PixelPTEReqWidthC; 1683 unsigned int *PixelPTEReqHeightC; 1684 unsigned int *dpte_row_width_luma_ub; 1685 unsigned int *dpte_row_width_chroma_ub; 1686 unsigned int *tdlut_groups_per_2row_ub; 1687 bool mrq_present; 1688 unsigned int MetaChunkSize; 1689 unsigned int MinMetaChunkSizeBytes; 1690 unsigned int *meta_row_width; 1691 unsigned int *meta_row_width_chroma; 1692 unsigned int *meta_row_height; 1693 unsigned int *meta_row_height_chroma; 1694 unsigned int *meta_req_width; 1695 unsigned int *meta_req_width_chroma; 1696 unsigned int *meta_req_height; 1697 unsigned int *meta_req_height_chroma; 1698 1699 // Output 1700 double *time_per_tdlut_group; 1701 double *DST_Y_PER_PTE_ROW_NOM_L; 1702 double *DST_Y_PER_PTE_ROW_NOM_C; 1703 double *time_per_pte_group_nom_luma; 1704 double *time_per_pte_group_vblank_luma; 1705 double *time_per_pte_group_flip_luma; 1706 double *time_per_pte_group_nom_chroma; 1707 double *time_per_pte_group_vblank_chroma; 1708 double *time_per_pte_group_flip_chroma; 1709 1710 double *DST_Y_PER_META_ROW_NOM_L; 1711 double *DST_Y_PER_META_ROW_NOM_C; 1712 1713 double *TimePerMetaChunkNominal; 1714 double *TimePerChromaMetaChunkNominal; 1715 double *TimePerMetaChunkVBlank; 1716 double *TimePerChromaMetaChunkVBlank; 1717 double *TimePerMetaChunkFlip; 1718 double *TimePerChromaMetaChunkFlip; 1719 }; 1720 1721 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params { 1722 const struct dml2_display_cfg *display_cfg; 1723 bool USRRetrainingRequired; 1724 unsigned int NumberOfActiveSurfaces; 1725 unsigned int MaxLineBufferLines; 1726 unsigned int LineBufferSize; 1727 unsigned int WritebackInterfaceBufferSize; 1728 double DCFCLK; 1729 double ReturnBW; 1730 bool SynchronizeTimings; 1731 bool SynchronizeDRRDisplaysForUCLKPStateChange; 1732 const unsigned int *dpte_group_bytes; 1733 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1734 unsigned int WritebackChunkSize; 1735 double SOCCLK; 1736 double DCFClkDeepSleep; 1737 const unsigned int *DETBufferSizeY; 1738 const unsigned int *DETBufferSizeC; 1739 const unsigned int *SwathHeightY; 1740 const unsigned int *SwathHeightC; 1741 const unsigned int *SwathWidthY; 1742 const unsigned int *SwathWidthC; 1743 const unsigned int *DPPPerSurface; 1744 const double *BytePerPixelDETY; 1745 const double *BytePerPixelDETC; 1746 const unsigned int *DSTXAfterScaler; 1747 const unsigned int *DSTYAfterScaler; 1748 bool UnboundedRequestEnabled; 1749 unsigned int CompressedBufferSizeInkByte; 1750 bool max_outstanding_when_urgent_expected; 1751 const unsigned int max_outstanding_requests; 1752 const unsigned int max_request_size_bytes; 1753 const unsigned int *meta_row_height_l; 1754 const unsigned int *meta_row_height_c; 1755 const enum dml2_pstate_method *uclk_pstate_switch_modes; 1756 1757 // Output 1758 struct dml2_core_internal_watermarks *Watermark; 1759 enum dml2_pstate_change_support *DRAMClockChangeSupport; 1760 bool *global_dram_clock_change_support_required; 1761 bool *global_dram_clock_change_supported; 1762 double *MaxActiveDRAMClockChangeLatencySupported; 1763 unsigned int *SubViewportLinesNeededInMALL; 1764 enum dml2_pstate_change_support *FCLKChangeSupport; 1765 bool *global_fclk_change_supported; 1766 double *MaxActiveFCLKChangeLatencySupported; 1767 bool *USRRetrainingSupport; 1768 double *VActiveLatencyHidingMargin; 1769 double *VActiveLatencyHidingUs; 1770 bool *g6_temp_read_support; 1771 enum dml2_pstate_change_support *temp_read_or_ppt_support; 1772 bool *global_temp_read_or_ppt_supported; 1773 }; 1774 1775 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params { 1776 const struct dml2_display_cfg *display_cfg; 1777 unsigned int ConfigReturnBufferSizeInKByte; 1778 unsigned int MaxTotalDETInKByte; 1779 unsigned int MinCompressedBufferSizeInKByte; 1780 unsigned int rob_buffer_size_kbytes; 1781 unsigned int pixel_chunk_size_kbytes; 1782 bool ForceSingleDPP; 1783 unsigned int NumberOfActiveSurfaces; 1784 unsigned int nomDETInKByte; 1785 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1786 unsigned int CompressedBufferSegmentSizeInkByte; 1787 double *ReadBandwidthLuma; 1788 double *ReadBandwidthChroma; 1789 double *MaximumSwathWidthLuma; 1790 double *MaximumSwathWidthChroma; 1791 unsigned int *Read256BytesBlockHeightY; 1792 unsigned int *Read256BytesBlockHeightC; 1793 unsigned int *Read256BytesBlockWidthY; 1794 unsigned int *Read256BytesBlockWidthC; 1795 bool *surf_linear128_l; 1796 bool *surf_linear128_c; 1797 enum dml2_odm_mode *ODMMode; 1798 unsigned int *BytePerPixY; 1799 unsigned int *BytePerPixC; 1800 double *BytePerPixDETY; 1801 double *BytePerPixDETC; 1802 unsigned int *DPPPerSurface; 1803 bool mrq_present; 1804 unsigned int dummy[2][DML2_MAX_PLANES]; 1805 unsigned int swath_width_luma_ub_single_dpp[DML2_MAX_PLANES]; 1806 unsigned int swath_width_chroma_ub_single_dpp[DML2_MAX_PLANES]; 1807 1808 // output 1809 unsigned int *req_per_swath_ub_l; 1810 unsigned int *req_per_swath_ub_c; 1811 unsigned int *swath_width_luma_ub; 1812 unsigned int *swath_width_chroma_ub; 1813 unsigned int *SwathWidth; 1814 unsigned int *SwathWidthChroma; 1815 unsigned int *SwathHeightY; 1816 unsigned int *SwathHeightC; 1817 unsigned int *request_size_bytes_luma; 1818 unsigned int *request_size_bytes_chroma; 1819 unsigned int *DETBufferSizeInKByte; 1820 unsigned int *DETBufferSizeY; 1821 unsigned int *DETBufferSizeC; 1822 unsigned int *full_swath_bytes_l; 1823 unsigned int *full_swath_bytes_c; 1824 unsigned int *full_swath_bytes_single_dpp_l; 1825 unsigned int *full_swath_bytes_single_dpp_c; 1826 bool *UnboundedRequestEnabled; 1827 unsigned int *compbuf_reserved_space_64b; 1828 unsigned int *CompressedBufferSizeInkByte; 1829 bool *ViewportSizeSupportPerSurface; 1830 bool *ViewportSizeSupport; 1831 bool *hw_debug5; 1832 1833 struct dml2_core_shared_calculation_funcs *funcs; 1834 }; 1835 1836 struct dml2_core_calcs_CalculateStutterEfficiency_locals { 1837 double DETBufferingTimeY; 1838 double SwathWidthYCriticalSurface; 1839 double SwathHeightYCriticalSurface; 1840 double VActiveTimeCriticalSurface; 1841 double FrameTimeCriticalSurface; 1842 unsigned int BytePerPixelYCriticalSurface; 1843 unsigned int DETBufferSizeYCriticalSurface; 1844 double MinTTUVBlankCriticalSurface; 1845 unsigned int BlockWidth256BytesYCriticalSurface; 1846 bool SinglePlaneCriticalSurface; 1847 bool SinglePipeCriticalSurface; 1848 double TotalCompressedReadBandwidth; 1849 double TotalRowReadBandwidth; 1850 double AverageDCCCompressionRate; 1851 double EffectiveCompressedBufferSize; 1852 double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer; 1853 double StutterBurstTime; 1854 unsigned int TotalActiveWriteback; 1855 double LinesInDETY; 1856 double LinesInDETYRoundedDownToSwath; 1857 double MaximumEffectiveCompressionLuma; 1858 double MaximumEffectiveCompressionChroma; 1859 double TotalZeroSizeRequestReadBandwidth; 1860 double TotalZeroSizeCompressedReadBandwidth; 1861 double AverageDCCZeroSizeFraction; 1862 double AverageZeroSizeCompressionRate; 1863 bool stream_visited[DML2_MAX_PLANES]; 1864 }; 1865 1866 struct dml2_core_calcs_CalculateStutterEfficiency_params { 1867 const struct dml2_display_cfg *display_cfg; 1868 unsigned int CompressedBufferSizeInkByte; 1869 bool UnboundedRequestEnabled; 1870 unsigned int MetaFIFOSizeInKEntries; 1871 unsigned int ZeroSizeBufferEntries; 1872 unsigned int PixelChunkSizeInKByte; 1873 unsigned int NumberOfActiveSurfaces; 1874 unsigned int ROBBufferSizeInKByte; 1875 double TotalDataReadBandwidth; 1876 double DCFCLK; 1877 double ReturnBW; 1878 unsigned int CompbufReservedSpace64B; 1879 unsigned int CompbufReservedSpaceZs; 1880 bool hw_debug5; 1881 double SRExitTime; 1882 double SRExitTimeLowPower; 1883 double SRExitZ8Time; 1884 bool SynchronizeTimings; 1885 double StutterEnterPlusExitWatermark; 1886 double LowPowerStutterEnterPlusExitWatermark; 1887 double Z8StutterEnterPlusExitWatermark; 1888 bool ProgressiveToInterlaceUnitInOPP; 1889 double *MinTTUVBlank; 1890 unsigned int *DPPPerSurface; 1891 unsigned int *DETBufferSizeY; 1892 unsigned int *BytePerPixelY; 1893 double *BytePerPixelDETY; 1894 unsigned int *SwathWidthY; 1895 unsigned int *SwathHeightY; 1896 unsigned int *SwathHeightC; 1897 unsigned int *BlockHeight256BytesY; 1898 unsigned int *BlockWidth256BytesY; 1899 unsigned int *BlockHeight256BytesC; 1900 unsigned int *BlockWidth256BytesC; 1901 unsigned int *DCCYMaxUncompressedBlock; 1902 unsigned int *DCCCMaxUncompressedBlock; 1903 double *ReadBandwidthSurfaceLuma; 1904 double *ReadBandwidthSurfaceChroma; 1905 double *meta_row_bw; 1906 double *dpte_row_bw; 1907 bool rob_alloc_compressed; 1908 1909 // output 1910 double *StutterEfficiencyNotIncludingVBlank; 1911 double *StutterEfficiency; 1912 double *LowPowerStutterEfficiencyNotIncludingVBlank; 1913 double *LowPowerStutterEfficiency; 1914 unsigned int *NumberOfStutterBurstsPerFrame; 1915 unsigned int *LowPowerNumberOfStutterBurstsPerFrame; 1916 double *Z8StutterEfficiencyNotIncludingVBlank; 1917 double *Z8StutterEfficiency; 1918 unsigned int *Z8NumberOfStutterBurstsPerFrame; 1919 double *StutterPeriod; 1920 bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1921 }; 1922 1923 struct dml2_core_calcs_CalculatePrefetchSchedule_params { 1924 const struct dml2_display_cfg *display_cfg; 1925 double HostVMInefficiencyFactor; 1926 struct dml2_core_internal_DmlPipe *myPipe; 1927 unsigned int DSCDelay; 1928 double DPPCLKDelaySubtotalPlusCNVCFormater; 1929 double DPPCLKDelaySCL; 1930 double DPPCLKDelaySCLLBOnly; 1931 double DPPCLKDelayCNVCCursor; 1932 double DISPCLKDelaySubtotal; 1933 unsigned int DPP_RECOUT_WIDTH; 1934 enum dml2_output_format_class OutputFormat; 1935 unsigned int MaxInterDCNTileRepeaters; 1936 unsigned int VStartup; 1937 unsigned int HostVMMinPageSize; 1938 bool DynamicMetadataEnable; 1939 bool DynamicMetadataVMEnabled; 1940 unsigned int DynamicMetadataLinesBeforeActiveRequired; 1941 unsigned int DynamicMetadataTransmittedBytes; 1942 double ExtraLatencyPrefetch; 1943 double TCalc; 1944 unsigned int vm_bytes; 1945 unsigned int PixelPTEBytesPerRow; 1946 double PrefetchSourceLinesY; 1947 unsigned int VInitPreFillY; 1948 unsigned int MaxNumSwathY; 1949 double PrefetchSourceLinesC; 1950 unsigned int VInitPreFillC; 1951 unsigned int MaxNumSwathC; 1952 unsigned int swath_width_luma_ub; // per-pipe 1953 unsigned int swath_width_chroma_ub; // per-pipe 1954 unsigned int SwathHeightY; 1955 unsigned int SwathHeightC; 1956 double TWait; 1957 double Ttrip; 1958 double Turg; 1959 bool setup_for_tdlut; 1960 bool use_max_lsw; 1961 unsigned int tdlut_pte_bytes_per_frame; 1962 unsigned int tdlut_bytes_per_frame; 1963 double tdlut_opt_time; 1964 double tdlut_drain_time; 1965 1966 unsigned int num_cursors; 1967 unsigned int cursor_bytes_per_chunk; 1968 unsigned int cursor_bytes_per_line; 1969 1970 // MRQ 1971 bool dcc_enable; 1972 bool mrq_present; 1973 unsigned int meta_row_bytes; 1974 double mall_prefetch_sdp_overhead_factor; 1975 1976 double impacted_dst_y_pre; 1977 double vactive_sw_bw_l; // per surface bw 1978 double vactive_sw_bw_c; // per surface bw 1979 1980 // output 1981 unsigned int *DSTXAfterScaler; 1982 unsigned int *DSTYAfterScaler; 1983 double *dst_y_prefetch; 1984 double *dst_y_per_vm_vblank; 1985 double *dst_y_per_row_vblank; 1986 double *VRatioPrefetchY; 1987 double *VRatioPrefetchC; 1988 double *RequiredPrefetchPixelDataBWLuma; 1989 double *RequiredPrefetchPixelDataBWChroma; 1990 double *RequiredPrefetchBWMax; 1991 bool *NotEnoughTimeForDynamicMetadata; 1992 double *Tno_bw; 1993 double *Tno_bw_flip; 1994 double *prefetch_vmrow_bw; 1995 double *Tdmdl_vm; 1996 double *Tdmdl; 1997 double *TSetup; 1998 double *Tpre_rounded; 1999 double *Tpre_oto; 2000 double *Tvm_trips; 2001 double *Tr0_trips; 2002 double *Tvm_trips_flip; 2003 double *Tr0_trips_flip; 2004 double *Tvm_trips_flip_rounded; 2005 double *Tr0_trips_flip_rounded; 2006 unsigned int *VUpdateOffsetPix; 2007 unsigned int *VUpdateWidthPix; 2008 unsigned int *VReadyOffsetPix; 2009 double *prefetch_cursor_bw; 2010 double *prefetch_sw_bytes; 2011 double *prefetch_swath_time_us; 2012 }; 2013 2014 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params { 2015 unsigned int num_active_planes; 2016 enum dml2_source_format_class *pixel_format; 2017 unsigned int rob_buffer_size_kbytes; 2018 unsigned int compressed_buffer_size_kbytes; 2019 unsigned int chunk_bytes_l; // same for all planes 2020 unsigned int chunk_bytes_c; 2021 unsigned int *detile_buffer_size_bytes_l; 2022 unsigned int *detile_buffer_size_bytes_c; 2023 unsigned int *full_swath_bytes_l; 2024 unsigned int *full_swath_bytes_c; 2025 unsigned int *lb_source_lines_l; 2026 unsigned int *lb_source_lines_c; 2027 unsigned int *swath_height_l; 2028 unsigned int *swath_height_c; 2029 double *prefetch_sw_bytes; 2030 double *Tpre_rounded; 2031 double *Tpre_oto; 2032 double estimated_dcfclk_mhz; 2033 double estimated_urg_bandwidth_required_mbps; 2034 double *line_time; 2035 double *dst_y_prefetch; 2036 2037 // output 2038 bool *recalc_prefetch_schedule; 2039 double *impacted_dst_y_pre; 2040 }; 2041 2042 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals { 2043 unsigned int max_Trpd_dcfclk_cycles; 2044 unsigned int burst_bytes_to_fill_det; 2045 double time_to_fill_det_us; 2046 unsigned int accumulated_return_path_dcfclk_cycles[DML2_MAX_PLANES]; 2047 bool prefetch_global_check_passed; 2048 unsigned int src_swath_bytes_l[DML2_MAX_PLANES]; 2049 unsigned int src_swath_bytes_c[DML2_MAX_PLANES]; 2050 unsigned int src_detile_buf_size_bytes_l[DML2_MAX_PLANES]; 2051 unsigned int src_detile_buf_size_bytes_c[DML2_MAX_PLANES]; 2052 }; 2053 2054 struct dml2_core_calcs_calculate_mcache_row_bytes_params { 2055 unsigned int num_chans; 2056 unsigned int mem_word_bytes; 2057 unsigned int mcache_size_bytes; 2058 unsigned int mcache_line_size_bytes; 2059 unsigned int gpuvm_enable; 2060 unsigned int gpuvm_page_size_kbytes; 2061 2062 //enum dml_rotation_angle rotation_angle; 2063 bool surf_vert; 2064 unsigned int vp_stationary; 2065 unsigned int tiling_mode; 2066 bool imall_enable; 2067 2068 unsigned int vp_start_x; 2069 unsigned int vp_start_y; 2070 unsigned int full_vp_width; 2071 unsigned int full_vp_height; 2072 unsigned int blk_width; 2073 unsigned int blk_height; 2074 unsigned int vmpg_width; 2075 unsigned int vmpg_height; 2076 unsigned int full_swath_bytes; 2077 unsigned int bytes_per_pixel; 2078 2079 // output 2080 unsigned int *num_mcaches; 2081 unsigned int *mcache_row_bytes; 2082 unsigned int *mcache_row_bytes_per_channel; 2083 unsigned int *meta_row_width_ub; 2084 double *dcc_dram_bw_nom_overhead_factor; 2085 double *dcc_dram_bw_pref_overhead_factor; 2086 unsigned int *mvmpg_width; 2087 unsigned int *mvmpg_height; 2088 unsigned int *full_vp_access_width_mvmpg_aligned; 2089 unsigned int *mvmpg_per_mcache_lb; 2090 }; 2091 2092 struct dml2_core_shared_calculate_mcache_setting_locals { 2093 struct dml2_core_calcs_calculate_mcache_row_bytes_params l_p; 2094 struct dml2_core_calcs_calculate_mcache_row_bytes_params c_p; 2095 2096 bool is_dual_plane; 2097 unsigned int mvmpg_width_l; 2098 unsigned int mvmpg_height_l; 2099 unsigned int full_vp_access_width_mvmpg_aligned_l; 2100 unsigned int mvmpg_per_mcache_lb_l; 2101 unsigned int meta_row_width_l; 2102 2103 unsigned int mvmpg_width_c; 2104 unsigned int mvmpg_height_c; 2105 unsigned int full_vp_access_width_mvmpg_aligned_c; 2106 unsigned int mvmpg_per_mcache_lb_c; 2107 unsigned int meta_row_width_c; 2108 2109 unsigned int lc_comb_last_mcache_size; 2110 double luma_time_factor; 2111 double mcache_remainder_l; 2112 double mcache_remainder_c; 2113 unsigned int mvmpg_access_width_l; 2114 unsigned int mvmpg_access_width_c; 2115 unsigned int avg_mcache_element_size_l; 2116 unsigned int avg_mcache_element_size_c; 2117 2118 unsigned int full_vp_access_width_l; 2119 unsigned int full_vp_access_width_c; 2120 }; 2121 2122 struct dml2_core_calcs_calculate_mcache_setting_params { 2123 bool dcc_enable; 2124 unsigned int num_chans; 2125 unsigned int mem_word_bytes; 2126 unsigned int mcache_size_bytes; 2127 unsigned int mcache_line_size_bytes; 2128 unsigned int gpuvm_enable; 2129 unsigned int gpuvm_page_size_kbytes; 2130 2131 enum dml2_source_format_class source_format; 2132 bool surf_vert; 2133 unsigned int vp_stationary; 2134 unsigned int tiling_mode; 2135 bool imall_enable; 2136 2137 unsigned int vp_start_x_l; 2138 unsigned int vp_start_y_l; 2139 unsigned int full_vp_width_l; 2140 unsigned int full_vp_height_l; 2141 unsigned int blk_width_l; 2142 unsigned int blk_height_l; 2143 unsigned int vmpg_width_l; 2144 unsigned int vmpg_height_l; 2145 unsigned int full_swath_bytes_l; 2146 unsigned int bytes_per_pixel_l; 2147 2148 unsigned int vp_start_x_c; 2149 unsigned int vp_start_y_c; 2150 unsigned int full_vp_width_c; 2151 unsigned int full_vp_height_c; 2152 unsigned int blk_width_c; 2153 unsigned int blk_height_c; 2154 unsigned int vmpg_width_c; 2155 unsigned int vmpg_height_c; 2156 unsigned int full_swath_bytes_c; 2157 unsigned int bytes_per_pixel_c; 2158 2159 // output 2160 unsigned int *num_mcaches_l; 2161 unsigned int *mcache_row_bytes_l; 2162 unsigned int *mcache_row_bytes_per_channel_l; 2163 unsigned int *mcache_offsets_l; 2164 unsigned int *mcache_shift_granularity_l; 2165 double *dcc_dram_bw_nom_overhead_factor_l; 2166 double *dcc_dram_bw_pref_overhead_factor_l; 2167 2168 unsigned int *num_mcaches_c; 2169 unsigned int *mcache_row_bytes_c; 2170 unsigned int *mcache_row_bytes_per_channel_c; 2171 unsigned int *mcache_offsets_c; 2172 unsigned int *mcache_shift_granularity_c; 2173 double *dcc_dram_bw_nom_overhead_factor_c; 2174 double *dcc_dram_bw_pref_overhead_factor_c; 2175 2176 bool *mall_comb_mcache_l; 2177 bool *mall_comb_mcache_c; 2178 bool *lc_comb_mcache; 2179 }; 2180 2181 struct dml2_core_calcs_calculate_tdlut_setting_params { 2182 // input params 2183 double dispclk_mhz; 2184 bool setup_for_tdlut; 2185 enum dml2_tdlut_width_mode tdlut_width_mode; 2186 enum dml2_tdlut_addressing_mode tdlut_addressing_mode; 2187 unsigned int cursor_buffer_size; 2188 bool gpuvm_enable; 2189 unsigned int gpuvm_page_size_kbytes; 2190 bool is_gfx11; 2191 bool tdlut_mpc_width_flag; 2192 2193 // output param 2194 unsigned int *tdlut_pte_bytes_per_frame; 2195 unsigned int *tdlut_bytes_per_frame; 2196 unsigned int *tdlut_groups_per_2row_ub; 2197 double *tdlut_opt_time; 2198 double *tdlut_drain_time; 2199 unsigned int *tdlut_bytes_to_deliver; 2200 unsigned int *tdlut_bytes_per_group; 2201 }; 2202 2203 struct dml2_core_calcs_calculate_peak_bandwidth_required_params { 2204 // output 2205 double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max]; 2206 double (*urg_bandwidth_required)[dml2_core_internal_bw_max]; 2207 double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max]; 2208 double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max]; 2209 double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 2210 double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 2211 2212 // input 2213 const struct dml2_display_cfg *display_cfg; 2214 bool inc_flip_bw; 2215 unsigned int num_active_planes; 2216 unsigned int *num_of_dpp; 2217 double *dcc_dram_bw_nom_overhead_factor_p0; 2218 double *dcc_dram_bw_nom_overhead_factor_p1; 2219 double *dcc_dram_bw_pref_overhead_factor_p0; 2220 double *dcc_dram_bw_pref_overhead_factor_p1; 2221 double *mall_prefetch_sdp_overhead_factor; 2222 double *mall_prefetch_dram_overhead_factor; 2223 double *surface_read_bandwidth_l; 2224 double *surface_read_bandwidth_c; 2225 double *prefetch_bandwidth_l; 2226 double *prefetch_bandwidth_c; 2227 double *prefetch_bandwidth_max; 2228 double *excess_vactive_fill_bw_l; 2229 double *excess_vactive_fill_bw_c; 2230 double *cursor_bw; 2231 double *dpte_row_bw; 2232 double *meta_row_bw; 2233 double *prefetch_cursor_bw; 2234 double *prefetch_vmrow_bw; 2235 double *flip_bw; 2236 double *urgent_burst_factor_l; 2237 double *urgent_burst_factor_c; 2238 double *urgent_burst_factor_cursor; 2239 double *urgent_burst_factor_prefetch_l; 2240 double *urgent_burst_factor_prefetch_c; 2241 double *urgent_burst_factor_prefetch_cursor; 2242 }; 2243 2244 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params { 2245 /* inputs */ 2246 const struct dml2_display_cfg *display_cfg; 2247 bool mrq_present; 2248 unsigned int num_active_planes; 2249 unsigned int *num_of_dpp; 2250 unsigned int *meta_row_height_l; 2251 unsigned int *meta_row_height_c; 2252 unsigned int *meta_row_bytes_per_row_ub_l; 2253 unsigned int *meta_row_bytes_per_row_ub_c; 2254 unsigned int *dpte_row_height_l; 2255 unsigned int *dpte_row_height_c; 2256 unsigned int *dpte_bytes_per_row_l; 2257 unsigned int *dpte_bytes_per_row_c; 2258 unsigned int *byte_per_pix_l; 2259 unsigned int *byte_per_pix_c; 2260 unsigned int *swath_width_l; 2261 unsigned int *swath_width_c; 2262 unsigned int *swath_height_l; 2263 unsigned int *swath_height_c; 2264 double latency_to_hide_us[DML2_MAX_PLANES]; 2265 2266 /* outputs */ 2267 unsigned int *bytes_required_l; 2268 unsigned int *bytes_required_c; 2269 }; 2270 2271 // A list of overridable function pointers in the core 2272 // shared calculation library. 2273 struct dml2_core_shared_calculation_funcs { 2274 void (*calculate_det_buffer_size)(struct dml2_core_shared_calculate_det_buffer_size_params *p); 2275 }; 2276 2277 struct dml2_core_internal_scratch { 2278 // Scratch space for function locals 2279 struct dml2_core_calcs_mode_support_locals dml_core_mode_support_locals; 2280 struct dml2_core_calcs_mode_programming_locals dml_core_mode_programming_locals; 2281 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals; 2282 struct dml2_core_calcs_CalculateVMRowAndSwath_locals CalculateVMRowAndSwath_locals; 2283 struct dml2_core_calcs_CalculatePrefetchSchedule_locals CalculatePrefetchSchedule_locals; 2284 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals CheckGlobalPrefetchAdmissibility_locals; 2285 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals CalculateSwathAndDETConfiguration_locals; 2286 struct dml2_core_shared_TruncToValidBPP_locals TruncToValidBPP_locals; 2287 struct dml2_core_shared_CalculateDETBufferSize_locals CalculateDETBufferSize_locals; 2288 struct dml2_core_shared_get_urgent_bandwidth_required_locals get_urgent_bandwidth_required_locals; 2289 struct dml2_core_shared_calculate_peak_bandwidth_required_locals calculate_peak_bandwidth_required_locals; 2290 struct dml2_core_shared_CalculateFlipSchedule_locals CalculateFlipSchedule_locals; 2291 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals rq_dlg_get_dlg_reg_locals; 2292 struct dml2_core_calcs_CalculateStutterEfficiency_locals CalculateStutterEfficiency_locals; 2293 2294 // Scratch space for function params 2295 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params; 2296 struct dml2_core_calcs_CalculateVMRowAndSwath_params CalculateVMRowAndSwath_params; 2297 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params CalculateSwathAndDETConfiguration_params; 2298 struct dml2_core_calcs_CalculateStutterEfficiency_params CalculateStutterEfficiency_params; 2299 struct dml2_core_calcs_CalculatePrefetchSchedule_params CalculatePrefetchSchedule_params; 2300 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params CheckGlobalPrefetchAdmissibility_params; 2301 struct dml2_core_calcs_calculate_mcache_setting_params calculate_mcache_setting_params; 2302 struct dml2_core_calcs_calculate_tdlut_setting_params calculate_tdlut_setting_params; 2303 struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params; 2304 struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals; 2305 struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params; 2306 struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params; 2307 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params; 2308 }; 2309 2310 //struct dml2_svp_mode_override; 2311 struct dml2_core_internal_display_mode_lib { 2312 struct dml2_core_ip_params ip; 2313 struct dml2_soc_bb soc; 2314 struct dml2_ip_capabilities ip_caps; 2315 2316 //@brief Mode Support and Mode programming struct 2317 // Used to hold input; intermediate and output of the calculations 2318 struct dml2_core_internal_mode_support ms; // struct for mode support 2319 struct dml2_core_internal_mode_program mp; // struct for mode programming 2320 // Available overridable calculators for core_shared. 2321 // if null, core_shared will use default calculators. 2322 struct dml2_core_shared_calculation_funcs funcs; 2323 2324 struct dml2_core_internal_scratch scratch; 2325 }; 2326 2327 struct dml2_core_calcs_mode_support_ex { 2328 struct dml2_core_internal_display_mode_lib *mode_lib; 2329 const struct dml2_display_cfg *in_display_cfg; 2330 const struct dml2_mcg_min_clock_table *min_clk_table; 2331 int min_clk_index; 2332 enum dml2_project_id project_id; 2333 //unsigned int in_state_index; 2334 struct dml2_core_internal_mode_support_info *out_evaluation_info; 2335 }; 2336 2337 struct core_display_cfg_support_info; 2338 2339 struct dml2_core_calcs_mode_programming_ex { 2340 struct dml2_core_internal_display_mode_lib *mode_lib; 2341 const struct dml2_display_cfg *in_display_cfg; 2342 const struct dml2_mcg_min_clock_table *min_clk_table; 2343 const struct core_display_cfg_support_info *cfg_support_info; 2344 int min_clk_index; 2345 enum dml2_project_id project_id; 2346 struct dml2_display_cfg_programming *programming; 2347 }; 2348 2349 #endif 2350