1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Copyright (c) 2014 Linaro Ltd. 3 * Copyright (c) 2014 Hisilicon Limited. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/interrupt.h> 8 #include <linux/etherdevice.h> 9 #include <linux/platform_device.h> 10 #include <linux/property.h> 11 #include <linux/of.h> 12 #include <linux/of_net.h> 13 #include <linux/of_mdio.h> 14 #include <linux/reset.h> 15 #include <linux/rtnetlink.h> 16 #include <linux/clk.h> 17 #include <linux/circ_buf.h> 18 19 #define STATION_ADDR_LOW 0x0000 20 #define STATION_ADDR_HIGH 0x0004 21 #define MAC_DUPLEX_HALF_CTRL 0x0008 22 #define MAX_FRM_SIZE 0x003c 23 #define PORT_MODE 0x0040 24 #define PORT_EN 0x0044 25 #define BITS_TX_EN BIT(2) 26 #define BITS_RX_EN BIT(1) 27 #define REC_FILT_CONTROL 0x0064 28 #define BIT_CRC_ERR_PASS BIT(5) 29 #define BIT_PAUSE_FRM_PASS BIT(4) 30 #define BIT_VLAN_DROP_EN BIT(3) 31 #define BIT_BC_DROP_EN BIT(2) 32 #define BIT_MC_MATCH_EN BIT(1) 33 #define BIT_UC_MATCH_EN BIT(0) 34 #define PORT_MC_ADDR_LOW 0x0068 35 #define PORT_MC_ADDR_HIGH 0x006C 36 #define CF_CRC_STRIP 0x01b0 37 #define MODE_CHANGE_EN 0x01b4 38 #define BIT_MODE_CHANGE_EN BIT(0) 39 #define COL_SLOT_TIME 0x01c0 40 #define RECV_CONTROL 0x01e0 41 #define BIT_STRIP_PAD_EN BIT(3) 42 #define BIT_RUNT_PKT_EN BIT(4) 43 #define CONTROL_WORD 0x0214 44 #define MDIO_SINGLE_CMD 0x03c0 45 #define MDIO_SINGLE_DATA 0x03c4 46 #define MDIO_CTRL 0x03cc 47 #define MDIO_RDATA_STATUS 0x03d0 48 49 #define MDIO_START BIT(20) 50 #define MDIO_R_VALID BIT(0) 51 #define MDIO_READ (BIT(17) | MDIO_START) 52 #define MDIO_WRITE (BIT(16) | MDIO_START) 53 54 #define RX_FQ_START_ADDR 0x0500 55 #define RX_FQ_DEPTH 0x0504 56 #define RX_FQ_WR_ADDR 0x0508 57 #define RX_FQ_RD_ADDR 0x050c 58 #define RX_FQ_VLDDESC_CNT 0x0510 59 #define RX_FQ_ALEMPTY_TH 0x0514 60 #define RX_FQ_REG_EN 0x0518 61 #define BITS_RX_FQ_START_ADDR_EN BIT(2) 62 #define BITS_RX_FQ_DEPTH_EN BIT(1) 63 #define BITS_RX_FQ_RD_ADDR_EN BIT(0) 64 #define RX_FQ_ALFULL_TH 0x051c 65 #define RX_BQ_START_ADDR 0x0520 66 #define RX_BQ_DEPTH 0x0524 67 #define RX_BQ_WR_ADDR 0x0528 68 #define RX_BQ_RD_ADDR 0x052c 69 #define RX_BQ_FREE_DESC_CNT 0x0530 70 #define RX_BQ_ALEMPTY_TH 0x0534 71 #define RX_BQ_REG_EN 0x0538 72 #define BITS_RX_BQ_START_ADDR_EN BIT(2) 73 #define BITS_RX_BQ_DEPTH_EN BIT(1) 74 #define BITS_RX_BQ_WR_ADDR_EN BIT(0) 75 #define RX_BQ_ALFULL_TH 0x053c 76 #define TX_BQ_START_ADDR 0x0580 77 #define TX_BQ_DEPTH 0x0584 78 #define TX_BQ_WR_ADDR 0x0588 79 #define TX_BQ_RD_ADDR 0x058c 80 #define TX_BQ_VLDDESC_CNT 0x0590 81 #define TX_BQ_ALEMPTY_TH 0x0594 82 #define TX_BQ_REG_EN 0x0598 83 #define BITS_TX_BQ_START_ADDR_EN BIT(2) 84 #define BITS_TX_BQ_DEPTH_EN BIT(1) 85 #define BITS_TX_BQ_RD_ADDR_EN BIT(0) 86 #define TX_BQ_ALFULL_TH 0x059c 87 #define TX_RQ_START_ADDR 0x05a0 88 #define TX_RQ_DEPTH 0x05a4 89 #define TX_RQ_WR_ADDR 0x05a8 90 #define TX_RQ_RD_ADDR 0x05ac 91 #define TX_RQ_FREE_DESC_CNT 0x05b0 92 #define TX_RQ_ALEMPTY_TH 0x05b4 93 #define TX_RQ_REG_EN 0x05b8 94 #define BITS_TX_RQ_START_ADDR_EN BIT(2) 95 #define BITS_TX_RQ_DEPTH_EN BIT(1) 96 #define BITS_TX_RQ_WR_ADDR_EN BIT(0) 97 #define TX_RQ_ALFULL_TH 0x05bc 98 #define RAW_PMU_INT 0x05c0 99 #define ENA_PMU_INT 0x05c4 100 #define STATUS_PMU_INT 0x05c8 101 #define MAC_FIFO_ERR_IN BIT(30) 102 #define TX_RQ_IN_TIMEOUT_INT BIT(29) 103 #define RX_BQ_IN_TIMEOUT_INT BIT(28) 104 #define TXOUTCFF_FULL_INT BIT(27) 105 #define TXOUTCFF_EMPTY_INT BIT(26) 106 #define TXCFF_FULL_INT BIT(25) 107 #define TXCFF_EMPTY_INT BIT(24) 108 #define RXOUTCFF_FULL_INT BIT(23) 109 #define RXOUTCFF_EMPTY_INT BIT(22) 110 #define RXCFF_FULL_INT BIT(21) 111 #define RXCFF_EMPTY_INT BIT(20) 112 #define TX_RQ_IN_INT BIT(19) 113 #define TX_BQ_OUT_INT BIT(18) 114 #define RX_BQ_IN_INT BIT(17) 115 #define RX_FQ_OUT_INT BIT(16) 116 #define TX_RQ_EMPTY_INT BIT(15) 117 #define TX_RQ_FULL_INT BIT(14) 118 #define TX_RQ_ALEMPTY_INT BIT(13) 119 #define TX_RQ_ALFULL_INT BIT(12) 120 #define TX_BQ_EMPTY_INT BIT(11) 121 #define TX_BQ_FULL_INT BIT(10) 122 #define TX_BQ_ALEMPTY_INT BIT(9) 123 #define TX_BQ_ALFULL_INT BIT(8) 124 #define RX_BQ_EMPTY_INT BIT(7) 125 #define RX_BQ_FULL_INT BIT(6) 126 #define RX_BQ_ALEMPTY_INT BIT(5) 127 #define RX_BQ_ALFULL_INT BIT(4) 128 #define RX_FQ_EMPTY_INT BIT(3) 129 #define RX_FQ_FULL_INT BIT(2) 130 #define RX_FQ_ALEMPTY_INT BIT(1) 131 #define RX_FQ_ALFULL_INT BIT(0) 132 133 #define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \ 134 TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT) 135 136 #define DESC_WR_RD_ENA 0x05cc 137 #define IN_QUEUE_TH 0x05d8 138 #define OUT_QUEUE_TH 0x05dc 139 #define QUEUE_TX_BQ_SHIFT 16 140 #define RX_BQ_IN_TIMEOUT_TH 0x05e0 141 #define TX_RQ_IN_TIMEOUT_TH 0x05e4 142 #define STOP_CMD 0x05e8 143 #define BITS_TX_STOP BIT(1) 144 #define BITS_RX_STOP BIT(0) 145 #define FLUSH_CMD 0x05eC 146 #define BITS_TX_FLUSH_CMD BIT(5) 147 #define BITS_RX_FLUSH_CMD BIT(4) 148 #define BITS_TX_FLUSH_FLAG_DOWN BIT(3) 149 #define BITS_TX_FLUSH_FLAG_UP BIT(2) 150 #define BITS_RX_FLUSH_FLAG_DOWN BIT(1) 151 #define BITS_RX_FLUSH_FLAG_UP BIT(0) 152 #define RX_CFF_NUM_REG 0x05f0 153 #define PMU_FSM_REG 0x05f8 154 #define RX_FIFO_PKT_IN_NUM 0x05fc 155 #define RX_FIFO_PKT_OUT_NUM 0x0600 156 157 #define RGMII_SPEED_1000 0x2c 158 #define RGMII_SPEED_100 0x2f 159 #define RGMII_SPEED_10 0x2d 160 #define MII_SPEED_100 0x0f 161 #define MII_SPEED_10 0x0d 162 #define GMAC_SPEED_1000 0x05 163 #define GMAC_SPEED_100 0x01 164 #define GMAC_SPEED_10 0x00 165 #define GMAC_FULL_DUPLEX BIT(4) 166 167 #define RX_BQ_INT_THRESHOLD 0x01 168 #define TX_RQ_INT_THRESHOLD 0x01 169 #define RX_BQ_IN_TIMEOUT 0x10000 170 #define TX_RQ_IN_TIMEOUT 0x50000 171 172 #define MAC_MAX_FRAME_SIZE 1600 173 #define DESC_SIZE 32 174 #define RX_DESC_NUM 1024 175 #define TX_DESC_NUM 1024 176 177 #define DESC_VLD_FREE 0 178 #define DESC_VLD_BUSY 0x80000000 179 #define DESC_FL_MID 0 180 #define DESC_FL_LAST 0x20000000 181 #define DESC_FL_FIRST 0x40000000 182 #define DESC_FL_FULL 0x60000000 183 #define DESC_DATA_LEN_OFF 16 184 #define DESC_BUFF_LEN_OFF 0 185 #define DESC_DATA_MASK 0x7ff 186 #define DESC_SG BIT(30) 187 #define DESC_FRAGS_NUM_OFF 11 188 189 /* DMA descriptor ring helpers */ 190 #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1)) 191 #define dma_cnt(n) ((n) >> 5) 192 #define dma_byte(n) ((n) << 5) 193 194 #define HW_CAP_TSO BIT(0) 195 #define GEMAC_V1 0 196 #define GEMAC_V2 (GEMAC_V1 | HW_CAP_TSO) 197 #define HAS_CAP_TSO(hw_cap) ((hw_cap) & HW_CAP_TSO) 198 199 #define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us" 200 201 enum phy_reset_delays { 202 PRE_DELAY, 203 PULSE, 204 POST_DELAY, 205 DELAYS_NUM, 206 }; 207 208 struct hix5hd2_desc { 209 __le32 buff_addr; 210 __le32 cmd; 211 } __aligned(32); 212 213 struct hix5hd2_desc_sw { 214 struct hix5hd2_desc *desc; 215 dma_addr_t phys_addr; 216 unsigned int count; 217 unsigned int size; 218 }; 219 220 struct hix5hd2_sg_desc_ring { 221 struct sg_desc *desc; 222 dma_addr_t phys_addr; 223 }; 224 225 struct frags_info { 226 __le32 addr; 227 __le32 size; 228 }; 229 230 /* hardware supported max skb frags num */ 231 #define SG_MAX_SKB_FRAGS 17 232 struct sg_desc { 233 __le32 total_len; 234 __le32 resvd0; 235 __le32 linear_addr; 236 __le32 linear_len; 237 /* reserve one more frags for memory alignment */ 238 struct frags_info frags[SG_MAX_SKB_FRAGS + 1]; 239 }; 240 241 #define QUEUE_NUMS 4 242 struct hix5hd2_priv { 243 struct hix5hd2_desc_sw pool[QUEUE_NUMS]; 244 #define rx_fq pool[0] 245 #define rx_bq pool[1] 246 #define tx_bq pool[2] 247 #define tx_rq pool[3] 248 struct hix5hd2_sg_desc_ring tx_ring; 249 250 void __iomem *base; 251 void __iomem *ctrl_base; 252 253 struct sk_buff *tx_skb[TX_DESC_NUM]; 254 struct sk_buff *rx_skb[RX_DESC_NUM]; 255 256 struct device *dev; 257 struct net_device *netdev; 258 259 struct device_node *phy_node; 260 phy_interface_t phy_mode; 261 262 unsigned long hw_cap; 263 unsigned int speed; 264 unsigned int duplex; 265 266 struct clk *mac_core_clk; 267 struct clk *mac_ifc_clk; 268 struct reset_control *mac_core_rst; 269 struct reset_control *mac_ifc_rst; 270 struct reset_control *phy_rst; 271 u32 phy_reset_delays[DELAYS_NUM]; 272 struct mii_bus *bus; 273 struct napi_struct napi; 274 struct work_struct tx_timeout_task; 275 }; 276 277 static inline void hix5hd2_mac_interface_reset(struct hix5hd2_priv *priv) 278 { 279 if (!priv->mac_ifc_rst) 280 return; 281 282 reset_control_assert(priv->mac_ifc_rst); 283 reset_control_deassert(priv->mac_ifc_rst); 284 } 285 286 static void hix5hd2_config_port(struct net_device *dev, u32 speed, u32 duplex) 287 { 288 struct hix5hd2_priv *priv = netdev_priv(dev); 289 u32 val; 290 291 priv->speed = speed; 292 priv->duplex = duplex; 293 294 switch (priv->phy_mode) { 295 case PHY_INTERFACE_MODE_RGMII: 296 if (speed == SPEED_1000) 297 val = RGMII_SPEED_1000; 298 else if (speed == SPEED_100) 299 val = RGMII_SPEED_100; 300 else 301 val = RGMII_SPEED_10; 302 break; 303 case PHY_INTERFACE_MODE_MII: 304 if (speed == SPEED_100) 305 val = MII_SPEED_100; 306 else 307 val = MII_SPEED_10; 308 break; 309 default: 310 netdev_warn(dev, "not supported mode\n"); 311 val = MII_SPEED_10; 312 break; 313 } 314 315 if (duplex) 316 val |= GMAC_FULL_DUPLEX; 317 writel_relaxed(val, priv->ctrl_base); 318 hix5hd2_mac_interface_reset(priv); 319 320 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); 321 if (speed == SPEED_1000) 322 val = GMAC_SPEED_1000; 323 else if (speed == SPEED_100) 324 val = GMAC_SPEED_100; 325 else 326 val = GMAC_SPEED_10; 327 writel_relaxed(val, priv->base + PORT_MODE); 328 writel_relaxed(0, priv->base + MODE_CHANGE_EN); 329 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); 330 } 331 332 static void hix5hd2_set_desc_depth(struct hix5hd2_priv *priv, int rx, int tx) 333 { 334 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); 335 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); 336 writel_relaxed(0, priv->base + RX_FQ_REG_EN); 337 338 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); 339 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); 340 writel_relaxed(0, priv->base + RX_BQ_REG_EN); 341 342 writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN); 343 writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH); 344 writel_relaxed(0, priv->base + TX_BQ_REG_EN); 345 346 writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN); 347 writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH); 348 writel_relaxed(0, priv->base + TX_RQ_REG_EN); 349 } 350 351 static void hix5hd2_set_rx_fq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) 352 { 353 writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN); 354 writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR); 355 writel_relaxed(0, priv->base + RX_FQ_REG_EN); 356 } 357 358 static void hix5hd2_set_rx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) 359 { 360 writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN); 361 writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR); 362 writel_relaxed(0, priv->base + RX_BQ_REG_EN); 363 } 364 365 static void hix5hd2_set_tx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) 366 { 367 writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN); 368 writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR); 369 writel_relaxed(0, priv->base + TX_BQ_REG_EN); 370 } 371 372 static void hix5hd2_set_tx_rq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) 373 { 374 writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN); 375 writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR); 376 writel_relaxed(0, priv->base + TX_RQ_REG_EN); 377 } 378 379 static void hix5hd2_set_desc_addr(struct hix5hd2_priv *priv) 380 { 381 hix5hd2_set_rx_fq(priv, priv->rx_fq.phys_addr); 382 hix5hd2_set_rx_bq(priv, priv->rx_bq.phys_addr); 383 hix5hd2_set_tx_rq(priv, priv->tx_rq.phys_addr); 384 hix5hd2_set_tx_bq(priv, priv->tx_bq.phys_addr); 385 } 386 387 static void hix5hd2_hw_init(struct hix5hd2_priv *priv) 388 { 389 u32 val; 390 391 /* disable and clear all interrupts */ 392 writel_relaxed(0, priv->base + ENA_PMU_INT); 393 writel_relaxed(~0, priv->base + RAW_PMU_INT); 394 395 writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL); 396 writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD); 397 writel_relaxed(0, priv->base + COL_SLOT_TIME); 398 399 val = RX_BQ_INT_THRESHOLD | TX_RQ_INT_THRESHOLD << QUEUE_TX_BQ_SHIFT; 400 writel_relaxed(val, priv->base + IN_QUEUE_TH); 401 402 writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH); 403 writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH); 404 405 hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM); 406 hix5hd2_set_desc_addr(priv); 407 } 408 409 static void hix5hd2_irq_enable(struct hix5hd2_priv *priv) 410 { 411 writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT); 412 } 413 414 static void hix5hd2_irq_disable(struct hix5hd2_priv *priv) 415 { 416 writel_relaxed(0, priv->base + ENA_PMU_INT); 417 } 418 419 static void hix5hd2_port_enable(struct hix5hd2_priv *priv) 420 { 421 writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA); 422 writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN); 423 } 424 425 static void hix5hd2_port_disable(struct hix5hd2_priv *priv) 426 { 427 writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN); 428 writel_relaxed(0, priv->base + DESC_WR_RD_ENA); 429 } 430 431 static void hix5hd2_hw_set_mac_addr(struct net_device *dev) 432 { 433 struct hix5hd2_priv *priv = netdev_priv(dev); 434 const unsigned char *mac = dev->dev_addr; 435 u32 val; 436 437 val = mac[1] | (mac[0] << 8); 438 writel_relaxed(val, priv->base + STATION_ADDR_HIGH); 439 440 val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24); 441 writel_relaxed(val, priv->base + STATION_ADDR_LOW); 442 } 443 444 static int hix5hd2_net_set_mac_address(struct net_device *dev, void *p) 445 { 446 int ret; 447 448 ret = eth_mac_addr(dev, p); 449 if (!ret) 450 hix5hd2_hw_set_mac_addr(dev); 451 452 return ret; 453 } 454 455 static void hix5hd2_adjust_link(struct net_device *dev) 456 { 457 struct hix5hd2_priv *priv = netdev_priv(dev); 458 struct phy_device *phy = dev->phydev; 459 460 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) { 461 hix5hd2_config_port(dev, phy->speed, phy->duplex); 462 phy_print_status(phy); 463 } 464 } 465 466 static void hix5hd2_rx_refill(struct hix5hd2_priv *priv) 467 { 468 struct hix5hd2_desc *desc; 469 struct sk_buff *skb; 470 u32 start, end, num, pos, i; 471 u32 len = MAC_MAX_FRAME_SIZE; 472 dma_addr_t addr; 473 474 /* software write pointer */ 475 start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR)); 476 /* logic read pointer */ 477 end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR)); 478 num = CIRC_SPACE(start, end, RX_DESC_NUM); 479 480 for (i = 0, pos = start; i < num; i++) { 481 if (priv->rx_skb[pos]) { 482 break; 483 } else { 484 skb = netdev_alloc_skb_ip_align(priv->netdev, len); 485 if (unlikely(skb == NULL)) 486 break; 487 } 488 489 addr = dma_map_single(priv->dev, skb->data, len, DMA_FROM_DEVICE); 490 if (dma_mapping_error(priv->dev, addr)) { 491 dev_kfree_skb_any(skb); 492 break; 493 } 494 495 desc = priv->rx_fq.desc + pos; 496 desc->buff_addr = cpu_to_le32(addr); 497 priv->rx_skb[pos] = skb; 498 desc->cmd = cpu_to_le32(DESC_VLD_FREE | 499 (len - 1) << DESC_BUFF_LEN_OFF); 500 pos = dma_ring_incr(pos, RX_DESC_NUM); 501 } 502 503 /* ensure desc updated */ 504 wmb(); 505 506 if (pos != start) 507 writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR); 508 } 509 510 static int hix5hd2_rx(struct net_device *dev, int limit) 511 { 512 struct hix5hd2_priv *priv = netdev_priv(dev); 513 struct sk_buff *skb; 514 struct hix5hd2_desc *desc; 515 dma_addr_t addr; 516 u32 start, end, num, pos, i, len; 517 518 /* software read pointer */ 519 start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR)); 520 /* logic write pointer */ 521 end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR)); 522 num = CIRC_CNT(end, start, RX_DESC_NUM); 523 if (num > limit) 524 num = limit; 525 526 /* ensure get updated desc */ 527 rmb(); 528 for (i = 0, pos = start; i < num; i++) { 529 skb = priv->rx_skb[pos]; 530 if (unlikely(!skb)) { 531 netdev_err(dev, "inconsistent rx_skb\n"); 532 break; 533 } 534 priv->rx_skb[pos] = NULL; 535 536 desc = priv->rx_bq.desc + pos; 537 len = (le32_to_cpu(desc->cmd) >> DESC_DATA_LEN_OFF) & 538 DESC_DATA_MASK; 539 addr = le32_to_cpu(desc->buff_addr); 540 dma_unmap_single(priv->dev, addr, MAC_MAX_FRAME_SIZE, 541 DMA_FROM_DEVICE); 542 543 skb_put(skb, len); 544 if (skb->len > MAC_MAX_FRAME_SIZE) { 545 netdev_err(dev, "rcv len err, len = %d\n", skb->len); 546 dev->stats.rx_errors++; 547 dev->stats.rx_length_errors++; 548 dev_kfree_skb_any(skb); 549 goto next; 550 } 551 552 skb->protocol = eth_type_trans(skb, dev); 553 napi_gro_receive(&priv->napi, skb); 554 dev->stats.rx_packets++; 555 dev->stats.rx_bytes += len; 556 next: 557 pos = dma_ring_incr(pos, RX_DESC_NUM); 558 } 559 560 if (pos != start) 561 writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR); 562 563 hix5hd2_rx_refill(priv); 564 565 return num; 566 } 567 568 static void hix5hd2_clean_sg_desc(struct hix5hd2_priv *priv, 569 struct sk_buff *skb, u32 pos) 570 { 571 struct sg_desc *desc; 572 dma_addr_t addr; 573 u32 len; 574 int i; 575 576 desc = priv->tx_ring.desc + pos; 577 578 addr = le32_to_cpu(desc->linear_addr); 579 len = le32_to_cpu(desc->linear_len); 580 dma_unmap_single(priv->dev, addr, len, DMA_TO_DEVICE); 581 582 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 583 addr = le32_to_cpu(desc->frags[i].addr); 584 len = le32_to_cpu(desc->frags[i].size); 585 dma_unmap_page(priv->dev, addr, len, DMA_TO_DEVICE); 586 } 587 } 588 589 static void hix5hd2_xmit_reclaim(struct net_device *dev) 590 { 591 struct sk_buff *skb; 592 struct hix5hd2_desc *desc; 593 struct hix5hd2_priv *priv = netdev_priv(dev); 594 unsigned int bytes_compl = 0, pkts_compl = 0; 595 u32 start, end, num, pos, i; 596 dma_addr_t addr; 597 598 netif_tx_lock(dev); 599 600 /* software read */ 601 start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR)); 602 /* logic write */ 603 end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR)); 604 num = CIRC_CNT(end, start, TX_DESC_NUM); 605 606 for (i = 0, pos = start; i < num; i++) { 607 skb = priv->tx_skb[pos]; 608 if (unlikely(!skb)) { 609 netdev_err(dev, "inconsistent tx_skb\n"); 610 break; 611 } 612 613 pkts_compl++; 614 bytes_compl += skb->len; 615 desc = priv->tx_rq.desc + pos; 616 617 if (skb_shinfo(skb)->nr_frags) { 618 hix5hd2_clean_sg_desc(priv, skb, pos); 619 } else { 620 addr = le32_to_cpu(desc->buff_addr); 621 dma_unmap_single(priv->dev, addr, skb->len, 622 DMA_TO_DEVICE); 623 } 624 625 priv->tx_skb[pos] = NULL; 626 dev_consume_skb_any(skb); 627 pos = dma_ring_incr(pos, TX_DESC_NUM); 628 } 629 630 if (pos != start) 631 writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR); 632 633 netif_tx_unlock(dev); 634 635 if (pkts_compl || bytes_compl) 636 netdev_completed_queue(dev, pkts_compl, bytes_compl); 637 638 if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl) 639 netif_wake_queue(priv->netdev); 640 } 641 642 static int hix5hd2_poll(struct napi_struct *napi, int budget) 643 { 644 struct hix5hd2_priv *priv = container_of(napi, 645 struct hix5hd2_priv, napi); 646 struct net_device *dev = priv->netdev; 647 int work_done = 0, task = budget; 648 int ints, num; 649 650 do { 651 hix5hd2_xmit_reclaim(dev); 652 num = hix5hd2_rx(dev, task); 653 work_done += num; 654 task -= num; 655 if ((work_done >= budget) || (num == 0)) 656 break; 657 658 ints = readl_relaxed(priv->base + RAW_PMU_INT); 659 writel_relaxed(ints, priv->base + RAW_PMU_INT); 660 } while (ints & DEF_INT_MASK); 661 662 if (work_done < budget) { 663 napi_complete_done(napi, work_done); 664 hix5hd2_irq_enable(priv); 665 } 666 667 return work_done; 668 } 669 670 static irqreturn_t hix5hd2_interrupt(int irq, void *dev_id) 671 { 672 struct net_device *dev = (struct net_device *)dev_id; 673 struct hix5hd2_priv *priv = netdev_priv(dev); 674 int ints = readl_relaxed(priv->base + RAW_PMU_INT); 675 676 writel_relaxed(ints, priv->base + RAW_PMU_INT); 677 if (likely(ints & DEF_INT_MASK)) { 678 hix5hd2_irq_disable(priv); 679 napi_schedule(&priv->napi); 680 } 681 682 return IRQ_HANDLED; 683 } 684 685 static u32 hix5hd2_get_desc_cmd(struct sk_buff *skb, unsigned long hw_cap) 686 { 687 u32 cmd = 0; 688 689 if (HAS_CAP_TSO(hw_cap)) { 690 if (skb_shinfo(skb)->nr_frags) 691 cmd |= DESC_SG; 692 cmd |= skb_shinfo(skb)->nr_frags << DESC_FRAGS_NUM_OFF; 693 } else { 694 cmd |= DESC_FL_FULL | 695 ((skb->len & DESC_DATA_MASK) << DESC_BUFF_LEN_OFF); 696 } 697 698 cmd |= (skb->len & DESC_DATA_MASK) << DESC_DATA_LEN_OFF; 699 cmd |= DESC_VLD_BUSY; 700 701 return cmd; 702 } 703 704 static int hix5hd2_fill_sg_desc(struct hix5hd2_priv *priv, 705 struct sk_buff *skb, u32 pos) 706 { 707 struct sg_desc *desc; 708 dma_addr_t addr; 709 int ret; 710 int i; 711 712 desc = priv->tx_ring.desc + pos; 713 714 desc->total_len = cpu_to_le32(skb->len); 715 addr = dma_map_single(priv->dev, skb->data, skb_headlen(skb), 716 DMA_TO_DEVICE); 717 if (unlikely(dma_mapping_error(priv->dev, addr))) 718 return -EINVAL; 719 desc->linear_addr = cpu_to_le32(addr); 720 desc->linear_len = cpu_to_le32(skb_headlen(skb)); 721 722 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 723 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 724 int len = skb_frag_size(frag); 725 726 addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE); 727 ret = dma_mapping_error(priv->dev, addr); 728 if (unlikely(ret)) 729 return -EINVAL; 730 desc->frags[i].addr = cpu_to_le32(addr); 731 desc->frags[i].size = cpu_to_le32(len); 732 } 733 734 return 0; 735 } 736 737 static netdev_tx_t hix5hd2_net_xmit(struct sk_buff *skb, struct net_device *dev) 738 { 739 struct hix5hd2_priv *priv = netdev_priv(dev); 740 struct hix5hd2_desc *desc; 741 dma_addr_t addr; 742 u32 pos; 743 u32 cmd; 744 int ret; 745 746 /* software write pointer */ 747 pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR)); 748 if (unlikely(priv->tx_skb[pos])) { 749 dev->stats.tx_dropped++; 750 dev->stats.tx_fifo_errors++; 751 netif_stop_queue(dev); 752 return NETDEV_TX_BUSY; 753 } 754 755 desc = priv->tx_bq.desc + pos; 756 757 cmd = hix5hd2_get_desc_cmd(skb, priv->hw_cap); 758 desc->cmd = cpu_to_le32(cmd); 759 760 if (skb_shinfo(skb)->nr_frags) { 761 ret = hix5hd2_fill_sg_desc(priv, skb, pos); 762 if (unlikely(ret)) { 763 dev_kfree_skb_any(skb); 764 dev->stats.tx_dropped++; 765 return NETDEV_TX_OK; 766 } 767 addr = priv->tx_ring.phys_addr + pos * sizeof(struct sg_desc); 768 } else { 769 addr = dma_map_single(priv->dev, skb->data, skb->len, 770 DMA_TO_DEVICE); 771 if (unlikely(dma_mapping_error(priv->dev, addr))) { 772 dev_kfree_skb_any(skb); 773 dev->stats.tx_dropped++; 774 return NETDEV_TX_OK; 775 } 776 } 777 desc->buff_addr = cpu_to_le32(addr); 778 779 priv->tx_skb[pos] = skb; 780 781 /* ensure desc updated */ 782 wmb(); 783 784 pos = dma_ring_incr(pos, TX_DESC_NUM); 785 writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR); 786 787 netif_trans_update(dev); 788 dev->stats.tx_packets++; 789 dev->stats.tx_bytes += skb->len; 790 netdev_sent_queue(dev, skb->len); 791 792 return NETDEV_TX_OK; 793 } 794 795 static void hix5hd2_free_dma_desc_rings(struct hix5hd2_priv *priv) 796 { 797 struct hix5hd2_desc *desc; 798 dma_addr_t addr; 799 int i; 800 801 for (i = 0; i < RX_DESC_NUM; i++) { 802 struct sk_buff *skb = priv->rx_skb[i]; 803 if (skb == NULL) 804 continue; 805 806 desc = priv->rx_fq.desc + i; 807 addr = le32_to_cpu(desc->buff_addr); 808 dma_unmap_single(priv->dev, addr, 809 MAC_MAX_FRAME_SIZE, DMA_FROM_DEVICE); 810 dev_kfree_skb_any(skb); 811 priv->rx_skb[i] = NULL; 812 } 813 814 for (i = 0; i < TX_DESC_NUM; i++) { 815 struct sk_buff *skb = priv->tx_skb[i]; 816 if (skb == NULL) 817 continue; 818 819 desc = priv->tx_rq.desc + i; 820 addr = le32_to_cpu(desc->buff_addr); 821 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); 822 dev_kfree_skb_any(skb); 823 priv->tx_skb[i] = NULL; 824 } 825 } 826 827 static int hix5hd2_net_open(struct net_device *dev) 828 { 829 struct hix5hd2_priv *priv = netdev_priv(dev); 830 struct phy_device *phy; 831 int ret; 832 833 ret = clk_prepare_enable(priv->mac_core_clk); 834 if (ret < 0) { 835 netdev_err(dev, "failed to enable mac core clk %d\n", ret); 836 return ret; 837 } 838 839 ret = clk_prepare_enable(priv->mac_ifc_clk); 840 if (ret < 0) { 841 clk_disable_unprepare(priv->mac_core_clk); 842 netdev_err(dev, "failed to enable mac ifc clk %d\n", ret); 843 return ret; 844 } 845 846 phy = of_phy_connect(dev, priv->phy_node, 847 &hix5hd2_adjust_link, 0, priv->phy_mode); 848 if (!phy) { 849 clk_disable_unprepare(priv->mac_ifc_clk); 850 clk_disable_unprepare(priv->mac_core_clk); 851 return -ENODEV; 852 } 853 854 phy_start(phy); 855 hix5hd2_hw_init(priv); 856 hix5hd2_rx_refill(priv); 857 858 netdev_reset_queue(dev); 859 netif_start_queue(dev); 860 napi_enable(&priv->napi); 861 862 hix5hd2_port_enable(priv); 863 hix5hd2_irq_enable(priv); 864 865 return 0; 866 } 867 868 static int hix5hd2_net_close(struct net_device *dev) 869 { 870 struct hix5hd2_priv *priv = netdev_priv(dev); 871 872 hix5hd2_port_disable(priv); 873 hix5hd2_irq_disable(priv); 874 napi_disable(&priv->napi); 875 netif_stop_queue(dev); 876 hix5hd2_free_dma_desc_rings(priv); 877 878 if (dev->phydev) { 879 phy_stop(dev->phydev); 880 phy_disconnect(dev->phydev); 881 } 882 883 clk_disable_unprepare(priv->mac_ifc_clk); 884 clk_disable_unprepare(priv->mac_core_clk); 885 886 return 0; 887 } 888 889 static void hix5hd2_tx_timeout_task(struct work_struct *work) 890 { 891 struct hix5hd2_priv *priv; 892 893 priv = container_of(work, struct hix5hd2_priv, tx_timeout_task); 894 895 rtnl_lock(); 896 if (netif_running(priv->netdev)) { 897 dev_close(priv->netdev); 898 dev_open(priv->netdev, NULL); 899 } 900 rtnl_unlock(); 901 } 902 903 static void hix5hd2_net_timeout(struct net_device *dev, unsigned int txqueue) 904 { 905 struct hix5hd2_priv *priv = netdev_priv(dev); 906 907 schedule_work(&priv->tx_timeout_task); 908 } 909 910 static const struct net_device_ops hix5hd2_netdev_ops = { 911 .ndo_open = hix5hd2_net_open, 912 .ndo_stop = hix5hd2_net_close, 913 .ndo_start_xmit = hix5hd2_net_xmit, 914 .ndo_tx_timeout = hix5hd2_net_timeout, 915 .ndo_set_mac_address = hix5hd2_net_set_mac_address, 916 }; 917 918 static const struct ethtool_ops hix5hd2_ethtools_ops = { 919 .get_link = ethtool_op_get_link, 920 .get_link_ksettings = phy_ethtool_get_link_ksettings, 921 .set_link_ksettings = phy_ethtool_set_link_ksettings, 922 }; 923 924 static int hix5hd2_mdio_wait_ready(struct mii_bus *bus) 925 { 926 struct hix5hd2_priv *priv = bus->priv; 927 void __iomem *base = priv->base; 928 int i, timeout = 10000; 929 930 for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) { 931 if (i == timeout) 932 return -ETIMEDOUT; 933 usleep_range(10, 20); 934 } 935 936 return 0; 937 } 938 939 static int hix5hd2_mdio_read(struct mii_bus *bus, int phy, int reg) 940 { 941 struct hix5hd2_priv *priv = bus->priv; 942 void __iomem *base = priv->base; 943 int val, ret; 944 945 ret = hix5hd2_mdio_wait_ready(bus); 946 if (ret < 0) 947 goto out; 948 949 writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD); 950 ret = hix5hd2_mdio_wait_ready(bus); 951 if (ret < 0) 952 goto out; 953 954 val = readl_relaxed(base + MDIO_RDATA_STATUS); 955 if (val & MDIO_R_VALID) { 956 dev_err(bus->parent, "SMI bus read not valid\n"); 957 ret = -ENODEV; 958 goto out; 959 } 960 961 val = readl_relaxed(priv->base + MDIO_SINGLE_DATA); 962 ret = (val >> 16) & 0xFFFF; 963 out: 964 return ret; 965 } 966 967 static int hix5hd2_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 968 { 969 struct hix5hd2_priv *priv = bus->priv; 970 void __iomem *base = priv->base; 971 int ret; 972 973 ret = hix5hd2_mdio_wait_ready(bus); 974 if (ret < 0) 975 goto out; 976 977 writel_relaxed(val, base + MDIO_SINGLE_DATA); 978 writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD); 979 ret = hix5hd2_mdio_wait_ready(bus); 980 out: 981 return ret; 982 } 983 984 static void hix5hd2_destroy_hw_desc_queue(struct hix5hd2_priv *priv) 985 { 986 int i; 987 988 for (i = 0; i < QUEUE_NUMS; i++) { 989 if (priv->pool[i].desc) { 990 dma_free_coherent(priv->dev, priv->pool[i].size, 991 priv->pool[i].desc, 992 priv->pool[i].phys_addr); 993 priv->pool[i].desc = NULL; 994 } 995 } 996 } 997 998 static int hix5hd2_init_hw_desc_queue(struct hix5hd2_priv *priv) 999 { 1000 struct device *dev = priv->dev; 1001 struct hix5hd2_desc *virt_addr; 1002 dma_addr_t phys_addr; 1003 int size, i; 1004 1005 priv->rx_fq.count = RX_DESC_NUM; 1006 priv->rx_bq.count = RX_DESC_NUM; 1007 priv->tx_bq.count = TX_DESC_NUM; 1008 priv->tx_rq.count = TX_DESC_NUM; 1009 1010 for (i = 0; i < QUEUE_NUMS; i++) { 1011 size = priv->pool[i].count * sizeof(struct hix5hd2_desc); 1012 virt_addr = dma_alloc_coherent(dev, size, &phys_addr, 1013 GFP_KERNEL); 1014 if (virt_addr == NULL) 1015 goto error_free_pool; 1016 1017 priv->pool[i].size = size; 1018 priv->pool[i].desc = virt_addr; 1019 priv->pool[i].phys_addr = phys_addr; 1020 } 1021 return 0; 1022 1023 error_free_pool: 1024 hix5hd2_destroy_hw_desc_queue(priv); 1025 1026 return -ENOMEM; 1027 } 1028 1029 static int hix5hd2_init_sg_desc_queue(struct hix5hd2_priv *priv) 1030 { 1031 struct sg_desc *desc; 1032 dma_addr_t phys_addr; 1033 1034 desc = dma_alloc_coherent(priv->dev, 1035 TX_DESC_NUM * sizeof(struct sg_desc), 1036 &phys_addr, GFP_KERNEL); 1037 if (!desc) 1038 return -ENOMEM; 1039 1040 priv->tx_ring.desc = desc; 1041 priv->tx_ring.phys_addr = phys_addr; 1042 1043 return 0; 1044 } 1045 1046 static void hix5hd2_destroy_sg_desc_queue(struct hix5hd2_priv *priv) 1047 { 1048 if (priv->tx_ring.desc) { 1049 dma_free_coherent(priv->dev, 1050 TX_DESC_NUM * sizeof(struct sg_desc), 1051 priv->tx_ring.desc, priv->tx_ring.phys_addr); 1052 priv->tx_ring.desc = NULL; 1053 } 1054 } 1055 1056 static inline void hix5hd2_mac_core_reset(struct hix5hd2_priv *priv) 1057 { 1058 if (!priv->mac_core_rst) 1059 return; 1060 1061 reset_control_assert(priv->mac_core_rst); 1062 reset_control_deassert(priv->mac_core_rst); 1063 } 1064 1065 static void hix5hd2_sleep_us(u32 time_us) 1066 { 1067 u32 time_ms; 1068 1069 if (!time_us) 1070 return; 1071 1072 time_ms = DIV_ROUND_UP(time_us, 1000); 1073 if (time_ms < 20) 1074 usleep_range(time_us, time_us + 500); 1075 else 1076 msleep(time_ms); 1077 } 1078 1079 static void hix5hd2_phy_reset(struct hix5hd2_priv *priv) 1080 { 1081 /* To make sure PHY hardware reset success, 1082 * we must keep PHY in deassert state first and 1083 * then complete the hardware reset operation 1084 */ 1085 reset_control_deassert(priv->phy_rst); 1086 hix5hd2_sleep_us(priv->phy_reset_delays[PRE_DELAY]); 1087 1088 reset_control_assert(priv->phy_rst); 1089 /* delay some time to ensure reset ok, 1090 * this depends on PHY hardware feature 1091 */ 1092 hix5hd2_sleep_us(priv->phy_reset_delays[PULSE]); 1093 reset_control_deassert(priv->phy_rst); 1094 /* delay some time to ensure later MDIO access */ 1095 hix5hd2_sleep_us(priv->phy_reset_delays[POST_DELAY]); 1096 } 1097 1098 static const struct of_device_id hix5hd2_of_match[]; 1099 1100 static int hix5hd2_dev_probe(struct platform_device *pdev) 1101 { 1102 struct device *dev = &pdev->dev; 1103 struct device_node *node = dev->of_node; 1104 struct net_device *ndev; 1105 struct hix5hd2_priv *priv; 1106 struct mii_bus *bus; 1107 int ret; 1108 1109 ndev = alloc_etherdev(sizeof(struct hix5hd2_priv)); 1110 if (!ndev) 1111 return -ENOMEM; 1112 1113 platform_set_drvdata(pdev, ndev); 1114 1115 priv = netdev_priv(ndev); 1116 priv->dev = dev; 1117 priv->netdev = ndev; 1118 1119 priv->hw_cap = (unsigned long)device_get_match_data(dev); 1120 1121 priv->base = devm_platform_ioremap_resource(pdev, 0); 1122 if (IS_ERR(priv->base)) { 1123 ret = PTR_ERR(priv->base); 1124 goto out_free_netdev; 1125 } 1126 1127 priv->ctrl_base = devm_platform_ioremap_resource(pdev, 1); 1128 if (IS_ERR(priv->ctrl_base)) { 1129 ret = PTR_ERR(priv->ctrl_base); 1130 goto out_free_netdev; 1131 } 1132 1133 priv->mac_core_clk = devm_clk_get(&pdev->dev, "mac_core"); 1134 if (IS_ERR(priv->mac_core_clk)) { 1135 netdev_err(ndev, "failed to get mac core clk\n"); 1136 ret = -ENODEV; 1137 goto out_free_netdev; 1138 } 1139 1140 ret = clk_prepare_enable(priv->mac_core_clk); 1141 if (ret < 0) { 1142 netdev_err(ndev, "failed to enable mac core clk %d\n", ret); 1143 goto out_free_netdev; 1144 } 1145 1146 priv->mac_ifc_clk = devm_clk_get(&pdev->dev, "mac_ifc"); 1147 if (IS_ERR(priv->mac_ifc_clk)) 1148 priv->mac_ifc_clk = NULL; 1149 1150 ret = clk_prepare_enable(priv->mac_ifc_clk); 1151 if (ret < 0) { 1152 netdev_err(ndev, "failed to enable mac ifc clk %d\n", ret); 1153 goto out_disable_mac_core_clk; 1154 } 1155 1156 priv->mac_core_rst = devm_reset_control_get(dev, "mac_core"); 1157 if (IS_ERR(priv->mac_core_rst)) 1158 priv->mac_core_rst = NULL; 1159 hix5hd2_mac_core_reset(priv); 1160 1161 priv->mac_ifc_rst = devm_reset_control_get(dev, "mac_ifc"); 1162 if (IS_ERR(priv->mac_ifc_rst)) 1163 priv->mac_ifc_rst = NULL; 1164 1165 priv->phy_rst = devm_reset_control_get(dev, "phy"); 1166 if (IS_ERR(priv->phy_rst)) { 1167 priv->phy_rst = NULL; 1168 } else { 1169 ret = of_property_read_u32_array(node, 1170 PHY_RESET_DELAYS_PROPERTY, 1171 priv->phy_reset_delays, 1172 DELAYS_NUM); 1173 if (ret) 1174 goto out_disable_clk; 1175 hix5hd2_phy_reset(priv); 1176 } 1177 1178 bus = mdiobus_alloc(); 1179 if (bus == NULL) { 1180 ret = -ENOMEM; 1181 goto out_disable_clk; 1182 } 1183 1184 bus->priv = priv; 1185 bus->name = "hix5hd2_mii_bus"; 1186 bus->read = hix5hd2_mdio_read; 1187 bus->write = hix5hd2_mdio_write; 1188 bus->parent = &pdev->dev; 1189 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); 1190 priv->bus = bus; 1191 1192 ret = of_mdiobus_register(bus, node); 1193 if (ret) 1194 goto err_free_mdio; 1195 1196 ret = of_get_phy_mode(node, &priv->phy_mode); 1197 if (ret) { 1198 netdev_err(ndev, "not find phy-mode\n"); 1199 goto err_mdiobus; 1200 } 1201 1202 priv->phy_node = of_parse_phandle(node, "phy-handle", 0); 1203 if (!priv->phy_node) { 1204 netdev_err(ndev, "not find phy-handle\n"); 1205 ret = -EINVAL; 1206 goto err_mdiobus; 1207 } 1208 1209 ndev->irq = platform_get_irq(pdev, 0); 1210 if (ndev->irq < 0) { 1211 ret = ndev->irq; 1212 goto out_phy_node; 1213 } 1214 1215 ret = devm_request_irq(dev, ndev->irq, hix5hd2_interrupt, 1216 0, pdev->name, ndev); 1217 if (ret) { 1218 netdev_err(ndev, "devm_request_irq failed\n"); 1219 goto out_phy_node; 1220 } 1221 1222 ret = of_get_ethdev_address(node, ndev); 1223 if (ret) { 1224 eth_hw_addr_random(ndev); 1225 netdev_warn(ndev, "using random MAC address %pM\n", 1226 ndev->dev_addr); 1227 } 1228 1229 INIT_WORK(&priv->tx_timeout_task, hix5hd2_tx_timeout_task); 1230 ndev->watchdog_timeo = 6 * HZ; 1231 ndev->priv_flags |= IFF_UNICAST_FLT; 1232 ndev->netdev_ops = &hix5hd2_netdev_ops; 1233 ndev->ethtool_ops = &hix5hd2_ethtools_ops; 1234 SET_NETDEV_DEV(ndev, dev); 1235 1236 if (HAS_CAP_TSO(priv->hw_cap)) 1237 ndev->hw_features |= NETIF_F_SG; 1238 1239 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 1240 ndev->vlan_features |= ndev->features; 1241 1242 ret = hix5hd2_init_hw_desc_queue(priv); 1243 if (ret) 1244 goto out_phy_node; 1245 1246 netif_napi_add(ndev, &priv->napi, hix5hd2_poll); 1247 1248 if (HAS_CAP_TSO(priv->hw_cap)) { 1249 ret = hix5hd2_init_sg_desc_queue(priv); 1250 if (ret) 1251 goto out_destroy_queue; 1252 } 1253 1254 ret = register_netdev(priv->netdev); 1255 if (ret) { 1256 netdev_err(ndev, "register_netdev failed!"); 1257 goto out_destroy_queue; 1258 } 1259 1260 clk_disable_unprepare(priv->mac_ifc_clk); 1261 clk_disable_unprepare(priv->mac_core_clk); 1262 1263 return ret; 1264 1265 out_destroy_queue: 1266 if (HAS_CAP_TSO(priv->hw_cap)) 1267 hix5hd2_destroy_sg_desc_queue(priv); 1268 netif_napi_del(&priv->napi); 1269 hix5hd2_destroy_hw_desc_queue(priv); 1270 out_phy_node: 1271 of_node_put(priv->phy_node); 1272 err_mdiobus: 1273 mdiobus_unregister(bus); 1274 err_free_mdio: 1275 mdiobus_free(bus); 1276 out_disable_clk: 1277 clk_disable_unprepare(priv->mac_ifc_clk); 1278 out_disable_mac_core_clk: 1279 clk_disable_unprepare(priv->mac_core_clk); 1280 out_free_netdev: 1281 free_netdev(ndev); 1282 1283 return ret; 1284 } 1285 1286 static void hix5hd2_dev_remove(struct platform_device *pdev) 1287 { 1288 struct net_device *ndev = platform_get_drvdata(pdev); 1289 struct hix5hd2_priv *priv = netdev_priv(ndev); 1290 1291 unregister_netdev(ndev); 1292 cancel_work_sync(&priv->tx_timeout_task); 1293 mdiobus_unregister(priv->bus); 1294 mdiobus_free(priv->bus); 1295 1296 if (HAS_CAP_TSO(priv->hw_cap)) 1297 hix5hd2_destroy_sg_desc_queue(priv); 1298 hix5hd2_destroy_hw_desc_queue(priv); 1299 of_node_put(priv->phy_node); 1300 free_netdev(ndev); 1301 } 1302 1303 static const struct of_device_id hix5hd2_of_match[] = { 1304 { .compatible = "hisilicon,hisi-gmac-v1", .data = (void *)GEMAC_V1 }, 1305 { .compatible = "hisilicon,hisi-gmac-v2", .data = (void *)GEMAC_V2 }, 1306 { .compatible = "hisilicon,hix5hd2-gmac", .data = (void *)GEMAC_V1 }, 1307 { .compatible = "hisilicon,hi3798cv200-gmac", .data = (void *)GEMAC_V2 }, 1308 { .compatible = "hisilicon,hi3516a-gmac", .data = (void *)GEMAC_V2 }, 1309 {}, 1310 }; 1311 1312 MODULE_DEVICE_TABLE(of, hix5hd2_of_match); 1313 1314 static struct platform_driver hix5hd2_dev_driver = { 1315 .driver = { 1316 .name = "hisi-gmac", 1317 .of_match_table = hix5hd2_of_match, 1318 }, 1319 .probe = hix5hd2_dev_probe, 1320 .remove = hix5hd2_dev_remove, 1321 }; 1322 1323 module_platform_driver(hix5hd2_dev_driver); 1324 1325 MODULE_DESCRIPTION("HISILICON Gigabit Ethernet MAC driver"); 1326 MODULE_LICENSE("GPL v2"); 1327 MODULE_ALIAS("platform:hisi-gmac"); 1328