1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_ETH_H 8 #define AIROHA_ETH_H 9 10 #include <linux/debugfs.h> 11 #include <linux/etherdevice.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/reset.h> 16 #include <linux/soc/airoha/airoha_offload.h> 17 #include <net/dsa.h> 18 19 #define AIROHA_MAX_NUM_GDM_PORTS 4 20 #define AIROHA_MAX_NUM_QDMA 2 21 #define AIROHA_MAX_NUM_IRQ_BANKS 4 22 #define AIROHA_MAX_DSA_PORTS 7 23 #define AIROHA_MAX_NUM_RSTS 3 24 #define AIROHA_MAX_MTU 9220 25 #define AIROHA_MAX_PACKET_SIZE 2048 26 #define AIROHA_NUM_QOS_CHANNELS 4 27 #define AIROHA_NUM_QOS_QUEUES 8 28 #define AIROHA_NUM_TX_RING 32 29 #define AIROHA_NUM_RX_RING 32 30 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \ 31 AIROHA_NUM_QOS_CHANNELS) 32 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64 33 #define AIROHA_FE_MC_MAX_VLAN_PORT 16 34 #define AIROHA_NUM_TX_IRQ 2 35 #define HW_DSCP_NUM 2048 36 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048) 37 #define TX_DSCP_NUM 1024 38 #define RX_DSCP_NUM(_n) \ 39 ((_n) == 2 ? 128 : \ 40 (_n) == 11 ? 128 : \ 41 (_n) == 15 ? 128 : \ 42 (_n) == 0 ? 1024 : 16) 43 44 #define PSE_RSV_PAGES 128 45 #define PSE_QUEUE_RSV_PAGES 64 46 47 #define QDMA_METER_IDX(_n) ((_n) & 0xff) 48 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3) 49 50 #define PPE_SRAM_NUM_ENTRIES (8 * 1024) 51 #define PPE_STATS_NUM_ENTRIES (4 * 1024) 52 #define PPE_DRAM_NUM_ENTRIES (16 * 1024) 53 #define PPE_ENTRY_SIZE 80 54 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10)) 55 56 #define MTK_HDR_LEN 4 57 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1 58 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 59 60 enum { 61 QDMA_INT_REG_IDX0, 62 QDMA_INT_REG_IDX1, 63 QDMA_INT_REG_IDX2, 64 QDMA_INT_REG_IDX3, 65 QDMA_INT_REG_IDX4, 66 QDMA_INT_REG_MAX 67 }; 68 69 enum { 70 HSGMII_LAN_7581_PCIE0_SRCPORT = 0x16, 71 HSGMII_LAN_7581_PCIE1_SRCPORT, 72 HSGMII_LAN_7581_ETH_SRCPORT, 73 HSGMII_LAN_7581_USB_SRCPORT, 74 }; 75 76 enum { 77 HSGMII_LAN_7583_ETH_SRCPORT = 0x16, 78 HSGMII_LAN_7583_PCIE_SRCPORT = 0x18, 79 HSGMII_LAN_7583_USB_SRCPORT, 80 }; 81 82 enum { 83 XSI_PCIE0_VIP_PORT_MASK = BIT(22), 84 XSI_PCIE1_VIP_PORT_MASK = BIT(23), 85 XSI_USB_VIP_PORT_MASK = BIT(25), 86 XSI_ETH_VIP_PORT_MASK = BIT(24), 87 }; 88 89 enum { 90 DEV_STATE_INITIALIZED, 91 DEV_STATE_REGISTERED, 92 }; 93 94 enum { 95 CDM_CRSN_QSEL_Q1 = 1, 96 CDM_CRSN_QSEL_Q5 = 5, 97 CDM_CRSN_QSEL_Q6 = 6, 98 CDM_CRSN_QSEL_Q15 = 15, 99 }; 100 101 enum { 102 CRSN_08 = 0x8, 103 CRSN_21 = 0x15, /* KA */ 104 CRSN_22 = 0x16, /* hit bind and force route to CPU */ 105 CRSN_24 = 0x18, 106 CRSN_25 = 0x19, 107 }; 108 109 enum airoha_gdm_index { 110 AIROHA_GDM1_IDX = 1, 111 AIROHA_GDM2_IDX = 2, 112 AIROHA_GDM3_IDX = 3, 113 AIROHA_GDM4_IDX = 4, 114 }; 115 116 enum { 117 FE_PSE_PORT_CDM1, 118 FE_PSE_PORT_GDM1, 119 FE_PSE_PORT_GDM2, 120 FE_PSE_PORT_GDM3, 121 FE_PSE_PORT_PPE1, 122 FE_PSE_PORT_CDM2, 123 FE_PSE_PORT_CDM3, 124 FE_PSE_PORT_CDM4, 125 FE_PSE_PORT_PPE2, 126 FE_PSE_PORT_GDM4, 127 FE_PSE_PORT_CDM5, 128 FE_PSE_PORT_DROP = 0xf, 129 }; 130 131 enum tx_sched_mode { 132 TC_SCH_WRR8, 133 TC_SCH_SP, 134 TC_SCH_WRR7, 135 TC_SCH_WRR6, 136 TC_SCH_WRR5, 137 TC_SCH_WRR4, 138 TC_SCH_WRR3, 139 TC_SCH_WRR2, 140 }; 141 142 enum trtcm_unit_type { 143 TRTCM_BYTE_UNIT, 144 TRTCM_PACKET_UNIT, 145 }; 146 147 enum trtcm_param_type { 148 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */ 149 TRTCM_TOKEN_RATE_MODE, 150 TRTCM_BUCKETSIZE_SHIFT_MODE, 151 TRTCM_BUCKET_COUNTER_MODE, 152 }; 153 154 enum trtcm_mode_type { 155 TRTCM_COMMIT_MODE, 156 TRTCM_PEAK_MODE, 157 }; 158 159 enum trtcm_param { 160 TRTCM_TICK_SEL = BIT(0), 161 TRTCM_PKT_MODE = BIT(1), 162 TRTCM_METER_MODE = BIT(2), 163 }; 164 165 #define MIN_TOKEN_SIZE 4096 166 #define MAX_TOKEN_SIZE_OFFSET 17 167 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6) 168 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0) 169 170 struct airoha_queue_entry { 171 union { 172 void *buf; 173 struct { 174 struct list_head list; 175 struct sk_buff *skb; 176 }; 177 }; 178 dma_addr_t dma_addr; 179 u16 dma_len; 180 }; 181 182 struct airoha_queue { 183 struct airoha_qdma *qdma; 184 185 /* protect concurrent queue accesses */ 186 spinlock_t lock; 187 struct airoha_queue_entry *entry; 188 struct airoha_qdma_desc *desc; 189 u16 head; 190 u16 tail; 191 192 int queued; 193 int ndesc; 194 int free_thr; 195 int buf_size; 196 197 struct napi_struct napi; 198 struct page_pool *page_pool; 199 struct sk_buff *skb; 200 201 struct list_head tx_list; 202 }; 203 204 struct airoha_tx_irq_queue { 205 struct airoha_qdma *qdma; 206 207 struct napi_struct napi; 208 209 int size; 210 u32 *q; 211 }; 212 213 struct airoha_hw_stats { 214 /* protect concurrent hw_stats accesses */ 215 spinlock_t lock; 216 struct u64_stats_sync syncp; 217 218 /* get_stats64 */ 219 u64 rx_ok_pkts; 220 u64 tx_ok_pkts; 221 u64 rx_ok_bytes; 222 u64 tx_ok_bytes; 223 u64 rx_multicast; 224 u64 rx_errors; 225 u64 rx_drops; 226 u64 tx_drops; 227 u64 rx_crc_error; 228 u64 rx_over_errors; 229 /* ethtool stats */ 230 u64 tx_broadcast; 231 u64 tx_multicast; 232 u64 tx_len[7]; 233 u64 rx_broadcast; 234 u64 rx_fragment; 235 u64 rx_jabber; 236 u64 rx_len[7]; 237 }; 238 239 enum { 240 AIROHA_FOE_STATE_INVALID, 241 AIROHA_FOE_STATE_UNBIND, 242 AIROHA_FOE_STATE_BIND, 243 AIROHA_FOE_STATE_FIN 244 }; 245 246 enum { 247 PPE_PKT_TYPE_IPV4_HNAPT = 0, 248 PPE_PKT_TYPE_IPV4_ROUTE = 1, 249 PPE_PKT_TYPE_BRIDGE = 2, 250 PPE_PKT_TYPE_IPV4_DSLITE = 3, 251 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, 252 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, 253 PPE_PKT_TYPE_IPV6_6RD = 7, 254 }; 255 256 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16) 257 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0) 258 259 #define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12) 260 #define AIROHA_FOE_MAC_WDMA_BAND BIT(11) 261 #define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0) 262 263 struct airoha_foe_mac_info_common { 264 u16 vlan1; 265 u16 etype; 266 267 u32 dest_mac_hi; 268 269 u16 vlan2; 270 u16 dest_mac_lo; 271 272 u32 src_mac_hi; 273 }; 274 275 struct airoha_foe_mac_info { 276 struct airoha_foe_mac_info_common common; 277 278 u16 pppoe_id; 279 u16 src_mac_lo; 280 281 u32 meter; 282 }; 283 284 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24) 285 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) 286 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) 287 288 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31) 289 #define AIROHA_FOE_IB1_BIND_UDP BIT(30) 290 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28) 291 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25) 292 #define AIROHA_FOE_IB1_BIND_TTL BIT(24) 293 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) 294 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22) 295 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20) 296 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16) 297 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15) 298 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) 299 300 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24) 301 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13) 302 #define AIROHA_FOE_IB2_PCP BIT(12) 303 #define AIROHA_FOE_IB2_MULTICAST BIT(11) 304 #define AIROHA_FOE_IB2_FAST_PATH BIT(10) 305 #define AIROHA_FOE_IB2_PSE_QOS BIT(9) 306 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5) 307 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0) 308 309 #define AIROHA_FOE_ACTDP GENMASK(31, 24) 310 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16) 311 #define AIROHA_FOE_CHANNEL GENMASK(15, 11) 312 #define AIROHA_FOE_QID GENMASK(10, 8) 313 #define AIROHA_FOE_DPI BIT(7) 314 #define AIROHA_FOE_TUNNEL BIT(6) 315 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0) 316 317 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16) 318 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9) 319 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5) 320 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0) 321 322 struct airoha_foe_bridge { 323 u32 dest_mac_hi; 324 325 u16 src_mac_hi; 326 u16 dest_mac_lo; 327 328 u32 src_mac_lo; 329 330 u32 ib2; 331 332 u32 rsv[5]; 333 334 u32 data; 335 336 struct airoha_foe_mac_info l2; 337 }; 338 339 struct airoha_foe_ipv4_tuple { 340 u32 src_ip; 341 u32 dest_ip; 342 union { 343 struct { 344 u16 dest_port; 345 u16 src_port; 346 }; 347 struct { 348 u8 protocol; 349 u8 _pad[3]; /* fill with 0xa5a5a5 */ 350 }; 351 u32 ports; 352 }; 353 }; 354 355 struct airoha_foe_ipv4 { 356 struct airoha_foe_ipv4_tuple orig_tuple; 357 358 u32 ib2; 359 360 struct airoha_foe_ipv4_tuple new_tuple; 361 362 u32 rsv[2]; 363 364 u32 data; 365 366 struct airoha_foe_mac_info l2; 367 }; 368 369 struct airoha_foe_ipv4_dslite { 370 struct airoha_foe_ipv4_tuple ip4; 371 372 u32 ib2; 373 374 u8 flow_label[3]; 375 u8 priority; 376 377 u32 rsv[4]; 378 379 u32 data; 380 381 struct airoha_foe_mac_info l2; 382 }; 383 384 struct airoha_foe_ipv6 { 385 u32 src_ip[4]; 386 u32 dest_ip[4]; 387 388 union { 389 struct { 390 u16 dest_port; 391 u16 src_port; 392 }; 393 struct { 394 u8 protocol; 395 u8 pad[3]; 396 }; 397 u32 ports; 398 }; 399 400 u32 data; 401 402 u32 ib2; 403 404 struct airoha_foe_mac_info_common l2; 405 406 u32 meter; 407 }; 408 409 struct airoha_foe_entry { 410 union { 411 struct { 412 u32 ib1; 413 union { 414 struct airoha_foe_bridge bridge; 415 struct airoha_foe_ipv4 ipv4; 416 struct airoha_foe_ipv4_dslite dslite; 417 struct airoha_foe_ipv6 ipv6; 418 DECLARE_FLEX_ARRAY(u32, d); 419 }; 420 }; 421 u8 data[PPE_ENTRY_SIZE]; 422 }; 423 }; 424 425 struct airoha_foe_stats { 426 u32 bytes; 427 u32 packets; 428 }; 429 430 struct airoha_foe_stats64 { 431 u64 bytes; 432 u64 packets; 433 }; 434 435 struct airoha_flow_data { 436 struct ethhdr eth; 437 438 union { 439 struct { 440 __be32 src_addr; 441 __be32 dst_addr; 442 } v4; 443 444 struct { 445 struct in6_addr src_addr; 446 struct in6_addr dst_addr; 447 } v6; 448 }; 449 450 __be16 src_port; 451 __be16 dst_port; 452 453 struct { 454 struct { 455 u16 id; 456 __be16 proto; 457 } hdr[2]; 458 u8 num; 459 } vlan; 460 struct { 461 u16 sid; 462 u8 num; 463 } pppoe; 464 }; 465 466 enum airoha_flow_entry_type { 467 FLOW_TYPE_L4, 468 FLOW_TYPE_L2, 469 FLOW_TYPE_L2_SUBFLOW, 470 }; 471 472 struct airoha_flow_table_entry { 473 union { 474 struct hlist_node list; /* PPE L3 flow entry */ 475 struct { 476 struct rhash_head l2_node; /* L2 flow entry */ 477 struct hlist_head l2_flows; /* PPE L2 subflows list */ 478 }; 479 }; 480 481 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */ 482 u32 hash; 483 484 struct airoha_foe_stats64 stats; 485 enum airoha_flow_entry_type type; 486 487 struct rhash_head node; 488 unsigned long cookie; 489 490 /* Must be last --ends in a flexible-array member. */ 491 struct airoha_foe_entry data; 492 }; 493 494 struct airoha_wdma_info { 495 u8 idx; 496 u8 queue; 497 u16 wcid; 498 u8 bss; 499 }; 500 501 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */ 502 #define RX_IRQ0_BANK_PIN_MASK 0x839f 503 #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000 504 #define RX_IRQ2_BANK_PIN_MASK 0x20 505 #define RX_IRQ3_BANK_PIN_MASK 0x40 506 #define RX_IRQ_BANK_PIN_MASK(_n) \ 507 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \ 508 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \ 509 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \ 510 RX_IRQ0_BANK_PIN_MASK) 511 512 struct airoha_irq_bank { 513 struct airoha_qdma *qdma; 514 515 /* protect concurrent irqmask accesses */ 516 spinlock_t irq_lock; 517 u32 irqmask[QDMA_INT_REG_MAX]; 518 int irq; 519 }; 520 521 struct airoha_qdma { 522 struct airoha_eth *eth; 523 void __iomem *regs; 524 525 atomic_t users; 526 527 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS]; 528 529 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 530 531 struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; 532 struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; 533 }; 534 535 struct airoha_gdm_port { 536 struct airoha_qdma *qdma; 537 struct airoha_eth *eth; 538 struct net_device *dev; 539 int id; 540 int nbq; 541 542 struct airoha_hw_stats stats; 543 544 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); 545 546 /* qos stats counters */ 547 u64 cpu_tx_packets; 548 u64 fwd_tx_packets; 549 550 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; 551 }; 552 553 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16) 554 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0) 555 556 struct airoha_ppe { 557 struct airoha_ppe_dev dev; 558 struct airoha_eth *eth; 559 560 void *foe; 561 dma_addr_t foe_dma; 562 563 struct rhashtable l2_flows; 564 565 struct hlist_head *foe_flow; 566 u16 *foe_check_time; 567 568 struct airoha_foe_stats *foe_stats; 569 dma_addr_t foe_stats_dma; 570 571 struct dentry *debugfs_dir; 572 }; 573 574 struct airoha_eth_soc_data { 575 u16 version; 576 const char * const *xsi_rsts_names; 577 int num_xsi_rsts; 578 int num_ppe; 579 struct { 580 int (*get_src_port_id)(struct airoha_gdm_port *port, int nbq); 581 u32 (*get_vip_port)(struct airoha_gdm_port *port, int nbq); 582 } ops; 583 }; 584 585 struct airoha_eth { 586 struct device *dev; 587 588 const struct airoha_eth_soc_data *soc; 589 590 unsigned long state; 591 void __iomem *fe_regs; 592 593 struct airoha_npu __rcu *npu; 594 595 struct airoha_ppe *ppe; 596 struct rhashtable flow_table; 597 598 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS]; 599 struct reset_control_bulk_data *xsi_rsts; 600 601 struct net_device *napi_dev; 602 603 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; 604 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; 605 }; 606 607 u32 airoha_rr(void __iomem *base, u32 offset); 608 void airoha_wr(void __iomem *base, u32 offset, u32 val); 609 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 610 611 #define airoha_fe_rr(eth, offset) \ 612 airoha_rr((eth)->fe_regs, (offset)) 613 #define airoha_fe_wr(eth, offset, val) \ 614 airoha_wr((eth)->fe_regs, (offset), (val)) 615 #define airoha_fe_rmw(eth, offset, mask, val) \ 616 airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) 617 #define airoha_fe_set(eth, offset, val) \ 618 airoha_rmw((eth)->fe_regs, (offset), 0, (val)) 619 #define airoha_fe_clear(eth, offset, val) \ 620 airoha_rmw((eth)->fe_regs, (offset), (val), 0) 621 622 #define airoha_qdma_rr(qdma, offset) \ 623 airoha_rr((qdma)->regs, (offset)) 624 #define airoha_qdma_wr(qdma, offset, val) \ 625 airoha_wr((qdma)->regs, (offset), (val)) 626 #define airoha_qdma_rmw(qdma, offset, mask, val) \ 627 airoha_rmw((qdma)->regs, (offset), (mask), (val)) 628 #define airoha_qdma_set(qdma, offset, val) \ 629 airoha_rmw((qdma)->regs, (offset), 0, (val)) 630 #define airoha_qdma_clear(qdma, offset, val) \ 631 airoha_rmw((qdma)->regs, (offset), (val), 0) 632 633 static inline bool airoha_is_lan_gdm_port(struct airoha_gdm_port *port) 634 { 635 /* GDM1 port on EN7581 SoC is connected to the lan dsa switch. 636 * GDM{2,3,4} can be used as wan port connected to an external 637 * phy module. 638 */ 639 return port->id == 1; 640 } 641 642 static inline bool airoha_is_7581(struct airoha_eth *eth) 643 { 644 return eth->soc->version == 0x7581; 645 } 646 647 static inline bool airoha_is_7583(struct airoha_eth *eth) 648 { 649 return eth->soc->version == 0x7583; 650 } 651 652 int airoha_get_fe_port(struct airoha_gdm_port *port); 653 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 654 struct airoha_gdm_port *port); 655 656 void airoha_ppe_set_cpu_port(struct airoha_gdm_port *port, u8 ppe_id); 657 bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index); 658 void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb, 659 u16 hash, bool rx_wlan); 660 int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data); 661 int airoha_ppe_init(struct airoha_eth *eth); 662 void airoha_ppe_deinit(struct airoha_eth *eth); 663 void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port); 664 u32 airoha_ppe_get_total_num_entries(struct airoha_ppe *ppe); 665 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe, 666 u32 hash); 667 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash, 668 struct airoha_foe_stats64 *stats); 669 670 #ifdef CONFIG_DEBUG_FS 671 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe); 672 #else 673 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) 674 { 675 return 0; 676 } 677 #endif 678 679 #endif /* AIROHA_ETH_H */ 680