xref: /linux/drivers/gpu/drm/tve200/tve200_drm.h (revision 976e3645923bdd2fe7893aae33fd7a21098bfb28)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
4  * Parts of this file were based on sources as follows:
5  *
6  * Copyright (C) 2006-2008 Intel Corporation
7  * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com>
8  * Copyright (C) 2007 Dave Airlie <airlied@linux.ie>
9  * Copyright (C) 2011 Texas Instruments
10  * Copyright (C) 2017 Eric Anholt
11  */
12 
13 #ifndef _TVE200_DRM_H_
14 #define _TVE200_DRM_H_
15 
16 #include <linux/irqreturn.h>
17 
18 #include <drm/drm_simple_kms_helper.h>
19 
20 struct clk;
21 struct drm_bridge;
22 struct drm_connector;
23 struct drm_device;
24 struct drm_file;
25 struct drm_mode_create_dumb;
26 struct drm_panel;
27 
28 /* Bits 2-31 are valid physical base addresses */
29 #define TVE200_Y_FRAME_BASE_ADDR	0x00
30 #define TVE200_U_FRAME_BASE_ADDR	0x04
31 #define TVE200_V_FRAME_BASE_ADDR	0x08
32 
33 #define TVE200_INT_EN			0x0C
34 #define TVE200_INT_CLR			0x10
35 #define TVE200_INT_STAT			0x14
36 #define TVE200_INT_BUS_ERR		BIT(7)
37 #define TVE200_INT_V_STATUS		BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME		BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME		BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME		BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN	BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN	BIT(1)
43 #define TVE200_INT_Y_FIFO_UNDERRUN	BIT(0)
44 #define TVE200_FIFO_UNDERRUNS		(TVE200_INT_V_FIFO_UNDERRUN | \
45 					 TVE200_INT_U_FIFO_UNDERRUN | \
46 					 TVE200_INT_Y_FIFO_UNDERRUN)
47 
48 #define TVE200_CTRL			0x18
49 #define TVE200_CTRL_YUV420		BIT(31)
50 #define TVE200_CTRL_CSMODE		BIT(30)
51 #define TVE200_CTRL_NONINTERLACE	BIT(28) /* 0 = non-interlace CCIR656 */
52 #define TVE200_CTRL_TVCLKP		BIT(27) /* Inverted clock phase */
53 /* Bits 24..26 define the burst size after arbitration on the bus */
54 #define TVE200_CTRL_BURST_4_WORDS	(0 << 24)
55 #define TVE200_CTRL_BURST_8_WORDS	(1 << 24)
56 #define TVE200_CTRL_BURST_16_WORDS	(2 << 24)
57 #define TVE200_CTRL_BURST_32_WORDS	(3 << 24)
58 #define TVE200_CTRL_BURST_64_WORDS	(4 << 24)
59 #define TVE200_CTRL_BURST_128_WORDS	(5 << 24)
60 #define TVE200_CTRL_BURST_256_WORDS	(6 << 24)
61 #define TVE200_CTRL_BURST_0_WORDS	(7 << 24) /* ? */
62 /*
63  * Bits 16..23 is the retry count*16 before issueing a new AHB transfer
64  * on the AHB bus.
65  */
66 #define TVE200_CTRL_RETRYCNT_MASK	GENMASK(23, 16)
67 #define TVE200_CTRL_RETRYCNT_16		(1 << 16)
68 #define TVE200_CTRL_BBBP		BIT(15) /* 0 = little-endian */
69 /* Bits 12..14 define the YCbCr ordering */
70 #define TVE200_CTRL_YCBCRODR_CB0Y0CR0Y1	(0 << 12)
71 #define TVE200_CTRL_YCBCRODR_Y0CB0Y1CR0	(1 << 12)
72 #define TVE200_CTRL_YCBCRODR_CR0Y0CB0Y1	(2 << 12)
73 #define TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0	(3 << 12)
74 #define TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0	(4 << 12)
75 #define TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0	(5 << 12)
76 #define TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0	(6 << 12)
77 #define TVE200_CTRL_YCBCRODR_Y0CR0Y1CB0	(7 << 12)
78 /* Bits 10..11 define the input resolution (framebuffer size) */
79 #define TVE200_CTRL_IPRESOL_CIF		(0 << 10)
80 #define TVE200_CTRL_IPRESOL_VGA		(1 << 10)
81 #define TVE200_CTRL_IPRESOL_D1		(2 << 10)
82 #define TVE200_CTRL_NTSC		BIT(9) /* 0 = PAL, 1 = NTSC */
83 #define TVE200_CTRL_INTERLACE		BIT(8) /* 1 = interlace, only for D1 */
84 #define TVE200_IPDMOD_RGB555		(0 << 6) /* TVE200_CTRL_YUV420 = 0 */
85 #define TVE200_IPDMOD_RGB565		(1 << 6)
86 #define TVE200_IPDMOD_RGB888		(2 << 6)
87 #define TVE200_IPDMOD_YUV420		(2 << 6) /* TVE200_CTRL_YUV420 = 1 */
88 #define TVE200_IPDMOD_YUV422		(3 << 6)
89 /* Bits 4 & 5 define when to fire the vblank IRQ */
90 #define TVE200_VSTSTYPE_VSYNC		(0 << 4) /* start of vsync */
91 #define TVE200_VSTSTYPE_VBP		(1 << 4) /* start of v back porch */
92 #define TVE200_VSTSTYPE_VAI		(2 << 4) /* start of v active image */
93 #define TVE200_VSTSTYPE_VFP		(3 << 4) /* start of v front porch */
94 #define TVE200_VSTSTYPE_BITS		(BIT(4) | BIT(5))
95 #define TVE200_BGR			BIT(1) /* 0 = RGB, 1 = BGR */
96 #define TVE200_TVEEN			BIT(0) /* Enable TVE block */
97 
98 #define TVE200_CTRL_2			0x1c
99 #define TVE200_CTRL_3			0x20
100 
101 #define TVE200_CTRL_4			0x24
102 #define TVE200_CTRL_4_RESET		BIT(0) /* triggers reset of TVE200 */
103 
104 struct tve200_drm_dev_private {
105 	struct drm_device *drm;
106 
107 	struct drm_connector *connector;
108 	struct drm_panel *panel;
109 	struct drm_bridge *bridge;
110 	struct drm_simple_display_pipe pipe;
111 
112 	void *regs;
113 	struct clk *pclk;
114 	struct clk *clk;
115 };
116 
117 #define to_tve200_connector(x) \
118 	container_of(x, struct tve200_drm_connector, connector)
119 
120 int tve200_display_init(struct drm_device *dev);
121 irqreturn_t tve200_irq(int irq, void *data);
122 int tve200_connector_init(struct drm_device *dev);
123 int tve200_encoder_init(struct drm_device *dev);
124 int tve200_dumb_create(struct drm_file *file_priv,
125 		      struct drm_device *dev,
126 		      struct drm_mode_create_dumb *args);
127 
128 #endif /* _TVE200_DRM_H_ */
129