1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _SMU73_DISCRETE_H_ 24 #define _SMU73_DISCRETE_H_ 25 26 #include "smu73.h" 27 28 #pragma pack(push, 1) 29 30 struct SMIO_Pattern { 31 uint16_t Voltage; 32 uint8_t Smio; 33 uint8_t padding; 34 }; 35 36 typedef struct SMIO_Pattern SMIO_Pattern; 37 38 struct SMIO_Table { 39 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 40 }; 41 42 typedef struct SMIO_Table SMIO_Table; 43 44 struct SMU73_Discrete_GraphicsLevel { 45 uint32_t MinVoltage; 46 47 uint32_t SclkFrequency; 48 49 uint8_t pcieDpmLevel; 50 uint8_t DeepSleepDivId; 51 uint16_t ActivityLevel; 52 uint32_t CgSpllFuncCntl3; 53 uint32_t CgSpllFuncCntl4; 54 uint32_t SpllSpreadSpectrum; 55 uint32_t SpllSpreadSpectrum2; 56 uint32_t CcPwrDynRm; 57 uint32_t CcPwrDynRm1; 58 uint8_t SclkDid; 59 uint8_t DisplayWatermark; 60 uint8_t EnabledForActivity; 61 uint8_t EnabledForThrottle; 62 uint8_t UpHyst; 63 uint8_t DownHyst; 64 uint8_t VoltageDownHyst; 65 uint8_t PowerThrottle; 66 }; 67 68 typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel; 69 70 struct SMU73_Discrete_ACPILevel { 71 uint32_t Flags; 72 uint32_t MinVoltage; 73 uint32_t SclkFrequency; 74 uint8_t SclkDid; 75 uint8_t DisplayWatermark; 76 uint8_t DeepSleepDivId; 77 uint8_t padding; 78 uint32_t CgSpllFuncCntl; 79 uint32_t CgSpllFuncCntl2; 80 uint32_t CgSpllFuncCntl3; 81 uint32_t CgSpllFuncCntl4; 82 uint32_t SpllSpreadSpectrum; 83 uint32_t SpllSpreadSpectrum2; 84 uint32_t CcPwrDynRm; 85 uint32_t CcPwrDynRm1; 86 }; 87 88 typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel; 89 90 struct SMU73_Discrete_Ulv { 91 uint32_t CcPwrDynRm; 92 uint32_t CcPwrDynRm1; 93 uint16_t VddcOffset; 94 uint8_t VddcOffsetVid; 95 uint8_t VddcPhase; 96 uint32_t Reserved; 97 }; 98 99 typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv; 100 101 struct SMU73_Discrete_MemoryLevel { 102 uint32_t MinVoltage; 103 uint32_t MinMvdd; 104 105 uint32_t MclkFrequency; 106 107 uint8_t StutterEnable; 108 uint8_t FreqRange; 109 uint8_t EnabledForThrottle; 110 uint8_t EnabledForActivity; 111 112 uint8_t UpHyst; 113 uint8_t DownHyst; 114 uint8_t VoltageDownHyst; 115 uint8_t padding; 116 117 uint16_t ActivityLevel; 118 uint8_t DisplayWatermark; 119 uint8_t MclkDivider; 120 }; 121 122 typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel; 123 124 struct SMU73_Discrete_LinkLevel { 125 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 126 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 127 uint8_t EnabledForActivity; 128 uint8_t SPC; 129 uint32_t DownThreshold; 130 uint32_t UpThreshold; 131 uint32_t Reserved; 132 }; 133 134 typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel; 135 136 137 // MC ARB DRAM Timing registers. 138 struct SMU73_Discrete_MCArbDramTimingTableEntry { 139 uint32_t McArbDramTiming; 140 uint32_t McArbDramTiming2; 141 uint8_t McArbBurstTime; 142 uint8_t TRRDS; 143 uint8_t TRRDL; 144 uint8_t padding; 145 }; 146 147 typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry; 148 149 struct SMU73_Discrete_MCArbDramTimingTable { 150 SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 151 }; 152 153 typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable; 154 155 // UVD VCLK/DCLK state (level) definition. 156 struct SMU73_Discrete_UvdLevel { 157 uint32_t VclkFrequency; 158 uint32_t DclkFrequency; 159 uint32_t MinVoltage; 160 uint8_t VclkDivider; 161 uint8_t DclkDivider; 162 uint8_t padding[2]; 163 }; 164 165 typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel; 166 167 // Clocks for other external blocks (VCE, ACP, SAMU). 168 struct SMU73_Discrete_ExtClkLevel { 169 uint32_t Frequency; 170 uint32_t MinVoltage; 171 uint8_t Divider; 172 uint8_t padding[3]; 173 }; 174 175 typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel; 176 177 struct SMU73_Discrete_StateInfo { 178 uint32_t SclkFrequency; 179 uint32_t MclkFrequency; 180 uint32_t VclkFrequency; 181 uint32_t DclkFrequency; 182 uint32_t SamclkFrequency; 183 uint32_t AclkFrequency; 184 uint32_t EclkFrequency; 185 uint16_t MvddVoltage; 186 uint16_t padding16; 187 uint8_t DisplayWatermark; 188 uint8_t McArbIndex; 189 uint8_t McRegIndex; 190 uint8_t SeqIndex; 191 uint8_t SclkDid; 192 int8_t SclkIndex; 193 int8_t MclkIndex; 194 uint8_t PCIeGen; 195 196 }; 197 198 typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo; 199 200 struct SMU73_Discrete_DpmTable { 201 // Multi-DPM controller settings 202 SMU73_PIDController GraphicsPIDController; 203 SMU73_PIDController MemoryPIDController; 204 SMU73_PIDController LinkPIDController; 205 206 uint32_t SystemFlags; 207 208 // SMIO masks for voltage and phase controls 209 uint32_t VRConfig; 210 uint32_t SmioMask1; 211 uint32_t SmioMask2; 212 SMIO_Table SmioTable1; 213 SMIO_Table SmioTable2; 214 215 uint32_t MvddLevelCount; 216 217 218 uint8_t BapmVddcVidHiSidd[SMU73_MAX_LEVELS_VDDC]; 219 uint8_t BapmVddcVidLoSidd[SMU73_MAX_LEVELS_VDDC]; 220 uint8_t BapmVddcVidHiSidd2[SMU73_MAX_LEVELS_VDDC]; 221 222 uint8_t GraphicsDpmLevelCount; 223 uint8_t MemoryDpmLevelCount; 224 uint8_t LinkLevelCount; 225 uint8_t MasterDeepSleepControl; 226 227 uint8_t UvdLevelCount; 228 uint8_t VceLevelCount; 229 uint8_t AcpLevelCount; 230 uint8_t SamuLevelCount; 231 232 uint8_t ThermOutGpio; 233 uint8_t ThermOutPolarity; 234 uint8_t ThermOutMode; 235 uint8_t BootPhases; 236 uint32_t Reserved[4]; 237 238 // State table entries for each DPM state 239 SMU73_Discrete_GraphicsLevel GraphicsLevel[SMU73_MAX_LEVELS_GRAPHICS]; 240 SMU73_Discrete_MemoryLevel MemoryACPILevel; 241 SMU73_Discrete_MemoryLevel MemoryLevel[SMU73_MAX_LEVELS_MEMORY]; 242 SMU73_Discrete_LinkLevel LinkLevel[SMU73_MAX_LEVELS_LINK]; 243 SMU73_Discrete_ACPILevel ACPILevel; 244 SMU73_Discrete_UvdLevel UvdLevel[SMU73_MAX_LEVELS_UVD]; 245 SMU73_Discrete_ExtClkLevel VceLevel[SMU73_MAX_LEVELS_VCE]; 246 SMU73_Discrete_ExtClkLevel AcpLevel[SMU73_MAX_LEVELS_ACP]; 247 SMU73_Discrete_ExtClkLevel SamuLevel[SMU73_MAX_LEVELS_SAMU]; 248 SMU73_Discrete_Ulv Ulv; 249 250 uint32_t SclkStepSize; 251 uint32_t Smio[SMU73_MAX_ENTRIES_SMIO]; 252 253 uint8_t UvdBootLevel; 254 uint8_t VceBootLevel; 255 uint8_t AcpBootLevel; 256 uint8_t SamuBootLevel; 257 258 uint8_t GraphicsBootLevel; 259 uint8_t GraphicsVoltageChangeEnable; 260 uint8_t GraphicsThermThrottleEnable; 261 uint8_t GraphicsInterval; 262 263 uint8_t VoltageInterval; 264 uint8_t ThermalInterval; 265 uint16_t TemperatureLimitHigh; 266 267 uint16_t TemperatureLimitLow; 268 uint8_t MemoryBootLevel; 269 uint8_t MemoryVoltageChangeEnable; 270 271 uint16_t BootMVdd; 272 uint8_t MemoryInterval; 273 uint8_t MemoryThermThrottleEnable; 274 275 uint16_t VoltageResponseTime; 276 uint16_t PhaseResponseTime; 277 278 uint8_t PCIeBootLinkLevel; 279 uint8_t PCIeGenInterval; 280 uint8_t DTEInterval; 281 uint8_t DTEMode; 282 283 uint8_t SVI2Enable; 284 uint8_t VRHotGpio; 285 uint8_t AcDcGpio; 286 uint8_t ThermGpio; 287 288 uint16_t PPM_PkgPwrLimit; 289 uint16_t PPM_TemperatureLimit; 290 291 uint16_t DefaultTdp; 292 uint16_t TargetTdp; 293 294 uint16_t FpsHighThreshold; 295 uint16_t FpsLowThreshold; 296 297 uint16_t TemperatureLimitEdge; 298 uint16_t TemperatureLimitHotspot; 299 uint16_t TemperatureLimitLiquid1; 300 uint16_t TemperatureLimitLiquid2; 301 uint16_t TemperatureLimitVrVddc; 302 uint16_t TemperatureLimitVrMvdd; 303 uint16_t TemperatureLimitPlx; 304 305 uint16_t FanGainEdge; 306 uint16_t FanGainHotspot; 307 uint16_t FanGainLiquid; 308 uint16_t FanGainVrVddc; 309 uint16_t FanGainVrMvdd; 310 uint16_t FanGainPlx; 311 uint16_t FanGainHbm; 312 313 uint8_t Liquid1_I2C_address; 314 uint8_t Liquid2_I2C_address; 315 uint8_t Vr_I2C_address; 316 uint8_t Plx_I2C_address; 317 318 uint8_t GeminiMode; 319 uint8_t spare17[3]; 320 uint32_t GeminiApertureHigh; 321 uint32_t GeminiApertureLow; 322 323 uint8_t Liquid_I2C_LineSCL; 324 uint8_t Liquid_I2C_LineSDA; 325 uint8_t Vr_I2C_LineSCL; 326 uint8_t Vr_I2C_LineSDA; 327 uint8_t Plx_I2C_LineSCL; 328 uint8_t Plx_I2C_LineSDA; 329 330 uint8_t spare1253[2]; 331 uint32_t spare123[2]; 332 333 uint8_t DTEAmbientTempBase; 334 uint8_t DTETjOffset; 335 uint8_t GpuTjMax; 336 uint8_t GpuTjHyst; 337 338 uint16_t BootVddc; 339 uint16_t BootVddci; 340 341 uint32_t BAPM_TEMP_GRADIENT; 342 343 uint32_t LowSclkInterruptThreshold; 344 uint32_t VddGfxReChkWait; 345 346 uint8_t ClockStretcherAmount; 347 uint8_t Sclk_CKS_masterEn0_7; 348 uint8_t Sclk_CKS_masterEn8_15; 349 uint8_t DPMFreezeAndForced; 350 351 uint8_t Sclk_voltageOffset[8]; 352 353 SMU_ClockStretcherDataTable ClockStretcherDataTable; 354 SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 355 }; 356 357 typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable; 358 359 360 // --------------------------------------------------- Fan Table ----------------------------------------------------------- 361 struct SMU73_Discrete_FanTable { 362 uint16_t FdoMode; 363 int16_t TempMin; 364 int16_t TempMed; 365 int16_t TempMax; 366 int16_t Slope1; 367 int16_t Slope2; 368 int16_t FdoMin; 369 int16_t HystUp; 370 int16_t HystDown; 371 int16_t HystSlope; 372 int16_t TempRespLim; 373 int16_t TempCurr; 374 int16_t SlopeCurr; 375 int16_t PwmCurr; 376 uint32_t RefreshPeriod; 377 int16_t FdoMax; 378 uint8_t TempSrc; 379 int8_t Padding; 380 }; 381 382 typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable; 383 384 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 385 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 386 387 388 389 struct SMU7_MclkDpmScoreboard { 390 391 uint32_t PercentageBusy; 392 393 int32_t PIDError; 394 int32_t PIDIntegral; 395 int32_t PIDOutput; 396 397 uint32_t SigmaDeltaAccum; 398 uint32_t SigmaDeltaOutput; 399 uint32_t SigmaDeltaLevel; 400 401 uint32_t UtilizationSetpoint; 402 403 uint8_t TdpClampMode; 404 uint8_t TdcClampMode; 405 uint8_t ThermClampMode; 406 uint8_t VoltageBusy; 407 408 int8_t CurrLevel; 409 int8_t TargLevel; 410 uint8_t LevelChangeInProgress; 411 uint8_t UpHyst; 412 413 uint8_t DownHyst; 414 uint8_t VoltageDownHyst; 415 uint8_t DpmEnable; 416 uint8_t DpmRunning; 417 418 uint8_t DpmForce; 419 uint8_t DpmForceLevel; 420 uint8_t DisplayWatermark; 421 uint8_t McArbIndex; 422 423 uint32_t MinimumPerfMclk; 424 425 uint8_t AcpiReq; 426 uint8_t AcpiAck; 427 uint8_t MclkSwitchInProgress; 428 uint8_t MclkSwitchCritical; 429 430 uint8_t IgnoreVBlank; 431 uint8_t TargetMclkIndex; 432 uint8_t TargetMvddIndex; 433 uint8_t MclkSwitchResult; 434 435 uint16_t VbiFailureCount; 436 uint8_t VbiWaitCounter; 437 uint8_t EnabledLevelsChange; 438 439 uint16_t LevelResidencyCounters[SMU73_MAX_LEVELS_MEMORY]; 440 uint16_t LevelSwitchCounters[SMU73_MAX_LEVELS_MEMORY]; 441 442 void (*TargetStateCalculator)(uint8_t); 443 void (*SavedTargetStateCalculator)(uint8_t); 444 445 uint16_t AutoDpmInterval; 446 uint16_t AutoDpmRange; 447 448 uint16_t VbiTimeoutCount; 449 uint16_t MclkSwitchingTime; 450 451 uint8_t fastSwitch; 452 uint8_t Save_PIC_VDDGFX_EXIT; 453 uint8_t Save_PIC_VDDGFX_ENTER; 454 uint8_t padding; 455 456 }; 457 458 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 459 460 struct SMU7_UlvScoreboard { 461 uint8_t EnterUlv; 462 uint8_t ExitUlv; 463 uint8_t UlvActive; 464 uint8_t WaitingForUlv; 465 uint8_t UlvEnable; 466 uint8_t UlvRunning; 467 uint8_t UlvMasterEnable; 468 uint8_t padding; 469 uint32_t UlvAbortedCount; 470 uint32_t UlvTimeStamp; 471 }; 472 473 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 474 475 struct VddgfxSavedRegisters { 476 uint32_t GPU_DBG[3]; 477 uint32_t MEC_BaseAddress_Hi; 478 uint32_t MEC_BaseAddress_Lo; 479 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 480 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 481 uint32_t CP_INT_CNTL; 482 }; 483 484 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 485 486 struct SMU7_VddGfxScoreboard { 487 uint8_t VddGfxEnable; 488 uint8_t VddGfxActive; 489 uint8_t VPUResetOccured; 490 uint8_t padding; 491 492 uint32_t VddGfxEnteredCount; 493 uint32_t VddGfxAbortedCount; 494 495 uint32_t VddGfxVid; 496 497 VddgfxSavedRegisters SavedRegisters; 498 }; 499 500 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 501 502 struct SMU7_TdcLimitScoreboard { 503 uint8_t Enable; 504 uint8_t Running; 505 uint16_t Alpha; 506 uint32_t FilteredIddc; 507 uint32_t IddcLimit; 508 uint32_t IddcHyst; 509 SMU7_HystController_Data HystControllerData; 510 }; 511 512 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 513 514 struct SMU7_PkgPwrLimitScoreboard { 515 uint8_t Enable; 516 uint8_t Running; 517 uint16_t Alpha; 518 uint32_t FilteredPkgPwr; 519 uint32_t Limit; 520 uint32_t Hyst; 521 uint32_t LimitFromDriver; 522 SMU7_HystController_Data HystControllerData; 523 }; 524 525 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 526 527 struct SMU7_BapmScoreboard { 528 uint32_t source_powers[SMU73_DTE_SOURCES]; 529 uint32_t source_powers_last[SMU73_DTE_SOURCES]; 530 int32_t entity_temperatures[SMU73_NUM_GPU_TES]; 531 int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES]; 532 int32_t Limit; 533 int32_t Hyst; 534 int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2]; 535 int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS]; 536 uint16_t ConfigTDPPowerScalar; 537 uint16_t FanSpeedPowerScalar; 538 uint16_t OverDrivePowerScalar; 539 uint16_t OverDriveLimitScalar; 540 uint16_t FinalPowerScalar; 541 uint8_t VariantID; 542 uint8_t spare997; 543 544 SMU7_HystController_Data HystControllerData; 545 546 int32_t temperature_gradient_slope; 547 int32_t temperature_gradient; 548 uint32_t measured_temperature; 549 }; 550 551 552 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 553 554 struct SMU7_AcpiScoreboard { 555 uint32_t SavedInterruptMask[2]; 556 uint8_t LastACPIRequest; 557 uint8_t CgBifResp; 558 uint8_t RequestType; 559 uint8_t Padding; 560 SMU73_Discrete_ACPILevel D0Level; 561 }; 562 563 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 564 565 struct SMU_QuadraticCoeffs { 566 int32_t m1; 567 uint32_t b; 568 569 int16_t m2; 570 uint8_t m1_shift; 571 uint8_t m2_shift; 572 }; 573 574 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs; 575 576 struct SMU73_Discrete_PmFuses { 577 /* dw0-dw1 */ 578 uint8_t BapmVddCVidHiSidd[8]; 579 580 /* dw2-dw3 */ 581 uint8_t BapmVddCVidLoSidd[8]; 582 583 /* dw4-dw5 */ 584 uint8_t VddCVid[8]; 585 586 /* dw1*/ 587 uint8_t SviLoadLineEn; 588 uint8_t SviLoadLineVddC; 589 uint8_t SviLoadLineTrimVddC; 590 uint8_t SviLoadLineOffsetVddC; 591 592 /* dw2 */ 593 uint16_t TDC_VDDC_PkgLimit; 594 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 595 uint8_t TDC_MAWt; 596 597 /* dw3 */ 598 uint8_t TdcWaterfallCtl; 599 uint8_t LPMLTemperatureMin; 600 uint8_t LPMLTemperatureMax; 601 uint8_t Reserved; 602 603 /* dw4-dw7 */ 604 uint8_t LPMLTemperatureScaler[16]; 605 606 /* dw8-dw9 */ 607 int16_t FuzzyFan_ErrorSetDelta; 608 int16_t FuzzyFan_ErrorRateSetDelta; 609 int16_t FuzzyFan_PwmSetDelta; 610 uint16_t Reserved6; 611 612 /* dw10-dw14 */ 613 uint8_t GnbLPML[16]; 614 615 /* dw15 */ 616 uint8_t GnbLPMLMaxVid; 617 uint8_t GnbLPMLMinVid; 618 uint8_t Reserved1[2]; 619 620 /* dw16 */ 621 uint16_t BapmVddCBaseLeakageHiSidd; 622 uint16_t BapmVddCBaseLeakageLoSidd; 623 624 /* AVFS */ 625 uint16_t VFT_Temp[3]; 626 uint16_t padding; 627 628 SMU_QuadraticCoeffs VFT_ATE[3]; 629 630 SMU_QuadraticCoeffs AVFS_GB; 631 SMU_QuadraticCoeffs ATE_ACBTC_GB; 632 633 SMU_QuadraticCoeffs P2V; 634 635 uint32_t PsmCharzFreq; 636 637 uint16_t InversionVoltage; 638 uint16_t PsmCharzTemp; 639 640 uint32_t EnabledAvfsModules; 641 }; 642 643 typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses; 644 645 struct SMU7_Discrete_Log_Header_Table { 646 uint32_t version; 647 uint32_t asic_id; 648 uint16_t flags; 649 uint16_t entry_size; 650 uint32_t total_size; 651 uint32_t num_of_entries; 652 uint8_t type; 653 uint8_t mode; 654 uint8_t filler_0[2]; 655 uint32_t filler_1[2]; 656 }; 657 658 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 659 660 struct SMU7_Discrete_Log_Cntl { 661 uint8_t Enabled; 662 uint8_t Type; 663 uint8_t padding[2]; 664 uint32_t BufferSize; 665 uint32_t SamplesLogged; 666 uint32_t SampleSize; 667 uint32_t AddrL; 668 uint32_t AddrH; 669 }; 670 671 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 672 673 #define CAC_ACC_NW_NUM_OF_SIGNALS 87 674 675 struct SMU7_Discrete_Cac_Collection_Table { 676 uint32_t temperature; 677 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 678 }; 679 680 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 681 682 struct SMU7_Discrete_Cac_Verification_Table { 683 uint32_t VddcTotalPower; 684 uint32_t VddcLeakagePower; 685 uint32_t VddcConstantPower; 686 uint32_t VddcGfxDynamicPower; 687 uint32_t VddcUvdDynamicPower; 688 uint32_t VddcVceDynamicPower; 689 uint32_t VddcAcpDynamicPower; 690 uint32_t VddcPcieDynamicPower; 691 uint32_t VddcDceDynamicPower; 692 uint32_t VddcCurrent; 693 uint32_t VddcVoltage; 694 uint32_t VddciTotalPower; 695 uint32_t VddciLeakagePower; 696 uint32_t VddciConstantPower; 697 uint32_t VddciDynamicPower; 698 uint32_t Vddr1TotalPower; 699 uint32_t Vddr1LeakagePower; 700 uint32_t Vddr1ConstantPower; 701 uint32_t Vddr1DynamicPower; 702 uint32_t spare[4]; 703 uint32_t temperature; 704 }; 705 706 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 707 708 struct SMU7_Discrete_Pm_Status_Table { 709 //Thermal entities 710 int32_t T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT]; 711 int32_t T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT]; 712 int32_t T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT]; 713 uint32_t T_hbm_acc; 714 715 //Voltage domains 716 uint32_t I_calc_max; 717 uint32_t I_calc_acc; 718 uint32_t P_meas_acc; 719 uint32_t V_meas_load_acc; 720 uint32_t I_meas_acc; 721 uint32_t P_meas_acc_vddci; 722 uint32_t V_meas_load_acc_vddci; 723 uint32_t I_meas_acc_vddci; 724 725 //Frequency 726 uint16_t Sclk_dpm_residency[8]; 727 uint16_t Uvd_dpm_residency[8]; 728 uint16_t Vce_dpm_residency[8]; 729 730 //Chip 731 uint32_t P_roc_acc; 732 uint32_t PkgPwr_max; 733 uint32_t PkgPwr_acc; 734 uint32_t MclkSwitchingTime_max; 735 uint32_t MclkSwitchingTime_acc; 736 uint32_t FanPwm_acc; 737 uint32_t FanRpm_acc; 738 uint32_t Gfx_busy_acc; 739 uint32_t Mc_busy_acc; 740 uint32_t Fps_acc; 741 742 uint32_t AccCnt; 743 }; 744 745 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 746 747 //FIXME THESE NEED TO BE UPDATED 748 #define SMU7_SCLK_CAC 0x561 749 #define SMU7_MCLK_CAC 0xF9 750 #define SMU7_VCLK_CAC 0x2DE 751 #define SMU7_DCLK_CAC 0x2DE 752 #define SMU7_ECLK_CAC 0x25E 753 #define SMU7_ACLK_CAC 0x25E 754 #define SMU7_SAMCLK_CAC 0x25E 755 #define SMU7_DISPCLK_CAC 0x100 756 #define SMU7_CAC_CONSTANT 0x2EE3430 757 #define SMU7_CAC_CONSTANT_SHIFT 18 758 759 #define SMU7_VDDCI_MCLK_CONST 1765 760 #define SMU7_VDDCI_MCLK_CONST_SHIFT 16 761 #define SMU7_VDDCI_VDDCI_CONST 50958 762 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 763 #define SMU7_VDDCI_CONST 11781 764 #define SMU7_VDDCI_STROBE_PWR 1331 765 766 #define SMU7_VDDR1_CONST 693 767 #define SMU7_VDDR1_CAC_WEIGHT 20 768 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 769 #define SMU7_VDDR1_STROBE_PWR 512 770 771 #define SMU7_AREA_COEFF_UVD 0xA78 772 #define SMU7_AREA_COEFF_VCE 0x190A 773 #define SMU7_AREA_COEFF_ACP 0x22D1 774 #define SMU7_AREA_COEFF_SAMU 0x534 775 776 //ThermOutMode values 777 #define SMU7_THERM_OUT_MODE_DISABLE 0x0 778 #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 779 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 780 781 #pragma pack(pop) 782 783 #endif 784 785