xref: /linux/include/linux/mfd/tps68470.h (revision 03ab8e6297acd1bc0eedaa050e2a1635c576fd11)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2017 Intel Corporation */
3 /* Functions to access TPS68470 power management chip. */
4 
5 #ifndef __LINUX_MFD_TPS68470_H
6 #define __LINUX_MFD_TPS68470_H
7 
8 /* Register addresses */
9 #define TPS68470_REG_POSTDIV2		0x06
10 #define TPS68470_REG_BOOSTDIV		0x07
11 #define TPS68470_REG_BUCKDIV		0x08
12 #define TPS68470_REG_PLLSWR		0x09
13 #define TPS68470_REG_XTALDIV		0x0A
14 #define TPS68470_REG_PLLDIV		0x0B
15 #define TPS68470_REG_POSTDIV		0x0C
16 #define TPS68470_REG_PLLCTL		0x0D
17 #define TPS68470_REG_PLLCTL2		0x0E
18 #define TPS68470_REG_CLKCFG1		0x0F
19 #define TPS68470_REG_CLKCFG2		0x10
20 #define TPS68470_REG_GPCTL0A		0x14
21 #define TPS68470_REG_GPCTL0B		0x15
22 #define TPS68470_REG_GPCTL1A		0x16
23 #define TPS68470_REG_GPCTL1B		0x17
24 #define TPS68470_REG_GPCTL2A		0x18
25 #define TPS68470_REG_GPCTL2B		0x19
26 #define TPS68470_REG_GPCTL3A		0x1A
27 #define TPS68470_REG_GPCTL3B		0x1B
28 #define TPS68470_REG_GPCTL4A		0x1C
29 #define TPS68470_REG_GPCTL4B		0x1D
30 #define TPS68470_REG_GPCTL5A		0x1E
31 #define TPS68470_REG_GPCTL5B		0x1F
32 #define TPS68470_REG_GPCTL6A		0x20
33 #define TPS68470_REG_GPCTL6B		0x21
34 #define TPS68470_REG_SGPO		0x22
35 #define TPS68470_REG_GPDI		0x26
36 #define TPS68470_REG_GPDO		0x27
37 #define TPS68470_REG_VCMVAL		0x3C
38 #define TPS68470_REG_VAUX1VAL		0x3D
39 #define TPS68470_REG_VAUX2VAL		0x3E
40 #define TPS68470_REG_VIOVAL		0x3F
41 #define TPS68470_REG_VSIOVAL		0x40
42 #define TPS68470_REG_VAVAL		0x41
43 #define TPS68470_REG_VDVAL		0x42
44 #define TPS68470_REG_S_I2C_CTL		0x43
45 #define TPS68470_REG_VCMCTL		0x44
46 #define TPS68470_REG_VAUX1CTL		0x45
47 #define TPS68470_REG_VAUX2CTL		0x46
48 #define TPS68470_REG_VACTL		0x47
49 #define TPS68470_REG_VDCTL		0x48
50 #define TPS68470_REG_RESET		0x50
51 #define TPS68470_REG_REVID		0xFF
52 
53 #define TPS68470_REG_MAX		TPS68470_REG_REVID
54 
55 /* Register field definitions */
56 
57 #define TPS68470_REG_RESET_MASK		GENMASK(7, 0)
58 #define TPS68470_VAVAL_AVOLT_MASK	GENMASK(6, 0)
59 
60 #define TPS68470_VDVAL_DVOLT_MASK	GENMASK(5, 0)
61 #define TPS68470_VCMVAL_VCVOLT_MASK	GENMASK(6, 0)
62 #define TPS68470_VIOVAL_IOVOLT_MASK	GENMASK(6, 0)
63 #define TPS68470_VSIOVAL_IOVOLT_MASK	GENMASK(6, 0)
64 #define TPS68470_VAUX1VAL_AUX1VOLT_MASK	GENMASK(6, 0)
65 #define TPS68470_VAUX2VAL_AUX2VOLT_MASK	GENMASK(6, 0)
66 
67 #define TPS68470_VACTL_EN_MASK		GENMASK(0, 0)
68 #define TPS68470_VDCTL_EN_MASK		GENMASK(0, 0)
69 #define TPS68470_VCMCTL_EN_MASK		GENMASK(0, 0)
70 #define TPS68470_S_I2C_CTL_EN_MASK	GENMASK(1, 0)
71 #define TPS68470_VAUX1CTL_EN_MASK	GENMASK(0, 0)
72 #define TPS68470_VAUX2CTL_EN_MASK	GENMASK(0, 0)
73 #define TPS68470_PLL_EN_MASK		GENMASK(0, 0)
74 
75 #define TPS68470_CLKCFG1_MODE_A_MASK	GENMASK(1, 0)
76 #define TPS68470_CLKCFG1_MODE_B_MASK	GENMASK(3, 2)
77 
78 #define TPS68470_CLKCFG2_DRV_STR_2MA	0x05
79 #define TPS68470_PLL_OUTPUT_ENABLE	0x02
80 #define TPS68470_CLK_SRC_XTAL		BIT(0)
81 #define TPS68470_PLLSWR_DEFAULT		GENMASK(1, 0)
82 #define TPS68470_OSC_EXT_CAP_DEFAULT	0x05
83 
84 #define TPS68470_OUTPUT_A_SHIFT		0x00
85 #define TPS68470_OUTPUT_B_SHIFT		0x02
86 #define TPS68470_CLK_SRC_SHIFT		GENMASK(2, 0)
87 #define TPS68470_OSC_EXT_CAP_SHIFT	BIT(2)
88 
89 #define TPS68470_GPIO_CTL_REG_A(x)	(TPS68470_REG_GPCTL0A + (x) * 2)
90 #define TPS68470_GPIO_CTL_REG_B(x)	(TPS68470_REG_GPCTL0B + (x) * 2)
91 #define TPS68470_GPIO_MODE_MASK		GENMASK(1, 0)
92 #define TPS68470_GPIO_MODE_IN		0
93 #define TPS68470_GPIO_MODE_IN_PULLUP	1
94 #define TPS68470_GPIO_MODE_OUT_CMOS	2
95 #define TPS68470_GPIO_MODE_OUT_ODRAIN	3
96 
97 #endif /* __LINUX_MFD_TPS68470_H */
98