1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for the TI TPS23881 PoE PSE Controller driver (I2C bus)
4 *
5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/delay.h>
10 #include <linux/firmware.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pse-pd/pse.h>
17
18 #define TPS23881_MAX_CHANS 8
19 #define TPS23881_MAX_IRQ_RETRIES 10
20
21 #define TPS23881_REG_IT 0x0
22 #define TPS23881_REG_IT_MASK 0x1
23 #define TPS23881_REG_IT_DISF BIT(2)
24 #define TPS23881_REG_IT_DETC BIT(3)
25 #define TPS23881_REG_IT_CLASC BIT(4)
26 #define TPS23881_REG_IT_IFAULT BIT(5)
27 #define TPS23881_REG_IT_SUPF BIT(7)
28 #define TPS23881_REG_DET_EVENT 0x5
29 #define TPS23881_REG_FAULT 0x7
30 #define TPS23881_REG_SUPF_EVENT 0xb
31 #define TPS23881_REG_TSD BIT(7)
32 #define TPS23881_REG_DISC 0xc
33 #define TPS23881_REG_PW_STATUS 0x10
34 #define TPS23881_REG_OP_MODE 0x12
35 #define TPS23881_REG_DISC_EN 0x13
36 #define TPS23881_OP_MODE_SEMIAUTO 0xaaaa
37 #define TPS23881_REG_DIS_EN 0x13
38 #define TPS23881_REG_DET_CLA_EN 0x14
39 #define TPS23881_REG_GEN_MASK 0x17
40 #define TPS23881_REG_CLCHE BIT(2)
41 #define TPS23881_REG_DECHE BIT(3)
42 #define TPS23881_REG_NBITACC BIT(5)
43 #define TPS23881_REG_INTEN BIT(7)
44 #define TPS23881_REG_PW_EN 0x19
45 #define TPS23881_REG_RESET 0x1a
46 #define TPS23881_REG_CLRAIN BIT(7)
47 #define TPS23881_REG_2PAIR_POL1 0x1e
48 #define TPS23881_REG_PORT_MAP 0x26
49 #define TPS23881_REG_PORT_POWER 0x29
50 #define TPS23881_REG_4PAIR_POL1 0x2a
51 #define TPS23881_REG_INPUT_V 0x2e
52 #define TPS23881_REG_CHAN1_A 0x30
53 #define TPS23881_REG_CHAN1_V 0x32
54 #define TPS23881_REG_FOLDBACK 0x40
55 #define TPS23881_REG_TPON BIT(0)
56 #define TPS23881_REG_FWREV 0x41
57 #define TPS23881_REG_DEVID 0x43
58 #define TPS23881_REG_DEVID_MASK 0xF0
59 #define TPS23881_DEVICE_ID 0x02
60 #define TPS23881_REG_CHAN1_CLASS 0x4c
61 #define TPS23881_REG_SRAM_CTRL 0x60
62 #define TPS23881_REG_SRAM_DATA 0x61
63
64 #define TPS23881_UV_STEP 3662
65 #define TPS23881_NA_STEP 70190
66 #define TPS23881_MW_STEP 500
67 #define TPS23881_MIN_PI_PW_LIMIT_MW 2000
68
69 struct tps23881_port_desc {
70 u8 chan[2];
71 bool is_4p;
72 int pw_pol;
73 bool exist;
74 };
75
76 struct tps23881_priv {
77 struct i2c_client *client;
78 struct pse_controller_dev pcdev;
79 struct device_node *np;
80 struct tps23881_port_desc port[TPS23881_MAX_CHANS];
81 };
82
to_tps23881_priv(struct pse_controller_dev * pcdev)83 static struct tps23881_priv *to_tps23881_priv(struct pse_controller_dev *pcdev)
84 {
85 return container_of(pcdev, struct tps23881_priv, pcdev);
86 }
87
88 /*
89 * Helper to extract a value from a u16 register value, which is made of two
90 * u8 registers. The function calculates the bit offset based on the channel
91 * and extracts the relevant bits using a provided field mask.
92 *
93 * @param reg_val: The u16 register value (composed of two u8 registers).
94 * @param chan: The channel number (0-7).
95 * @param field_offset: The base bit offset to apply (e.g., 0 or 4).
96 * @param field_mask: The mask to apply to extract the required bits.
97 * @return: The extracted value for the specific channel.
98 */
tps23881_calc_val(u16 reg_val,u8 chan,u8 field_offset,u16 field_mask)99 static u16 tps23881_calc_val(u16 reg_val, u8 chan, u8 field_offset,
100 u16 field_mask)
101 {
102 if (chan >= 4)
103 reg_val >>= 8;
104
105 return (reg_val >> field_offset) & field_mask;
106 }
107
108 /*
109 * Helper to combine individual channel values into a u16 register value.
110 * The function sets the value for a specific channel in the appropriate
111 * position.
112 *
113 * @param reg_val: The current u16 register value.
114 * @param chan: The channel number (0-7).
115 * @param field_offset: The base bit offset to apply (e.g., 0 or 4).
116 * @param field_mask: The mask to apply for the field (e.g., 0x0F).
117 * @param field_val: The value to set for the specific channel (masked by
118 * field_mask).
119 * @return: The updated u16 register value with the channel value set.
120 */
tps23881_set_val(u16 reg_val,u8 chan,u8 field_offset,u16 field_mask,u16 field_val)121 static u16 tps23881_set_val(u16 reg_val, u8 chan, u8 field_offset,
122 u16 field_mask, u16 field_val)
123 {
124 field_val &= field_mask;
125
126 if (chan < 4) {
127 reg_val &= ~(field_mask << field_offset);
128 reg_val |= (field_val << field_offset);
129 } else {
130 reg_val &= ~(field_mask << (field_offset + 8));
131 reg_val |= (field_val << (field_offset + 8));
132 }
133
134 return reg_val;
135 }
136
137 static int
tps23881_pi_set_pw_pol_limit(struct tps23881_priv * priv,int id,u8 pw_pol,bool is_4p)138 tps23881_pi_set_pw_pol_limit(struct tps23881_priv *priv, int id, u8 pw_pol,
139 bool is_4p)
140 {
141 struct i2c_client *client = priv->client;
142 int ret, reg;
143 u16 val;
144 u8 chan;
145
146 chan = priv->port[id].chan[0];
147 if (!is_4p) {
148 reg = TPS23881_REG_2PAIR_POL1 + (chan % 4);
149 } else {
150 /* One chan is enough to configure the 4p PI power limit */
151 if ((chan % 4) < 2)
152 reg = TPS23881_REG_4PAIR_POL1;
153 else
154 reg = TPS23881_REG_4PAIR_POL1 + 1;
155 }
156
157 ret = i2c_smbus_read_word_data(client, reg);
158 if (ret < 0)
159 return ret;
160
161 val = tps23881_set_val(ret, chan, 0, 0xff, pw_pol);
162 return i2c_smbus_write_word_data(client, reg, val);
163 }
164
tps23881_pi_enable_manual_pol(struct tps23881_priv * priv,int id)165 static int tps23881_pi_enable_manual_pol(struct tps23881_priv *priv, int id)
166 {
167 struct i2c_client *client = priv->client;
168 int ret;
169 u8 chan;
170 u16 val;
171
172 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FOLDBACK);
173 if (ret < 0)
174 return ret;
175
176 /* No need to test if the chan is PoE4 as setting either bit for a
177 * 4P configured port disables the automatic configuration on both
178 * channels.
179 */
180 chan = priv->port[id].chan[0];
181 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4));
182 return i2c_smbus_write_byte_data(client, TPS23881_REG_FOLDBACK, val);
183 }
184
tps23881_pi_enable(struct pse_controller_dev * pcdev,int id)185 static int tps23881_pi_enable(struct pse_controller_dev *pcdev, int id)
186 {
187 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
188 struct i2c_client *client = priv->client;
189 u8 chan;
190 u16 val;
191 int ret;
192
193 if (id >= TPS23881_MAX_CHANS)
194 return -ERANGE;
195
196 chan = priv->port[id].chan[0];
197 val = tps23881_set_val(0, chan, 0, BIT(chan % 4), BIT(chan % 4));
198
199 if (priv->port[id].is_4p) {
200 chan = priv->port[id].chan[1];
201 val = tps23881_set_val(val, chan, 0, BIT(chan % 4),
202 BIT(chan % 4));
203 }
204
205 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val);
206 if (ret)
207 return ret;
208
209 /* Enable DC disconnect*/
210 chan = priv->port[id].chan[0];
211 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DISC_EN);
212 if (ret < 0)
213 return ret;
214
215 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4));
216 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DISC_EN, val);
217 if (ret)
218 return ret;
219
220 return 0;
221 }
222
tps23881_pi_disable(struct pse_controller_dev * pcdev,int id)223 static int tps23881_pi_disable(struct pse_controller_dev *pcdev, int id)
224 {
225 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
226 struct i2c_client *client = priv->client;
227 u8 chan;
228 u16 val;
229 int ret;
230
231 if (id >= TPS23881_MAX_CHANS)
232 return -ERANGE;
233
234 chan = priv->port[id].chan[0];
235 val = tps23881_set_val(0, chan, 4, BIT(chan % 4), BIT(chan % 4));
236
237 if (priv->port[id].is_4p) {
238 chan = priv->port[id].chan[1];
239 val = tps23881_set_val(val, chan, 4, BIT(chan % 4),
240 BIT(chan % 4));
241 }
242
243 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val);
244 if (ret)
245 return ret;
246
247 /* PWOFF command resets lots of register which need to be
248 * configured again. According to the datasheet "It may take upwards
249 * of 5ms after PWOFFn command for all register values to be updated"
250 */
251 mdelay(5);
252
253 /* Disable DC disconnect*/
254 chan = priv->port[id].chan[0];
255 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DISC_EN);
256 if (ret < 0)
257 return ret;
258
259 val = tps23881_set_val(ret, chan, 0, 0, BIT(chan % 4));
260 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DISC_EN, val);
261 if (ret)
262 return ret;
263
264 /* Enable detection and classification */
265 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DET_CLA_EN);
266 if (ret < 0)
267 return ret;
268
269 chan = priv->port[id].chan[0];
270 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4));
271 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), BIT(chan % 4));
272
273 if (priv->port[id].is_4p) {
274 chan = priv->port[id].chan[1];
275 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4),
276 BIT(chan % 4));
277 val = tps23881_set_val(val, chan, 4, BIT(chan % 4),
278 BIT(chan % 4));
279 }
280
281 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val);
282 if (ret)
283 return ret;
284
285 /* No power policy */
286 if (priv->port[id].pw_pol < 0)
287 return 0;
288
289 ret = tps23881_pi_enable_manual_pol(priv, id);
290 if (ret < 0)
291 return ret;
292
293 /* Set power policy */
294 return tps23881_pi_set_pw_pol_limit(priv, id, priv->port[id].pw_pol,
295 priv->port[id].is_4p);
296 }
297
298 static int
tps23881_pi_get_admin_state(struct pse_controller_dev * pcdev,int id,struct pse_admin_state * admin_state)299 tps23881_pi_get_admin_state(struct pse_controller_dev *pcdev, int id,
300 struct pse_admin_state *admin_state)
301 {
302 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
303 struct i2c_client *client = priv->client;
304 bool enabled;
305 u8 chan;
306 u16 val;
307 int ret;
308
309 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS);
310 if (ret < 0)
311 return ret;
312
313 chan = priv->port[id].chan[0];
314 val = tps23881_calc_val(ret, chan, 0, BIT(chan % 4));
315 enabled = !!(val);
316
317 if (priv->port[id].is_4p) {
318 chan = priv->port[id].chan[1];
319 val = tps23881_calc_val(ret, chan, 0, BIT(chan % 4));
320 enabled &= !!(val);
321 }
322
323 /* Return enabled status only if both channel are on this state */
324 if (enabled)
325 admin_state->c33_admin_state =
326 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
327 else
328 admin_state->c33_admin_state =
329 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
330
331 return 0;
332 }
333
334 static int
tps23881_pi_get_pw_status(struct pse_controller_dev * pcdev,int id,struct pse_pw_status * pw_status)335 tps23881_pi_get_pw_status(struct pse_controller_dev *pcdev, int id,
336 struct pse_pw_status *pw_status)
337 {
338 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
339 struct i2c_client *client = priv->client;
340 bool delivering;
341 u8 chan;
342 u16 val;
343 int ret;
344
345 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS);
346 if (ret < 0)
347 return ret;
348
349 chan = priv->port[id].chan[0];
350 val = tps23881_calc_val(ret, chan, 4, BIT(chan % 4));
351 delivering = !!(val);
352
353 if (priv->port[id].is_4p) {
354 chan = priv->port[id].chan[1];
355 val = tps23881_calc_val(ret, chan, 4, BIT(chan % 4));
356 delivering &= !!(val);
357 }
358
359 /* Return delivering status only if both channel are on this state */
360 if (delivering)
361 pw_status->c33_pw_status =
362 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING;
363 else
364 pw_status->c33_pw_status =
365 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED;
366
367 return 0;
368 }
369
tps23881_pi_get_voltage(struct pse_controller_dev * pcdev,int id)370 static int tps23881_pi_get_voltage(struct pse_controller_dev *pcdev, int id)
371 {
372 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
373 struct i2c_client *client = priv->client;
374 int ret;
375 u64 uV;
376
377 ret = i2c_smbus_read_word_data(client, TPS23881_REG_INPUT_V);
378 if (ret < 0)
379 return ret;
380
381 uV = ret & 0x3fff;
382 uV *= TPS23881_UV_STEP;
383
384 return (int)uV;
385 }
386
387 static int
tps23881_pi_get_chan_current(struct tps23881_priv * priv,u8 chan)388 tps23881_pi_get_chan_current(struct tps23881_priv *priv, u8 chan)
389 {
390 struct i2c_client *client = priv->client;
391 int reg, ret;
392 u64 tmp_64;
393
394 /* Registers 0x30 to 0x3d */
395 reg = TPS23881_REG_CHAN1_A + (chan % 4) * 4 + (chan >= 4);
396 ret = i2c_smbus_read_word_data(client, reg);
397 if (ret < 0)
398 return ret;
399
400 tmp_64 = ret & 0x3fff;
401 tmp_64 *= TPS23881_NA_STEP;
402 /* uA = nA / 1000 */
403 tmp_64 = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000);
404 return (int)tmp_64;
405 }
406
tps23881_pi_get_pw_class(struct pse_controller_dev * pcdev,int id)407 static int tps23881_pi_get_pw_class(struct pse_controller_dev *pcdev,
408 int id)
409 {
410 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
411 struct i2c_client *client = priv->client;
412 int ret, reg;
413 u8 chan;
414
415 chan = priv->port[id].chan[0];
416 reg = TPS23881_REG_CHAN1_CLASS + (chan % 4);
417 ret = i2c_smbus_read_word_data(client, reg);
418 if (ret < 0)
419 return ret;
420
421 return tps23881_calc_val(ret, chan, 4, 0x0f);
422 }
423
424 static int
tps23881_pi_get_actual_pw(struct pse_controller_dev * pcdev,int id)425 tps23881_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id)
426 {
427 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
428 int ret, uV, uA;
429 u64 tmp_64;
430 u8 chan;
431
432 ret = tps23881_pi_get_voltage(&priv->pcdev, id);
433 if (ret < 0)
434 return ret;
435 uV = ret;
436
437 chan = priv->port[id].chan[0];
438 ret = tps23881_pi_get_chan_current(priv, chan);
439 if (ret < 0)
440 return ret;
441 uA = ret;
442
443 if (priv->port[id].is_4p) {
444 chan = priv->port[id].chan[1];
445 ret = tps23881_pi_get_chan_current(priv, chan);
446 if (ret < 0)
447 return ret;
448 uA += ret;
449 }
450
451 tmp_64 = uV;
452 tmp_64 *= uA;
453 /* mW = uV * uA / 1000000000 */
454 return DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000);
455 }
456
457 static int
tps23881_pi_get_pw_limit_chan(struct tps23881_priv * priv,u8 chan)458 tps23881_pi_get_pw_limit_chan(struct tps23881_priv *priv, u8 chan)
459 {
460 struct i2c_client *client = priv->client;
461 int ret, reg;
462 u16 val;
463
464 reg = TPS23881_REG_2PAIR_POL1 + (chan % 4);
465 ret = i2c_smbus_read_word_data(client, reg);
466 if (ret < 0)
467 return ret;
468
469 val = tps23881_calc_val(ret, chan, 0, 0xff);
470 return val * TPS23881_MW_STEP;
471 }
472
tps23881_pi_get_pw_limit(struct pse_controller_dev * pcdev,int id)473 static int tps23881_pi_get_pw_limit(struct pse_controller_dev *pcdev, int id)
474 {
475 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
476 int ret, mW;
477 u8 chan;
478
479 chan = priv->port[id].chan[0];
480 ret = tps23881_pi_get_pw_limit_chan(priv, chan);
481 if (ret < 0)
482 return ret;
483
484 mW = ret;
485 if (priv->port[id].is_4p) {
486 chan = priv->port[id].chan[1];
487 ret = tps23881_pi_get_pw_limit_chan(priv, chan);
488 if (ret < 0)
489 return ret;
490 mW += ret;
491 }
492
493 return mW;
494 }
495
tps23881_pi_set_pw_limit(struct pse_controller_dev * pcdev,int id,int max_mW)496 static int tps23881_pi_set_pw_limit(struct pse_controller_dev *pcdev,
497 int id, int max_mW)
498 {
499 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
500 u8 pw_pol;
501 int ret;
502
503 if (max_mW < TPS23881_MIN_PI_PW_LIMIT_MW || MAX_PI_PW < max_mW) {
504 dev_err(&priv->client->dev,
505 "power limit %d out of ranges [%d,%d]",
506 max_mW, TPS23881_MIN_PI_PW_LIMIT_MW, MAX_PI_PW);
507 return -ERANGE;
508 }
509
510 ret = tps23881_pi_enable_manual_pol(priv, id);
511 if (ret < 0)
512 return ret;
513
514 pw_pol = DIV_ROUND_CLOSEST_ULL(max_mW, TPS23881_MW_STEP);
515
516 /* Save power policy to reconfigure it after a disabled call */
517 priv->port[id].pw_pol = pw_pol;
518 return tps23881_pi_set_pw_pol_limit(priv, id, pw_pol,
519 priv->port[id].is_4p);
520 }
521
522 static int
tps23881_pi_get_pw_limit_ranges(struct pse_controller_dev * pcdev,int id,struct pse_pw_limit_ranges * pw_limit_ranges)523 tps23881_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id,
524 struct pse_pw_limit_ranges *pw_limit_ranges)
525 {
526 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
527
528 c33_pw_limit_ranges = kzalloc(sizeof(*c33_pw_limit_ranges),
529 GFP_KERNEL);
530 if (!c33_pw_limit_ranges)
531 return -ENOMEM;
532
533 c33_pw_limit_ranges->min = TPS23881_MIN_PI_PW_LIMIT_MW;
534 c33_pw_limit_ranges->max = MAX_PI_PW;
535 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges;
536
537 /* Return the number of ranges */
538 return 1;
539 }
540
541 /* Parse managers subnode into a array of device node */
542 static int
tps23881_get_of_channels(struct tps23881_priv * priv,struct device_node * chan_node[TPS23881_MAX_CHANS])543 tps23881_get_of_channels(struct tps23881_priv *priv,
544 struct device_node *chan_node[TPS23881_MAX_CHANS])
545 {
546 struct device_node *channels_node, *node;
547 int i, ret;
548
549 if (!priv->np)
550 return -EINVAL;
551
552 channels_node = of_find_node_by_name(priv->np, "channels");
553 if (!channels_node)
554 return -EINVAL;
555
556 for_each_child_of_node(channels_node, node) {
557 u32 chan_id;
558
559 if (!of_node_name_eq(node, "channel"))
560 continue;
561
562 ret = of_property_read_u32(node, "reg", &chan_id);
563 if (ret) {
564 ret = -EINVAL;
565 goto out;
566 }
567
568 if (chan_id >= TPS23881_MAX_CHANS || chan_node[chan_id]) {
569 dev_err(&priv->client->dev,
570 "wrong number of port (%d)\n", chan_id);
571 ret = -EINVAL;
572 goto out;
573 }
574
575 of_node_get(node);
576 chan_node[chan_id] = node;
577 }
578
579 of_node_put(channels_node);
580 return 0;
581
582 out:
583 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
584 of_node_put(chan_node[i]);
585 chan_node[i] = NULL;
586 }
587
588 of_node_put(node);
589 of_node_put(channels_node);
590 return ret;
591 }
592
593 struct tps23881_port_matrix {
594 u8 pi_id;
595 u8 lgcl_chan[2];
596 u8 hw_chan[2];
597 bool is_4p;
598 bool exist;
599 };
600
601 static int
tps23881_match_channel(const struct pse_pi_pairset * pairset,struct device_node * chan_node[TPS23881_MAX_CHANS])602 tps23881_match_channel(const struct pse_pi_pairset *pairset,
603 struct device_node *chan_node[TPS23881_MAX_CHANS])
604 {
605 int i;
606
607 /* Look on every channels */
608 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
609 if (pairset->np == chan_node[i])
610 return i;
611 }
612
613 return -ENODEV;
614 }
615
616 static bool
tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int chan)617 tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
618 int chan)
619 {
620 int i;
621
622 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
623 if (port_matrix[i].exist &&
624 (port_matrix[i].hw_chan[0] == chan ||
625 port_matrix[i].hw_chan[1] == chan))
626 return false;
627 }
628
629 return true;
630 }
631
632 /* Fill port matrix with the matching channels */
633 static int
tps23881_match_port_matrix(struct pse_pi * pi,int pi_id,struct device_node * chan_node[TPS23881_MAX_CHANS],struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])634 tps23881_match_port_matrix(struct pse_pi *pi, int pi_id,
635 struct device_node *chan_node[TPS23881_MAX_CHANS],
636 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
637 {
638 int ret;
639
640 if (!pi->pairset[0].np)
641 return 0;
642
643 ret = tps23881_match_channel(&pi->pairset[0], chan_node);
644 if (ret < 0)
645 return ret;
646
647 if (!tps23881_is_chan_free(port_matrix, ret)) {
648 pr_err("tps23881: channel %d already used\n", ret);
649 return -ENODEV;
650 }
651
652 port_matrix[pi_id].hw_chan[0] = ret;
653 port_matrix[pi_id].exist = true;
654
655 if (!pi->pairset[1].np)
656 return 0;
657
658 ret = tps23881_match_channel(&pi->pairset[1], chan_node);
659 if (ret < 0)
660 return ret;
661
662 if (!tps23881_is_chan_free(port_matrix, ret)) {
663 pr_err("tps23881: channel %d already used\n", ret);
664 return -ENODEV;
665 }
666
667 if (port_matrix[pi_id].hw_chan[0] / 4 != ret / 4) {
668 pr_err("tps23881: 4-pair PSE can only be set within the same 4 ports group");
669 return -ENODEV;
670 }
671
672 port_matrix[pi_id].hw_chan[1] = ret;
673 port_matrix[pi_id].is_4p = true;
674
675 return 0;
676 }
677
678 static int
tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int port_cnt)679 tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
680 int port_cnt)
681 {
682 bool used;
683 int i, j;
684
685 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
686 used = false;
687
688 for (j = 0; j < port_cnt; j++) {
689 if (port_matrix[j].hw_chan[0] == i) {
690 used = true;
691 break;
692 }
693
694 if (port_matrix[j].is_4p &&
695 port_matrix[j].hw_chan[1] == i) {
696 used = true;
697 break;
698 }
699 }
700
701 if (!used)
702 return i;
703 }
704
705 return -ENODEV;
706 }
707
708 /* Sort the port matrix to following particular hardware ports matrix
709 * specification of the tps23881. The device has two 4-ports groups and
710 * each 4-pair powered device has to be configured to use two consecutive
711 * logical channel in each 4 ports group (1 and 2 or 3 and 4). Also the
712 * hardware matrix has to be fully configured even with unused chan to be
713 * valid.
714 */
715 static int
tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])716 tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
717 {
718 struct tps23881_port_matrix tmp_port_matrix[TPS23881_MAX_CHANS] = {0};
719 int i, ret, port_cnt = 0, cnt_4ch_grp1 = 0, cnt_4ch_grp2 = 4;
720
721 /* Configure 4p port matrix */
722 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
723 int *cnt;
724
725 if (!port_matrix[i].exist || !port_matrix[i].is_4p)
726 continue;
727
728 if (port_matrix[i].hw_chan[0] < 4)
729 cnt = &cnt_4ch_grp1;
730 else
731 cnt = &cnt_4ch_grp2;
732
733 tmp_port_matrix[port_cnt].exist = true;
734 tmp_port_matrix[port_cnt].is_4p = true;
735 tmp_port_matrix[port_cnt].pi_id = i;
736 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0];
737 tmp_port_matrix[port_cnt].hw_chan[1] = port_matrix[i].hw_chan[1];
738
739 /* 4-pair ports have to be configured with consecutive
740 * logical channels 0 and 1, 2 and 3.
741 */
742 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++;
743 tmp_port_matrix[port_cnt].lgcl_chan[1] = (*cnt)++;
744
745 port_cnt++;
746 }
747
748 /* Configure 2p port matrix */
749 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
750 int *cnt;
751
752 if (!port_matrix[i].exist || port_matrix[i].is_4p)
753 continue;
754
755 if (port_matrix[i].hw_chan[0] < 4)
756 cnt = &cnt_4ch_grp1;
757 else
758 cnt = &cnt_4ch_grp2;
759
760 tmp_port_matrix[port_cnt].exist = true;
761 tmp_port_matrix[port_cnt].pi_id = i;
762 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++;
763 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0];
764
765 port_cnt++;
766 }
767
768 /* Complete the rest of the first 4 port group matrix even if
769 * channels are unused
770 */
771 while (cnt_4ch_grp1 < 4) {
772 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt);
773 if (ret < 0) {
774 pr_err("tps23881: port matrix issue, no chan available\n");
775 return ret;
776 }
777
778 if (port_cnt >= TPS23881_MAX_CHANS) {
779 pr_err("tps23881: wrong number of channels\n");
780 return -ENODEV;
781 }
782 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp1;
783 tmp_port_matrix[port_cnt].hw_chan[0] = ret;
784 cnt_4ch_grp1++;
785 port_cnt++;
786 }
787
788 /* Complete the rest of the second 4 port group matrix even if
789 * channels are unused
790 */
791 while (cnt_4ch_grp2 < 8) {
792 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt);
793 if (ret < 0) {
794 pr_err("tps23881: port matrix issue, no chan available\n");
795 return -ENODEV;
796 }
797
798 if (port_cnt >= TPS23881_MAX_CHANS) {
799 pr_err("tps23881: wrong number of channels\n");
800 return -ENODEV;
801 }
802 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp2;
803 tmp_port_matrix[port_cnt].hw_chan[0] = ret;
804 cnt_4ch_grp2++;
805 port_cnt++;
806 }
807
808 memcpy(port_matrix, tmp_port_matrix, sizeof(tmp_port_matrix));
809
810 return port_cnt;
811 }
812
813 /* Write port matrix to the hardware port matrix and the software port
814 * matrix.
815 */
816 static int
tps23881_write_port_matrix(struct tps23881_priv * priv,struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int port_cnt)817 tps23881_write_port_matrix(struct tps23881_priv *priv,
818 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
819 int port_cnt)
820 {
821 struct i2c_client *client = priv->client;
822 u8 pi_id, lgcl_chan, hw_chan;
823 u16 val = 0;
824 int i;
825
826 for (i = 0; i < port_cnt; i++) {
827 pi_id = port_matrix[i].pi_id;
828 lgcl_chan = port_matrix[i].lgcl_chan[0];
829 hw_chan = port_matrix[i].hw_chan[0] % 4;
830
831 /* Set software port matrix for existing ports */
832 if (port_matrix[i].exist) {
833 priv->port[pi_id].chan[0] = lgcl_chan;
834 priv->port[pi_id].exist = true;
835 }
836
837 /* Initialize power policy internal value */
838 priv->port[pi_id].pw_pol = -1;
839
840 /* Set hardware port matrix for all ports */
841 val |= hw_chan << (lgcl_chan * 2);
842
843 if (!port_matrix[i].is_4p)
844 continue;
845
846 lgcl_chan = port_matrix[i].lgcl_chan[1];
847 hw_chan = port_matrix[i].hw_chan[1] % 4;
848
849 /* Set software port matrix for existing ports */
850 if (port_matrix[i].exist) {
851 priv->port[pi_id].is_4p = true;
852 priv->port[pi_id].chan[1] = lgcl_chan;
853 }
854
855 /* Set hardware port matrix for all ports */
856 val |= hw_chan << (lgcl_chan * 2);
857 }
858
859 /* Write hardware ports matrix */
860 return i2c_smbus_write_word_data(client, TPS23881_REG_PORT_MAP, val);
861 }
862
863 static int
tps23881_set_ports_conf(struct tps23881_priv * priv,struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])864 tps23881_set_ports_conf(struct tps23881_priv *priv,
865 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
866 {
867 struct i2c_client *client = priv->client;
868 int i, ret;
869 u16 val;
870
871 /* Set operating mode */
872 ret = i2c_smbus_write_word_data(client, TPS23881_REG_OP_MODE,
873 TPS23881_OP_MODE_SEMIAUTO);
874 if (ret)
875 return ret;
876
877 /* Disable DC disconnect */
878 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DIS_EN, 0x0);
879 if (ret)
880 return ret;
881
882 /* Set port power allocation */
883 val = 0;
884 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
885 if (!port_matrix[i].exist)
886 continue;
887
888 if (port_matrix[i].is_4p)
889 val |= 0xf << ((port_matrix[i].lgcl_chan[0] / 2) * 4);
890 else
891 val |= 0x3 << ((port_matrix[i].lgcl_chan[0] / 2) * 4);
892 }
893 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PORT_POWER, val);
894 if (ret)
895 return ret;
896
897 /* Enable detection and classification */
898 val = 0;
899 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
900 if (!port_matrix[i].exist)
901 continue;
902
903 val |= BIT(port_matrix[i].lgcl_chan[0]) |
904 BIT(port_matrix[i].lgcl_chan[0] + 4);
905 if (port_matrix[i].is_4p)
906 val |= BIT(port_matrix[i].lgcl_chan[1]) |
907 BIT(port_matrix[i].lgcl_chan[1] + 4);
908 }
909 return i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val);
910 }
911
912 static int
tps23881_set_ports_matrix(struct tps23881_priv * priv,struct device_node * chan_node[TPS23881_MAX_CHANS])913 tps23881_set_ports_matrix(struct tps23881_priv *priv,
914 struct device_node *chan_node[TPS23881_MAX_CHANS])
915 {
916 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS] = {0};
917 int i, ret;
918
919 /* Update with values for every PSE PIs */
920 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
921 ret = tps23881_match_port_matrix(&priv->pcdev.pi[i], i,
922 chan_node, port_matrix);
923 if (ret)
924 return ret;
925 }
926
927 ret = tps23881_sort_port_matrix(port_matrix);
928 if (ret < 0)
929 return ret;
930
931 ret = tps23881_write_port_matrix(priv, port_matrix, ret);
932 if (ret)
933 return ret;
934
935 return tps23881_set_ports_conf(priv, port_matrix);
936 }
937
tps23881_setup_pi_matrix(struct pse_controller_dev * pcdev)938 static int tps23881_setup_pi_matrix(struct pse_controller_dev *pcdev)
939 {
940 struct device_node *chan_node[TPS23881_MAX_CHANS] = {NULL};
941 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
942 int ret, i;
943
944 ret = tps23881_get_of_channels(priv, chan_node);
945 if (ret < 0) {
946 dev_warn(&priv->client->dev,
947 "Unable to parse port-matrix, default matrix will be used\n");
948 return 0;
949 }
950
951 ret = tps23881_set_ports_matrix(priv, chan_node);
952
953 for (i = 0; i < TPS23881_MAX_CHANS; i++)
954 of_node_put(chan_node[i]);
955
956 return ret;
957 }
958
959 static int tps23881_power_class_table[] = {
960 -ERANGE,
961 4000,
962 7000,
963 15500,
964 30000,
965 15500,
966 15500,
967 -ERANGE,
968 45000,
969 60000,
970 75000,
971 90000,
972 15500,
973 45000,
974 -ERANGE,
975 -ERANGE,
976 };
977
tps23881_pi_get_pw_req(struct pse_controller_dev * pcdev,int id)978 static int tps23881_pi_get_pw_req(struct pse_controller_dev *pcdev, int id)
979 {
980 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
981 struct i2c_client *client = priv->client;
982 u8 reg, chan;
983 int ret;
984 u16 val;
985
986 /* For a 4-pair the classification need 5ms to be completed */
987 if (priv->port[id].is_4p)
988 mdelay(5);
989
990 chan = priv->port[id].chan[0];
991 reg = TPS23881_REG_DISC + (chan % 4);
992 ret = i2c_smbus_read_word_data(client, reg);
993 if (ret < 0)
994 return ret;
995
996 val = tps23881_calc_val(ret, chan, 4, 0xf);
997 return tps23881_power_class_table[val];
998 }
999
1000 static const struct pse_controller_ops tps23881_ops = {
1001 .setup_pi_matrix = tps23881_setup_pi_matrix,
1002 .pi_enable = tps23881_pi_enable,
1003 .pi_disable = tps23881_pi_disable,
1004 .pi_get_admin_state = tps23881_pi_get_admin_state,
1005 .pi_get_pw_status = tps23881_pi_get_pw_status,
1006 .pi_get_pw_class = tps23881_pi_get_pw_class,
1007 .pi_get_actual_pw = tps23881_pi_get_actual_pw,
1008 .pi_get_voltage = tps23881_pi_get_voltage,
1009 .pi_get_pw_limit = tps23881_pi_get_pw_limit,
1010 .pi_set_pw_limit = tps23881_pi_set_pw_limit,
1011 .pi_get_pw_limit_ranges = tps23881_pi_get_pw_limit_ranges,
1012 .pi_get_pw_req = tps23881_pi_get_pw_req,
1013 };
1014
1015 static const char fw_parity_name[] = "ti/tps23881/tps23881-parity-14.bin";
1016 static const char fw_sram_name[] = "ti/tps23881/tps23881-sram-14.bin";
1017
1018 struct tps23881_fw_conf {
1019 u8 reg;
1020 u8 val;
1021 };
1022
1023 static const struct tps23881_fw_conf tps23881_fw_parity_conf[] = {
1024 {.reg = 0x60, .val = 0x01},
1025 {.reg = 0x62, .val = 0x00},
1026 {.reg = 0x63, .val = 0x80},
1027 {.reg = 0x60, .val = 0xC4},
1028 {.reg = 0x1D, .val = 0xBC},
1029 {.reg = 0xD7, .val = 0x02},
1030 {.reg = 0x91, .val = 0x00},
1031 {.reg = 0x90, .val = 0x00},
1032 {.reg = 0xD7, .val = 0x00},
1033 {.reg = 0x1D, .val = 0x00},
1034 { /* sentinel */ }
1035 };
1036
1037 static const struct tps23881_fw_conf tps23881_fw_sram_conf[] = {
1038 {.reg = 0x60, .val = 0xC5},
1039 {.reg = 0x62, .val = 0x00},
1040 {.reg = 0x63, .val = 0x80},
1041 {.reg = 0x60, .val = 0xC0},
1042 {.reg = 0x1D, .val = 0xBC},
1043 {.reg = 0xD7, .val = 0x02},
1044 {.reg = 0x91, .val = 0x00},
1045 {.reg = 0x90, .val = 0x00},
1046 {.reg = 0xD7, .val = 0x00},
1047 {.reg = 0x1D, .val = 0x00},
1048 { /* sentinel */ }
1049 };
1050
tps23881_flash_sram_fw_part(struct i2c_client * client,const char * fw_name,const struct tps23881_fw_conf * fw_conf)1051 static int tps23881_flash_sram_fw_part(struct i2c_client *client,
1052 const char *fw_name,
1053 const struct tps23881_fw_conf *fw_conf)
1054 {
1055 const struct firmware *fw = NULL;
1056 int i, ret;
1057
1058 ret = request_firmware(&fw, fw_name, &client->dev);
1059 if (ret)
1060 return ret;
1061
1062 dev_dbg(&client->dev, "Flashing %s\n", fw_name);
1063
1064 /* Prepare device for RAM download */
1065 while (fw_conf->reg) {
1066 ret = i2c_smbus_write_byte_data(client, fw_conf->reg,
1067 fw_conf->val);
1068 if (ret)
1069 goto out;
1070
1071 fw_conf++;
1072 }
1073
1074 /* Flash the firmware file */
1075 for (i = 0; i < fw->size; i++) {
1076 ret = i2c_smbus_write_byte_data(client,
1077 TPS23881_REG_SRAM_DATA,
1078 fw->data[i]);
1079 if (ret)
1080 goto out;
1081 }
1082
1083 out:
1084 release_firmware(fw);
1085 return ret;
1086 }
1087
tps23881_flash_sram_fw(struct i2c_client * client)1088 static int tps23881_flash_sram_fw(struct i2c_client *client)
1089 {
1090 int ret;
1091
1092 ret = tps23881_flash_sram_fw_part(client, fw_parity_name,
1093 tps23881_fw_parity_conf);
1094 if (ret)
1095 return ret;
1096
1097 ret = tps23881_flash_sram_fw_part(client, fw_sram_name,
1098 tps23881_fw_sram_conf);
1099 if (ret)
1100 return ret;
1101
1102 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_SRAM_CTRL, 0x18);
1103 if (ret)
1104 return ret;
1105
1106 mdelay(12);
1107
1108 return 0;
1109 }
1110
1111 /* Convert interrupt events to 0xff to be aligned with the chan
1112 * number.
1113 */
tps23881_irq_export_chans_helper(u16 reg_val,u8 field_offset)1114 static u8 tps23881_irq_export_chans_helper(u16 reg_val, u8 field_offset)
1115 {
1116 u8 val;
1117
1118 val = (reg_val >> (4 + field_offset) & 0xf0) |
1119 (reg_val >> field_offset & 0x0f);
1120
1121 return val;
1122 }
1123
1124 /* Convert chan number to port number */
tps23881_set_notifs_helper(struct tps23881_priv * priv,u8 chans,unsigned long * notifs,unsigned long * notifs_mask,enum ethtool_pse_event event)1125 static void tps23881_set_notifs_helper(struct tps23881_priv *priv,
1126 u8 chans,
1127 unsigned long *notifs,
1128 unsigned long *notifs_mask,
1129 enum ethtool_pse_event event)
1130 {
1131 u8 chan;
1132 int i;
1133
1134 if (!chans)
1135 return;
1136
1137 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
1138 if (!priv->port[i].exist)
1139 continue;
1140 /* No need to look at the 2nd channel in case of PoE4 as
1141 * both registers are set.
1142 */
1143 chan = priv->port[i].chan[0];
1144
1145 if (BIT(chan) & chans) {
1146 *notifs_mask |= BIT(i);
1147 notifs[i] |= event;
1148 }
1149 }
1150 }
1151
tps23881_irq_event_over_temp(struct tps23881_priv * priv,u16 reg_val,unsigned long * notifs,unsigned long * notifs_mask)1152 static void tps23881_irq_event_over_temp(struct tps23881_priv *priv,
1153 u16 reg_val,
1154 unsigned long *notifs,
1155 unsigned long *notifs_mask)
1156 {
1157 int i;
1158
1159 if (reg_val & TPS23881_REG_TSD) {
1160 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
1161 if (!priv->port[i].exist)
1162 continue;
1163
1164 *notifs_mask |= BIT(i);
1165 notifs[i] |= ETHTOOL_PSE_EVENT_OVER_TEMP;
1166 }
1167 }
1168 }
1169
tps23881_irq_event_over_current(struct tps23881_priv * priv,u16 reg_val,unsigned long * notifs,unsigned long * notifs_mask)1170 static int tps23881_irq_event_over_current(struct tps23881_priv *priv,
1171 u16 reg_val,
1172 unsigned long *notifs,
1173 unsigned long *notifs_mask)
1174 {
1175 int i, ret;
1176 u8 chans;
1177
1178 chans = tps23881_irq_export_chans_helper(reg_val, 0);
1179 if (!chans)
1180 return 0;
1181
1182 tps23881_set_notifs_helper(priv, chans, notifs, notifs_mask,
1183 ETHTOOL_PSE_EVENT_OVER_CURRENT |
1184 ETHTOOL_C33_PSE_EVENT_DISCONNECTION);
1185
1186 /* Over Current event resets the power limit registers so we need
1187 * to configured it again.
1188 */
1189 for_each_set_bit(i, notifs_mask, priv->pcdev.nr_lines) {
1190 if (priv->port[i].pw_pol < 0)
1191 continue;
1192
1193 ret = tps23881_pi_enable_manual_pol(priv, i);
1194 if (ret < 0)
1195 return ret;
1196
1197 /* Set power policy */
1198 ret = tps23881_pi_set_pw_pol_limit(priv, i,
1199 priv->port[i].pw_pol,
1200 priv->port[i].is_4p);
1201 if (ret < 0)
1202 return ret;
1203 }
1204
1205 return 0;
1206 }
1207
tps23881_irq_event_disconnection(struct tps23881_priv * priv,u16 reg_val,unsigned long * notifs,unsigned long * notifs_mask)1208 static void tps23881_irq_event_disconnection(struct tps23881_priv *priv,
1209 u16 reg_val,
1210 unsigned long *notifs,
1211 unsigned long *notifs_mask)
1212 {
1213 u8 chans;
1214
1215 chans = tps23881_irq_export_chans_helper(reg_val, 4);
1216 if (chans)
1217 tps23881_set_notifs_helper(priv, chans, notifs, notifs_mask,
1218 ETHTOOL_C33_PSE_EVENT_DISCONNECTION);
1219 }
1220
tps23881_irq_event_detection(struct tps23881_priv * priv,u16 reg_val,unsigned long * notifs,unsigned long * notifs_mask)1221 static int tps23881_irq_event_detection(struct tps23881_priv *priv,
1222 u16 reg_val,
1223 unsigned long *notifs,
1224 unsigned long *notifs_mask)
1225 {
1226 enum ethtool_pse_event event;
1227 int reg, ret, i, val;
1228 unsigned long chans;
1229
1230 chans = tps23881_irq_export_chans_helper(reg_val, 0);
1231 for_each_set_bit(i, &chans, TPS23881_MAX_CHANS) {
1232 reg = TPS23881_REG_DISC + (i % 4);
1233 ret = i2c_smbus_read_word_data(priv->client, reg);
1234 if (ret < 0)
1235 return ret;
1236
1237 val = tps23881_calc_val(ret, i, 0, 0xf);
1238 /* If detection valid */
1239 if (val == 0x4)
1240 event = ETHTOOL_C33_PSE_EVENT_DETECTION;
1241 else
1242 event = ETHTOOL_C33_PSE_EVENT_DISCONNECTION;
1243
1244 tps23881_set_notifs_helper(priv, BIT(i), notifs,
1245 notifs_mask, event);
1246 }
1247
1248 return 0;
1249 }
1250
tps23881_irq_event_classification(struct tps23881_priv * priv,u16 reg_val,unsigned long * notifs,unsigned long * notifs_mask)1251 static int tps23881_irq_event_classification(struct tps23881_priv *priv,
1252 u16 reg_val,
1253 unsigned long *notifs,
1254 unsigned long *notifs_mask)
1255 {
1256 int reg, ret, val, i;
1257 unsigned long chans;
1258
1259 chans = tps23881_irq_export_chans_helper(reg_val, 4);
1260 for_each_set_bit(i, &chans, TPS23881_MAX_CHANS) {
1261 reg = TPS23881_REG_DISC + (i % 4);
1262 ret = i2c_smbus_read_word_data(priv->client, reg);
1263 if (ret < 0)
1264 return ret;
1265
1266 val = tps23881_calc_val(ret, i, 4, 0xf);
1267 /* Do not report classification event for unknown class */
1268 if (!val || val == 0x8 || val == 0xf)
1269 continue;
1270
1271 tps23881_set_notifs_helper(priv, BIT(i), notifs,
1272 notifs_mask,
1273 ETHTOOL_C33_PSE_EVENT_CLASSIFICATION);
1274 }
1275
1276 return 0;
1277 }
1278
tps23881_irq_event_handler(struct tps23881_priv * priv,u16 reg,unsigned long * notifs,unsigned long * notifs_mask)1279 static int tps23881_irq_event_handler(struct tps23881_priv *priv, u16 reg,
1280 unsigned long *notifs,
1281 unsigned long *notifs_mask)
1282 {
1283 struct i2c_client *client = priv->client;
1284 int ret, val;
1285
1286 /* The Supply event bit is repeated twice so we only need to read
1287 * the one from the first byte.
1288 */
1289 if (reg & TPS23881_REG_IT_SUPF) {
1290 ret = i2c_smbus_read_word_data(client, TPS23881_REG_SUPF_EVENT);
1291 if (ret < 0)
1292 return ret;
1293 tps23881_irq_event_over_temp(priv, ret, notifs, notifs_mask);
1294 }
1295
1296 if (reg & (TPS23881_REG_IT_IFAULT | TPS23881_REG_IT_IFAULT << 8 |
1297 TPS23881_REG_IT_DISF | TPS23881_REG_IT_DISF << 8)) {
1298 ret = i2c_smbus_read_word_data(client, TPS23881_REG_FAULT);
1299 if (ret < 0)
1300 return ret;
1301 ret = tps23881_irq_event_over_current(priv, ret, notifs,
1302 notifs_mask);
1303 if (ret)
1304 return ret;
1305
1306 tps23881_irq_event_disconnection(priv, ret, notifs, notifs_mask);
1307 }
1308
1309 if (reg & (TPS23881_REG_IT_DETC | TPS23881_REG_IT_DETC << 8 |
1310 TPS23881_REG_IT_CLASC | TPS23881_REG_IT_CLASC << 8)) {
1311 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DET_EVENT);
1312 if (ret < 0)
1313 return ret;
1314
1315 val = ret;
1316 ret = tps23881_irq_event_detection(priv, val, notifs,
1317 notifs_mask);
1318 if (ret)
1319 return ret;
1320
1321 ret = tps23881_irq_event_classification(priv, val, notifs,
1322 notifs_mask);
1323 if (ret)
1324 return ret;
1325 }
1326 return 0;
1327 }
1328
tps23881_irq_handler(int irq,struct pse_controller_dev * pcdev,unsigned long * notifs,unsigned long * notifs_mask)1329 static int tps23881_irq_handler(int irq, struct pse_controller_dev *pcdev,
1330 unsigned long *notifs,
1331 unsigned long *notifs_mask)
1332 {
1333 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
1334 struct i2c_client *client = priv->client;
1335 int ret, it_mask, retry;
1336
1337 /* Get interruption mask */
1338 ret = i2c_smbus_read_word_data(client, TPS23881_REG_IT_MASK);
1339 if (ret < 0)
1340 return ret;
1341 it_mask = ret;
1342
1343 /* Read interrupt register until it frees the interruption pin. */
1344 retry = 0;
1345 while (true) {
1346 if (retry > TPS23881_MAX_IRQ_RETRIES) {
1347 dev_err(&client->dev, "interrupt never freed");
1348 return -ETIMEDOUT;
1349 }
1350
1351 ret = i2c_smbus_read_word_data(client, TPS23881_REG_IT);
1352 if (ret < 0)
1353 return ret;
1354
1355 /* No more relevant interruption */
1356 if (!(ret & it_mask))
1357 return 0;
1358
1359 ret = tps23881_irq_event_handler(priv, (u16)ret, notifs,
1360 notifs_mask);
1361 if (ret)
1362 return ret;
1363
1364 retry++;
1365 }
1366 return 0;
1367 }
1368
tps23881_setup_irq(struct tps23881_priv * priv,int irq)1369 static int tps23881_setup_irq(struct tps23881_priv *priv, int irq)
1370 {
1371 struct i2c_client *client = priv->client;
1372 struct pse_irq_desc irq_desc = {
1373 .name = "tps23881-irq",
1374 .map_event = tps23881_irq_handler,
1375 };
1376 int ret;
1377 u16 val;
1378
1379 if (!irq) {
1380 dev_err(&client->dev, "interrupt is missing");
1381 return -EINVAL;
1382 }
1383
1384 val = TPS23881_REG_IT_IFAULT | TPS23881_REG_IT_SUPF |
1385 TPS23881_REG_IT_DETC | TPS23881_REG_IT_CLASC |
1386 TPS23881_REG_IT_DISF;
1387 val |= val << 8;
1388 ret = i2c_smbus_write_word_data(client, TPS23881_REG_IT_MASK, val);
1389 if (ret)
1390 return ret;
1391
1392 ret = i2c_smbus_read_word_data(client, TPS23881_REG_GEN_MASK);
1393 if (ret < 0)
1394 return ret;
1395
1396 val = TPS23881_REG_INTEN | TPS23881_REG_CLCHE | TPS23881_REG_DECHE;
1397 val |= val << 8;
1398 val |= (u16)ret;
1399 ret = i2c_smbus_write_word_data(client, TPS23881_REG_GEN_MASK, val);
1400 if (ret < 0)
1401 return ret;
1402
1403 /* Reset interrupts registers */
1404 ret = i2c_smbus_write_word_data(client, TPS23881_REG_RESET,
1405 TPS23881_REG_CLRAIN);
1406 if (ret < 0)
1407 return ret;
1408
1409 return devm_pse_irq_helper(&priv->pcdev, irq, 0, &irq_desc);
1410 }
1411
tps23881_i2c_probe(struct i2c_client * client)1412 static int tps23881_i2c_probe(struct i2c_client *client)
1413 {
1414 struct device *dev = &client->dev;
1415 struct tps23881_priv *priv;
1416 struct gpio_desc *reset;
1417 int ret;
1418 u8 val;
1419
1420 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1421 dev_err(dev, "i2c check functionality failed\n");
1422 return -ENXIO;
1423 }
1424
1425 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1426 if (!priv)
1427 return -ENOMEM;
1428
1429 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1430 if (IS_ERR(reset))
1431 return dev_err_probe(&client->dev, PTR_ERR(reset), "Failed to get reset GPIO\n");
1432
1433 if (reset) {
1434 /* TPS23880 datasheet (Rev G) indicates minimum reset pulse is 5us */
1435 usleep_range(5, 10);
1436 gpiod_set_value_cansleep(reset, 0); /* De-assert reset */
1437
1438 /* TPS23880 datasheet indicates the minimum time after power on reset
1439 * should be 20ms, but the document describing how to load SRAM ("How
1440 * to Load TPS2388x SRAM and Parity Code over I2C" (Rev E))
1441 * indicates we should delay that programming by at least 50ms. So
1442 * we'll wait the entire 50ms here to ensure we're safe to go to the
1443 * SRAM loading proceedure.
1444 */
1445 msleep(50);
1446 }
1447
1448 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_DEVID);
1449 if (ret < 0)
1450 return ret;
1451
1452 if (FIELD_GET(TPS23881_REG_DEVID_MASK, ret) != TPS23881_DEVICE_ID) {
1453 dev_err(dev, "Wrong device ID\n");
1454 return -ENXIO;
1455 }
1456
1457 ret = tps23881_flash_sram_fw(client);
1458 if (ret < 0)
1459 return ret;
1460
1461 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FWREV);
1462 if (ret < 0)
1463 return ret;
1464
1465 dev_info(&client->dev, "Firmware revision 0x%x\n", ret);
1466
1467 /* Set configuration B, 16 bit access on a single device address */
1468 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_GEN_MASK);
1469 if (ret < 0)
1470 return ret;
1471
1472 val = ret | TPS23881_REG_NBITACC;
1473 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_GEN_MASK, val);
1474 if (ret)
1475 return ret;
1476
1477 priv->client = client;
1478 i2c_set_clientdata(client, priv);
1479 priv->np = dev->of_node;
1480
1481 priv->pcdev.owner = THIS_MODULE;
1482 priv->pcdev.ops = &tps23881_ops;
1483 priv->pcdev.dev = dev;
1484 priv->pcdev.types = ETHTOOL_PSE_C33;
1485 priv->pcdev.nr_lines = TPS23881_MAX_CHANS;
1486 priv->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_STATIC;
1487 ret = devm_pse_controller_register(dev, &priv->pcdev);
1488 if (ret) {
1489 return dev_err_probe(dev, ret,
1490 "failed to register PSE controller\n");
1491 }
1492
1493 ret = tps23881_setup_irq(priv, client->irq);
1494 if (ret)
1495 return ret;
1496
1497 return ret;
1498 }
1499
1500 static const struct i2c_device_id tps23881_id[] = {
1501 { "tps23881" },
1502 { }
1503 };
1504 MODULE_DEVICE_TABLE(i2c, tps23881_id);
1505
1506 static const struct of_device_id tps23881_of_match[] = {
1507 { .compatible = "ti,tps23881", },
1508 { },
1509 };
1510 MODULE_DEVICE_TABLE(of, tps23881_of_match);
1511
1512 static struct i2c_driver tps23881_driver = {
1513 .probe = tps23881_i2c_probe,
1514 .id_table = tps23881_id,
1515 .driver = {
1516 .name = "tps23881",
1517 .of_match_table = tps23881_of_match,
1518 },
1519 };
1520 module_i2c_driver(tps23881_driver);
1521
1522 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>");
1523 MODULE_DESCRIPTION("TI TPS23881 PoE PSE Controller driver");
1524 MODULE_LICENSE("GPL");
1525