1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the TI TPS23881 PoE PSE Controller driver (I2C bus) 4 * 5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/firmware.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pse-pd/pse.h> 17 18 #define TPS23881_MAX_CHANS 8 19 #define TPS23881_MAX_IRQ_RETRIES 10 20 21 #define TPS23881_REG_IT 0x0 22 #define TPS23881_REG_IT_MASK 0x1 23 #define TPS23881_REG_IT_DISF BIT(2) 24 #define TPS23881_REG_IT_DETC BIT(3) 25 #define TPS23881_REG_IT_CLASC BIT(4) 26 #define TPS23881_REG_IT_IFAULT BIT(5) 27 #define TPS23881_REG_IT_SUPF BIT(7) 28 #define TPS23881_REG_DET_EVENT 0x5 29 #define TPS23881_REG_FAULT 0x7 30 #define TPS23881_REG_SUPF_EVENT 0xb 31 #define TPS23881_REG_TSD BIT(7) 32 #define TPS23881_REG_DISC 0xc 33 #define TPS23881_REG_PW_STATUS 0x10 34 #define TPS23881_REG_OP_MODE 0x12 35 #define TPS23881_REG_DISC_EN 0x13 36 #define TPS23881_OP_MODE_SEMIAUTO 0xaaaa 37 #define TPS23881_REG_DIS_EN 0x13 38 #define TPS23881_REG_DET_CLA_EN 0x14 39 #define TPS23881_REG_GEN_MASK 0x17 40 #define TPS23881_REG_CLCHE BIT(2) 41 #define TPS23881_REG_DECHE BIT(3) 42 #define TPS23881_REG_NBITACC BIT(5) 43 #define TPS23881_REG_INTEN BIT(7) 44 #define TPS23881_REG_PW_EN 0x19 45 #define TPS23881_REG_RESET 0x1a 46 #define TPS23881_REG_CLRAIN BIT(7) 47 #define TPS23881_REG_2PAIR_POL1 0x1e 48 #define TPS23881_REG_PORT_MAP 0x26 49 #define TPS23881_REG_PORT_POWER 0x29 50 #define TPS23881_REG_4PAIR_POL1 0x2a 51 #define TPS23881_REG_INPUT_V 0x2e 52 #define TPS23881_REG_CHAN1_A 0x30 53 #define TPS23881_REG_CHAN1_V 0x32 54 #define TPS23881_REG_FOLDBACK 0x40 55 #define TPS23881_REG_TPON BIT(0) 56 #define TPS23881_REG_FWREV 0x41 57 #define TPS23881_REG_DEVID 0x43 58 #define TPS23881_REG_CHAN1_CLASS 0x4c 59 #define TPS23881_REG_SRAM_CTRL 0x60 60 #define TPS23881_REG_SRAM_DATA 0x61 61 62 #define TPS23881_UV_STEP 3662 63 #define TPS23881_NA_STEP 89500 64 #define TPS23881_MW_STEP 500 65 #define TPS23881_MIN_PI_PW_LIMIT_MW 2000 66 67 struct tps23881_port_desc { 68 u8 chan[2]; 69 bool is_4p; 70 int pw_pol; 71 bool exist; 72 }; 73 74 struct tps23881_priv { 75 struct i2c_client *client; 76 struct pse_controller_dev pcdev; 77 struct device_node *np; 78 struct tps23881_port_desc port[TPS23881_MAX_CHANS]; 79 }; 80 81 static struct tps23881_priv *to_tps23881_priv(struct pse_controller_dev *pcdev) 82 { 83 return container_of(pcdev, struct tps23881_priv, pcdev); 84 } 85 86 /* 87 * Helper to extract a value from a u16 register value, which is made of two 88 * u8 registers. The function calculates the bit offset based on the channel 89 * and extracts the relevant bits using a provided field mask. 90 * 91 * @param reg_val: The u16 register value (composed of two u8 registers). 92 * @param chan: The channel number (0-7). 93 * @param field_offset: The base bit offset to apply (e.g., 0 or 4). 94 * @param field_mask: The mask to apply to extract the required bits. 95 * @return: The extracted value for the specific channel. 96 */ 97 static u16 tps23881_calc_val(u16 reg_val, u8 chan, u8 field_offset, 98 u16 field_mask) 99 { 100 if (chan >= 4) 101 reg_val >>= 8; 102 103 return (reg_val >> field_offset) & field_mask; 104 } 105 106 /* 107 * Helper to combine individual channel values into a u16 register value. 108 * The function sets the value for a specific channel in the appropriate 109 * position. 110 * 111 * @param reg_val: The current u16 register value. 112 * @param chan: The channel number (0-7). 113 * @param field_offset: The base bit offset to apply (e.g., 0 or 4). 114 * @param field_mask: The mask to apply for the field (e.g., 0x0F). 115 * @param field_val: The value to set for the specific channel (masked by 116 * field_mask). 117 * @return: The updated u16 register value with the channel value set. 118 */ 119 static u16 tps23881_set_val(u16 reg_val, u8 chan, u8 field_offset, 120 u16 field_mask, u16 field_val) 121 { 122 field_val &= field_mask; 123 124 if (chan < 4) { 125 reg_val &= ~(field_mask << field_offset); 126 reg_val |= (field_val << field_offset); 127 } else { 128 reg_val &= ~(field_mask << (field_offset + 8)); 129 reg_val |= (field_val << (field_offset + 8)); 130 } 131 132 return reg_val; 133 } 134 135 static int 136 tps23881_pi_set_pw_pol_limit(struct tps23881_priv *priv, int id, u8 pw_pol, 137 bool is_4p) 138 { 139 struct i2c_client *client = priv->client; 140 int ret, reg; 141 u16 val; 142 u8 chan; 143 144 chan = priv->port[id].chan[0]; 145 if (!is_4p) { 146 reg = TPS23881_REG_2PAIR_POL1 + (chan % 4); 147 } else { 148 /* One chan is enough to configure the 4p PI power limit */ 149 if ((chan % 4) < 2) 150 reg = TPS23881_REG_4PAIR_POL1; 151 else 152 reg = TPS23881_REG_4PAIR_POL1 + 1; 153 } 154 155 ret = i2c_smbus_read_word_data(client, reg); 156 if (ret < 0) 157 return ret; 158 159 val = tps23881_set_val(ret, chan, 0, 0xff, pw_pol); 160 return i2c_smbus_write_word_data(client, reg, val); 161 } 162 163 static int tps23881_pi_enable_manual_pol(struct tps23881_priv *priv, int id) 164 { 165 struct i2c_client *client = priv->client; 166 int ret; 167 u8 chan; 168 u16 val; 169 170 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FOLDBACK); 171 if (ret < 0) 172 return ret; 173 174 /* No need to test if the chan is PoE4 as setting either bit for a 175 * 4P configured port disables the automatic configuration on both 176 * channels. 177 */ 178 chan = priv->port[id].chan[0]; 179 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4)); 180 return i2c_smbus_write_byte_data(client, TPS23881_REG_FOLDBACK, val); 181 } 182 183 static int tps23881_pi_enable(struct pse_controller_dev *pcdev, int id) 184 { 185 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 186 struct i2c_client *client = priv->client; 187 u8 chan; 188 u16 val; 189 int ret; 190 191 if (id >= TPS23881_MAX_CHANS) 192 return -ERANGE; 193 194 chan = priv->port[id].chan[0]; 195 val = tps23881_set_val(0, chan, 0, BIT(chan % 4), BIT(chan % 4)); 196 197 if (priv->port[id].is_4p) { 198 chan = priv->port[id].chan[1]; 199 val = tps23881_set_val(val, chan, 0, BIT(chan % 4), 200 BIT(chan % 4)); 201 } 202 203 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val); 204 if (ret) 205 return ret; 206 207 /* Enable DC disconnect*/ 208 chan = priv->port[id].chan[0]; 209 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DISC_EN); 210 if (ret < 0) 211 return ret; 212 213 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4)); 214 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DISC_EN, val); 215 if (ret) 216 return ret; 217 218 return 0; 219 } 220 221 static int tps23881_pi_disable(struct pse_controller_dev *pcdev, int id) 222 { 223 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 224 struct i2c_client *client = priv->client; 225 u8 chan; 226 u16 val; 227 int ret; 228 229 if (id >= TPS23881_MAX_CHANS) 230 return -ERANGE; 231 232 chan = priv->port[id].chan[0]; 233 val = tps23881_set_val(0, chan, 4, BIT(chan % 4), BIT(chan % 4)); 234 235 if (priv->port[id].is_4p) { 236 chan = priv->port[id].chan[1]; 237 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), 238 BIT(chan % 4)); 239 } 240 241 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val); 242 if (ret) 243 return ret; 244 245 /* PWOFF command resets lots of register which need to be 246 * configured again. According to the datasheet "It may take upwards 247 * of 5ms after PWOFFn command for all register values to be updated" 248 */ 249 mdelay(5); 250 251 /* Disable DC disconnect*/ 252 chan = priv->port[id].chan[0]; 253 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DISC_EN); 254 if (ret < 0) 255 return ret; 256 257 val = tps23881_set_val(ret, chan, 0, 0, BIT(chan % 4)); 258 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DISC_EN, val); 259 if (ret) 260 return ret; 261 262 /* Enable detection and classification */ 263 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DET_CLA_EN); 264 if (ret < 0) 265 return ret; 266 267 chan = priv->port[id].chan[0]; 268 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4)); 269 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), BIT(chan % 4)); 270 271 if (priv->port[id].is_4p) { 272 chan = priv->port[id].chan[1]; 273 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), 274 BIT(chan % 4)); 275 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), 276 BIT(chan % 4)); 277 } 278 279 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val); 280 if (ret) 281 return ret; 282 283 /* No power policy */ 284 if (priv->port[id].pw_pol < 0) 285 return 0; 286 287 ret = tps23881_pi_enable_manual_pol(priv, id); 288 if (ret < 0) 289 return ret; 290 291 /* Set power policy */ 292 return tps23881_pi_set_pw_pol_limit(priv, id, priv->port[id].pw_pol, 293 priv->port[id].is_4p); 294 } 295 296 static int 297 tps23881_pi_get_admin_state(struct pse_controller_dev *pcdev, int id, 298 struct pse_admin_state *admin_state) 299 { 300 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 301 struct i2c_client *client = priv->client; 302 bool enabled; 303 u8 chan; 304 u16 val; 305 int ret; 306 307 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS); 308 if (ret < 0) 309 return ret; 310 311 chan = priv->port[id].chan[0]; 312 val = tps23881_calc_val(ret, chan, 0, BIT(chan % 4)); 313 enabled = !!(val); 314 315 if (priv->port[id].is_4p) { 316 chan = priv->port[id].chan[1]; 317 val = tps23881_calc_val(ret, chan, 0, BIT(chan % 4)); 318 enabled &= !!(val); 319 } 320 321 /* Return enabled status only if both channel are on this state */ 322 if (enabled) 323 admin_state->c33_admin_state = 324 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 325 else 326 admin_state->c33_admin_state = 327 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 328 329 return 0; 330 } 331 332 static int 333 tps23881_pi_get_pw_status(struct pse_controller_dev *pcdev, int id, 334 struct pse_pw_status *pw_status) 335 { 336 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 337 struct i2c_client *client = priv->client; 338 bool delivering; 339 u8 chan; 340 u16 val; 341 int ret; 342 343 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS); 344 if (ret < 0) 345 return ret; 346 347 chan = priv->port[id].chan[0]; 348 val = tps23881_calc_val(ret, chan, 4, BIT(chan % 4)); 349 delivering = !!(val); 350 351 if (priv->port[id].is_4p) { 352 chan = priv->port[id].chan[1]; 353 val = tps23881_calc_val(ret, chan, 4, BIT(chan % 4)); 354 delivering &= !!(val); 355 } 356 357 /* Return delivering status only if both channel are on this state */ 358 if (delivering) 359 pw_status->c33_pw_status = 360 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; 361 else 362 pw_status->c33_pw_status = 363 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; 364 365 return 0; 366 } 367 368 static int tps23881_pi_get_voltage(struct pse_controller_dev *pcdev, int id) 369 { 370 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 371 struct i2c_client *client = priv->client; 372 int ret; 373 u64 uV; 374 375 ret = i2c_smbus_read_word_data(client, TPS23881_REG_INPUT_V); 376 if (ret < 0) 377 return ret; 378 379 uV = ret & 0x3fff; 380 uV *= TPS23881_UV_STEP; 381 382 return (int)uV; 383 } 384 385 static int 386 tps23881_pi_get_chan_current(struct tps23881_priv *priv, u8 chan) 387 { 388 struct i2c_client *client = priv->client; 389 int reg, ret; 390 u64 tmp_64; 391 392 /* Registers 0x30 to 0x3d */ 393 reg = TPS23881_REG_CHAN1_A + (chan % 4) * 4 + (chan >= 4); 394 ret = i2c_smbus_read_word_data(client, reg); 395 if (ret < 0) 396 return ret; 397 398 tmp_64 = ret & 0x3fff; 399 tmp_64 *= TPS23881_NA_STEP; 400 /* uA = nA / 1000 */ 401 tmp_64 = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000); 402 return (int)tmp_64; 403 } 404 405 static int tps23881_pi_get_pw_class(struct pse_controller_dev *pcdev, 406 int id) 407 { 408 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 409 struct i2c_client *client = priv->client; 410 int ret, reg; 411 u8 chan; 412 413 chan = priv->port[id].chan[0]; 414 reg = TPS23881_REG_CHAN1_CLASS + (chan % 4); 415 ret = i2c_smbus_read_word_data(client, reg); 416 if (ret < 0) 417 return ret; 418 419 return tps23881_calc_val(ret, chan, 4, 0x0f); 420 } 421 422 static int 423 tps23881_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id) 424 { 425 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 426 int ret, uV, uA; 427 u64 tmp_64; 428 u8 chan; 429 430 ret = tps23881_pi_get_voltage(&priv->pcdev, id); 431 if (ret < 0) 432 return ret; 433 uV = ret; 434 435 chan = priv->port[id].chan[0]; 436 ret = tps23881_pi_get_chan_current(priv, chan); 437 if (ret < 0) 438 return ret; 439 uA = ret; 440 441 if (priv->port[id].is_4p) { 442 chan = priv->port[id].chan[1]; 443 ret = tps23881_pi_get_chan_current(priv, chan); 444 if (ret < 0) 445 return ret; 446 uA += ret; 447 } 448 449 tmp_64 = uV; 450 tmp_64 *= uA; 451 /* mW = uV * uA / 1000000000 */ 452 return DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000); 453 } 454 455 static int 456 tps23881_pi_get_pw_limit_chan(struct tps23881_priv *priv, u8 chan) 457 { 458 struct i2c_client *client = priv->client; 459 int ret, reg; 460 u16 val; 461 462 reg = TPS23881_REG_2PAIR_POL1 + (chan % 4); 463 ret = i2c_smbus_read_word_data(client, reg); 464 if (ret < 0) 465 return ret; 466 467 val = tps23881_calc_val(ret, chan, 0, 0xff); 468 return val * TPS23881_MW_STEP; 469 } 470 471 static int tps23881_pi_get_pw_limit(struct pse_controller_dev *pcdev, int id) 472 { 473 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 474 int ret, mW; 475 u8 chan; 476 477 chan = priv->port[id].chan[0]; 478 ret = tps23881_pi_get_pw_limit_chan(priv, chan); 479 if (ret < 0) 480 return ret; 481 482 mW = ret; 483 if (priv->port[id].is_4p) { 484 chan = priv->port[id].chan[1]; 485 ret = tps23881_pi_get_pw_limit_chan(priv, chan); 486 if (ret < 0) 487 return ret; 488 mW += ret; 489 } 490 491 return mW; 492 } 493 494 static int tps23881_pi_set_pw_limit(struct pse_controller_dev *pcdev, 495 int id, int max_mW) 496 { 497 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 498 u8 pw_pol; 499 int ret; 500 501 if (max_mW < TPS23881_MIN_PI_PW_LIMIT_MW || MAX_PI_PW < max_mW) { 502 dev_err(&priv->client->dev, 503 "power limit %d out of ranges [%d,%d]", 504 max_mW, TPS23881_MIN_PI_PW_LIMIT_MW, MAX_PI_PW); 505 return -ERANGE; 506 } 507 508 ret = tps23881_pi_enable_manual_pol(priv, id); 509 if (ret < 0) 510 return ret; 511 512 pw_pol = DIV_ROUND_CLOSEST_ULL(max_mW, TPS23881_MW_STEP); 513 514 /* Save power policy to reconfigure it after a disabled call */ 515 priv->port[id].pw_pol = pw_pol; 516 return tps23881_pi_set_pw_pol_limit(priv, id, pw_pol, 517 priv->port[id].is_4p); 518 } 519 520 static int 521 tps23881_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id, 522 struct pse_pw_limit_ranges *pw_limit_ranges) 523 { 524 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 525 526 c33_pw_limit_ranges = kzalloc(sizeof(*c33_pw_limit_ranges), 527 GFP_KERNEL); 528 if (!c33_pw_limit_ranges) 529 return -ENOMEM; 530 531 c33_pw_limit_ranges->min = TPS23881_MIN_PI_PW_LIMIT_MW; 532 c33_pw_limit_ranges->max = MAX_PI_PW; 533 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges; 534 535 /* Return the number of ranges */ 536 return 1; 537 } 538 539 /* Parse managers subnode into a array of device node */ 540 static int 541 tps23881_get_of_channels(struct tps23881_priv *priv, 542 struct device_node *chan_node[TPS23881_MAX_CHANS]) 543 { 544 struct device_node *channels_node, *node; 545 int i, ret; 546 547 if (!priv->np) 548 return -EINVAL; 549 550 channels_node = of_find_node_by_name(priv->np, "channels"); 551 if (!channels_node) 552 return -EINVAL; 553 554 for_each_child_of_node(channels_node, node) { 555 u32 chan_id; 556 557 if (!of_node_name_eq(node, "channel")) 558 continue; 559 560 ret = of_property_read_u32(node, "reg", &chan_id); 561 if (ret) { 562 ret = -EINVAL; 563 goto out; 564 } 565 566 if (chan_id >= TPS23881_MAX_CHANS || chan_node[chan_id]) { 567 dev_err(&priv->client->dev, 568 "wrong number of port (%d)\n", chan_id); 569 ret = -EINVAL; 570 goto out; 571 } 572 573 of_node_get(node); 574 chan_node[chan_id] = node; 575 } 576 577 of_node_put(channels_node); 578 return 0; 579 580 out: 581 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 582 of_node_put(chan_node[i]); 583 chan_node[i] = NULL; 584 } 585 586 of_node_put(node); 587 of_node_put(channels_node); 588 return ret; 589 } 590 591 struct tps23881_port_matrix { 592 u8 pi_id; 593 u8 lgcl_chan[2]; 594 u8 hw_chan[2]; 595 bool is_4p; 596 bool exist; 597 }; 598 599 static int 600 tps23881_match_channel(const struct pse_pi_pairset *pairset, 601 struct device_node *chan_node[TPS23881_MAX_CHANS]) 602 { 603 int i; 604 605 /* Look on every channels */ 606 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 607 if (pairset->np == chan_node[i]) 608 return i; 609 } 610 611 return -ENODEV; 612 } 613 614 static bool 615 tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 616 int chan) 617 { 618 int i; 619 620 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 621 if (port_matrix[i].exist && 622 (port_matrix[i].hw_chan[0] == chan || 623 port_matrix[i].hw_chan[1] == chan)) 624 return false; 625 } 626 627 return true; 628 } 629 630 /* Fill port matrix with the matching channels */ 631 static int 632 tps23881_match_port_matrix(struct pse_pi *pi, int pi_id, 633 struct device_node *chan_node[TPS23881_MAX_CHANS], 634 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 635 { 636 int ret; 637 638 if (!pi->pairset[0].np) 639 return 0; 640 641 ret = tps23881_match_channel(&pi->pairset[0], chan_node); 642 if (ret < 0) 643 return ret; 644 645 if (!tps23881_is_chan_free(port_matrix, ret)) { 646 pr_err("tps23881: channel %d already used\n", ret); 647 return -ENODEV; 648 } 649 650 port_matrix[pi_id].hw_chan[0] = ret; 651 port_matrix[pi_id].exist = true; 652 653 if (!pi->pairset[1].np) 654 return 0; 655 656 ret = tps23881_match_channel(&pi->pairset[1], chan_node); 657 if (ret < 0) 658 return ret; 659 660 if (!tps23881_is_chan_free(port_matrix, ret)) { 661 pr_err("tps23881: channel %d already used\n", ret); 662 return -ENODEV; 663 } 664 665 if (port_matrix[pi_id].hw_chan[0] / 4 != ret / 4) { 666 pr_err("tps23881: 4-pair PSE can only be set within the same 4 ports group"); 667 return -ENODEV; 668 } 669 670 port_matrix[pi_id].hw_chan[1] = ret; 671 port_matrix[pi_id].is_4p = true; 672 673 return 0; 674 } 675 676 static int 677 tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 678 int port_cnt) 679 { 680 bool used; 681 int i, j; 682 683 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 684 used = false; 685 686 for (j = 0; j < port_cnt; j++) { 687 if (port_matrix[j].hw_chan[0] == i) { 688 used = true; 689 break; 690 } 691 692 if (port_matrix[j].is_4p && 693 port_matrix[j].hw_chan[1] == i) { 694 used = true; 695 break; 696 } 697 } 698 699 if (!used) 700 return i; 701 } 702 703 return -ENODEV; 704 } 705 706 /* Sort the port matrix to following particular hardware ports matrix 707 * specification of the tps23881. The device has two 4-ports groups and 708 * each 4-pair powered device has to be configured to use two consecutive 709 * logical channel in each 4 ports group (1 and 2 or 3 and 4). Also the 710 * hardware matrix has to be fully configured even with unused chan to be 711 * valid. 712 */ 713 static int 714 tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 715 { 716 struct tps23881_port_matrix tmp_port_matrix[TPS23881_MAX_CHANS] = {0}; 717 int i, ret, port_cnt = 0, cnt_4ch_grp1 = 0, cnt_4ch_grp2 = 4; 718 719 /* Configure 4p port matrix */ 720 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 721 int *cnt; 722 723 if (!port_matrix[i].exist || !port_matrix[i].is_4p) 724 continue; 725 726 if (port_matrix[i].hw_chan[0] < 4) 727 cnt = &cnt_4ch_grp1; 728 else 729 cnt = &cnt_4ch_grp2; 730 731 tmp_port_matrix[port_cnt].exist = true; 732 tmp_port_matrix[port_cnt].is_4p = true; 733 tmp_port_matrix[port_cnt].pi_id = i; 734 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0]; 735 tmp_port_matrix[port_cnt].hw_chan[1] = port_matrix[i].hw_chan[1]; 736 737 /* 4-pair ports have to be configured with consecutive 738 * logical channels 0 and 1, 2 and 3. 739 */ 740 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++; 741 tmp_port_matrix[port_cnt].lgcl_chan[1] = (*cnt)++; 742 743 port_cnt++; 744 } 745 746 /* Configure 2p port matrix */ 747 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 748 int *cnt; 749 750 if (!port_matrix[i].exist || port_matrix[i].is_4p) 751 continue; 752 753 if (port_matrix[i].hw_chan[0] < 4) 754 cnt = &cnt_4ch_grp1; 755 else 756 cnt = &cnt_4ch_grp2; 757 758 tmp_port_matrix[port_cnt].exist = true; 759 tmp_port_matrix[port_cnt].pi_id = i; 760 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++; 761 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0]; 762 763 port_cnt++; 764 } 765 766 /* Complete the rest of the first 4 port group matrix even if 767 * channels are unused 768 */ 769 while (cnt_4ch_grp1 < 4) { 770 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt); 771 if (ret < 0) { 772 pr_err("tps23881: port matrix issue, no chan available\n"); 773 return ret; 774 } 775 776 if (port_cnt >= TPS23881_MAX_CHANS) { 777 pr_err("tps23881: wrong number of channels\n"); 778 return -ENODEV; 779 } 780 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp1; 781 tmp_port_matrix[port_cnt].hw_chan[0] = ret; 782 cnt_4ch_grp1++; 783 port_cnt++; 784 } 785 786 /* Complete the rest of the second 4 port group matrix even if 787 * channels are unused 788 */ 789 while (cnt_4ch_grp2 < 8) { 790 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt); 791 if (ret < 0) { 792 pr_err("tps23881: port matrix issue, no chan available\n"); 793 return -ENODEV; 794 } 795 796 if (port_cnt >= TPS23881_MAX_CHANS) { 797 pr_err("tps23881: wrong number of channels\n"); 798 return -ENODEV; 799 } 800 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp2; 801 tmp_port_matrix[port_cnt].hw_chan[0] = ret; 802 cnt_4ch_grp2++; 803 port_cnt++; 804 } 805 806 memcpy(port_matrix, tmp_port_matrix, sizeof(tmp_port_matrix)); 807 808 return port_cnt; 809 } 810 811 /* Write port matrix to the hardware port matrix and the software port 812 * matrix. 813 */ 814 static int 815 tps23881_write_port_matrix(struct tps23881_priv *priv, 816 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 817 int port_cnt) 818 { 819 struct i2c_client *client = priv->client; 820 u8 pi_id, lgcl_chan, hw_chan; 821 u16 val = 0; 822 int i; 823 824 for (i = 0; i < port_cnt; i++) { 825 pi_id = port_matrix[i].pi_id; 826 lgcl_chan = port_matrix[i].lgcl_chan[0]; 827 hw_chan = port_matrix[i].hw_chan[0] % 4; 828 829 /* Set software port matrix for existing ports */ 830 if (port_matrix[i].exist) { 831 priv->port[pi_id].chan[0] = lgcl_chan; 832 priv->port[pi_id].exist = true; 833 } 834 835 /* Initialize power policy internal value */ 836 priv->port[pi_id].pw_pol = -1; 837 838 /* Set hardware port matrix for all ports */ 839 val |= hw_chan << (lgcl_chan * 2); 840 841 if (!port_matrix[i].is_4p) 842 continue; 843 844 lgcl_chan = port_matrix[i].lgcl_chan[1]; 845 hw_chan = port_matrix[i].hw_chan[1] % 4; 846 847 /* Set software port matrix for existing ports */ 848 if (port_matrix[i].exist) { 849 priv->port[pi_id].is_4p = true; 850 priv->port[pi_id].chan[1] = lgcl_chan; 851 } 852 853 /* Set hardware port matrix for all ports */ 854 val |= hw_chan << (lgcl_chan * 2); 855 } 856 857 /* Write hardware ports matrix */ 858 return i2c_smbus_write_word_data(client, TPS23881_REG_PORT_MAP, val); 859 } 860 861 static int 862 tps23881_set_ports_conf(struct tps23881_priv *priv, 863 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 864 { 865 struct i2c_client *client = priv->client; 866 int i, ret; 867 u16 val; 868 869 /* Set operating mode */ 870 ret = i2c_smbus_write_word_data(client, TPS23881_REG_OP_MODE, 871 TPS23881_OP_MODE_SEMIAUTO); 872 if (ret) 873 return ret; 874 875 /* Disable DC disconnect */ 876 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DIS_EN, 0x0); 877 if (ret) 878 return ret; 879 880 /* Set port power allocation */ 881 val = 0; 882 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 883 if (!port_matrix[i].exist) 884 continue; 885 886 if (port_matrix[i].is_4p) 887 val |= 0xf << ((port_matrix[i].lgcl_chan[0] / 2) * 4); 888 else 889 val |= 0x3 << ((port_matrix[i].lgcl_chan[0] / 2) * 4); 890 } 891 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PORT_POWER, val); 892 if (ret) 893 return ret; 894 895 /* Enable detection and classification */ 896 val = 0; 897 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 898 if (!port_matrix[i].exist) 899 continue; 900 901 val |= BIT(port_matrix[i].lgcl_chan[0]) | 902 BIT(port_matrix[i].lgcl_chan[0] + 4); 903 if (port_matrix[i].is_4p) 904 val |= BIT(port_matrix[i].lgcl_chan[1]) | 905 BIT(port_matrix[i].lgcl_chan[1] + 4); 906 } 907 return i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val); 908 } 909 910 static int 911 tps23881_set_ports_matrix(struct tps23881_priv *priv, 912 struct device_node *chan_node[TPS23881_MAX_CHANS]) 913 { 914 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS] = {0}; 915 int i, ret; 916 917 /* Update with values for every PSE PIs */ 918 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 919 ret = tps23881_match_port_matrix(&priv->pcdev.pi[i], i, 920 chan_node, port_matrix); 921 if (ret) 922 return ret; 923 } 924 925 ret = tps23881_sort_port_matrix(port_matrix); 926 if (ret < 0) 927 return ret; 928 929 ret = tps23881_write_port_matrix(priv, port_matrix, ret); 930 if (ret) 931 return ret; 932 933 return tps23881_set_ports_conf(priv, port_matrix); 934 } 935 936 static int tps23881_setup_pi_matrix(struct pse_controller_dev *pcdev) 937 { 938 struct device_node *chan_node[TPS23881_MAX_CHANS] = {NULL}; 939 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 940 int ret, i; 941 942 ret = tps23881_get_of_channels(priv, chan_node); 943 if (ret < 0) { 944 dev_warn(&priv->client->dev, 945 "Unable to parse port-matrix, default matrix will be used\n"); 946 return 0; 947 } 948 949 ret = tps23881_set_ports_matrix(priv, chan_node); 950 951 for (i = 0; i < TPS23881_MAX_CHANS; i++) 952 of_node_put(chan_node[i]); 953 954 return ret; 955 } 956 957 static int tps23881_power_class_table[] = { 958 -ERANGE, 959 4000, 960 7000, 961 15500, 962 30000, 963 15500, 964 15500, 965 -ERANGE, 966 45000, 967 60000, 968 75000, 969 90000, 970 15500, 971 45000, 972 -ERANGE, 973 -ERANGE, 974 }; 975 976 static int tps23881_pi_get_pw_req(struct pse_controller_dev *pcdev, int id) 977 { 978 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 979 struct i2c_client *client = priv->client; 980 u8 reg, chan; 981 int ret; 982 u16 val; 983 984 /* For a 4-pair the classification need 5ms to be completed */ 985 if (priv->port[id].is_4p) 986 mdelay(5); 987 988 chan = priv->port[id].chan[0]; 989 reg = TPS23881_REG_DISC + (chan % 4); 990 ret = i2c_smbus_read_word_data(client, reg); 991 if (ret < 0) 992 return ret; 993 994 val = tps23881_calc_val(ret, chan, 4, 0xf); 995 return tps23881_power_class_table[val]; 996 } 997 998 static const struct pse_controller_ops tps23881_ops = { 999 .setup_pi_matrix = tps23881_setup_pi_matrix, 1000 .pi_enable = tps23881_pi_enable, 1001 .pi_disable = tps23881_pi_disable, 1002 .pi_get_admin_state = tps23881_pi_get_admin_state, 1003 .pi_get_pw_status = tps23881_pi_get_pw_status, 1004 .pi_get_pw_class = tps23881_pi_get_pw_class, 1005 .pi_get_actual_pw = tps23881_pi_get_actual_pw, 1006 .pi_get_voltage = tps23881_pi_get_voltage, 1007 .pi_get_pw_limit = tps23881_pi_get_pw_limit, 1008 .pi_set_pw_limit = tps23881_pi_set_pw_limit, 1009 .pi_get_pw_limit_ranges = tps23881_pi_get_pw_limit_ranges, 1010 .pi_get_pw_req = tps23881_pi_get_pw_req, 1011 }; 1012 1013 struct tps23881_info { 1014 u8 dev_id; /* device ID and silicon revision */ 1015 const char *fw_parity_name; /* parity code firmware file name */ 1016 const char *fw_sram_name; /* SRAM code firmware file name */ 1017 }; 1018 1019 enum tps23881_model { 1020 TPS23881, 1021 TPS23881B, 1022 }; 1023 1024 static const struct tps23881_info tps23881_info[] = { 1025 [TPS23881] = { 1026 .dev_id = 0x22, 1027 .fw_parity_name = "ti/tps23881/tps23881-parity-14.bin", 1028 .fw_sram_name = "ti/tps23881/tps23881-sram-14.bin", 1029 }, 1030 [TPS23881B] = { 1031 .dev_id = 0x24, 1032 /* skip SRAM load, ROM provides Clause 145 hardware-level support */ 1033 }, 1034 }; 1035 1036 struct tps23881_fw_conf { 1037 u8 reg; 1038 u8 val; 1039 }; 1040 1041 static const struct tps23881_fw_conf tps23881_fw_parity_conf[] = { 1042 {.reg = 0x60, .val = 0x01}, 1043 {.reg = 0x62, .val = 0x00}, 1044 {.reg = 0x63, .val = 0x80}, 1045 {.reg = 0x60, .val = 0xC4}, 1046 {.reg = 0x1D, .val = 0xBC}, 1047 {.reg = 0xD7, .val = 0x02}, 1048 {.reg = 0x91, .val = 0x00}, 1049 {.reg = 0x90, .val = 0x00}, 1050 {.reg = 0xD7, .val = 0x00}, 1051 {.reg = 0x1D, .val = 0x00}, 1052 { /* sentinel */ } 1053 }; 1054 1055 static const struct tps23881_fw_conf tps23881_fw_sram_conf[] = { 1056 {.reg = 0x60, .val = 0xC5}, 1057 {.reg = 0x62, .val = 0x00}, 1058 {.reg = 0x63, .val = 0x80}, 1059 {.reg = 0x60, .val = 0xC0}, 1060 {.reg = 0x1D, .val = 0xBC}, 1061 {.reg = 0xD7, .val = 0x02}, 1062 {.reg = 0x91, .val = 0x00}, 1063 {.reg = 0x90, .val = 0x00}, 1064 {.reg = 0xD7, .val = 0x00}, 1065 {.reg = 0x1D, .val = 0x00}, 1066 { /* sentinel */ } 1067 }; 1068 1069 static int tps23881_flash_sram_fw_part(struct i2c_client *client, 1070 const char *fw_name, 1071 const struct tps23881_fw_conf *fw_conf) 1072 { 1073 const struct firmware *fw = NULL; 1074 int i, ret; 1075 1076 ret = request_firmware(&fw, fw_name, &client->dev); 1077 if (ret) 1078 return ret; 1079 1080 dev_dbg(&client->dev, "Flashing %s\n", fw_name); 1081 1082 /* Prepare device for RAM download */ 1083 while (fw_conf->reg) { 1084 ret = i2c_smbus_write_byte_data(client, fw_conf->reg, 1085 fw_conf->val); 1086 if (ret) 1087 goto out; 1088 1089 fw_conf++; 1090 } 1091 1092 /* Flash the firmware file */ 1093 for (i = 0; i < fw->size; i++) { 1094 ret = i2c_smbus_write_byte_data(client, 1095 TPS23881_REG_SRAM_DATA, 1096 fw->data[i]); 1097 if (ret) 1098 goto out; 1099 } 1100 1101 out: 1102 release_firmware(fw); 1103 return ret; 1104 } 1105 1106 static int tps23881_flash_sram_fw(struct i2c_client *client, 1107 const struct tps23881_info *info) 1108 { 1109 int ret; 1110 1111 ret = tps23881_flash_sram_fw_part(client, info->fw_parity_name, 1112 tps23881_fw_parity_conf); 1113 if (ret) 1114 return ret; 1115 1116 ret = tps23881_flash_sram_fw_part(client, info->fw_sram_name, 1117 tps23881_fw_sram_conf); 1118 if (ret) 1119 return ret; 1120 1121 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_SRAM_CTRL, 0x18); 1122 if (ret) 1123 return ret; 1124 1125 mdelay(12); 1126 1127 return 0; 1128 } 1129 1130 /* Convert interrupt events to 0xff to be aligned with the chan 1131 * number. 1132 */ 1133 static u8 tps23881_irq_export_chans_helper(u16 reg_val, u8 field_offset) 1134 { 1135 u8 val; 1136 1137 val = (reg_val >> (4 + field_offset) & 0xf0) | 1138 (reg_val >> field_offset & 0x0f); 1139 1140 return val; 1141 } 1142 1143 /* Convert chan number to port number */ 1144 static void tps23881_set_notifs_helper(struct tps23881_priv *priv, 1145 u8 chans, 1146 unsigned long *notifs, 1147 unsigned long *notifs_mask, 1148 enum ethtool_pse_event event) 1149 { 1150 u8 chan; 1151 int i; 1152 1153 if (!chans) 1154 return; 1155 1156 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 1157 if (!priv->port[i].exist) 1158 continue; 1159 /* No need to look at the 2nd channel in case of PoE4 as 1160 * both registers are set. 1161 */ 1162 chan = priv->port[i].chan[0]; 1163 1164 if (BIT(chan) & chans) { 1165 *notifs_mask |= BIT(i); 1166 notifs[i] |= event; 1167 } 1168 } 1169 } 1170 1171 static void tps23881_irq_event_over_temp(struct tps23881_priv *priv, 1172 u16 reg_val, 1173 unsigned long *notifs, 1174 unsigned long *notifs_mask) 1175 { 1176 int i; 1177 1178 if (reg_val & TPS23881_REG_TSD) { 1179 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 1180 if (!priv->port[i].exist) 1181 continue; 1182 1183 *notifs_mask |= BIT(i); 1184 notifs[i] |= ETHTOOL_PSE_EVENT_OVER_TEMP; 1185 } 1186 } 1187 } 1188 1189 static int tps23881_irq_event_over_current(struct tps23881_priv *priv, 1190 u16 reg_val, 1191 unsigned long *notifs, 1192 unsigned long *notifs_mask) 1193 { 1194 int i, ret; 1195 u8 chans; 1196 1197 chans = tps23881_irq_export_chans_helper(reg_val, 0); 1198 if (!chans) 1199 return 0; 1200 1201 tps23881_set_notifs_helper(priv, chans, notifs, notifs_mask, 1202 ETHTOOL_PSE_EVENT_OVER_CURRENT | 1203 ETHTOOL_C33_PSE_EVENT_DISCONNECTION); 1204 1205 /* Over Current event resets the power limit registers so we need 1206 * to configured it again. 1207 */ 1208 for_each_set_bit(i, notifs_mask, priv->pcdev.nr_lines) { 1209 if (priv->port[i].pw_pol < 0) 1210 continue; 1211 1212 ret = tps23881_pi_enable_manual_pol(priv, i); 1213 if (ret < 0) 1214 return ret; 1215 1216 /* Set power policy */ 1217 ret = tps23881_pi_set_pw_pol_limit(priv, i, 1218 priv->port[i].pw_pol, 1219 priv->port[i].is_4p); 1220 if (ret < 0) 1221 return ret; 1222 } 1223 1224 return 0; 1225 } 1226 1227 static void tps23881_irq_event_disconnection(struct tps23881_priv *priv, 1228 u16 reg_val, 1229 unsigned long *notifs, 1230 unsigned long *notifs_mask) 1231 { 1232 u8 chans; 1233 1234 chans = tps23881_irq_export_chans_helper(reg_val, 4); 1235 if (chans) 1236 tps23881_set_notifs_helper(priv, chans, notifs, notifs_mask, 1237 ETHTOOL_C33_PSE_EVENT_DISCONNECTION); 1238 } 1239 1240 static int tps23881_irq_event_detection(struct tps23881_priv *priv, 1241 u16 reg_val, 1242 unsigned long *notifs, 1243 unsigned long *notifs_mask) 1244 { 1245 enum ethtool_pse_event event; 1246 int reg, ret, i, val; 1247 unsigned long chans; 1248 1249 chans = tps23881_irq_export_chans_helper(reg_val, 0); 1250 for_each_set_bit(i, &chans, TPS23881_MAX_CHANS) { 1251 reg = TPS23881_REG_DISC + (i % 4); 1252 ret = i2c_smbus_read_word_data(priv->client, reg); 1253 if (ret < 0) 1254 return ret; 1255 1256 val = tps23881_calc_val(ret, i, 0, 0xf); 1257 /* If detection valid */ 1258 if (val == 0x4) 1259 event = ETHTOOL_C33_PSE_EVENT_DETECTION; 1260 else 1261 event = ETHTOOL_C33_PSE_EVENT_DISCONNECTION; 1262 1263 tps23881_set_notifs_helper(priv, BIT(i), notifs, 1264 notifs_mask, event); 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int tps23881_irq_event_classification(struct tps23881_priv *priv, 1271 u16 reg_val, 1272 unsigned long *notifs, 1273 unsigned long *notifs_mask) 1274 { 1275 int reg, ret, val, i; 1276 unsigned long chans; 1277 1278 chans = tps23881_irq_export_chans_helper(reg_val, 4); 1279 for_each_set_bit(i, &chans, TPS23881_MAX_CHANS) { 1280 reg = TPS23881_REG_DISC + (i % 4); 1281 ret = i2c_smbus_read_word_data(priv->client, reg); 1282 if (ret < 0) 1283 return ret; 1284 1285 val = tps23881_calc_val(ret, i, 4, 0xf); 1286 /* Do not report classification event for unknown class */ 1287 if (!val || val == 0x8 || val == 0xf) 1288 continue; 1289 1290 tps23881_set_notifs_helper(priv, BIT(i), notifs, 1291 notifs_mask, 1292 ETHTOOL_C33_PSE_EVENT_CLASSIFICATION); 1293 } 1294 1295 return 0; 1296 } 1297 1298 static int tps23881_irq_event_handler(struct tps23881_priv *priv, u16 reg, 1299 unsigned long *notifs, 1300 unsigned long *notifs_mask) 1301 { 1302 struct i2c_client *client = priv->client; 1303 int ret, val; 1304 1305 /* The Supply event bit is repeated twice so we only need to read 1306 * the one from the first byte. 1307 */ 1308 if (reg & TPS23881_REG_IT_SUPF) { 1309 ret = i2c_smbus_read_word_data(client, TPS23881_REG_SUPF_EVENT); 1310 if (ret < 0) 1311 return ret; 1312 tps23881_irq_event_over_temp(priv, ret, notifs, notifs_mask); 1313 } 1314 1315 if (reg & (TPS23881_REG_IT_IFAULT | TPS23881_REG_IT_IFAULT << 8 | 1316 TPS23881_REG_IT_DISF | TPS23881_REG_IT_DISF << 8)) { 1317 ret = i2c_smbus_read_word_data(client, TPS23881_REG_FAULT); 1318 if (ret < 0) 1319 return ret; 1320 ret = tps23881_irq_event_over_current(priv, ret, notifs, 1321 notifs_mask); 1322 if (ret) 1323 return ret; 1324 1325 tps23881_irq_event_disconnection(priv, ret, notifs, notifs_mask); 1326 } 1327 1328 if (reg & (TPS23881_REG_IT_DETC | TPS23881_REG_IT_DETC << 8 | 1329 TPS23881_REG_IT_CLASC | TPS23881_REG_IT_CLASC << 8)) { 1330 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DET_EVENT); 1331 if (ret < 0) 1332 return ret; 1333 1334 val = ret; 1335 ret = tps23881_irq_event_detection(priv, val, notifs, 1336 notifs_mask); 1337 if (ret) 1338 return ret; 1339 1340 ret = tps23881_irq_event_classification(priv, val, notifs, 1341 notifs_mask); 1342 if (ret) 1343 return ret; 1344 } 1345 return 0; 1346 } 1347 1348 static int tps23881_irq_handler(int irq, struct pse_controller_dev *pcdev, 1349 unsigned long *notifs, 1350 unsigned long *notifs_mask) 1351 { 1352 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 1353 struct i2c_client *client = priv->client; 1354 int ret, it_mask, retry; 1355 1356 /* Get interruption mask */ 1357 ret = i2c_smbus_read_word_data(client, TPS23881_REG_IT_MASK); 1358 if (ret < 0) 1359 return ret; 1360 it_mask = ret; 1361 1362 /* Read interrupt register until it frees the interruption pin. */ 1363 retry = 0; 1364 while (true) { 1365 if (retry > TPS23881_MAX_IRQ_RETRIES) { 1366 dev_err(&client->dev, "interrupt never freed"); 1367 return -ETIMEDOUT; 1368 } 1369 1370 ret = i2c_smbus_read_word_data(client, TPS23881_REG_IT); 1371 if (ret < 0) 1372 return ret; 1373 1374 /* No more relevant interruption */ 1375 if (!(ret & it_mask)) 1376 return 0; 1377 1378 ret = tps23881_irq_event_handler(priv, (u16)ret, notifs, 1379 notifs_mask); 1380 if (ret) 1381 return ret; 1382 1383 retry++; 1384 } 1385 return 0; 1386 } 1387 1388 static int tps23881_setup_irq(struct tps23881_priv *priv, int irq) 1389 { 1390 struct i2c_client *client = priv->client; 1391 struct pse_irq_desc irq_desc = { 1392 .name = "tps23881-irq", 1393 .map_event = tps23881_irq_handler, 1394 }; 1395 int ret; 1396 u16 val; 1397 1398 if (!irq) { 1399 dev_err(&client->dev, "interrupt is missing"); 1400 return -EINVAL; 1401 } 1402 1403 val = TPS23881_REG_IT_IFAULT | TPS23881_REG_IT_SUPF | 1404 TPS23881_REG_IT_DETC | TPS23881_REG_IT_CLASC | 1405 TPS23881_REG_IT_DISF; 1406 val |= val << 8; 1407 ret = i2c_smbus_write_word_data(client, TPS23881_REG_IT_MASK, val); 1408 if (ret) 1409 return ret; 1410 1411 ret = i2c_smbus_read_word_data(client, TPS23881_REG_GEN_MASK); 1412 if (ret < 0) 1413 return ret; 1414 1415 val = TPS23881_REG_INTEN | TPS23881_REG_CLCHE | TPS23881_REG_DECHE; 1416 val |= val << 8; 1417 val |= (u16)ret; 1418 ret = i2c_smbus_write_word_data(client, TPS23881_REG_GEN_MASK, val); 1419 if (ret < 0) 1420 return ret; 1421 1422 /* Reset interrupts registers */ 1423 ret = i2c_smbus_write_word_data(client, TPS23881_REG_RESET, 1424 TPS23881_REG_CLRAIN); 1425 if (ret < 0) 1426 return ret; 1427 1428 return devm_pse_irq_helper(&priv->pcdev, irq, 0, &irq_desc); 1429 } 1430 1431 static int tps23881_i2c_probe(struct i2c_client *client) 1432 { 1433 struct device *dev = &client->dev; 1434 const struct tps23881_info *info; 1435 struct tps23881_priv *priv; 1436 struct gpio_desc *reset; 1437 int ret; 1438 u8 val; 1439 1440 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1441 dev_err(dev, "i2c check functionality failed\n"); 1442 return -ENXIO; 1443 } 1444 1445 info = i2c_get_match_data(client); 1446 if (!info) 1447 return -EINVAL; 1448 1449 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1450 if (!priv) 1451 return -ENOMEM; 1452 1453 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1454 if (IS_ERR(reset)) 1455 return dev_err_probe(&client->dev, PTR_ERR(reset), "Failed to get reset GPIO\n"); 1456 1457 if (reset) { 1458 /* TPS23880 datasheet (Rev G) indicates minimum reset pulse is 5us */ 1459 usleep_range(5, 10); 1460 gpiod_set_value_cansleep(reset, 0); /* De-assert reset */ 1461 1462 /* TPS23880 datasheet indicates the minimum time after power on reset 1463 * should be 20ms, but the document describing how to load SRAM ("How 1464 * to Load TPS2388x SRAM and Parity Code over I2C" (Rev E)) 1465 * indicates we should delay that programming by at least 50ms. So 1466 * we'll wait the entire 50ms here to ensure we're safe to go to the 1467 * SRAM loading procedure. 1468 */ 1469 msleep(50); 1470 } 1471 1472 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_DEVID); 1473 if (ret < 0) 1474 return ret; 1475 1476 if (ret != info->dev_id) { 1477 dev_err(dev, "Wrong device ID\n"); 1478 return -ENXIO; 1479 } 1480 1481 if (info->fw_sram_name) { 1482 ret = tps23881_flash_sram_fw(client, info); 1483 if (ret < 0) 1484 return ret; 1485 } 1486 1487 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FWREV); 1488 if (ret < 0) 1489 return ret; 1490 1491 if (ret == 0xFF) { 1492 dev_err(&client->dev, "Device entered safe mode\n"); 1493 return -ENXIO; 1494 } 1495 dev_info(&client->dev, "Firmware revision 0x%x%s\n", ret, 1496 ret == 0x00 ? " (ROM firmware)" : ""); 1497 1498 /* Set configuration B, 16 bit access on a single device address */ 1499 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_GEN_MASK); 1500 if (ret < 0) 1501 return ret; 1502 1503 val = ret | TPS23881_REG_NBITACC; 1504 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_GEN_MASK, val); 1505 if (ret) 1506 return ret; 1507 1508 priv->client = client; 1509 i2c_set_clientdata(client, priv); 1510 priv->np = dev->of_node; 1511 1512 priv->pcdev.owner = THIS_MODULE; 1513 priv->pcdev.ops = &tps23881_ops; 1514 priv->pcdev.dev = dev; 1515 priv->pcdev.types = ETHTOOL_PSE_C33; 1516 priv->pcdev.nr_lines = TPS23881_MAX_CHANS; 1517 priv->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_STATIC; 1518 ret = devm_pse_controller_register(dev, &priv->pcdev); 1519 if (ret) { 1520 return dev_err_probe(dev, ret, 1521 "failed to register PSE controller\n"); 1522 } 1523 1524 ret = tps23881_setup_irq(priv, client->irq); 1525 if (ret) 1526 return ret; 1527 1528 return ret; 1529 } 1530 1531 static const struct i2c_device_id tps23881_id[] = { 1532 { "tps23881", .driver_data = (kernel_ulong_t)&tps23881_info[TPS23881] }, 1533 { "tps23881b", .driver_data = (kernel_ulong_t)&tps23881_info[TPS23881B] }, 1534 { } 1535 }; 1536 MODULE_DEVICE_TABLE(i2c, tps23881_id); 1537 1538 static const struct of_device_id tps23881_of_match[] = { 1539 { 1540 .compatible = "ti,tps23881", 1541 .data = &tps23881_info[TPS23881] 1542 }, 1543 { 1544 .compatible = "ti,tps23881b", 1545 .data = &tps23881_info[TPS23881B] 1546 }, 1547 { }, 1548 }; 1549 MODULE_DEVICE_TABLE(of, tps23881_of_match); 1550 1551 static struct i2c_driver tps23881_driver = { 1552 .probe = tps23881_i2c_probe, 1553 .id_table = tps23881_id, 1554 .driver = { 1555 .name = "tps23881", 1556 .of_match_table = tps23881_of_match, 1557 }, 1558 }; 1559 module_i2c_driver(tps23881_driver); 1560 1561 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>"); 1562 MODULE_DESCRIPTION("TI TPS23881 PoE PSE Controller driver"); 1563 MODULE_LICENSE("GPL"); 1564