1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * thread_info.h: LoongArch low-level thread information 4 * 5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef _ASM_THREAD_INFO_H 9 #define _ASM_THREAD_INFO_H 10 11 #ifdef __KERNEL__ 12 13 #ifndef __ASSEMBLER__ 14 15 #include <asm/processor.h> 16 17 /* 18 * low level task data that entry.S needs immediate access to 19 * - this struct should fit entirely inside of one cache line 20 * - this struct shares the supervisor stack pages 21 * - if the contents of this structure are changed, the assembly constants 22 * must also be changed 23 */ 24 struct thread_info { 25 struct task_struct *task; /* main task structure */ 26 unsigned long flags; /* low level flags */ 27 unsigned long tp_value; /* thread pointer */ 28 __u32 cpu; /* current CPU */ 29 int preempt_count; /* 0 => preemptible, <0 => BUG */ 30 struct pt_regs *regs; 31 unsigned long syscall; /* syscall number */ 32 unsigned long syscall_work; /* SYSCALL_WORK_ flags */ 33 }; 34 35 /* 36 * macros/functions for gaining access to the thread information structure 37 */ 38 #define INIT_THREAD_INFO(tsk) \ 39 { \ 40 .task = &tsk, \ 41 .flags = _TIF_FIXADE, \ 42 .cpu = 0, \ 43 .preempt_count = INIT_PREEMPT_COUNT, \ 44 } 45 46 /* How to get the thread information struct from C. */ 47 register struct thread_info *__current_thread_info __asm__("$tp"); 48 current_thread_info(void)49static inline struct thread_info *current_thread_info(void) 50 { 51 return __current_thread_info; 52 } 53 54 register unsigned long current_stack_pointer __asm__("$sp"); 55 56 #endif /* !__ASSEMBLER__ */ 57 58 /* thread information allocation */ 59 #define THREAD_SIZE SZ_16K 60 #define THREAD_MASK (THREAD_SIZE - 1UL) 61 #define THREAD_SIZE_ORDER ilog2(THREAD_SIZE / PAGE_SIZE) 62 /* 63 * thread information flags 64 * - these are process state flags that various assembly files may need to 65 * access 66 * - pending work-to-be-done flags are in LSW 67 * - other flags in MSW 68 * 69 * Tell the generic TIF infrastructure which special bits loongarch supports 70 */ 71 #define HAVE_TIF_NEED_RESCHED_LAZY 72 #define HAVE_TIF_RESTORE_SIGMASK 73 74 #include <asm-generic/thread_info_tif.h> 75 76 /* Architecture specific bits */ 77 #define TIF_NOHZ 16 /* in adaptive nohz mode */ 78 #define TIF_USEDFPU 17 /* FPU was used by this task this quantum (SMP) */ 79 #define TIF_USEDSIMD 18 /* SIMD has been used this quantum */ 80 #define TIF_FIXADE 19 /* Fix address errors in software */ 81 #define TIF_LOGADE 20 /* Log address errors to syslog */ 82 #define TIF_32BIT_REGS 21 /* 32-bit general purpose registers */ 83 #define TIF_32BIT_ADDR 22 /* 32-bit address space */ 84 #define TIF_LOAD_WATCH 23 /* If set, load watch registers */ 85 #define TIF_SINGLESTEP 24 /* Single Step */ 86 #define TIF_LSX_CTX_LIVE 25 /* LSX context must be preserved */ 87 #define TIF_LASX_CTX_LIVE 26 /* LASX context must be preserved */ 88 #define TIF_USEDLBT 27 /* LBT was used by this task this quantum (SMP) */ 89 #define TIF_LBT_CTX_LIVE 28 /* LBT context must be preserved */ 90 91 #define _TIF_NOHZ BIT(TIF_NOHZ) 92 #define _TIF_USEDFPU BIT(TIF_USEDFPU) 93 #define _TIF_USEDSIMD BIT(TIF_USEDSIMD) 94 #define _TIF_FIXADE BIT(TIF_FIXADE) 95 #define _TIF_LOGADE BIT(TIF_LOGADE) 96 #define _TIF_32BIT_REGS BIT(TIF_32BIT_REGS) 97 #define _TIF_32BIT_ADDR BIT(TIF_32BIT_ADDR) 98 #define _TIF_LOAD_WATCH BIT(TIF_LOAD_WATCH) 99 #define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) 100 #define _TIF_LSX_CTX_LIVE BIT(TIF_LSX_CTX_LIVE) 101 #define _TIF_LASX_CTX_LIVE BIT(TIF_LASX_CTX_LIVE) 102 #define _TIF_USEDLBT BIT(TIF_USEDLBT) 103 #define _TIF_LBT_CTX_LIVE BIT(TIF_LBT_CTX_LIVE) 104 105 #endif /* __KERNEL__ */ 106 #endif /* _ASM_THREAD_INFO_H */ 107